( DOC No. HX8369-A00-DS ) HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver Version 02 October, 2010 HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents October, 2010 1. General Description ..........................................................................................................................10 2. Features .............................................................................................................................................11 2.1 2.2 2.3 2.4 2.5 3. Display........................................................................................................................................11 Display module...........................................................................................................................11 Display / Control interface ..........................................................................................................12 Input power.................................................................................................................................12 Miscellaneous.............................................................................................................................12 Device Overview ...............................................................................................................................13 3.1 Block diagram.............................................................................................................................13 3.2 Pin description............................................................................................................................14 3.3 Pin assignment...........................................................................................................................18 3.4 PAD coordinates.........................................................................................................................19 3.4.1 Bump arrangement ................................................................................................................27 4. Interface .............................................................................................................................................29 4.1 System interface.........................................................................................................................29 4.1.1 DBI-A / DBI-B interface ..........................................................................................................31 4.2 Serial data transfer interface (DBI-C) .........................................................................................42 4.2.2 DPI interface (Display Pixel Interface) ...................................................................................46 5. Function Description ........................................................................................................................52 5.1 Display data GRAM....................................................................................................................52 5.2 Address counter (AC).................................................................................................................52 5.3 Source, gate and memory map..................................................................................................53 5.3.1 480RGB x 864 resolution.......................................................................................................53 5.3.2 480RGB x 854 resolution.......................................................................................................54 5.3.3 480RGB x 800 resolution.......................................................................................................55 5.3.4 480RGB x 640 resolution.......................................................................................................56 5.3.5 360RGB x 640 resolution.......................................................................................................57 5.3.6 480RGB x 720 resolution.......................................................................................................58 5.4 MCU to memory write / read direction........................................................................................59 5.5 Fully display, partial display, vertical scrolling display ................................................................61 5.5.1 Fully display ...........................................................................................................................61 5.5.2 Vertical scrolling display.........................................................................................................67 5.5.3 Tearing effect output line........................................................................................................70 5.6 Color depth conversion ..............................................................................................................74 5.6.1 Color depth conversion Look-up tables .................................................................................74 5.7 Oscillator.....................................................................................................................................80 5.8 Source driver ..............................................................................................................................81 5.9 LCD power generation scheme..................................................................................................82 5.10 DC/DC converter circuit..............................................................................................................83 5.10.1 Use PFM DC/DC converter ...............................................................................................83 5.10.2 Use HX5186-A...................................................................................................................84 5.11 Idle display .................................................................................................................................85 5.12 Gamma characteristic correction function..................................................................................86 5.13 Characteristics of I/O................................................................................................................128 5.13.1 Output or bi-directional (I/O) pins ....................................................................................128 5.13.2 Input pins .........................................................................................................................128 5.14 GIP control singal .....................................................................................................................129 5.15 Sleep Out –command and self-diagnostic functions of the display module.............................130 5.15.1 Register loading detection ...............................................................................................130 5.15.2 Functionality detection .....................................................................................................131 Himax Confidential - P.2- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, 2010 HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents October, 2010 5.16 Power on/off sequence.............................................................................................................132 5.16.1 Case 1: RESX line is held high or unstable by host at power on ....................................133 5.16.2 Case 2: RESX line is held low by host at power on ........................................................134 5.17 Uncontrolled power off .............................................................................................................134 5.18 Content adaptive brightness control (CABC) function .............................................................135 5.18.1 Module architectures .......................................................................................................136 5.18.2 CABC block .....................................................................................................................137 5.18.3 Brightness control block ..................................................................................................138 5.18.4 Minimum brightness setting of CABC function ................................................................139 5.19 OTP programing .......................................................................................................................140 5.19.1 OTP table.........................................................................................................................140 5.19.2 OTP programming flow....................................................................................................143 5.19.3 Programming sequence ..................................................................................................144 5.19.4 OTP Programming example of VCOM setting VCMC_F and VCMC_B .........................145 5.19.5 OTP Programming example of ID1, ID2 and ID3 ............................................................146 5.19.6 OTP read example of 0x1Bh (VCOM setting re-load) .....................................................147 5.19.7 OTP read example of VCMC_F1.....................................................................................148 5.20 Temperature sensor control......................................................................................................149 6. Command.........................................................................................................................................150 6.1 Command list ...........................................................................................................................150 6.1.1 Standard command..............................................................................................................150 6.1.2 User define command list table............................................................................................154 6.2 Command description ..............................................................................................................158 6.2.1 NOP (00h) ............................................................................................................................158 6.2.2 Software reset (01h) ............................................................................................................159 6.2.3 RDNUMPE: Read number of the parity errors (05h) ...........................................................160 6.2.4 Get_red_channel (06h) ........................................................................................................161 6.2.5 Get_green_channel (07h) ....................................................................................................162 6.2.6 Get_blue_channel (08h) ......................................................................................................163 6.2.7 Get_power_mode (0Ah).......................................................................................................164 6.2.8 Read display MADCTL (0Bh)...............................................................................................165 6.2.9 Get_pixel_format (0Ch)........................................................................................................167 6.2.10 Get_display_mode (0Dh).................................................................................................169 6.2.11 Get_signal_mode (0Eh)...................................................................................................170 6.2.12 Get_diagnostic_result (0Fh) ............................................................................................171 6.2.13 Enter_sleep_mode (10h) .................................................................................................172 6.2.14 Exit_sleep_omde (11h) ....................................................................................................173 6.2.15 Enter_partial_mode (12h) ................................................................................................174 6.2.16 Enter_normal_mode (13h)...............................................................................................175 6.2.17 Exit_inversion_mode (20h)..............................................................................................176 6.2.18 Enter_inversion_mode (21h) ...........................................................................................177 6.2.19 Set_gamma_curve (26h) .................................................................................................178 6.2.20 Set_display_off (28h).......................................................................................................179 6.2.21 Set_display_on (29h).......................................................................................................180 6.2.22 Set_clumn_address (2Ah) ...............................................................................................181 6.2.23 Set_page_address (2Bh).................................................................................................182 6.2.24 Write_memory_start (2Ch) ..............................................................................................183 6.2.25 Colour Set (2Dh)..............................................................................................................184 6.2.26 Raed_memory_start (2Eh) ..............................................................................................187 6.2.27 Set_partial_area (30h) .....................................................................................................188 6.2.28 Set_scroll_area (33h) ......................................................................................................190 6.2.29 Tearing effect line off (34h) ..............................................................................................193 6.2.30 Set_tear_on (35h)............................................................................................................194 6.2.31 Set_address_mode (36h) ................................................................................................195 Himax Confidential - P.32010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents 6.2.32 6.2.33 6.2.34 6.2.35 6.2.36 6.2.37 6.2.38 6.2.39 6.2.40 6.2.41 6.2.42 6.2.43 6.2.44 6.2.45 6.2.46 6.2.47 6.2.48 6.2.49 6.2.50 6.2.51 6.2.52 6.2.53 6.2.54 6.2.55 6.2.56 6.2.57 6.2.58 6.2.59 6.2.60 6.2.61 6.2.62 6.2.63 6.2.64 6.2.65 6.2.66 6.2.67 6.2.68 6.2.69 6.2.70 6.2.71 6.2.72 6.2.73 7. October, 2010 Set_scroll_start (37h).......................................................................................................197 Idle mode off (38h)...........................................................................................................198 Enter_Idle_mode (39h) ....................................................................................................199 Set_pixel_format (3Ah) ....................................................................................................200 Write_memory_contiune (3Ch)........................................................................................201 Raed_memory_continue (3Eh)........................................................................................202 Set tear scan lines (44h)..................................................................................................203 Get the current scanline(45h) ..........................................................................................204 Write display brightness (51h) .........................................................................................205 Read display brightness value (52h) ...............................................................................206 Write CTRL display (53h) ................................................................................................207 Read CTRL value display (54h) ......................................................................................208 Write content adaptive brightness control (55h) ..............................................................209 Read content adaptive brightness control (56h)..............................................................210 Write CABC minimum brightness (5Eh) ..........................................................................211 Read CABC minimum brightness (5Fh) ..........................................................................212 Read automatic brightness control self-diagnostic result (68h) ......................................213 Read_DDB_start (A1h)....................................................................................................214 Read_DDB_continue (A8h) .............................................................................................216 Read ID1 (DAh) ...............................................................................................................217 Read ID2 (DBh) ...............................................................................................................218 Read ID3 (DCh) ...............................................................................................................219 SETOSC: Set internal oscillator (B0h).............................................................................220 SETPOWER: Set power (B1h) ........................................................................................221 SETDISP: Set display related register (B2h)...................................................................230 SETRGBIF: Set RGB interface related register (B3h).....................................................233 SETCYC: Set display waveform cycle (B4h)...................................................................234 SETVCOM: Set VCOM voltage (B6h) .............................................................................237 SETEXTC: Set extension command (B9h) .....................................................................240 SETOTP: Set OTP (BBh) ................................................................................................241 SETDGCLUT: Set DGC LUT (C1h) .................................................................................242 SETID: Set ID (C3h) ........................................................................................................244 SETCABC: Set CABC Control (C9h)...............................................................................245 SETPANEL (CCh)............................................................................................................247 SETGIP (D5h)..................................................................................................................248 SETTPSNR (D8h)............................................................................................................255 SETGAMMA: Set gamma curve related setting (E0h) ....................................................260 SETOTPKEY (E9h) .........................................................................................................262 GETHXID (F4h) ...............................................................................................................263 SETCNCD/GETCNCD (FDh) ..........................................................................................264 SET SPI READ INDEX (FEh) ..........................................................................................265 GETSPIREAD: Read command data (FFh) ....................................................................266 Power Supply ..................................................................................................................................267 7.1 Power supply setup ..................................................................................................................267 7.1.1 Architecture 1 with PFM circuit ............................................................................................267 7.1.2 Architecture 2 with HX5186-A..............................................................................................268 7.2 Voltage configuration................................................................................................................269 8. Electrical Characteristics ...............................................................................................................270 8.1 8.2 8.3 Absolute maximum ratings .......................................................................................................270 ESD protection level.................................................................................................................270 DC characteristics ....................................................................................................................271 Himax Confidential - P.42010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents October, 2010 8.4 AC characteristics ....................................................................................................................272 8.4.1 DBI Type A interface characteristics ....................................................................................272 8.4.2 DBI Type B interface characteristics ....................................................................................273 8.4.3 DBI Type C interface characteristics....................................................................................274 8.4.4 DPI interface characteristics ................................................................................................275 8.4.5 Reset input timing ................................................................................................................279 8.4.6 DPI Interface Power On/Off Timing......................................................................................280 9. Layout Recommendation ...............................................................................................................282 10. Maximum Layout Resistance.........................................................................................................283 11. Ordering Information ......................................................................................................................284 12. Revision History..............................................................................................................................284 Himax Confidential - P.52010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Figures October, 2010 Figure 4.1: DBI-A system interface protocol, write to register or GRAM ...................................31 Figure 4.2: DBI-A system interface protocol, read from register or GRAM................................31 Figure 4.3: DBI-B system interface protocol, write to register or GRAM ...................................32 Figure 4.4: DBI-B system interface protocol, read from register or GRAM................................32 Figure 4.5 Example of DBI-B system 24-bit parallel bus interface.............................................33 Figure 4.6: Write data for RGB 8-8-8 (16.7M colours) bit Input in 24-bit parallel interface........33 Figure 4.7: Example of DBI-A- / DBI-B system 18-bit parallel bus interface..............................34 Figure 4.8: Write data for RGB 5-6-5 (65k colours) bit input in 18-bit parallel interface ............34 Figure 4.9: Write data for RGB 6-6-6(262k colours) bit input in 18-bit parallel interface ...........34 Figure 4.10: Write data for RGB 8-8-8 (16.7M colours) bit input in 18-bit parallel interface......35 Figure 4.11: Example of DBI-A- / DBI-B system 16-bit bus interface.........................................36 Figure 4.12: Write data for RGB 5-6-5 (65k colours) bit input in 16-bit parallel interface ..........36 Figure 4.13: Write data for RGB 6-6-6 (262k colours) bit input in 16-bit parallel interface ........37 Figure 4.14: Write data for RGB 8-8-8-bit (16.7M colours) input in 16-bit parallel interface......37 Figure 4.15: Example of DBI-A- / DBI-B- system 9-bit bus interface .........................................38 Figure 4.16: Write data for RGB 5-6-5(65k colours) bit input in 9-bit parallel interface .............38 Figure 4.17: Write data for RGB 6-6-6-bit (262k colours) input in 9-bit parallel interface..........39 Figure 4.18: Write data for RGB 8-8-8-bit (16.7 M colours) input in 9-bit parallel interface.......39 Figure 4.19: Example of DBI-A- / DBI-B-system 8-bit bus interface ..........................................40 Figure 4.20: Write data for RGB 5-6-5 (65k colours) bit input in 8-bit parallel interface ............40 Figure 4.21: Write data for RGB 6-6-6-bit (262k colours) input in 8-bit parallel interface..........41 Figure 4.22: Write data for RGB 8-8-8-bit (16.7 M colours) input in 8-bit parallel interface.......41 Figure 4.23: Serial data stream, write mode ..............................................................................42 Figure 4.24: DBI Type C: Serial interface protocol 3-wire/4-wire, write mode ...........................43 Figure 4.25: Type C:Serial interface protocol 3-wire/4-wire read mode.....................................44 Figure 4.26: Display module data transfer recovery ..................................................................45 Figure 4.27: PCLK cycle.............................................................................................................46 Figure 4.28: General timing diagram..........................................................................................47 Figure 4.29: DPI (480RGB x 864) timing diagram .....................................................................47 Figure 4.30: 16-bit / pixel 65K colours order on the DPI I/F.......................................................49 Figure 4.31: 18-bit / pixel: 262k colours order on the DPI I/F ....................................................50 Figure 4.32: 24-bit / pixel color order on the RGB I/F ................................................................51 Figure 5.1: MCU to Memory write / read direction .....................................................................59 Figure 5.2: MY, MX, MV setting of 480RGB x 864 dot ..............................................................59 Figure 5.3: MY, MX, MV setting of 480RGB x 864 dot ..............................................................59 Figure 5.4: Address direction settings........................................................................................60 Figure 5.5: 480RGB x 864 resolution.........................................................................................61 Figure 5.6: 480RGB x 854 resolution.........................................................................................62 Figure 5.7: 480RGB x 800 resolution.........................................................................................63 Figure 5.8: 480RGB x 640 resolution.........................................................................................64 Figure 5.9: 360RGB x 640 resolution.........................................................................................65 Figure 5.10: 480RGB x 720 resolution.......................................................................................66 Figure 5.11: Vertical scrolling .....................................................................................................67 Figure 5.12: Memory map of vertical scrolling 1 ........................................................................67 Figure 5.13: Memory map of vertical scrolling 2 ........................................................................68 Figure 5.14: Vertical scroll example 1 ........................................................................................69 Figure 5.15: Vertical scroll example 2 ........................................................................................69 Figure 5.16: Tearing effect output line–mode 1..........................................................................70 Figure 5.17: Tearing effect output line–mode 2..........................................................................70 Figure 5.18: Tearing effect output line–timing diagrm ................................................................70 Figure 5.19: Tearing effect output line –tearing effect line timing...............................................71 Figure 5.20: Tearing effect output line–definition of tf, tr ............................................................71 Figure 5.21: Tearing effect output line–example 1 (Timing) .......................................................72 Figure 5.22: Tearing effect output line–example 1 (Image)........................................................72 Figure 5.23: Tearing effect output line–example 2 (Timing) .......................................................73 Himax Confidential - P.62010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Figures October, 2010 Figure 5.24: Tearing effect output line–example 2 (Image)........................................................73 Figure 5.25: OSC aritecture .......................................................................................................80 Figure 5.26: LCD power generation scheme .............................................................................82 Figure 5.27: DC/DC converter circuit (PFM Type C)–PCCS=10................................................83 Figure 5.28: DC/DC converter circuit (HX5186-A) .....................................................................84 Figure 5.29: Idle mode grayscale control ...................................................................................85 Figure 5.30: Grayscale control ...................................................................................................86 Figure 5.31: Gamma resister stream and gamma reference voltage ........................................88 Figure 5.32: Gamma resister stream .........................................................................................89 Figure 5.33: Sleep out flow chart–command and self-diagnostic functions.............................130 Figure 5.34: Sleep out flow chart internal function detection ...................................................131 Figure 5.35: Case 1: RESX line is held high or unstable by host at power on ........................133 Figure 5.36: Case 2: RESX line is held low by host at power on.............................................134 Figure 5.37: CABC block diagram............................................................................................135 Figure 5.38: Module architecture .............................................................................................136 Figure 5.39: CABC gain / CABC duty generation ....................................................................137 Figure 5.40: CABC_PWM_OUT output duty............................................................................138 Figure 5.41: OTP programming sequence...............................................................................143 Figure 5.42: OTP programming sequence example 1. ............................................................145 Figure 5.43: OTP programming sequence example 2. ............................................................146 Figure 5.44: OTP programming sequence index 0x1Bh read flow. .........................................147 Figure 5.45: OTP programming sequence read flow. ..............................................................148 Figure 5.46: Temperature sensor .............................................................................................149 Figure 7.1: Power supply with PFM circuit ...............................................................................267 Figure 7.2: Power supply with HX5186-A ................................................................................268 Figure 8.1: DBI Type A interface characteristics(CLK-E mode) ...............................................272 Figure 8.2: DBI Type B interface characteristics ......................................................................273 Figure 8.3: DBI Type C interface characteristics......................................................................274 Figure 8.4: DPI interface characteristics ..................................................................................275 Figure 8.5: Vertical Timings for RGB I/F...................................................................................277 Figure 8.6: Horizontal Timing for RGB I/F ................................................................................278 Figure 8.7: Reset input timing ..................................................................................................279 Figure 8.8 Power On Timing ....................................................................................................280 Figure 8.9 Power Off Timing ....................................................................................................281 Figure 9.1: Layout recommendation ........................................................................................282 Himax Confidential - P.72010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Tables October, 2010 Table 4.1: Interface selection .....................................................................................................29 Table 4.2: Pin connection based on different interface ..............................................................30 Table 5.1: Addresses counter range...........................................................................................52 Table 5.2: Memory map of 480RGB x 864 resolution ................................................................53 Table 5.3: Memory map of 480RGB x 854 resolution ................................................................54 Table 5.4: Memory map of 480RGB x 800 resolution ................................................................55 Table 5.5: Memory map of 480RGB x 640 resolution ................................................................56 Table 5.6: Memory map of 360RGB x640 resolution .................................................................57 Table 5.7: Memory map of 480RGB x 720 resolution ................................................................58 Table 5.8: 480RGB x 864 resolution (SRAM assignment) .........................................................61 Table 5.9: 480RGB x 854 resolution (SRAM assignment) .........................................................62 Table 5.10: 480RGB x 800 resolution (SRAM assignment) .......................................................63 Table 5.11: 480RGB x 640 resolution (SRAM assignment) .......................................................64 Table 5.12: 360RGB x 640 resolution (SRAM assignment) .......................................................65 Table 5.13: 480RGB x 720 resolution (SRAM assignment) .......................................................66 Table 5.14: AC characteristics of tearing effect signal ...............................................................71 Table 5.15: Look-up tables-1 ......................................................................................................74 Table 5.16: Look-up tables-2 ......................................................................................................75 Table 5.17: Look-up tables-3 ......................................................................................................76 Table 5.18: Look-up tables-4 ......................................................................................................77 Table 5.19: Look-up tables-5 ......................................................................................................78 Table 5.20: Look-up tables-6 ......................................................................................................79 Table 5.21: Gamma-Adjustment registers..................................................................................87 Table 5.22: Offset adjustment 0~5 .............................................................................................90 Table 5.23: Center adjustment ...................................................................................................90 Table 5.24: VinP0 .......................................................................................................................91 Table 5.25: VinP1 .......................................................................................................................92 Table 5.26: VinP2 .......................................................................................................................93 Table 5.27: VinP14 .....................................................................................................................94 Table 5.28: VinP15 .....................................................................................................................95 Table 5.29: VinP16 .....................................................................................................................96 Table 5.30: VinP5 .......................................................................................................................98 Table 5.31: VinP11 ...................................................................................................................100 Table 5.32: VinP3 .....................................................................................................................101 Table 5.33: VinP4 .....................................................................................................................102 Table 5.34: VinP6 .....................................................................................................................102 Table 5.35: VinP7 .....................................................................................................................103 Table 5.36: VinP8 .....................................................................................................................103 Table 5.37: VinP9 .....................................................................................................................104 Table 5.38: VinP10 ...................................................................................................................104 Table 5.39: VinP12 ...................................................................................................................105 Table 5.40: VinP13 ...................................................................................................................105 Table 5.41: VinN0 .....................................................................................................................106 Table 5.42: VinN1 .....................................................................................................................107 Table 5.43: VinN2 .....................................................................................................................108 Table 5.44: VinN14 ...................................................................................................................109 Table 5.45: VinN15 ...................................................................................................................110 Table 5.46: VinN16 ................................................................................................................... 111 Table 5.47: VinN5 .....................................................................................................................113 Table 5.48: VinN11 ...................................................................................................................115 Table 5.49: VinN3 .....................................................................................................................116 Table 5.50: VinN4 .....................................................................................................................117 Table 5.51: VinN6 .....................................................................................................................117 Table 5.52: VinN7 .....................................................................................................................118 Table 5.53: VinN8 .....................................................................................................................118 Himax Confidential - P.8- This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, 2010 HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver List of Tables October, 2010 Table 5.54: VinN9 .....................................................................................................................119 Table 5.55: VinN10 ...................................................................................................................119 Table 5.56: VinN12 ...................................................................................................................120 Table 5.57: VinN13 ...................................................................................................................120 Table 5.58: Voltage calculation formula of 64-grayscale voltage (positive polarity).................122 Table 5.59: Voltage calculation formula of 64-grayscale voltage (negative polarity) ...............124 Table 5.60: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity)127 Table 5.61 Characteristics of output or bi-directional (I/O) pins ...............................................128 Table 5.62 Characteristics of input pins ...................................................................................128 Table 5.63 CABC timing table ..................................................................................................138 Table 5.64: OTP Programming sequence ................................................................................144 Table 7.1: Adoptability of component .......................................................................................269 Table 8.1: Absolute maximum rating ........................................................................................270 Table 8.2: ESD protection level ................................................................................................270 Table 8.3: DC characteristic .....................................................................................................271 Table 8.4: DBI Type A interface characteristics ........................................................................272 Table 8.5: DBI Type B interface characteristics........................................................................273 Table 8.6: DBI Type C interface characteristics .......................................................................274 Table 8.7: DPI interface characteristics....................................................................................276 Table 8.8 Vertical Timings for RGB I/F .....................................................................................277 Table 8.9 Horizontal Timings for RGB I/F.................................................................................278 Table 8.10: Reset timing...........................................................................................................279 Table 10.1: Maximum layout resistance ...................................................................................283 Himax Confidential - P.92010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. October, HX8369-A00 480RGB x 864 dot, 16.7M color, with internal GRAM, TFT Mobile Single Chip Driver Version 02 October, 2010 1. General Description This document describes Himax’s HX8369-A00 supports WVGA resolution driving controller. The HX8369-A00 is designed to provide a single-chip solution that combines a source driver, power supply circuit to drive a TFT dot matrix LCD with 480RGBx864 dots at maximum. The HX8369-A00 can be operated in low-voltage condition for the interface and integrated internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage follower circuit for liquid crystal driver. In addition, The HX8369-A00 also supports various functions to reduce the power consumption of a LCD system via software control. The HX8369-A00 supports several interface modes, including MPU DBI Type A/Type B interface mode, RGB DBI Type C interface mode. The interface mode is selected by the external hardware pins BS3~0. The HX8369-A00 is suitable for any small portable battery-driven and long-term driving products, such as small PDAs, digital cellular phones and bi-directional pagers. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.10October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 2. Features 2.1 Display Single chip solution for a WVGA GIP (Gate In Panel) type TFT LCD display Resolution: 480RGB x 864 480RGB x 854 480RGB x 800 480RGB x 640 480RGB x 720 360RGB x 640 Display color modes Full color mode: 16.7M colours (24-bit 8(R):8(G):8(B)) Reduce color mode: 262k colours (18-bit 6(R):6(G):6(B)) 65k colours (16-bit 5(R):6(G):5(B)) 8 colors (Idle mode on): 8 colors (3-bit binary mode) 2.2 Display module Support 1440 source channel outputs Internal level shifter for GIP gate control Supports 1-dot / 2-dot / column / Zig-Zag inversion Gamma correction (1 preset gamma curve) On module VCOM control (-2 to 0V common electrode output voltage range) On module DC/DC converter VSP=4.7 to 5.7V VSN=-5.7 to -4.7V Positive source output voltage level: VSPR=3.5V to 5V Negative source output voltage level: VSNR=-5V to -3.5V Positive gate driver output voltage level: VGH=+9V to +20V Negative gate driver output voltage level: VGL=-6V to -13.5V GIP most negative reference voltage: LVGL=VGL –VDD3 VCOM=-2.0V to 0V, a step=16mV Frame memory area 480 (H) x 864 (V) x 24-bit Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.11October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 2.3 Display / Control interface Display interface types supported MPU mode DBI Type B (80 System) interface (16- / 18- / 24-bit bus) DBI Type A (68 System) interface (16- / 18- bit bus) DBI Type C (Serial data transfer interface) interface RGB mode 16 bit/pixel R(5), G(6), B(5) 18 bit/pixel R(6), G(6), B(6) 24 bit/pixel R(8), G(8), B(8) 2.4 Input power I/O and interface power supply (VDD1): 1.65V to 3.3V Analog power supply (VDD2): 2.3V to 4.8V Logic power supply (VDD3): 2.3V to 4.8V DSI power supply (DSI_VCC): 1.65V to 3.3V MDDI power supply (DSI_VCC): 2.3V to 3.3V OTP programming voltage (VPP): 7.5V ± 0.2V 2.5 Miscellaneous Partial display mode Software programmable color depth mode Oscillator for display clock generation Low power consumption, suitable for battery operated systems CMOS compatible inputs Proprietary multi phase driving for lower power consumption GAS function for preventing image sticking when abnormal power off Optimized layout for COG assembly Temperature range: -40 to +85 °C HBM ESD (Human Body Mode)>2KV, MM(Machine Mode)>±200V and Latch up>±200mA Support inversion mode DC/DC converter for source Support DC COM driving VCOM voltage generator On-chip OTP program voltage generator OTP memory to store initialization register settings 3 times MTP for VCOM setting ,ID setting Support CABC (Content Adaptive Brightness Control) function Support DGC (Digital Gamma Correction) function Temperature Sensor Control Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.12October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 3. Device Overview 3.1 Block diagram Note: MPU I/F display data path RGB I/F display data path PWM_OUT S1 ~ S1441 VDD1 VDD2 VDD3 OTP VPP BS3-0 CSX RDX_E WRX_DCX DCX_SCL DB23~0 ABC function 4 MPU I/F 24-bit 18-bit 16-bit 9-bit 8-bit 24 SDI SDO DSI_LDO_ENB/ MDDI_LDO_ENB DSI_CLKP (MDDI_STBP) / DSI_CLKN (MDDI_STBN) DSI_D0P (MDDI_D1P)/ DSI_D0N (MDDI_D1N) DSI_D1P (MDDI_D0P)/ DSI_D1N (MDDI_D0N) DSI_VCC / MDDI_VCC DSI_VSS/ MDDI_VSS OSC Internal register D/A Converter circuit SPI I/F 3-wire VSYNC_TE HSYNC PCLK DE RESX RGB I/F 16-bit 18-bit 24-bit Source driver GRAM control 24-bit display data Digital Gamma Correction Data Latch GRAM V0~255 Grayscale voltage generator 24-bit display data Mode selection VGS CABC function 2 Gamma adjusting circuit 2 2 DSI / MDDI Interface VTESTOUTP / VTESTOUTN TE Timing Control 2 RC OSC Gate Control Unit Temperature sensor control Generator Timing GOUTL_1~ GOUTL_10 20 GOUTR1~ GOUTR_10 TEST2~1 VCI PFM DC / DC Converter Voltage reference VCOM Cricuit VSSA VSSAC DSI_LDO VDDD VDDDN VREF VSPR VSNR V COM V COM R LVGL C41AP / C41AN V GL V GH C24AP / C24AN C23AP / C23AN C22AP / C22AN C21AP / C21AN VSP VSN VCSW2 VCSW1 VSSD Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.13October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 3.2 Pin description Host interface pins Signals I/O Pin no. Connected with Description Select the MPU interface mode as listed below: BS3 I 4 CSX I 1 RESX I 1 RDX_E I 1 DCX_SCL I 1 WRX_DCX I 1 DB23~0 I/O 24 VSSD / VDD1 BS1 BS0 MPU interface mode DB pins Display mode DB23-DB8: Unused, Type 1 DB7-DB0: Data DB23-DB9:Unused, 0 0 0 1 Type 1 DB8-DB0: Data DB23-DB16: Unused, 0 0 1 0 Type 1 DB15-DB0: Data DB23-DB18: Unused, 0 0 1 1 Type 1 DB17-DB0: Data DB23-DB8: Unused 0 1 0 0 DBI TYPE-B 8-bit Type 1 DB7-DB0: Data DB23-DB9:Unused, 0 1 0 1 DBI TYPE-B 9-bit Type 1 DB8-DB0: Data DB23-DB16: Unused, 0 1 1 0 DBI TYPE-B 16-bit Type 1 DB15-DB0: Data DB23-DB18: Unused, 0 1 1 1 DBI TYPE-B 18-bit Type 1 DB17-DB0: Data 1 0 0 0 1 0 0 1 1 0 1 0 DBI TYPE-B 24-bit DB23-DB0: Data Type 1 1 1 0 0 DPI/DBI TYPE-C SDI/SDO, 1 1 0 1 Type 3 Option 1 DB23-DB0 DPI/DBI TYPE-C SDI/SDO, 1 1 1 0 Type 3 Option 2 DB23-DB0 DPI/DBI TYPE-C SDI/SDO, 1 1 1 1 Type 3 Option 3 DB23-DB0 Pixel format (RGB565 / RGB666 / RGB888) is selected by DCS command (0x3Ah) Note 1: 3-wire serial Interface only active on MDDI / Hibernation mode. Must be connected to VSSD or VDD1. 0 BS3 ~ BS0 BS2 0 0 0 DBI TYPE-A 8-bit (CLK-E) DBI TYPE-A 9-bit (CLK-E) DBI TYPE-A 16-bit (CLK-E) DBI TYPE-A 18-bit (CLK-E) Chip select signal. Low: chip can be accessed; MPU High: chip cannot be accessed. If this pin is not used, please connect it to VSSD or VDD1. MPU or Reset pin. Setting either pin low initializes the LSI. Must be reset after reset circuit power is supplied (Must be connected to VSSD or VDD1). DBI Type-A: 0: Read/Write disable, 1: Read / Write enable. MPU DBI Type-B: Serves as a read signal and read data at the low level. If not use, let it open or connected to VDD1. DBI Type-A/B: Data / Command Selection pin MPU DBI Type-C: it servers as SCL (Serial Clock) If not use, let it open or connected to VDD1. DBI Type-B mode: Serves as a write signal and write data at the low level. MPU DBI Type-A mode: 0: Read/Write disable, 1: Read / Write enable. If not use, let it open or connected to VDD1. DBI type interface: Data bus Used Unused 8-bit bus DB7-0 DB23-8 9-bit bus DB8-0 DB23-9 16-bit bus DB15-0 DB23-16 18-bit bus DB17-0 DB23-18 24-bit bus DB23-0 DPI type interface: MPU Data bus Used Unused DB21-17, DB23-22, 16-bit bus DB13-8, DB16-14, DB5-1 DB7-6, DB0 DB21-16, DB23-22, 18-bit bus DB13-8, DB15-14, DB5-0 DB7-6 24-bit bus DB23-0 Let the unused pins open for each mode. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.14October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 SDO SDI O I 1 1 MPU MPU Serial data output. Let it to open in MPU interface mode. Serial data input pin in serial interface operation. Clock input and RGB interface HSYNC I 1 MPU DE I 1 MPU VSYNC I 1 MPU PCLK I 1 MPU Line synchronizing signal. Must be connected to VSSD or VDD1 if not used. A data enable signal in RGB I/F mode. Has to be fixed to VSSD level in MPU interface mode. Serves VS signal pin on RGB interface. (Input pad). Must be connected to VSSD or VDD1 if not used. Dot clock signal. Must be connected to VSSD or VDD1 if not used. Source driver output pins S1 to S1441 O 1441 LCD TE O 1 MPU Output voltages applied to the liquid crystal. RGB resolution Source channels 360RGB S1 ~ S540, S901 ~ S1440 480RGB S1 to S1440 480RGB+Z inversion S1 to S1441 Serves TE (Tearing Effect ) pin on MPU interface. GIP control singal and bias voltage CGOUT1_L CGOUT2_L CGOUT3_L CGOUT4_L CGOUT5_L CGOUT6_L CGOUT7_L CGOUT8_L CGOUT9_L CGOUT10_L CGOUT1_R CGOUT2_R CGOUT3_R CGOUT4_R CGOUT5_R CGOUT6_R CGOUT7_R CGOUT8_R CGOUT9_R CGOUT10_R O 14 GIP Signals for right side GIP on panel view (Left side in IC bump view), Unused pins should be left open. O 14 GIP Signals for Right side GIP on panel view (Right side in IC bump view), Unused pins should be left open. O VBIAS Power supply pins 2 GIP Bias voltage for some special GIP circuits. If not used, leave this pin open. PCCS0 ~ PCCS1 I Select the VSP/VSN bumping method as listed below: PCCS1 PCCS0 Driving mode 0 0 Setting invalid 0 1 Setting invalid 1 0 PFM one Inductor Mode (Type C) 1 1 Charge Bump Mode(Use HX5186-A) 2 VSSD / VDD3 A power supply for the I/O circuit. VDD1=1.65 to 3.3V A power supply for the analog power. VDD2=2.3 to 4.8V VDD2 input level should be same as VDD3 input level to avoid the level-mismatching at internal level shifter circuit. Must be connected to VSSD or VDD3. VDD1 I 5 Power supply VDD2 I 6 Power supply VDD3 I 6 VSSA P 6 VSSAC P 2 VSSD P 16 VPP I 2 Power supply Power supply Power supply Power supply Power supply A power supply for the logic power, DC/DC converter VDD3=2.3 to 4.8V. Analoge ground. VSSA=0V. When using the COG method, connect to VSSD on the FPC to prevent noise. Analoge ground. Must connect to VSSA on the FPC. Ground for the internal logic. VSSD=0V. When using the COG method, connect to VSSA on the FPC to prevent noise. External high voltage pin used in OTP mode and operates at 7.5V. If not used, let it open. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.15October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Output Pins of Power and reference voltage Stabilizing capacitor Stabilizing capacitor VSP VSN Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Input voltage from the set-up circuit (4.7V to 5.5V). it is generated from VDD3. Input voltage from the set-up circuit (-4.7V to -5.5V). it is generated from VDD3. Positive boosting reference voltage input. Negative boosting reference voltage input. VSP I 7 VSN I 6 VSPC VSNC I I 1 1 VSPR O 2 VSNR O 2 VDDD O 19 VDDDN O 5 VREF O 2 VGH O 10 VGL O 10 Stabilizing capacitor LVGL O 15 Stabilizing capacitor VCOM O 14 Stabilizing capacitor VCOMR I 1 Input Reference voltage from internal band gap circuit. The tolerance of VREF voltage is ± 3 ﹪.(1.8V fixed) Output voltage from the step-up circuit, it is generated from VSP and VSN. Connect to a stabilizing capacitor between VSSA and VGH. Output voltage from the step-up circuit, it is generated from VSP and VSN. Connect to a stabilizing capacitor between VSSA and VGL. Place a schottkey barrier diode between VSSA and VGL. Most negative voltage for some special GIP circuits. If not used, connect to VGL. The power supply of common voltage in DC com driving. The voltage range is set between -2V to 0V. It must be connected a stabilizing capacitor 2.2u to VSSD. The input pad of external VCOM voltage. C21AP, C21AN C22AP, C22AN I/O 16 Step-up Capacitor Connect to the step-up capacitors according to the DC/DC pumping factor by pumping the VGL voltage. C23AP, C23AN C24AP, C24AN I/O 16 Step-up Capacitor Connect to the step-up capacitors according to the DC/DC pumping factor by pumping the VGH voltage. C41AP, C41AN I/O 6 Step-up Capacitor Connect to the step-up capacitors according to the DC/DC pumping factor by pumping the LVGL voltage. VCSW1 O 4 - VCSW2 O 4 - Positive regulated voltage output (3.5V to VSP - 0.5) Positive regulated voltage output (-3.5V to VSN + 0.5) Internal logic voltage output Internal logic voltage output (-2.5V fixed) DC/DC pumping Boosting control output1, it needs to connect to the gate pin of NMOS on external DC/DC converter circuit. (0 to VDD3) Boosting control output2, it needs to connect to the gate pin of PMOS on external DC/DC converter circuit. (0 to VDD3) CABC & ABC & Ambient light sensor CABC_PWM_OUT Backlight on/fff control pin. If use CABC function, the pin can connect to external LED driver IC. The output voltage range=0 to VDD1. O 1 - I 1 Open TEST1 I 1 Open TEST2 I 1 Open VTESTOUTP O 1 Open VTESTOUTN O 1 Open - 2 Open Dummy pads. Available for measuring the COG contact resistance. They are short-circuited within the chip. - 17 3 Open Open Not used. Let it open. Dummy pad. Connect to grand internally. Test Pins OSC DUMMYR1 DUMMYR2 DUMMY17~1 IOGNDDUM Oscillator input for test purpose. If not used, please let it open or connected to VSSD.(weak pull low) A test pin. This pin is by internal logic function test.This pin can output on FPC. If not used, let it open or connected to VSSD.(weak pull low) A test pin. This pin is by internal logic function test.This pin can output on FPC. If not used, let it open or connected to VSSD.(weak pull low) A test pin. Disconnect it. This pin will output Gamma voltage. This pin can output on FPC. A test pin. Disconnect it. This pin will output Gamma voltage. This pin can output on FPC. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.16October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 MIPI-DSI interface parts DSI_D0P, DSI_D0N DSI_CP, DSI_CN DSI_D1P, DSI_D1N DSI_VCC I/O 6 DSI Host MIPI-DSI Data differential signal input pins. (Data lane 0) I 6 DSI Host MIPI-DSI CLOCK differential signal input pins. I 6 DSI Host MIPI-DSI Data differential signal input pins. (Data lane 1) P 5 DSI_VSS P 9 DSI_LDO DSI_LDO_ENB O I 2 1 MDDI_STBP, MDDI _STBN - 6 MDDI _D0P, MDDI _D0N - 6 MDDI _D1P, MDDI _D1N - 6 MDDI _VCC P 5 MDDI _VSS P 9 High Speed Interface Host High Speed Interface Host High Speed Interface Host Power Supply or Capacitor Ground MDDI _LDO O 2 Capacitor MDDI_LDO_ENB I 1 Input Power Supply Power supply for the MIPI DSI analog power.DSI_VCC=1.65V to 3.3V MIPI DSI analogy ground. DSI_VSS=0V. When using the COG method, Ground connect to VSSA on the FPC to prevent noise. Capacitor If not used, please open these pins. Input It must be connected to VDD1 or VSSD. (latch type) MDDI interface parts High Speed Interface clock differential signal input pins. If not used, please let it connected to VSSD. High Speed Interface Data differential signal input pins (Data lane 0). If not used, please let it connected to VSSD. High Speed Interface Data differential signal input pins. (Data lane 1) If not used, please let it connected to VSSD. High Speed Interface I/O power supply pin, 2.3V to 3.3V. High Speed Interface I/O ground pin. High Speed Interface regulator output pin. If not used, please open these pins. It must be connected to VDD1 or VSSD. (latch type) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.17October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 3.3 Pin assignment (A1) DUMMY17 S1441 S1440 S1439 S1438 NO.1 Chip Size : 22430 x 1701 um (Include scribe line = 80 um) DUMMY1 CGOUT1_L CGOUT2_L CGOUT3_L CGOUT4_L CGOUT5_L CGOUT5_L CGOUT6_L CGOUT6_L CGOUT7_L CGOUT7_L CGOUT8_L CGOUT8_L CGOUT9_L CGOUT10_L VGL VGL VGL VBIAS LVGL LVGL LVGL DUMMY2 VCOM VCOM VCOM DUMMY3 DUMMYR1 DUMMYR2 DUMMY4 VGL VGL VGL LVGL LVGL LVGL LVGL LVGL VCOM VCOM VCOM VCOM C41AP C41AP C41AP C41AN C41AN C41AN VGH VGH VGH VGH VGH VGH C21AP C21AP C21AP C21AP C21AN C21AN C21AN C21AN C23AP C23AP C23AP C23AP C23AN C23AN C23AN C23AN C22AP C22AP C22AP C22AP C22AN C22AN C22AN C22AN C24AP C24AP C24AP C24AP C24AN C24AN C24AN C24AN VPP VPP VDDDN VDDDN VDDDN VDDDN VDDDN VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VREF VREF VSSA VSSA VSSA VSSA VSSA VSSA VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VDDD VDDD VDDD VDDD VDDD VDDD VDD1 VDD1 VDD1 VDD1 VDD1 CABC_PWM_OUT TE TEST1 TEST2 BS0 BS1 BS2 BS3 RESX IOGNDDUM DB23/TS7 DB22/TS6 DB21/TS5 DB20/TS4 DB19/TS3 DB18/TS2 DB17/TS1 DB16/TS0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 IOGNDDUM RDX_E WRX_DCX DCX_SCL CSX IOGNDDUM SDI SDO VSYNC HSYNC DE PCLK DSI_LDO_ENB/MDDI_LDO_ENB DUMMY5 OSC PCCS0 PCCS1 DSI_VSS/MDDI_VSS DSI_D0N/MDDI_D1N DSI_D0N/MDDI_D1N DSI_D0N/MDDI_D1N DSI_D0P/MDDI_D1P DSI_D0P/MDDI_D1P DSI_D0P/MDDI_D1P DSI_VSS/MDDI_VSS DSI_CLKN/MDDI_STBN DSI_CLKN/MDDI_STBN DSI_CLKN/MDDI_STBN DSI_CLKP/MDDI_STBP DSI_CLKP/MDDI_STBP DSI_CLKP/MDDI_STBP DSI_VSS/MDDI_VSS DSI_D1N/MDDI_D0N DSI_D1N/MDDI_D0N DSI_D1N/MDDI_D0N DSI_D1P/MDDI_D0P DSI_D1P/MDDI_D0P DSI_D1P/MDDI_D0P DSI_VSS/MDDI_VSS DSI_LDO/MDDI_LDO DSI_LDO/MDDI_LDO DSI_VCC/MDDI_VCC DSI_VCC/MDDI_VCC DSI_VCC/MDDI_VCC DSI_VCC/MDDI_VCC DSI_VCC/MDDI_VCC DSI_VSS/MDDI_VSS DSI_VSS/MDDI_VSS DSI_VSS/MDDI_VSS DSI_VSS/MDDI_VSS DSI_VSS/MDDI_VSS VSSAC VSSAC VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VSPR VSPR VSPC VSP VSP VSP VSP VSP VSP VSP VCSW1 VCSW1 VCSW1 VCSW1 VCSW2 VCSW2 VCSW2 VCSW2 VSNR VSNR VSNC VSN VSN VSN VSN VSN VSN VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VGH VGH VGH VGH VCOM VCOM VCOM VCOM LVGL LVGL LVGL LVGL VTESTOUTP DUMMY6 VCOMR VTESTOUTN VCOM VCOM VCOM DUMMY7 DUMMY8 LVGL LVGL LVGL VBIAS VGL VGL VGL VGL CGOUT10_R CGOUT9_R CGOUT8_R CGOUT8_R CGOUT7_R CGOUT7_R CGOUT6_R CGOUT6_R CGOUT5_R CGOUT5_R CGOUT4_R CGOUT3_R CGOUT2_R NO.312 CGOUT1_R DUMMY9 DUMMY10 NO.1760 Chip thickness: 250 um ± 25 um Pad Location:PAD Center Coordinate Origin: Chip Center Au Bump Size: 1. 50 um x 80 um Input: No.1 ~ No.312 2. 15 um x 95 um Staggered LCD output side No.313 ~ No.1760 The chip size includes the core size seal ring size, and scribe line size Au bump pitch: Refer to Pad Coordinate . Au bump height : 12 um ± 3 um Numbers in the figure corresponds to pad coordinate numbers . Top View BUMP Chip Face Up (Bump View) HX8369-A00 Pin Assignment S722 S721 DUMMY14 DUMMY13 DUMMY12 DUMMY11 S720 S719 Y NO.1033 X S2 S2 S1 DUMMY16 DUMMY15 NO.313 (A2) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.18October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 3.4 PAD coordinates No. Name X Y No. Name X Y No. Name X Y No. 1 DUMMY1 -10885 -672 61 C21AN -6685 -672 121 VDDD -2485 -672 181 2 CGOUT1_L -10815 -672 62 C21AN -6615 -672 122 VDD1 -2415 -672 182 3 CGOUT2_L -10745 -672 63 C23AP -6545 -672 123 VDD1 -2345 -672 183 4 CGOUT3_L -10675 -672 64 C23AP -6475 -672 124 VDD1 -2275 -672 184 5 CGOUT4_L -10605 -672 65 C23AP -6405 -672 125 VDD1 -2205 -672 185 6 CGOUT5_L -10535 -672 66 C23AP -6335 -672 126 VDD1 -2135 -672 186 7 CGOUT5_L -10465 -672 67 C23AN -6265 -672 127 CABC_PWM_OUT -2065 -672 187 8 CGOUT6_L -10395 -672 68 C23AN -6195 -672 128 TE -1995 -672 188 9 CGOUT6_L -10325 -672 69 C23AN -6125 -672 129 TEST1 -1925 -672 189 10 CGOUT7_L -10255 -672 70 C23AN -6055 -672 130 TEST2 -1855 -672 190 11 CGOUT7_L -10185 -672 71 C22AP -5985 -672 131 BS0 -1785 -672 191 12 CGOUT8_L -10115 -672 72 C22AP -5915 -672 132 BS1 -1715 -672 192 13 CGOUT8_L -10045 -672 73 C22AP -5845 -672 133 BS2 -1645 -672 193 14 CGOUT9_L -9975 -672 74 C22AP -5775 -672 134 BS3 -1575 -672 194 15 CGOUT10_L -9905 -672 75 C22AN -5705 -672 135 RESX -1505 -672 195 16 VGL -9835 -672 76 C22AN -5635 -672 136 IOGNDDUM -1435 -672 196 17 VGL -9765 -672 77 C22AN -5565 -672 137 DB23 -1365 -672 197 18 VGL -9695 -672 78 C22AN -5495 -672 138 DB22 -1295 -672 198 19 VBIAS -9625 -672 79 C24AP -5425 -672 139 DB21 -1225 -672 199 20 LVGL -9555 -672 80 C24AP -5355 -672 140 DB20 -1155 -672 200 21 LVGL -9485 -672 81 C24AP -5285 -672 141 DB19 -1085 -672 201 22 LVGL -9415 -672 82 C24AP -5215 -672 142 DB18 -1015 -672 202 23 DUMMY2 -9345 -672 83 C24AN -5145 -672 143 DB17 -945 -672 203 24 VCOM -9275 -672 84 C24AN -5075 -672 144 DB16 -875 -672 204 25 VCOM -9205 -672 85 C24AN -5005 -672 145 DB15 -805 -672 205 26 VCOM -9135 -672 86 C24AN -4935 -672 146 DB14 -735 -672 206 27 DUMMY3 -9065 -672 87 VPP -4865 -672 147 DB13 -665 -672 207 28 DUMMYR1 -8995 -672 88 VPP -4795 -672 148 DB12 -595 -672 208 29 DUMMYR2 -8925 -672 89 VDDDN -4725 -672 149 DB11 -525 -672 209 30 DUMMY4 -8855 -672 90 VDDDN -4655 -672 150 DB10 -455 -672 210 31 VGL -8785 -672 91 VDDDN -4585 -672 151 DB9 -385 -672 211 32 33 34 35 36 37 38 39 VGL VGL LVGL LVGL LVGL LVGL LVGL VCOM -8715 -8645 -8575 -8505 -8435 -8365 -8295 -8225 -672 -672 -672 -672 -672 -672 -672 -672 92 93 94 95 96 97 98 99 VDDDN VDDDN VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 -4515 -4445 -4375 -4305 -4235 -4165 -4095 -4025 -672 -672 -672 -672 -672 -672 -672 -672 152 153 154 155 156 157 158 159 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 -315 -245 -175 -105 -35 35 105 175 -672 -672 -672 -672 -672 -672 -672 -672 212 213 214 215 216 217 218 219 Name DSI_D0N / MDDI_D1N DSI_D0P / MDDI_D1P DSI_D0P / MDDI_D1P DSI_D0P / MDDI_D1P DSI_VSS / MDDI_VSS DSI_CN / MDDI_STBN DSI_CN / MDDI_STBN DSI_CN / MDDI_STBN DSI_CP / MDDI_STBP DSI_CP / MDDI_STBP DSI_CP / MDDI_STBP DSI_VSS / MDDI_VSS DSI_D1N / MDDI_D0N DSI_D1N / MDDI_D0N DSI_D1N / MDDI_D0N DSI_D1P / MDDI_D0P DSI_D1P / MDDI_D0P DSI_D1P / MDDI_D0P DSI_VSS / MDDI_VSS DSI_LDO / MDDI_LDO DSI_LDO / MDDI_LDO DSI_VCC / MDDI_VCC DSI_VCC / MDDI_VCC DSI_VCC / MDDI_VCC DSI_VCC / MDDI_VCC DSI_VCC / MDDI_VCC DSI_VSS / MDDI_VSS DSI_VSS / MDDI_VSS DSI_VSS / MDDI_VSS DSI_VSS / MDDI_VSS DSI_VSS / MDDI_VSS VSSAC VSSAC VSSD VSSD VSSD VSSD VSSD VSSD 40 41 42 VCOM VCOM VCOM -8155 -8085 -8015 -672 -672 -672 100 101 102 VREF VREF VSSA -3955 -3885 -3815 -672 -672 -672 160 161 162 DB0 IOGNDDUM RDX_E 245 315 385 -672 -672 -672 220 221 222 43 44 C41AP C41AP -7945 -7875 -672 -672 103 104 VSSA VSSA -3745 -3675 -672 -672 163 164 WRX_DCX DCX_SCL 455 525 -672 -672 45 46 47 48 49 C41AP C41AN C41AN C41AN VGH -7805 -7735 -7665 -7595 -7525 -672 -672 -672 -672 -672 105 106 107 108 109 VSSA VSSA VSSA VSSD VSSD -3605 -3535 -3465 -3395 -3325 -672 -672 -672 -672 -672 165 166 167 168 169 CSX IOGNDDUM SDI SDO VSYNC 595 665 735 805 875 50 51 52 VGH VGH VGH -7455 -7385 -7315 -672 -672 -672 110 111 112 VSSD VSSD VSSD -3255 -3185 -3115 -672 -672 -672 170 171 172 HSYNC DE PCLK 53 VGH -7245 -672 113 VSSD -3045 -672 173 54 55 VGH C21AP -7175 -7105 -672 -672 114 115 VSSD VSSD -2975 -2905 -672 -672 174 175 56 57 C21AP C21AP -7035 -6965 -672 -672 116 117 VDDD VDDD -2835 -2765 -672 -672 176 177 58 C21AP -6895 -672 118 VDDD -2695 -672 178 59 C21AN -6825 -672 119 VDDD -2625 -672 179 60 C21AN -6755 -672 120 VDDD -2555 -672 180 X Y 1715 -672 1785 -672 1855 -672 1925 -672 1995 -672 2065 -672 2135 -672 2205 -672 2275 -672 2345 -672 2415 -672 2485 -672 2555 -672 2625 -672 2695 -672 2765 -672 2835 -672 2905 -672 2975 -672 3045 -672 3115 -672 3185 -672 3255 -672 3325 -672 3395 -672 3465 -672 3535 -672 3605 -672 3675 -672 3745 -672 3815 -672 3885 3955 4025 4095 4165 4235 4305 4375 -672 -672 -672 -672 -672 -672 -672 -672 VSSD VSSD VDDD 4445 4515 4585 -672 -672 -672 223 224 VDDD VDDD 4655 4725 -672 -672 -672 -672 -672 -672 -672 225 226 227 228 229 VDDD VDDD VDDD VDDD VDDD 4795 4865 4935 5005 5075 -672 -672 -672 -672 -672 945 1015 1085 -672 -672 -672 230 231 232 VDDD VDDD VDDD 5145 5215 5285 -672 -672 -672 DSI_LDO_ENB 1155 -672 233 VDDD 5355 -672 DUMMY5 OSC 1225 1295 -672 -672 234 235 VDDD VSPR 5425 5495 -672 -672 PCCS0 PCCS1 DSI_VSS / MDDI_VSS DSI_D0N / MDDI_D1N DSI_D0N / MDDI_D1N 1365 1435 -672 -672 236 237 VSPR VSPC 5565 5635 -672 -672 1505 -672 238 VSP 5705 -672 1575 -672 239 VSP 5775 -672 1645 -672 240 VSP 5845 -672 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.19October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. Name 241 242 243 VSP VSP VSP X 5915 5985 6055 Y -672 -672 -672 No. 301 302 303 Name CGOUT7_R CGOUT7_R CGOUT6_R X 10115 10185 10255 Y -672 -672 -672 No. 361 362 363 Name S47 S48 S49 X 10230 10215 10200 Y 500 613 500 No. 421 422 423 Name S107 S108 S109 X 9330 9315 9300 Y 500 613 500 244 245 246 VSP VCSW1 VCSW1 6125 6195 6265 -672 -672 -672 304 305 306 CGOUT6_R CGOUT5_R CGOUT5_R 10325 10395 10465 -672 -672 -672 364 365 366 S50 S51 S52 10185 10170 10155 613 500 613 424 425 426 S110 S111 S112 9285 9270 9255 613 500 613 247 248 VCSW1 VCSW1 6335 6405 -672 -672 307 308 CGOUT4_R CGOUT3_R 10535 10605 -672 -672 367 368 S53 S54 10140 10125 500 613 427 428 S113 S114 9240 9225 500 613 249 VCSW2 6475 -672 309 CGOUT2_R 10675 -672 369 S55 10110 500 429 S115 9210 500 250 VCSW2 6545 -672 310 CGOUT1_R 10745 -672 370 S56 10095 613 430 S116 9195 613 251 252 253 VCSW2 VCSW2 VSNR 6615 6685 6755 -672 -672 -672 311 312 313 DUMMY9 DUMMY10 DUMMY15 10815 10885 10950 -672 -672 500 371 372 373 S57 S58 S59 10080 10065 10050 500 613 500 431 432 433 S117 S118 S119 9180 9165 9150 500 613 500 254 255 VSNR VSNC 6825 6895 -672 -672 314 315 DUMMY16 S1 10935 10920 613 500 374 375 S60 S61 10035 10020 613 500 434 435 S120 S121 9135 9120 613 500 256 257 258 VSN VSN VSN 6965 7035 7105 -672 -672 -672 316 317 318 S2 S3 S4 10905 10890 10875 613 500 613 376 377 378 S62 S63 S64 10005 9990 9975 613 500 613 436 437 438 S122 S123 S124 9105 9090 9075 613 500 613 259 260 VSN VSN 7175 7245 -672 -672 319 320 S5 S6 10860 10845 500 613 379 380 S65 S66 9960 9945 500 613 439 440 S125 S126 9060 9045 500 613 261 262 VSN VDD3 7315 7385 -672 -672 321 322 S7 S8 10830 10815 500 613 381 382 S67 S68 9930 9915 500 613 441 442 S127 S128 9030 9015 500 613 263 VDD3 7455 -672 323 S9 10800 500 383 S69 9900 500 443 S129 9000 500 264 265 VDD3 VDD3 7525 7595 -672 -672 324 325 S10 S11 10785 10770 613 500 384 385 S70 S71 9885 9870 613 500 444 445 S130 S131 8985 8970 613 500 266 267 VDD3 VDD3 7665 7735 -672 -672 326 327 S12 S13 10755 10740 613 500 386 387 S72 S73 9855 9840 613 500 446 447 S132 S133 8955 8940 613 500 268 VGH 7805 -672 328 S14 10725 613 388 S74 9825 613 448 S134 8925 613 269 270 VGH VGH 7875 7945 -672 -672 329 330 S15 S16 10710 10695 500 613 389 390 S75 S76 9810 9795 500 613 449 450 S135 S136 8910 8895 500 613 271 272 VGH VCOM 8015 8085 -672 -672 331 332 S17 S18 10680 10665 500 613 391 392 S77 S78 9780 9765 500 613 451 452 S137 S138 8880 8865 500 613 273 274 VCOM VCOM 8155 8225 -672 -672 333 334 S19 S20 10650 10635 500 613 393 394 S79 S80 9750 9735 500 613 453 454 S139 S140 8850 8835 500 613 275 VCOM 8295 -672 335 S21 10620 500 395 S81 9720 500 455 S141 8820 500 276 277 LVGL LVGL 8365 8435 -672 -672 336 337 S22 S23 10605 10590 613 500 396 397 S82 S83 9705 9690 613 500 456 457 S142 S143 8805 8790 613 500 278 279 LVGL LVGL 8505 8575 -672 -672 338 339 S24 S25 10575 10560 613 500 398 399 S84 S85 9675 9660 613 500 458 459 S144 S145 8775 8760 613 500 280 281 282 VTESTOUTP DUMMY6 VCOMR 8645 8715 8785 -672 -672 -672 340 341 342 S26 S27 S28 10545 10530 10515 613 500 613 400 401 402 S86 S87 S88 9645 9630 9615 613 500 613 460 461 462 S146 S147 S148 8745 8730 8715 613 500 613 283 284 VTESTOUTN VCOM 8855 8925 -672 -672 343 344 S29 S30 10500 10485 500 613 403 404 S89 S90 9600 9585 500 613 463 464 S149 S150 8700 8685 500 613 285 286 VCOM VCOM 8995 9065 -672 -672 345 346 S31 S32 10470 10455 500 613 405 406 S91 S92 9570 9555 500 613 465 466 S151 S152 8670 8655 500 613 287 288 DUMMY7 DUMMY8 9135 9205 -672 -672 347 348 S33 S34 10440 10425 500 613 407 408 S93 S94 9540 9525 500 613 467 468 S153 S154 8640 8625 500 613 289 LVGL 9275 -672 349 S35 10410 500 409 S95 9510 500 469 S155 8610 500 290 291 LVGL LVGL 9345 9415 -672 -672 350 351 S36 S37 10395 10380 613 500 410 411 S96 S97 9495 9480 613 500 470 471 S156 S157 8595 8580 613 500 292 293 294 VBIAS VGL VGL 9485 9555 9625 -672 -672 -672 352 353 354 S38 S39 S40 10365 10350 10335 613 500 613 412 413 414 S98 S99 S100 9465 9450 9435 613 500 613 472 473 474 S158 S159 S160 8565 8550 8535 613 500 613 295 296 VGL VGL 9695 9765 -672 -672 355 356 S41 S42 10320 10305 500 613 415 416 S101 S102 9420 9405 500 613 475 476 S161 S162 8520 8505 500 613 297 CGOUT10_R 9835 -672 357 S43 10290 500 417 S103 9390 500 477 S163 8490 500 298 CGOUT9_R 9905 -672 358 S44 10275 613 418 S104 9375 613 478 S164 8475 613 299 300 CGOUT8_R CGOUT8_R 9975 10045 -672 -672 359 360 S45 S46 10260 10245 500 613 419 420 S105 S106 9360 9345 500 613 479 480 S165 S166 8460 8445 500 613 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.20October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. 481 482 483 Name S167 S168 S169 X 8430 8415 8400 Y 500 613 500 No. 541 542 543 Name S227 S228 S229 X 7530 7515 7500 Y 500 613 500 No. 601 602 603 Name S287 S288 S289 X 6630 6615 6600 Y 500 613 500 No. 661 662 663 Name S347 S348 S349 X 5730 5715 5700 Y 500 613 500 484 485 486 S170 S171 S172 8385 8370 8355 613 500 613 544 545 546 S230 S231 S232 7485 7470 7455 613 500 613 604 605 606 S290 S291 S292 6585 6570 6555 613 500 613 664 665 666 S350 S351 S352 5685 5670 5655 613 500 613 487 488 S173 S174 8340 8325 500 613 547 548 S233 S234 7440 7425 500 613 607 608 S293 S294 6540 6525 500 613 667 668 S353 S354 5640 5625 500 613 489 S175 8310 500 549 S235 7410 500 609 S295 6510 500 669 S355 5610 500 490 S176 8295 613 550 S236 7395 613 610 S296 6495 613 670 S356 5595 613 491 492 493 S177 S178 S179 8280 8265 8250 500 613 500 551 552 553 S237 S238 S239 7380 7365 7350 500 613 500 611 612 613 S297 S298 S299 6480 6465 6450 500 613 500 671 672 673 S357 S358 S359 5580 5565 5550 500 613 500 494 495 S180 S181 8235 8220 613 500 554 555 S240 S241 7335 7320 613 500 614 615 S300 S301 6435 6420 613 500 674 675 S360 S361 5535 5520 613 500 496 497 498 S182 S183 S184 8205 8190 8175 613 500 613 556 557 558 S242 S243 S244 7305 7290 7275 613 500 613 616 617 618 S302 S303 S304 6405 6390 6375 613 500 613 676 677 678 S362 S363 S364 5505 5490 5475 613 500 613 499 500 S185 S186 8160 8145 500 613 559 560 S245 S246 7260 7245 500 613 619 620 S305 S306 6360 6345 500 613 679 680 S365 S366 5460 5445 500 613 501 502 S187 S188 8130 8115 500 613 561 562 S247 S248 7230 7215 500 613 621 622 S307 S308 6330 6315 500 613 681 682 S367 S368 5430 5415 500 613 503 S189 8100 500 563 S249 7200 500 623 S309 6300 500 683 S369 5400 500 504 505 S190 S191 8085 8070 613 500 564 565 S250 S251 7185 7170 613 500 624 625 S310 S311 6285 6270 613 500 684 685 S370 S371 5385 5370 613 500 506 507 S192 S193 8055 8040 613 500 566 567 S252 S253 7155 7140 613 500 626 627 S312 S313 6255 6240 613 500 686 687 S372 S373 5355 5340 613 500 508 S194 8025 613 568 S254 7125 613 628 S314 6225 613 688 S374 5325 613 509 510 S195 S196 8010 7995 500 613 569 570 S255 S256 7110 7095 500 613 629 630 S315 S316 6210 6195 500 613 689 690 S375 S376 5310 5295 500 613 511 512 S197 S198 7980 7965 500 613 571 572 S257 S258 7080 7065 500 613 631 632 S317 S318 6180 6165 500 613 691 692 S377 S378 5280 5265 500 613 513 514 S199 S200 7950 7935 500 613 573 574 S259 S260 7050 7035 500 613 633 634 S319 S320 6150 6135 500 613 693 694 S379 S380 5250 5235 500 613 515 S201 7920 500 575 S261 7020 500 635 S321 6120 500 695 S381 5220 500 516 517 S202 S203 7905 7890 613 500 576 577 S262 S263 7005 6990 613 500 636 637 S322 S323 6105 6090 613 500 696 697 S382 S383 5205 5190 613 500 518 519 S204 S205 7875 7860 613 500 578 579 S264 S265 6975 6960 613 500 638 639 S324 S325 6075 6060 613 500 698 699 S384 S385 5175 5160 613 500 520 521 522 S206 S207 S208 7845 7830 7815 613 500 613 580 581 582 S266 S267 S268 6945 6930 6915 613 500 613 640 641 642 S326 S327 S328 6045 6030 6015 613 500 613 700 701 702 S386 S387 S388 5145 5130 5115 613 500 613 523 524 S209 S210 7800 7785 500 613 583 584 S269 S270 6900 6885 500 613 643 644 S329 S330 6000 5985 500 613 703 704 S389 S390 5100 5085 500 613 525 526 S211 S212 7770 7755 500 613 585 586 S271 S272 6870 6855 500 613 645 646 S331 S332 5970 5955 500 613 705 706 S391 S392 5070 5055 500 613 527 528 S213 S214 7740 7725 500 613 587 588 S273 S274 6840 6825 500 613 647 648 S333 S334 5940 5925 500 613 707 708 S393 S394 5040 5025 500 613 529 S215 7710 500 589 S275 6810 500 649 S335 5910 500 709 S395 5010 500 530 531 S216 S217 7695 7680 613 500 590 591 S276 S277 6795 6780 613 500 650 651 S336 S337 5895 5880 613 500 710 711 S396 S397 4995 4980 613 500 532 533 534 S218 S219 S220 7665 7650 7635 613 500 613 592 593 594 S278 S279 S280 6765 6750 6735 613 500 613 652 653 654 S338 S339 S340 5865 5850 5835 613 500 613 712 713 714 S398 S399 S400 4965 4950 4935 613 500 613 535 536 S221 S222 7620 7605 500 613 595 596 S281 S282 6720 6705 500 613 655 656 S341 S342 5820 5805 500 613 715 716 S401 S402 4920 4905 500 613 537 S223 7590 500 597 S283 6690 500 657 S343 5790 500 717 S403 4890 500 538 S224 7575 613 598 S284 6675 613 658 S344 5775 613 718 S404 4875 613 539 540 S225 S226 7560 7545 500 613 599 600 S285 S286 6660 6645 500 613 659 660 S345 S346 5760 5745 500 613 719 720 S405 S406 4860 4845 500 613 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.21October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. 721 722 723 Name S407 S408 S409 X 4830 4815 4800 Y 500 613 500 No. 781 782 783 Name S467 S468 S469 X 3930 3915 3900 Y 500 613 500 No. 841 842 843 Name S527 S528 S529 X 3030 3015 3000 Y 500 613 500 No. 901 902 903 Name S587 S588 S589 X 2130 2115 2100 Y 500 613 500 724 725 726 S410 S411 S412 4785 4770 4755 613 500 613 784 785 786 S470 S471 S472 3885 3870 3855 613 500 613 844 845 846 S530 S531 S532 2985 2970 2955 613 500 613 904 905 906 S590 S591 S592 2085 2070 2055 613 500 613 727 728 S413 S414 4740 4725 500 613 787 788 S473 S474 3840 3825 500 613 847 848 S533 S534 2940 2925 500 613 907 908 S593 S594 2040 2025 500 613 729 S415 4710 500 789 S475 3810 500 849 S535 2910 500 909 S595 2010 500 730 S416 4695 613 790 S476 3795 613 850 S536 2895 613 910 S596 1995 613 731 732 733 S417 S418 S419 4680 4665 4650 500 613 500 791 792 793 S477 S478 S479 3780 3765 3750 500 613 500 851 852 853 S537 S538 S539 2880 2865 2850 500 613 500 911 912 913 S597 S598 S599 1980 1965 1950 500 613 500 734 735 S420 S421 4635 4620 613 500 794 795 S480 S481 3735 3720 613 500 854 855 S540 S541 2835 2820 613 500 914 915 S600 S601 1935 1920 613 500 736 737 738 S422 S423 S424 4605 4590 4575 613 500 613 796 797 798 S482 S483 S484 3705 3690 3675 613 500 613 856 857 858 S542 S543 S544 2805 2790 2775 613 500 613 916 917 918 S602 S603 S604 1905 1890 1875 613 500 613 739 740 S425 S426 4560 4545 500 613 799 800 S485 S486 3660 3645 500 613 859 860 S545 S546 2760 2745 500 613 919 920 S605 S606 1860 1845 500 613 741 742 S427 S428 4530 4515 500 613 801 802 S487 S488 3630 3615 500 613 861 862 S547 S548 2730 2715 500 613 921 922 S607 S608 1830 1815 500 613 743 S429 4500 500 803 S489 3600 500 863 S549 2700 500 923 S609 1800 500 744 745 S430 S431 4485 4470 613 500 804 805 S490 S491 3585 3570 613 500 864 865 S550 S551 2685 2670 613 500 924 925 S610 S611 1785 1770 613 500 746 747 S432 S433 4455 4440 613 500 806 807 S492 S493 3555 3540 613 500 866 867 S552 S553 2655 2640 613 500 926 927 S612 S613 1755 1740 613 500 748 S434 4425 613 808 S494 3525 613 868 S554 2625 613 928 S614 1725 613 749 750 S435 S436 4410 4395 500 613 809 810 S495 S496 3510 3495 500 613 869 870 S555 S556 2610 2595 500 613 929 930 S615 S616 1710 1695 500 613 751 752 S437 S438 4380 4365 500 613 811 812 S497 S498 3480 3465 500 613 871 872 S557 S558 2580 2565 500 613 931 932 S617 S618 1680 1665 500 613 753 754 S439 S440 4350 4335 500 613 813 814 S499 S500 3450 3435 500 613 873 874 S559 S560 2550 2535 500 613 933 934 S619 S620 1650 1635 500 613 755 S441 4320 500 815 S501 3420 500 875 S561 2520 500 935 S621 1620 500 756 757 S442 S443 4305 4290 613 500 816 817 S502 S503 3405 3390 613 500 876 877 S562 S563 2505 2490 613 500 936 937 S622 S623 1605 1590 613 500 758 759 S444 S445 4275 4260 613 500 818 819 S504 S505 3375 3360 613 500 878 879 S564 S565 2475 2460 613 500 938 939 S624 S625 1575 1560 613 500 760 761 762 S446 S447 S448 4245 4230 4215 613 500 613 820 821 822 S506 S507 S508 3345 3330 3315 613 500 613 880 881 882 S566 S567 S568 2445 2430 2415 613 500 613 940 941 942 S626 S627 S628 1545 1530 1515 613 500 613 763 764 S449 S450 4200 4185 500 613 823 824 S509 S510 3300 3285 500 613 883 884 S569 S570 2400 2385 500 613 943 944 S629 S630 1500 1485 500 613 765 766 S451 S452 4170 4155 500 613 825 826 S511 S512 3270 3255 500 613 885 886 S571 S572 2370 2355 500 613 945 946 S631 S632 1470 1455 500 613 767 768 S453 S454 4140 4125 500 613 827 828 S513 S514 3240 3225 500 613 887 888 S573 S574 2340 2325 500 613 947 948 S633 S634 1440 1425 500 613 769 S455 4110 500 829 S515 3210 500 889 S575 2310 500 949 S635 1410 500 770 771 S456 S457 4095 4080 613 500 830 831 S516 S517 3195 3180 613 500 890 891 S576 S577 2295 2280 613 500 950 951 S636 S637 1395 1380 613 500 772 773 774 S458 S459 S460 4065 4050 4035 613 500 613 832 833 834 S518 S519 S520 3165 3150 3135 613 500 613 892 893 894 S578 S579 S580 2265 2250 2235 613 500 613 952 953 954 S638 S639 S640 1365 1350 1335 613 500 613 775 776 S461 S462 4020 4005 500 613 835 836 S521 S522 3120 3105 500 613 895 896 S581 S582 2220 2205 500 613 955 956 S641 S642 1320 1305 500 613 777 S463 3990 500 837 S523 3090 500 897 S583 2190 500 957 S643 1290 500 778 S464 3975 613 838 S524 3075 613 898 S584 2175 613 958 S644 1275 613 779 780 S465 S466 3960 3945 500 613 839 840 S525 S526 3060 3045 500 613 899 900 S585 S586 2160 2145 500 613 959 960 S645 S646 1260 1245 500 613 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.22October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. 961 962 963 Name S647 S648 S649 X 1230 1215 1200 Y 500 613 500 No. 1021 1022 1023 Name S707 S708 S709 X 330 315 300 Y 500 613 500 No. 1081 1082 1083 Name S763 S764 S765 X -765 -780 -795 Y 613 500 613 No. 1141 1142 1143 Name S823 S824 S825 X -1665 -1680 -1695 Y 613 500 613 964 965 966 S650 S651 S652 1185 1170 1155 613 500 613 1024 1025 1026 S710 S711 S712 285 270 255 613 500 613 1084 1085 1086 S766 S767 S768 -810 -825 -840 500 613 500 1144 1145 1146 S826 S827 S828 -1710 -1725 -1740 500 613 500 967 968 S653 S654 1140 1125 500 613 1027 1028 S713 S714 240 225 500 613 1087 1088 S769 S770 -855 -870 613 500 1147 1148 S829 S830 -1755 -1770 613 500 969 S655 1110 500 1029 S715 210 500 1089 S771 -885 613 1149 S831 -1785 613 970 S656 1095 613 1030 S716 195 613 1090 S772 -900 500 1150 S832 -1800 500 971 972 973 S657 S658 S659 1080 1065 1050 500 613 500 1031 1032 1033 S717 S718 S719 180 165 150 500 613 500 1091 1092 1093 S773 S774 S775 -915 -930 -945 613 500 613 1151 1152 1153 S833 S834 S835 -1815 -1830 -1845 613 500 613 974 975 S660 S661 1035 1020 613 500 1034 1035 S720 DUMMY11 135 90 613 613 1094 1095 S776 S777 -960 -975 500 613 1154 1155 S836 S837 -1860 -1875 500 613 976 977 978 S662 S663 S664 1005 990 975 613 500 613 1036 1037 1038 DUMMY12 DUMMY13 DUMMY14 30 -30 -90 613 613 613 1096 1097 1098 S778 S779 S780 -990 -1005 -1020 500 613 500 1156 1157 1158 S838 S839 S840 -1890 -1905 -1920 500 613 500 979 980 S665 S666 960 945 500 613 1039 1040 S721 S722 -135 -150 613 500 1099 1100 S781 S782 -1035 -1050 613 500 1159 1160 S841 S842 -1935 -1950 613 500 981 S667 930 500 1041 S723 -165 613 1101 S783 -1065 613 1161 S843 -1965 613 982 983 S668 S669 915 900 613 500 1042 1043 S724 S725 -180 -195 500 613 1102 1103 S784 S785 -1080 -1095 500 613 1162 1163 S844 S845 -1980 -1995 500 613 984 S670 885 613 1044 S726 -210 500 1104 S786 -1110 500 1164 S846 -2010 500 985 986 S671 S672 870 855 500 613 1045 1046 S727 S728 -225 -240 613 500 1105 1106 S787 S788 -1125 -1140 613 500 1165 1166 S847 S848 -2025 -2040 613 500 987 988 S673 S674 840 825 500 613 1047 1048 S729 S730 -255 -270 613 500 1107 1108 S789 S790 -1155 -1170 613 500 1167 1168 S849 S850 -2055 -2070 613 500 989 S675 810 500 1049 S731 -285 613 1109 S791 -1185 613 1169 S851 -2085 613 990 991 S676 S677 795 780 613 500 1050 1051 S732 S733 -300 -315 500 613 1110 1111 S792 S793 -1200 -1215 500 613 1170 1171 S852 S853 -2100 -2115 500 613 992 S678 765 613 1052 S734 -330 500 1112 S794 -1230 500 1172 S854 -2130 500 993 S679 750 500 1053 S735 -345 613 1113 S795 -1245 613 1173 S855 -2145 613 994 995 S680 S681 735 720 613 500 1054 1055 S736 S737 -360 -375 500 613 1114 1115 S796 S797 -1260 -1275 500 613 1174 1175 S856 S857 -2160 -2175 500 613 996 S682 705 613 1056 S738 -390 500 1116 S798 -1290 500 1176 S858 -2190 500 997 998 S683 S684 690 675 500 613 1057 1058 S739 S740 -405 -420 613 500 1117 1118 S799 S800 -1305 -1320 613 500 1177 1178 S859 S860 -2205 -2220 613 500 999 S685 660 500 1059 S741 -435 613 1119 S801 -1335 613 1179 S861 -2235 613 1000 1001 S686 S687 645 630 613 500 1060 1061 S742 S743 -450 -465 500 613 1120 1121 S802 S803 -1350 -1365 500 613 1180 1181 S862 S863 -2250 -2265 500 613 1002 S688 615 613 1062 S744 -480 500 1122 S804 -1380 500 1182 S864 -2280 500 1003 S689 600 500 1063 S745 -495 613 1123 S805 -1395 613 1183 S865 -2295 613 1004 1005 S690 S691 585 570 613 500 1064 1065 S746 S747 -510 -525 500 613 1124 1125 S806 S807 -1410 -1425 500 613 1184 1185 S866 S867 -2310 -2325 500 613 1006 S692 555 613 1066 S748 -540 500 1126 S808 -1440 500 1186 S868 -2340 500 1007 1008 S693 S694 540 525 500 613 1067 1068 S749 S750 -555 -570 613 500 1127 1128 S809 S810 -1455 -1470 613 500 1187 1188 S869 S870 -2355 -2370 613 500 1009 S695 510 500 1069 S751 -585 613 1129 S811 -1485 613 1189 S871 -2385 613 1010 S696 495 613 1070 S752 -600 500 1130 S812 -1500 500 1190 S872 -2400 500 1011 1012 1013 S697 S698 S699 480 465 450 500 613 500 1071 1072 1073 S753 S754 S755 -615 -630 -645 613 500 613 1131 1132 1133 S813 S814 S815 -1515 -1530 -1545 613 500 613 1191 1192 1193 S873 S874 S875 -2415 -2430 -2445 613 500 613 1014 1015 S700 S701 435 420 613 500 1074 1075 S756 S757 -660 -675 500 613 1134 1135 S816 S817 -1560 -1575 500 613 1194 1195 S876 S877 -2460 -2475 500 613 1016 1017 S702 S703 405 390 613 500 1076 1077 S758 S759 -690 -705 500 613 1136 1137 S818 S819 -1590 -1605 500 613 1196 1197 S878 S879 -2490 -2505 500 613 1018 1019 1020 S704 S705 S706 375 360 345 613 500 613 1078 1079 1080 S760 S761 S762 -720 -735 -750 500 613 500 1138 1139 1140 S820 S821 S822 -1620 -1635 -1650 500 613 500 1198 1199 1200 S880 S881 S882 -2520 -2535 -2550 500 613 500 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.23October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. 1201 1202 1203 Name S883 S884 S885 X -2565 -2580 -2595 Y 613 500 613 No. 1261 1262 1263 Name S943 S944 S945 X -3465 -3480 -3495 Y 613 500 613 No. 1321 1322 1323 Name S1003 S1004 S1005 X -4365 -4380 -4395 Y 613 500 613 No. 1381 1382 1383 Name S1063 S1064 S1065 X -5265 -5280 -5295 Y 613 500 613 1204 1205 1206 S886 S887 S888 -2610 -2625 -2640 500 613 500 1264 1265 1266 S946 S947 S948 -3510 -3525 -3540 500 613 500 1324 1325 1326 S1006 S1007 S1008 -4410 -4425 -4440 500 613 500 1384 1385 1386 S1066 S1067 S1068 -5310 -5325 -5340 500 613 500 1207 1208 S889 S890 -2655 -2670 613 500 1267 1268 S949 S950 -3555 -3570 613 500 1327 1328 S1009 S1010 -4455 -4470 613 500 1387 1388 S1069 S1070 -5355 -5370 613 500 1209 S891 -2685 613 1269 S951 -3585 613 1329 S1011 -4485 613 1389 S1071 -5385 613 1210 S892 -2700 500 1270 S952 -3600 500 1330 S1012 -4500 500 1390 S1072 -5400 500 1211 1212 1213 S893 S894 S895 -2715 -2730 -2745 613 500 613 1271 1272 1273 S953 S954 S955 -3615 -3630 -3645 613 500 613 1331 1332 1333 S1013 S1014 S1015 -4515 -4530 -4545 613 500 613 1391 1392 1393 S1073 S1074 S1075 -5415 -5430 -5445 613 500 613 1214 1215 S896 S897 -2760 -2775 500 613 1274 1275 S956 S957 -3660 -3675 500 613 1334 1335 S1016 S1017 -4560 -4575 500 613 1394 1395 S1076 S1077 -5460 -5475 500 613 1216 1217 1218 S898 S899 S900 -2790 -2805 -2820 500 613 500 1276 1277 1278 S958 S959 S960 -3690 -3705 -3720 500 613 500 1336 1337 1338 S1018 S1019 S1020 -4590 -4605 -4620 500 613 500 1396 1397 1398 S1078 S1079 S1080 -5490 -5505 -5520 500 613 500 1219 1220 S901 S902 -2835 -2850 613 500 1279 1280 S961 S962 -3735 -3750 613 500 1339 1340 S1021 S1022 -4635 -4650 613 500 1399 1400 S1081 S1082 -5535 -5550 613 500 1221 S903 -2865 613 1281 S963 -3765 613 1341 S1023 -4665 613 1401 S1083 -5565 613 1222 1223 S904 S905 -2880 -2895 500 613 1282 1283 S964 S965 -3780 -3795 500 613 1342 1343 S1024 S1025 -4680 -4695 500 613 1402 1403 S1084 S1085 -5580 -5595 500 613 1224 S906 -2910 500 1284 S966 -3810 500 1344 S1026 -4710 500 1404 S1086 -5610 500 1225 1226 S907 S908 -2925 -2940 613 500 1285 1286 S967 S968 -3825 -3840 613 500 1345 1346 S1027 S1028 -4725 -4740 613 500 1405 1406 S1087 S1088 -5625 -5640 613 500 1227 1228 S909 S910 -2955 -2970 613 500 1287 1288 S969 S970 -3855 -3870 613 500 1347 1348 S1029 S1030 -4755 -4770 613 500 1407 1408 S1089 S1090 -5655 -5670 613 500 1229 S911 -2985 613 1289 S971 -3885 613 1349 S1031 -4785 613 1409 S1091 -5685 613 1230 1231 S912 S913 -3000 -3015 500 613 1290 1291 S972 S973 -3900 -3915 500 613 1350 1351 S1032 S1033 -4800 -4815 500 613 1410 1411 S1092 S1093 -5700 -5715 500 613 1232 S914 -3030 500 1292 S974 -3930 500 1352 S1034 -4830 500 1412 S1094 -5730 500 1233 S915 -3045 613 1293 S975 -3945 613 1353 S1035 -4845 613 1413 S1095 -5745 613 1234 1235 S916 S917 -3060 -3075 500 613 1294 1295 S976 S977 -3960 -3975 500 613 1354 1355 S1036 S1037 -4860 -4875 500 613 1414 1415 S1096 S1097 -5760 -5775 500 613 1236 S918 -3090 500 1296 S978 -3990 500 1356 S1038 -4890 500 1416 S1098 -5790 500 1237 1238 S919 S920 -3105 -3120 613 500 1297 1298 S979 S980 -4005 -4020 613 500 1357 1358 S1039 S1040 -4905 -4920 613 500 1417 1418 S1099 S1100 -5805 -5820 613 500 1239 S921 -3135 613 1299 S981 -4035 613 1359 S1041 -4935 613 1419 S1101 -5835 613 1240 1241 S922 S923 -3150 -3165 500 613 1300 1301 S982 S983 -4050 -4065 500 613 1360 1361 S1042 S1043 -4950 -4965 500 613 1420 1421 S1102 S1103 -5850 -5865 500 613 1242 S924 -3180 500 1302 S984 -4080 500 1362 S1044 -4980 500 1422 S1104 -5880 500 1243 S925 -3195 613 1303 S985 -4095 613 1363 S1045 -4995 613 1423 S1105 -5895 613 1244 1245 S926 S927 -3210 -3225 500 613 1304 1305 S986 S987 -4110 -4125 500 613 1364 1365 S1046 S1047 -5010 -5025 500 613 1424 1425 S1106 S1107 -5910 -5925 500 613 1246 S928 -3240 500 1306 S988 -4140 500 1366 S1048 -5040 500 1426 S1108 -5940 500 1247 1248 S929 S930 -3255 -3270 613 500 1307 1308 S989 S990 -4155 -4170 613 500 1367 1368 S1049 S1050 -5055 -5070 613 500 1427 1428 S1109 S1110 -5955 -5970 613 500 1249 S931 -3285 613 1309 S991 -4185 613 1369 S1051 -5085 613 1429 S1111 -5985 613 1250 S932 -3300 500 1310 S992 -4200 500 1370 S1052 -5100 500 1430 S1112 -6000 500 1251 1252 1253 S933 S934 S935 -3315 -3330 -3345 613 500 613 1311 1312 1313 S993 S994 S995 -4215 -4230 -4245 613 500 613 1371 1372 1373 S1053 S1054 S1055 -5115 -5130 -5145 613 500 613 1431 1432 1433 S1113 S1114 S1115 -6015 -6030 -6045 613 500 613 1254 1255 S936 S937 -3360 -3375 500 613 1314 1315 S996 S997 -4260 -4275 500 613 1374 1375 S1056 S1057 -5160 -5175 500 613 1434 1435 S1116 S1117 -6060 -6075 500 613 1256 1257 S938 S939 -3390 -3405 500 613 1316 1317 S998 S999 -4290 -4305 500 613 1376 1377 S1058 S1059 -5190 -5205 500 613 1436 1437 S1118 S1119 -6090 -6105 500 613 1258 1259 1260 S940 S941 S942 -3420 -3435 -3450 500 613 500 1318 1319 1320 S1000 S1001 S1002 -4320 -4335 -4350 500 613 500 1378 1379 1380 S1060 S1061 S1062 -5220 -5235 -5250 500 613 500 1438 1439 1440 S1120 S1121 S1122 -6120 -6135 -6150 500 613 500 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.24October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. 1441 1442 1443 Name S1123 S1124 S1125 X -6165 -6180 -6195 Y 613 500 613 No. 1501 1502 1503 Name S1183 S1184 S1185 X -7065 -7080 -7095 Y 613 500 613 No. 1561 1562 1563 Name S1243 S1244 S1245 X -7965 -7980 -7995 Y 613 500 613 No. 1621 1622 1623 Name S1303 S1304 S1305 X -8865 -8880 -8895 Y 613 500 613 1444 1445 1446 S1126 S1127 S1128 -6210 -6225 -6240 500 613 500 1504 1505 1506 S1186 S1187 S1188 -7110 -7125 -7140 500 613 500 1564 1565 1566 S1246 S1247 S1248 -8010 -8025 -8040 500 613 500 1624 1625 1626 S1306 S1307 S1308 -8910 -8925 -8940 500 613 500 1447 1448 S1129 S1130 -6255 -6270 613 500 1507 1508 S1189 S1190 -7155 -7170 613 500 1567 1568 S1249 S1250 -8055 -8070 613 500 1627 1628 S1309 S1310 -8955 -8970 613 500 1449 S1131 -6285 613 1509 S1191 -7185 613 1569 S1251 -8085 613 1629 S1311 -8985 613 1450 S1132 -6300 500 1510 S1192 -7200 500 1570 S1252 -8100 500 1630 S1312 -9000 500 1451 1452 1453 S1133 S1134 S1135 -6315 -6330 -6345 613 500 613 1511 1512 1513 S1193 S1194 S1195 -7215 -7230 -7245 613 500 613 1571 1572 1573 S1253 S1254 S1255 -8115 -8130 -8145 613 500 613 1631 1632 1633 S1313 S1314 S1315 -9015 -9030 -9045 613 500 613 1454 1455 S1136 S1137 -6360 -6375 500 613 1514 1515 S1196 S1197 -7260 -7275 500 613 1574 1575 S1256 S1257 -8160 -8175 500 613 1634 1635 S1316 S1317 -9060 -9075 500 613 1456 1457 1458 S1138 S1139 S1140 -6390 -6405 -6420 500 613 500 1516 1517 1518 S1198 S1199 S1200 -7290 -7305 -7320 500 613 500 1576 1577 1578 S1258 S1259 S1260 -8190 -8205 -8220 500 613 500 1636 1637 1638 S1318 S1319 S1320 -9090 -9105 -9120 500 613 500 1459 1460 S1141 S1142 -6435 -6450 613 500 1519 1520 S1201 S1202 -7335 -7350 613 500 1579 1580 S1261 S1262 -8235 -8250 613 500 1639 1640 S1321 S1322 -9135 -9150 613 500 1461 S1143 -6465 613 1521 S1203 -7365 613 1581 S1263 -8265 613 1641 S1323 -9165 613 1462 1463 S1144 S1145 -6480 -6495 500 613 1522 1523 S1204 S1205 -7380 -7395 500 613 1582 1583 S1264 S1265 -8280 -8295 500 613 1642 1643 S1324 S1325 -9180 -9195 500 613 1464 S1146 -6510 500 1524 S1206 -7410 500 1584 S1266 -8310 500 1644 S1326 -9210 500 1465 1466 S1147 S1148 -6525 -6540 613 500 1525 1526 S1207 S1208 -7425 -7440 613 500 1585 1586 S1267 S1268 -8325 -8340 613 500 1645 1646 S1327 S1328 -9225 -9240 613 500 1467 1468 S1149 S1150 -6555 -6570 613 500 1527 1528 S1209 S1210 -7455 -7470 613 500 1587 1588 S1269 S1270 -8355 -8370 613 500 1647 1648 S1329 S1330 -9255 -9270 613 500 1469 S1151 -6585 613 1529 S1211 -7485 613 1589 S1271 -8385 613 1649 S1331 -9285 613 1470 1471 S1152 S1153 -6600 -6615 500 613 1530 1531 S1212 S1213 -7500 -7515 500 613 1590 1591 S1272 S1273 -8400 -8415 500 613 1650 1651 S1332 S1333 -9300 -9315 500 613 1472 S1154 -6630 500 1532 S1214 -7530 500 1592 S1274 -8430 500 1652 S1334 -9330 500 1473 S1155 -6645 613 1533 S1215 -7545 613 1593 S1275 -8445 613 1653 S1335 -9345 613 1474 1475 S1156 S1157 -6660 -6675 500 613 1534 1535 S1216 S1217 -7560 -7575 500 613 1594 1595 S1276 S1277 -8460 -8475 500 613 1654 1655 S1336 S1337 -9360 -9375 500 613 1476 S1158 -6690 500 1536 S1218 -7590 500 1596 S1278 -8490 500 1656 S1338 -9390 500 1477 1478 S1159 S1160 -6705 -6720 613 500 1537 1538 S1219 S1220 -7605 -7620 613 500 1597 1598 S1279 S1280 -8505 -8520 613 500 1657 1658 S1339 S1340 -9405 -9420 613 500 1479 S1161 -6735 613 1539 S1221 -7635 613 1599 S1281 -8535 613 1659 S1341 -9435 613 1480 1481 S1162 S1163 -6750 -6765 500 613 1540 1541 S1222 S1223 -7650 -7665 500 613 1600 1601 S1282 S1283 -8550 -8565 500 613 1660 1661 S1342 S1343 -9450 -9465 500 613 1482 S1164 -6780 500 1542 S1224 -7680 500 1602 S1284 -8580 500 1662 S1344 -9480 500 1483 S1165 -6795 613 1543 S1225 -7695 613 1603 S1285 -8595 613 1663 S1345 -9495 613 1484 1485 S1166 S1167 -6810 -6825 500 613 1544 1545 S1226 S1227 -7710 -7725 500 613 1604 1605 S1286 S1287 -8610 -8625 500 613 1664 1665 S1346 S1347 -9510 -9525 500 613 1486 S1168 -6840 500 1546 S1228 -7740 500 1606 S1288 -8640 500 1666 S1348 -9540 500 1487 1488 S1169 S1170 -6855 -6870 613 500 1547 1548 S1229 S1230 -7755 -7770 613 500 1607 1608 S1289 S1290 -8655 -8670 613 500 1667 1668 S1349 S1350 -9555 -9570 613 500 1489 S1171 -6885 613 1549 S1231 -7785 613 1609 S1291 -8685 613 1669 S1351 -9585 613 1490 S1172 -6900 500 1550 S1232 -7800 500 1610 S1292 -8700 500 1670 S1352 -9600 500 1491 1492 1493 S1173 S1174 S1175 -6915 -6930 -6945 613 500 613 1551 1552 1553 S1233 S1234 S1235 -7815 -7830 -7845 613 500 613 1611 1612 1613 S1293 S1294 S1295 -8715 -8730 -8745 613 500 613 1671 1672 1673 S1353 S1354 S1355 -9615 -9630 -9645 613 500 613 1494 1495 S1176 S1177 -6960 -6975 500 613 1554 1555 S1236 S1237 -7860 -7875 500 613 1614 1615 S1296 S1297 -8760 -8775 500 613 1674 1675 S1356 S1357 -9660 -9675 500 613 1496 1497 S1178 S1179 -6990 -7005 500 613 1556 1557 S1238 S1239 -7890 -7905 500 613 1616 1617 S1298 S1299 -8790 -8805 500 613 1676 1677 S1358 S1359 -9690 -9705 500 613 1498 1499 1500 S1180 S1181 S1182 -7020 -7035 -7050 500 613 500 1558 1559 1560 S1240 S1241 S1242 -7920 -7935 -7950 500 613 500 1618 1619 1620 S1300 S1301 S1302 -8820 -8835 -8850 500 613 500 1678 1679 1680 S1360 S1361 S1362 -9720 -9735 -9750 500 613 500 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.25October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 No. 1681 1682 Name S1363 S1364 X -9765 -9780 Y 613 500 No. 1741 1742 Name S1423 S1424 X -10665 -10680 Y 613 500 1683 1684 1685 1686 S1365 S1366 S1367 S1368 -9795 -9810 -9825 -9840 613 500 613 500 1743 1744 1745 1746 S1425 S1426 S1427 S1428 -10695 -10710 -10725 -10740 613 500 613 500 1687 1688 S1369 S1370 -9855 -9870 613 500 1747 1748 S1429 S1430 -10755 -10770 613 500 1689 S1371 -9885 613 1749 S1431 -10785 613 1690 S1372 -9900 500 1750 S1432 -10800 500 1691 1692 1693 S1373 S1374 S1375 -9915 -9930 -9945 613 500 613 1751 1752 1753 S1433 S1434 S1435 -10815 -10830 -10845 613 500 613 1694 1695 S1376 S1377 -9960 -9975 500 613 1754 1755 S1436 S1437 -10860 -10875 500 613 1696 1697 1698 S1378 S1379 S1380 -9990 -10005 -10020 500 613 500 1756 1757 1758 S1438 S1439 S1440 -10890 -10905 -10920 500 613 500 1699 S1381 -10035 613 1759 S1441 (for Zig-Zag) -10935 613 1700 S1382 -10050 500 1760 Dummy17 -10950 500 1701 1702 1703 S1383 S1384 S1385 -10065 -10080 -10095 613 500 613 1704 1705 S1386 S1387 -10110 -10125 500 613 1706 1707 S1388 S1389 -10140 -10155 500 613 1708 1709 S1390 S1391 -10170 -10185 500 613 1710 1711 1712 S1392 S1393 S1394 -10200 -10215 -10230 500 613 500 1713 1714 S1395 S1396 -10245 -10260 613 500 1715 1716 S1397 S1398 -10275 -10290 613 500 1717 S1399 -10305 613 1718 1719 S1400 S1401 -10320 -10335 500 613 1720 1721 S1402 S1403 -10350 -10365 500 613 1722 1723 S1404 S1405 -10380 -10395 500 613 1724 S1406 -10410 500 1725 S1407 -10425 613 1726 S1408 -10440 500 1727 1728 1729 S1409 S1410 S1411 -10455 -10470 -10485 613 500 613 1730 1731 S1412 S1413 -10500 -10515 500 613 1732 S1414 -10530 500 1733 S1415 -10545 613 1734 1735 1736 S1416 S1417 S1418 -10560 -10575 -10590 500 613 500 1737 1738 S1419 S1420 -10605 -10620 613 500 1739 1740 S1421 S1422 -10635 -10650 613 500 Alignment mark A1 A2 X -11060 11060 Y 600 600 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.26October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 3.4.1 Bump arrangement 15 15 208 18 95 I/O pins (No. 313-1760) 113 95 15 15 50 2 15 Bump area = 1425 um Bump area = 4000 um2 80 I/O pins (No. 1-312) 15 70 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.27October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.28October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4. Interface 4.1 System interface The HX8369-A00 supports DBI (Display Bus Interface) and DPI (Display Pixel Interface). Where DBI supports (16-/9-/8-bit interface) Parallel Interface (Type A, Type B) and Serial interface (Type C). The interface mode can be selected by BS3-0 pins setting as show in Table 4.1. BS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 BS2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 Interface DBI TYPE-A 8-bit (CLK-E) DBI TYPE-A 9-bit (CLK-E) DBI TYPE-A 16-bit (CLK-E) DBI TYPE-A 18-bit (CLK-E) DBI TYPE-B 8-bit DBI TYPE-B 9-bit DBI TYPE-B 16-bit DBI TYPE-B 18-bit DBI TYPE-B 24-bit DPI / DBI TYPE-C Option 1 DPI / DBI TYPE-C Option 2 DPI / DBI TYPE-C Option 3 Table 4.1: Interface selection Display data GRAM GRAM GRAM GRAM GRAM GRAM GRAM GRAM GRAM DPI / GRAM DPI / GRAM DPI / GRAM Display mode Type 1 Type 1 Type 1 Type 1 Type 1 Type 1 Type 1 Type 1 Type 1 Type 3 Type 3 Type 3 The HX8369-A00 includes an index register (IR), which is stored the index data of internal control register and GRAM. When DCX=”L”, the command via DBI interface write into register. When DCX=”H”, GRAM data via R2Ch register can be written through data bus. When the data is written into the GRAM from the MPU, it is first written into the write-data latch and then automatically written into the GRAM by internal operation. Data is read through the read-data latch when reading from the GRAM. When data is read from the GRAM to the MPU, it is first read from GRAM to the read-data latch and then data is read to MPU through the read-data latch in next read operation. Therefore, the read data in data bus in first read operation is invalid, and the read data in data bus in second and the following read operation is valid. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.29October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Interface RDX_E WRX_DCX DCX_SCL DBI Type C 3-wire serial interface + DPI interface Unused Unused SCL DBI Type A 8-bit parallel E RW DCX DBI Type A 9-bit parallel E RW DCX DBI Type A 16-bit parallel E RW DCX DBI Type A 18-bit parallel E RW DCX DBI Type C 4-wire serial interface + DPI interface Unused DCX SCL DBI Type B 8-bit parallel RDX WRX DCX DBI Type B 9-bit parallel RDX WRX DCX DBI Type B 16-bit parallel RDX WRX DCX DBI Type B 18-bit parallel RDX WRX DCX DBI Type B 24-bit parallel RDX WRX DCX D23–D0 or other input pin DB23–DB0: 24-bit data bus DB21–DB16, DB13-DB8, DB5-DB0: 18-bit data bus DB21–DB17, DB13-DB8, DB5-DB1: 16-bit data bus SDI/SDO DB23–DB8: Unused, DB7–DB0: 8-bit data bus DB23–DB9: Unused, DB8–DB0: 9-bit data bus DB23–DB16: Unused, DB15–DB0: 16-bit data bus DB23–DB18: Unused, DB17–DB0: 18-bit data bus DB23–DB0: 24-bit data bus DB21–DB16, DB13-DB8, DB5-DB0: 18-bit data bus DB21–DB17, DB13-DB8, DB5-DB1: 16-bit data bus SDI/SDO DB23–DB8: Unused, D7–D0: 8-bit data bus DB23–DB9: Unused, DB8–DB0: 9-bit data bus DB23–DB16: Unused, DB15–DB0: 16-bit data bus DB23–DB18: Unused, DB17–DB0: 18-bit data bus DB23–DB0: 24-bit data bus Table 4.2: Pin connection based on different interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.30October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.1.1 DBI-A / DBI-B interface The selection of DBI interface is by BS3 pin. When this pin is low state (VSSD), the interface is use DBI system. And use BS2 to BS0 pins to selsect DBI interfacr mode. The parallel interface timing diagram is described in Figure 4.1 to Figure 4.4. Figure 4.1: DBI-A system interface protocol, write to register or GRAM Figure 4.2: DBI-A system interface protocol, read from register or GRAM Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.31October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Figure 4.3: DBI-B system interface protocol, write to register or GRAM Figure 4.4: DBI-B system interface protocol, read from register or GRAM Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.32October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.1.1.1 24-bit parallel bus system interface The DBI-B system 24-bit bus parallel data transfer can be used by setting “BS3-0” pins to “1010”. The Figure 4.5 is the example of interface with 18-bit DBI-A / DBI-B microcomputer system interface. Figure 4.5 Example of DBI-B system 24-bit parallel bus interface There are one type data format to write display data at 24-bit bus Interface. See Figure 4.6. Figure 4.6: Write data for RGB 8-8-8 (16.7M colours) bit Input in 24-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.33October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.1.1.2 18-bit parallel bus system interface The DBI-A system 18-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0011”. And the DBI-B system 18-bit bus parallel data transfer can be used by setting “BS3-0”pins to “0111”. The Figure 4.7 is the example of interface with 18-bit DBI-A / DBI-B microcomputer system interface. Figure 4.7: Example of DBI-A- / DBI-B system 18-bit parallel bus interface There are three types data format to write display data at 18-bit bus Interface. See Figure 4.8 to Figure 4.10. Under this type, the data format can select as 16- / 18- / 24-bit by register R3Ah. (set_pixel_format) 65k Color Data DCX MEMWR 1st write 2nd write 0 1 1 D17 x x D16 x x D15 D14 R14 R24 R13 R23 D13 R12 R22 D12 D11 R11 R21 GRAM Write command code R10 G15 G14 G13 G12 G11 G10 R20 G25 G24 G23 G22 G21 G20 D10 D9 D8 D7 16-bit D6 D5 D4 D3 D2 D1 D0 GRAM Write B14 B24 B13 B23 B12 B22 B11 B21 B10 B20 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 16-bit Look-Up Table for 65k Color data mapping (16-bit to 24-bit) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.8: Write data for RGB 5-6-5 (65k colours) bit input in 18-bit parallel interface 262k Color Data MEMWR 1st write 2nd write DCX 0 1 1 D17 R15 R25 D16 R14 R24 D15 R13 R23 D14 D13 D12 D11 R12 R22 GRAM Write command code R11 R10 G15 G14 G13 G12 G11 G10 R21 R20 G25 G24 G23 G22 G21 G20 D10 D9 D8 18-bit D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write B15 B25 B14 B24 B13 B23 B12 B22 B11 B21 B10 B20 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 18-bit Look-Up Table for 262k Color data mapping (18-bit to 24-bit) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.9: Write data for RGB 6-6-6(262k colours) bit input in 18-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.34October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 16.7M Color Data DCX MEMWR 1st write 2nd write 3rd write 0 1 1 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write command code R17 R1 6 R1 5 R1 4 R1 3 R1 2 R1 1 R1 0 x x G17 G16 G15 G14 G13 G12 G11 G10 B17 B16 B15 B14 B13 B12 B11 B10 x x R27 R26 R25 R24 R23 R22 R21 R20 G2 7 G2 6 G2 5 G2 4 G23 G22 G21 G2 0 x x B27 B26 B25 B24 B23 B22 B21 B20 24-bit GRAM Write 1st pixel (R1/G1/B1) x 2nd pixel (R2/G2/B2) 24-bit GRAM R1 16.7M Color Data DCX MEMWR 1st write 2nd write MEMWR 1st write 2nd write 3rd write 0 1 1 0 0 1 1 1 D17 D16 D15 G1 B1 R2 D14 D13 D12 D11 D10 G2 D9 B2 R3 D8 D7 G3 D6 B3 D5 D4 D3 D2 D1 D0 GRAM Write command code R11 R10 x x G17 G16 G15 G14 G13 G12 G11 G10 B11 B10 x x R27 R26 R25 R24 R23 R22 R21 R20 The other command GRAM Write command code R2 7 R2 6 R2 5 R2 4 R2 3 R2 2 R2 1 R2 0 x x G2 7 G2 6 G2 5 G2 4 G2 3 G22 G21 G20 B27 B26 B25 B24 B23 B22 B21 B20 x x R3 7 R3 6 R3 5 R3 4 R33 R32 R31 R30 G37 G36 G35 G34 G33 G32 G31 G30 x x B37 B36 B35 B34 B33 B32 B31 B30 R17 B17 R16 B16 R15 B15 R14 B14 R13 B13 R12 B12 24-bit GRAM Write 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 3rd pixel (R3/G3/B3) R27 ~ R20 will be neglected and are not used 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.10: Write data for RGB 8-8-8 (16.7M colours) bit input in 18-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.35October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.1.1.3 16-bit parallel bus system interface The DBI-A system 16-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0010”. And the DBI-B system 16-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0110”. The Figure 4.11 is the example of interface with 16-bit DBI-A / DBI-B microcomputer system interface. Figure 4.11: Example of DBI-A- / DBI-B system 16-bit bus interface There are three types data format to write display data at 16-bit bus Interface. See Figure 4.12 to Figure 4. 14. Under this type, the data format can select as 16- / 18- / 24-bit by register R3Ah. (set_pixel_format) 65k Color Data DCX MEMWR 1st write 2nd write 0 1 1 D15 R14 R24 D14 R13 R23 D13 R12 R22 D12 D11 D10 R11 R21 GRAM Write command code R10 G15 G14 G13 G12 G11 G10 R20 G25 G24 G23 G22 G21 G20 D9 D8 D7 16-bit D6 D5 D4 D3 D2 D1 D0 GRAM Write B14 B24 B13 B23 B12 B22 B11 B21 B10 B20 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 16-bit Look-Up Table for 65k Color data mapping (16-bit to 24-bit) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.12: Write data for RGB 5-6-5 (65k colours) bit input in 16-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.36October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Figure 4.13: Write data for RGB 6-6-6 (262k colours) bit input in 16-bit parallel interface Figure 4.14: Write data for RGB 8-8-8-bit (16.7M colours) input in 16-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.37October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.1.1.4 9-bit parallel bus system interface The DBI-A system 9-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0001”. And the DBI-B system 9-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0101”. The Figure 4.15 is the example of interface with 9-bit DBI-A / DBI-B microcomputer system interface. Figure 4.15: Example of DBI-A- / DBI-B- system 9-bit bus interface There are three types data format to write display data at 9-bit bus Interface. See Figure 4.16 to Figure 4. 18. Under this type, the data format can select as 16-/18-/ 24-bit by register R3Ah. (set_pixel_format) 65k Color Data DCX MEMWR 1st write 2nd write 3rd write 4th write 0 1 1 1 1 D8 x x x x D7 R14 G12 R24 G22 D6 D5 D4 D3 D2 D1 D0 GRAM Write command code R13 R12 R11 R10 G15 G14 G13 G11 G10 B14 B13 B12 B11 B10 R23 R22 R21 R20 G25 G24 G23 G21 G20 B24 B23 B22 B21 B20 16-bit GRAM Write 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 16-bit Look-Up Table for 65k Color data mapping ( 16-bit to 24-bit ) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.16: Write data for RGB 5-6-5(65k colours) bit input in 9-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.38October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 262k Color Data DCX D8 D7 MEMWR 1st write 2nd write 3rd write 4th write 0 1 1 1 1 R15 G12 R25 G22 R14 G11 R24 G21 D6 D5 D4 D3 D2 D1 D0 GRAM Write command code R13 R12 R11 R10 G15 G14 G13 G10 B15 B14 B13 B12 B11 B10 R23 R22 R21 R20 G25 G24 G23 G20 B25 B24 B23 B22 B21 B20 18-bit GRAM Write 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 18-bit Look-Up Table for 262k Color data mapping ( 18-bit to 24-bit ) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.17: Write data for RGB 6-6-6-bit (262k colours) input in 9-bit parallel interface 16.7M Color Data DCX D8 D7 MEMWR 1st write 2nd write 3rd write 4th write 5th write 6th write 0 1 1 1 1 1 1 R17 G17 B17 R27 G27 B27 R16 G16 B16 R26 G26 B26 D6 D5 D4 D3 D2 GRAM Write command code R15 R14 R13 R12 R11 G15 G14 G13 G12 G11 B15 B14 B13 B12 B11 R25 R24 R23 R22 R21 G25 G24 G23 G22 G21 B25 B24 B23 B22 B21 24-bit D1 D0 GRAM Write R10 G10 B10 R20 G20 B20 x x x x x x 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.18: Write data for RGB 8-8-8-bit (16.7 M colours) input in 9-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.39October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.1.1.5 8-bit parallel bus system interface The DBI-A system 8-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0000”. And the DBI-B system 8-bit bus parallel data transfer can be used by setting “BS3-0” pins to “0100”. The Figure 4.19 is the example of interface with 8-bit DBI-A / DBI-B microcomputer system interface. Figure 4.19: Example of DBI-A- / DBI-B-system 8-bit bus interface There are three types data format to write display data at 8-bit bus Interface. See Figure 4. 20 to Figure 4. 22. Under this type, the data format can select as 16-/18-/ 24-bit by register R3Ah. (set_pixel_format) 65k Color Data DCX MEMWR 1st write 2nd write 3rd write 4th write 0 1 1 1 1 D7 R14 G12 R24 G22 D6 D5 D4 D3 D2 D1 D0 GRAM Write command code R13 R12 R11 R10 G15 G14 G13 G11 G10 B14 B13 B12 B11 B10 R23 R22 R21 R20 G25 G24 G23 G21 G20 B24 B23 B22 B21 B20 16-bit GRAM Write 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 16-bit Look-Up Table for 65k Color data mapping ( 16-bit to 24-bit ) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.20: Write data for RGB 5-6-5 (65k colours) bit input in 8-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.40October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 262k Color Data DCX MEMWR 1st write 2nd write 3rd write 4th write 5th write 6th write 0 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write x x x x x x x x x x x x 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) GRAM Write command code R15 R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 B10 R25 R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 B20 18-bit 18-bit Look-Up Table for 262k Color data mapping ( 18-bit to 24-bit ) 24-bit 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.21: Write data for RGB 6-6-6-bit (262k colours) input in 8-bit parallel interface 16.7M Color Data DCX MEMWR 1st write 2nd write 3rd write 4th write 5th write 6th write 0 1 1 1 1 1 1 D7 R17 G17 B17 R27 G27 B27 D6 D5 D4 D3 D2 D1 GRAM Write command code R16 R15 R14 R13 R12 R11 G16 G15 G14 G13 G12 G11 B16 B15 B14 B13 B12 B11 R26 R25 R24 R23 R22 R21 G26 G25 G24 G23 G22 G21 B26 B25 B24 B23 B22 B21 24-bit D0 GRAM Write R10 G10 B10 R20 G20 B20 1st pixel (R1/G1/B1) 2nd pixel (R2/G2/B2) 24-bit GRAM R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure 4.22: Write data for RGB 8-8-8-bit (16.7 M colours) input in 8-bit parallel interface Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.41October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2 Serial data transfer interface (DBI-C) The HX8369-A00 supports three type serial data transfer interface, the interface selection by setting BS3-0 pins. The BS3-0 set “1101” is select 3-wire option 1 serial bus. The BS3-0 set “1110” is select 3-wire option 2 serial bus. The BS3-0 is set “1111” when select 4-wire option 3 serial bus. The 3-wire serial bus is use: chip select line (CSX), serial input/output data (SDI and SDO) and the serial transfer clock line (DCX_SCL).The 4-wire serial bus is use: chip select line (CSX), data/command select (WRX_DCX), serial input/output data (SDI and SDO) and the serial transfer clock line (DCX_SCL). 4.2.1.1 Serial data write mode The 3-pin serial data packet contains a control bit D/CX and a transmission byte and in 4-pin serial case, data packet contains just transmission byte and control signal D/CX is transferred by WRX_DCX pin. If DCX is low, the transmission byte is command byte. If D/CX is high, the transmission byte is stored in to command register or GRAM. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or serial input/output data (SDI and SDO) have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. Where 3-wire serial write format include two types (8-/16-bit) is according command code. Figure 4.23: Serial data stream, write mode Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.42October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Figure 4.24: DBI Type C: Serial interface protocol 3-wire/4-wire, write mode Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.43October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2.1.2 Serial data read mode The micro-controller first has to send a command and then the following byte is transmitted in the opposite direction. The 3-wire serial read data format which just needs 8-bit. Figure 4.25: Type C:Serial interface protocol 3-wire/4-wire read mode Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.44October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 If there is a break on data transmission when transmit a command before a whole byte has been completed, then the display module will have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following figure. Figure 4.26: Display module data transfer recovery Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.45October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2.2 DPI interface (Display Pixel Interface) The HX8369-A00 uses 16 or 18-bit or 24-bit parallel RGB interface which includes: HS, VSYNC, DE, PCLK, DB23~DB0. The interface is active after Power On sequence. Pixel clock (PCLK) is running all the time without stopping and it is used to entering HSYNC, VSYNC, DE and DB23~DB0– lines states when there is a rising edge of the PCLK. The PCLK cannot be used as continue internal clock for other functions of the display module e.g. Sleep In– mode etc. Vertical synchronization (VSYNC) is used to tell when there is received a new frame of the display. This is negative (“-“, “0”, low) active and its state is read to the display module by a rising edge of the PCLK-line. Horizontal synchronization (HSYNC) is used to tell when there is received a new line of the frame. This is negative (“-“, “0”, low) active and its state is read to the display module by a rising edge of the PCLK- line. Data enable (DE) is used to tell when there is received RGB information that should be transferred on the display. This is positive (“+”, “1”, high) active and its state is read to the display module by a rising edge of the PCLK-line. DB23~DB0 (24 bit: R7-R0, G7-G0 and B7-B0; 18 bit: R5- R0, G5-G0 and B5-B0; 16 bit: R4- R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is transferred on the display (when DE=1 and there is a rising edge of PCLK). DB23~DB0– lines can be set to “0” (low) or “1” (high). These lines are read by a rising edge of the PCLK-line. The pixel clock cycle is described in the following figure. Note: PCLK is an unsynchronized signal (It can be stopped). Figure 4.27: PCLK cycle Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.46October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2.2.1 General timing diagram Vertical Sync. 0 1 Invisble Image = Timing information what is not possible to see on the display = Blanking Time Vsync VBP DE = 0 (Low) Display Area (VAdr + HAdr) – period when valid display data are transferred from host to display module VAdr DE = 1 (High) VFP 1 Horizontal Sync. 0 Hsync HBP HAdr HFP HP Figure 4.28: General timing diagram Figure 4.29: DPI (480RGB x 864) timing diagram The image information must be correct on the display, when the timings are in range on the interface. However, the image information can be incorrect on the display, when timings are out of the range on the interface (Out of the range timings cannot cause any damage on the display module or it cannot cause any damage on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical sync.), when there is returned from out of the range to in range interface timings. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.47October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 The DPI interface includes two types which are 16-/18-/24-bit data format by register 3Ah (set_pixel_format) to select. DPI interface displaying moving pictures can be selected to rewrite into the GRAM or not through GRAM. The selection is set by register DM[1:0] and RM. RM The bit is used to select an interface for the Frame Memory access operation. The Frame Memory is accessed only via the interface defined by RM bit. Because the interface can be selected separately from display operation mode, writing data to the Frame Memory is possible via system interface when RM = 0, even in the DPI display operation. RM setting is enabled from the next frame. Wait 1 frame to transfer data after setting. RM 0 1 Interface for RAM access DBI Interface (CPU) DPI Interface (RGB) DM[1:0] The bit is used to select display operation mode. The setting allows switching between display operation in synchronization with internal oscillation clock, VSYNC, or DPI signal. Note that switching between VSYNC and DPI operation is prohibited. DM 1 0 0 1 1 DM 0 0 1 0 1 Operation Mode Internal clock operation (displaying still pictures) RGB interface : capture mode 1 (displaying moving pictures) RGB interface : capture mode 2 (rewriting still pictures while displaying moving pictures) RGB interface : through mode (displaying moving pictures) Internal clock operation RGB data format Display Mode Internal oscillation clock DPI signal (VSYNC+HSYNC) VSYNC signal only RGB data bypass GRAM mode Frame Memory Access Setting (RM) MPU interface (RM=0) RGB interface (RM=1) Display Operation Mode (DM[1:0]) Internal clock operation (DM[1:0]=00) RGB interface : VS & HS (DM[1:0]=01) MPU interface (RM=0) RGB interface : VS & HS (DM[1:0]=01) Bypass frame memory RGB interface (RM=1) RGB interface : VS & HS (DM[1:0]=11) Internal clock operation (DM[1:0]=00) Note: RGB interface capture mode is only for 24-bit / pixel color order. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.48October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2.2.2 16-bit / pixel color order on the DPI I/F Note: The data order is shown as follows, MSB=DB23, LSB=DB0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0 for Red and Blue data. Un-used pin DB23, DB22, DB16, DB15, DB14, DB7, DB6 and DB0 are set to open. Figure 4.30: 16-bit / pixel 65K colours order on the DPI I/F Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.49October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2.2.3 18--bit / pixel color order on the DPI I/F Note: The Data order is shown as follows, MSB = DB23, LSB = DB0 and Picture Data is MSB = Bit5, LSB = Bit0 for Red, Green and Blue data. Un-used pin DB23, DB22, DB15, DB14, DB7 and DB6 are set to open. Figure 4.31: 18-bit / pixel: 262k colours order on the DPI I/F Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.50October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 4.2.2.4 24--bit / pixel color order on the RGB I/F Note: The Data order is shown as follows, MSB = DB23, LSB = DB0 and Picture Data is MSB = Bit7, LSB = Bit0 for Red, Green and Blue data. Figure 4.32: 24-bit / pixel color order on the RGB I/F Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.51October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5. Function Description 5.1 Display data GRAM HX8369-A00 support the display data RAM that stores display dots and consists of 9,953,280 bits (480x864x24 bits). There is no restriction on access to the RAM even when the display data on the same address is loaded to DAC There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. 5.2 Address counter (AC) The HX8369-A00 contains an address counter (AC) which assigns address for writing/reading pixel data to/from GRAM. The address pointers set the position of GRAM whose addresses range: RES_SEL2 RES_SEL 1 RES_SEL 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 MV 0 1 0 1 0 1 0 1 0 1 0 1 X range 0~479d. 0~863d. 0~479d.. 0~853d. 0~479d. 0~799d. 0~479d. 0~639d. 0~359d. 0~639d. 0~479d. 0~719d. Y range 0~863d. 0~479d. 0~853d. 0~479d. 0~799d. 0~479d. 0~639d. 0~479d. 0~639d. 0~359d. 0~719d. 0~479d. Panel resolution 480RGBX864 dot 480RGBX854 dot 480RGBX800 dot 480RGBX640 dot 360 RGBX640 dot 480RGBX720 dot Table 5.1: Addresses counter range Every time when a pixel data is written into the GRAM, the X address or Y address of AC will be automatically increased by 1 (or decreased by 1), which is decided by the register (MV, MX and MY bit) setting. To simplify the address control of GRAM access, the window address function allows for writing data only to a window area of GRAM specified by registers. After data is written to the GRAM, the AC will be increased or decreased within setting window address-range which is specified by the Column address register (start: SC, end: EC) or the Row address register (start: SP, end: EP). Therefore, the data can be written consecutively without thinking a data wrap by those bit function. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.52October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.3 Source, gate and memory map 480RGB x 864 resolution --- S1435 S1436 S1437 S1438 S1439 S1440 RGB=1 S6 RGB=0 S5 RGB=1 S4 RGB=0 RA S3 RGB=1 S2 RGB=0 S1 RGB=0 Source Out RGB=1 5.3.1 SA MY=0 MY=1 0 1 863 862 2 861 3 860 4 859 5 858 6 857 7 856 8 9 855 : : : : : : : : --------------------: : : : : : : : : : : : : : : : : : : : : : : 7 857 858 6 5 859 4 860 3 861 2 1 863 CA G0 7-0 B0 7-0 R1 7-0 G1 7-0 B1 7-0 854 856 862 R0 7-0 0 MX=0 0 MX=1 479 1 478 R478 7-0 G478 7-0 B478 7-0 R479 7-0 G479 7-0 B479 7-0 ML=0 ML=1 0 1 863 862 2 861 860 3 4 5 859 858 6 857 7 856 8 9 855 854 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : --------------------- : : : : : : 478 479 1 0 : : 856 7 857 858 6 5 859 4 860 3 861 862 2 1 863 0 Note:RA=Row Address CA=Colum Address SA=Scan Address MX=Colum address direction parameter MY=Row address direction parameter ML=Scan direction parameter RGB=Red,Green and Blue pixel position change Table 5.2: Memory map of 480RGB x 864 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.53October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 480RGB x 854 resolution --- S1435 S1436 S1437 S1438 S1439 S1440 RGB=1 S6 RGB=0 S5 RGB=1 S4 RGB=0 RA S3 RGB=1 S2 RGB=0 S1 RGB=0 Source Out RGB=1 5.3.2 SA MY=0 MY=1 0 1 853 852 2 851 3 850 4 849 5 848 6 847 7 846 8 9 845 : : : : : : : : --------------------: : : : : : : : : : : : : : : : : : : : : : : 7 847 848 6 5 849 4 850 3 851 2 1 853 CA G0 7-0 B0 7-0 R1 7-0 G1 7-0 B1 7-0 844 846 852 R0 7-0 0 MX=0 0 MX=1 479 1 478 R478 7-0 G478 7-0 B478 7-0 R479 7-0 G479 7-0 B479 7-0 ML=0 ML=1 0 1 853 852 2 851 850 3 4 5 849 848 6 847 7 846 8 9 845 844 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : --------------------- : : : : : : 478 479 1 0 : : 846 7 847 848 6 5 849 4 850 3 851 852 2 1 853 0 Note:RA=Row Address CA=Colum Address SA=Scan Address MX=Colum address direction parameter MY=Row address direction parameter ML=Scan direction parameter RGB=Red,Green and Blue pixel position change Table 5.3: Memory map of 480RGB x 854 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.54October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 480RGB x 800 resolution --- S1435 S1436 S1437 S1438 S1439 S1440 RGB=1 S6 RGB=0 S5 RGB=1 S4 RGB=0 RA S3 RGB=1 S2 RGB=0 S1 RGB=0 Source Out RGB=1 5.3.3 SA MY=0 MY=1 5 795 794 6 793 7 792 8 9 791 790 : : : : : : : : --------------------: : : : : : : : : : : : : : : : : : : : : 0 1 799 798 2 797 796 3 4 : : 792 7 793 794 6 5 795 4 796 3 797 2 1 798 799 CA R0 7-0 G0 7-0 B0 7-0 R1 7-0 G1 7-0 B1 7-0 0 MX=0 0 MX=1 479 1 478 R478 7-0 G478 7-0 B478 7-0 R479 7-0 G479 7-0 B479 7-0 ML=0 ML=1 0 1 799 798 2 797 796 3 4 5 795 794 6 793 7 792 8 9 791 790 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : --------------------- : : : : : : 478 479 1 0 : : 792 7 793 794 6 5 795 4 796 3 797 798 2 1 799 0 Note:RA=Row Address CA=Colum Address SA=Scan Address MX=Colum address direction parameter MY=Row address direction parameter ML=Scan direction parameter RGB=Red,Green and Blue pixel position change Table 5.4: Memory map of 480RGB x 800 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.55October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 480RGB x 640 resolution --- S1435 S1436 S1437 S1438 S1439 S1440 RGB=1 S6 RGB=0 S5 RGB=1 S4 RGB=0 RA S3 RGB=1 S2 RGB=0 S1 RGB=0 Source Out RGB=1 5.3.4 SA MY=0 MY=1 0 1 639 2 637 3 636 4 635 5 634 6 633 7 632 8 9 631 : : : : : : : : --------------------: : : : : : : : : : : : : : : : : : : : : : 7 633 634 6 5 635 4 636 3 637 2 1 CA R1 7-0 G1 7-0 B1 7-0 630 : 639 G0 7-0 B0 7-0 638 632 638 R0 7-0 0 MX=0 0 MX=1 479 1 478 R478 7-0 G478 7-0 B478 7-0 R479 7-0 G479 7-0 B479 7-0 ML=0 ML=1 0 1 639 2 637 3 636 4 635 5 634 6 633 7 632 8 9 631 638 630 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : --------------------- : : : : : : 478 479 1 0 : : 632 7 633 634 6 5 635 4 636 3 637 638 2 1 639 0 Note:RA=Row Address CA=Colum Address SA=Scan Address MX=Colum address direction parameter MY=Row address direction parameter ML=Scan direction parameter RGB=Red,Green and Blue pixel position change Table 5.5: Memory map of 480RGB x 640 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.56October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 360RGB x 640 resolution --- S1435 S1436 S1437 S1438 S1439 S1440 RGB=1 S6 RGB=0 S5 RGB=1 S4 RGB=0 RA S3 RGB=1 S2 RGB=0 S1 RGB=0 Source Out RGB=1 5.3.5 SA MY=0 MY=1 0 1 639 2 637 3 636 4 635 5 634 6 633 7 632 8 9 631 : : : : : : : : --------------------: : : : : : : : : : : : : : : : : : : : : : 7 633 634 6 5 635 4 636 3 637 2 1 CA R1 7-0 G1 7-0 B1 7-0 630 : 639 G0 7-0 B0 7-0 638 632 638 R0 7-0 0 MX=0 0 MX=1 359 1 358 R358 7-0 G358 7-0 B358 7-0 R359 7-0 G359 7-0 B359 7-0 ML=0 ML=1 0 1 639 2 637 3 636 4 635 5 634 6 633 7 632 8 9 631 638 630 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : --------------------- : : : : : : 358 359 1 0 : : 632 7 633 634 6 5 635 4 636 3 637 638 2 1 639 0 Note:RA=Row Address CA=Colum Address SA=Scan Address MX=Colum address direction parameter MY=Row address direction parameter ML=Scan direction parameter RGB=Red,Green and Blue pixel position change Table 5.6: Memory map of 360RGB x640 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.57October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 480RGB x 720 resolution --- S1435 S1436 S1437 S1438 S1439 S1440 RGB=1 S6 RGB=0 S5 RGB=1 S4 RGB=0 RA S3 RGB=1 S2 RGB=0 S1 RGB=0 Source Out RGB=1 5.3.6 SA MY=0 MY=1 5 715 714 6 713 7 712 8 9 711 710 : : : : : : : : --------------------: : : : : : : : : : : : : : : : : : : : : 0 1 719 718 2 717 716 3 4 : : 712 7 713 714 6 5 715 4 716 3 717 2 1 718 719 CA R0 7-0 G0 7-0 B0 7-0 R1 7-0 G1 7-0 B1 7-0 0 MX=0 0 MX=1 479 1 478 R478 7-0 G478 7-0 B478 7-0 R479 7-0 G479 7-0 B479 7-0 ML=0 ML=1 0 1 719 718 2 717 716 3 4 5 715 714 6 713 7 712 8 9 711 710 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : --------------------- : : : : : : 478 479 1 0 : : 712 7 713 714 6 5 715 4 716 3 717 718 2 1 719 0 Note:RA=Row Address CA=Colum Address SA=Scan Address MX=Colum address direction parameter MY=Row address direction parameter ML=Scan direction parameter RGB=Red,Green and Blue pixel position change Table 5.7: Memory map of 480RGB x 720 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.58October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.4 MCU to memory write / read direction Data stream from MCU is like this figure B E Figure 5.1: MCU to Memory write / read direction The data is written in the order as illustrated above. The counter that dictates which physical memory the data is to be written is controlled by “Memory Access Control” Command, Bits MY, MX, MV as described below. Physical Row Pointer MV MX MY Figure 5.2: MY, MX, MV setting of 480RGB x 864 dot MV 0 MX 0 MY 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 CASET Direct to Physical Column Pointer PASET Direct to Physical Row Pointer Direct to (863-Physical Row Pointer) Direct to Physical Column Pointer with SC Direct to (479-Physical Column Pointer) Direct to Physical Row Pointer Direct to (479-Physical Column Pointer) Direct to (863-Physical Row Pointer) Direct to Physical Row Pointer Direct to Physical Column Pointer Direct to (863-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Row Pointer Direct to (479-Physical Column Pointer) Direct to (863-Physical Row Pointer) Direct to (479-Physical Column Pointer) Figure 5.3: MY, MX, MV setting of 480RGB x 864 dot Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.59October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 The following figure depicts the update method set by MV, MX and MY bit. Display Data Direction Memory Access Control MV MX MY Image in the Host H/W Position (0,0) B Normal 0 0 Image in the Driver (GRAM) B X,Y address (0,0) X: CASET Y: RASET 0 E E B Y-Mirror 0 0 E H/W Position (0,0) 1 E X,Y address (0,0) X: CASET Y: RASET B B X-Mirror 0 1 0 E B X-Mirror Y-Mirror 0 1 1 E B X-Y Exchange 1 0 H/W Position (0,0) B X,Y address (0,0) X: CASET Y: RASET 0 E E B X-Y Exchange Y-Mirror 1 0 H/W Position (0,0) 1 X,Y address (0,0) X: CASET Y: RASET E B X-Y Exchange X-Mirror 1 1 H/W Position (0,0) B 1 1 B B X,Y address (0,0) X: CASET Y: RASET 0 E E X-Y Exchange X-Mirror Y-Mirror E H/W Position (0,0) E 1 E B X,Y address (0,0) X: CASET Y: RASET Figure 5.4: Address direction settings Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.60October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.5 Fully display, partial display, vertical scrolling display 5.5.1 Fully display Example: (1) 480RGBx864 dot display mode. (2) NORON (Normal Display Mode On) instruction (R13h). (3) SC=0x000h, EC=0x1DFh (R2Ah) and SP=0x000h, EP=0x35Fh (R2Bh), ML=0. ------35A000H 35B000H 35C000H 35D000H 35E000H 35F000H --------------------------------------------------------- 1DEh DB---DB 23 ---0 0001DEH 0011DEH 0021DEH 0031DEH 0041DEH 0051DEH 1DFh DB---DB 23 ---0 0001DFH 0011DFH 0021DFH 0031DFH 0041DFH 0051DFH --------- ------- ------35Ah 35Bh 35Ch 35Dh 35Eh 35Fh --------- ------- 001h DB---DB 23 ---0 000001H 001001H 002001H 003001H 004001H 005001H ------- 000h 001h 002h 003h 004h 005h 000h DB---DB 23 ---0 000000H 001000H 002000H 003000H 004000H 005000H GRAM 35A001H 35B001H 35C001H 35D001H 35E001H 35F001H ------------------------------------------------- 35A1DEH 35B1DEH 35C1DEH 35D1DEH 35E1DEH 35F1DEH 35A1DFH 35B1DFH 35C1DFH 35D1DFH 35E1DFH 35F1DFH Table 5.8: 480RGB x 864 resolution (SRAM assignment) 480 columns 21 22 23 30 31 32 0V 0W 0X 0Y 0Z 00h 00 01 02 03 04 1W 1X 1Y 1Z 01h 10 11 12 13 14 2X 2Y 2Z 20 21 22 23 3Y 3Z 30 31 32 864lines 864lines 480 x 864 x24bit Frame memory W0 W1 35Dh X0 X1 X2 35Eh Y0 Y1 Y2 35Fh Z0 Z1 Z2 Y3 Z3 Z4 Z5 05 ZV 0V 1DFh 20 05 1DEh 14 1DDh 04 13 01h 03 12 00h 02 11 1DFh 01 10 1DEh 01h 00 01h 1DDh 00h 00h 0W 0X 0Y 0Z 1W 1X 1Y 1Z 2X 2Y 2Z 3Y 3Z 480 x 864 LCD panel WX WY WZ W0 W1 XW XX XY XZ 35Dh X0 X1 X2 YW YX YY YZ 35Eh Y0 Y1 Y2 Y3 ZW ZX ZY ZZ 35Fh Z0 Z1 Z2 Z3 Z4 Z5 ZV WX WY WZ XW XX XY XZ YW YX YY YZ ZW ZX ZY ZZ 480 columns Figure 5.5: 480RGB x 864 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.61October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example: (1) 480RGBx854 dot display mode. (2) NORON (Normal Display Mode On) instruction (R13h). (3) SC=0x000h, EC=0x1DFh (R2Ah) and SP=0x000h, EP=0x355h (R2Bh), ML=0. 000h GRAM 001h DB---DB --------- DB---DB 1DEh 1DFh DB---DB DB---DB 23 ---0 23 ---0 0001DEH 0011DEH 0021DEH 0031DEH 0041DEH 0051DEH 0001DFH 0011DFH 0021DFH 0031DFH 0041DFH 0051DFH --------23 ---0 23 ---0 000h 001h 002h 003h 004h 005h 000000H 001000H 002000H 003000H 004000H 005000H 000001H 001001H 002001H 003001H 004001H 005001H ------------------------------------------------- ------- ------- ------- --------- ------- ------- 350h 351h 352h 353h 354h 355h 350000H 351000H 352000H 353000H 354000H 355000H 350001H 351001H 352001H 353001H 354001H 355001H ------------------------------------------------- 3501DEH 3511DEH 3521DEH 3531DEH 3541DEH 3551DEH 3501DFH 3511DFH 3521DFH 3531DFH 3541DFH 3551DFH Table 5.9: 480RGB x 854 resolution (SRAM assignment) 1DFh 1DEh 1DDh 01h 00h 1DFh 1DEh 1DDh 01h 00h 854 lines 854 lines Figure 5.6: 480RGB x 854 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.62October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example: (1) 480RGBx800 dot display mode. (2) NORON (Normal Display Mode On) instruction (R13h). (3) SC=0x000h, EC=0x1DFh (R2Ah) and SP=0x000h, EP=0x31Fh (R2Bh), ML=0. ------31A000H 31B000H 31C000H 31D000H 31E000H 31F000H --------------------------------------------------------- 1DEh DB---DB 23 ---0 0001DEH 0011DEH 0021DEH 0031DEH 0041DEH 0051DEH 1DFh DB---DB 23 ---0 0001DFH 0011DFH 0021DFH 0031DFH 0041DFH 0051DFH --------- ------- ------31Ah 31Bh 31Ch 31Dh 31Eh 31Fh --------- ------- 001h DB---DB 23 ---0 000001H 001001H 002001H 003001H 004001H 005001H ------- 000h 001h 002h 003h 004h 005h 000h DB---DB 23 ---0 000000H 001000H 002000H 003000H 004000H 005000H GRAM 31A001H 31B001H 31C001H 31D001H 31E001H 31F001H ------------------------------------------------- 31A1DEH 31B1DEH 31C1DEH 31D1DEH 31E1DEH 31F1DEH 31A1DFH 31B1DFH 31C1DFH 31D1DFH 31E1DFH 31F1DFH Table 5.10: 480RGB x 800 resolution (SRAM assignment) Figure 5.7: 480RGB x 800 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.63October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example: (1) 480RGBx640 dot display mode. (2) NORON (Normal Display Mode On) instruction (R13h). (3) SC=0x000h, EC=0x1DFh (R2Ah) and SP=0x000h, EP=0x27Fh (R2Bh), ML=0. ------27A000H 27B000H 27C000H 27D000H 27E000H 27F000H 1DEh DB---DB 23 ---0 0001DEH 0011DEH 0021DEH 0031DEH 0041DEH 0051DEH --------------------------------------------------------- 1DFh DB---DB 23 ---0 0001DFH 0011DFH 0021DFH 0031DFH 0041DFH 0051DFH --------- ------- ------27Ah 27Bh 27Ch 27Dh 27Eh 27Fh --------- ------- 001h DB---DB 23 ---0 000001H 001001H 002001H 003001H 004001H 005001H ------- 000h 001h 002h 003h 004h 005h 000h DB---DB 23 ---0 000000H 001000H 002000H 003000H 004000H 005000H GRAM 27A001H 27B001H 27C001H 27D001H 27E001H 27F001H ------------------------------------------------- 27A1DEH 27B1DEH 27C1DEH 27D1DEH 27E1DEH 27F1DEH 27A1DFH 27B1DFH 27C1DFH 27D1DFH 27E1DFH 27F1DFH Table 5.11: 480RGB x 640 resolution (SRAM assignment) 1DFh 1DEh 1DDh 01h 00h 1DFh 1DEh 1DDh 01h 00h 640lines 640lines Figure 5.8: 480RGB x 640 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.64October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example: (1) 360RGBx640 dot display mode. (2) NORON (Normal Display Mode On) instruction (R13h). (3) SC=0x000h, EC=0x167h (R2Ah) and SP=0x000h, EP=0x27Fh (R2Bh), ML=0. ------27A000H 27B000H 27C000H 27D000H 27E000H 27F000H --------------------------------------------------------- 166h DB---DB 23 ---0 000166H 001166H 002166H 003166H 004166H 005166H 167h DB---DB 23 ---0 000167H 001167H 002167H 003167H 004167H 005167H --------- ------- ------27Ah 27Bh 27Ch 27Dh 27Eh 27Fh --------- ------- 001h DB---DB 23 ---0 000001H 001001H 002001H 003001H 004001H 005001H ------- 000h 001h 002h 003h 004h 005h 000h DB---DB 23 ---0 000000H 001000H 002000H 003000H 004000H 005000H GRAM 27A001H 27B001H 27C001H 27D001H 27E001H 27F001H ------------------------------------------------- 27A166H 27B166H 27C166H 27D166H 27E166H 27F166H 27A167H 27B167H 27C167H 27D167H 27E167H 27F167H Table 5.12: 360RGB x 640 resolution (SRAM assignment) Figure 5.9: 360RGB x 640 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.65October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example: (1) 480RGBx720 dot display mode. (2) NORON (Normal Display Mode On) instruction (R13h). (3) SC=0x000h, EC=0x1DFh (R2Ah) and SP=0x000h, EP=0x2CFh (R2Bh), ML=0. ------2CA000H 2CB000H 2CC000H 2CD000H 2CE000H 2CF000H --------------------------------------------------------- 1DEh DB---DB 23 ---0 0001DEH 0011DEH 0021DEH 0031DEH 0041DEH 0051DEH 1DFh DB---DB 23 ---0 0001DFH 0011DFH 0021DFH 0031DFH 0041DFH 0051DFH --------- ------- ------2CAh 2CBh 2CCh 2CDh 2CEh 2CFh --------- ------- 001h DB---DB 23 ---0 000001H 001001H 002001H 003001H 004001H 005001H ------- 000h 001h 002h 003h 004h 005h 000h DB---DB 23 ---0 000000H 001000H 002000H 003000H 004000H 005000H GRAM 2CA001H 2CB001H 2CC001H 2CD001H 2CE001H 2CF001H ------------------------------------------------- 2CA1DEH 2CB1DEH 2CC1DEH 2CD1DEH 2CE1DEH 2CF1DEH 2CA1DFH 2CB1DFH 2CC1DFH 2CD1DFH 2CE1DFH 2CF1DFH Table 5.13: 480RGB x 720 resolution (SRAM assignment) Figure 5.10: 480RGB x 720 resolution Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.66October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.5.2 Vertical scrolling display The vertical scrolling display is specified by VSCRDEF instruction (R33h) and VSCRSADD instruction (R37h). Original Scrolling TFA VSA BFA Figure 5.11: Vertical scrolling When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=Panel total scan lines. In this case, scrolling is applied as shown below. 5.5.2.1 Example: 480RGB X 864 When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=864. In this case, scrolling is applied as shown below. Example (1) TFA=2, VSA=862, BFA=0 when MADCTL B4=0 Figure 5.12: Memory map of vertical scrolling 1 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.67October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example (2) TFA=2, VSA=860, BFA=2 when MADCTL B4=0 Figure 5.13: Memory map of vertical scrolling 2 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.68October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.5.2.2 Vertical scroll example There are 2 types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h). Case 1: TFA + VSA + BFA≠864 Do not set TFA + VSA + BFA≠864. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=864 (Scrolling) Example (1) When TFA=0, VSA=864, BFA=0 and VSCRSADD=40.MADCTL parameter B4=”0” P h y s ic a l L in e P o in t e r M e m o r y P h ysica l A x is (0 ,0 ) D isp la y A xis ( 0 , 0 ) 2 1 V S CRS A DD 1 2 F ra m e M e m o ry D is p la y In cr e m e n t V S CRS A DD P h y s ic a l L in e P o in t e r D isp la y A xis ( 0 ,0 ) 2 1 1 2 V S CRS A DD D is p la y F ra m e M e m o ry Figure 5.14: Vertical scroll example 1 Example (2) TFA=30, VSA=834, BFA=0 and VSCRSADD =80. MADCTRL parameter B4=”1” Physical Line Pointer Memory Physical Axis (0,0) Display Axis (0,0) 2 3 3 2 VSCRSADD Frame Memory Display Increment VSCRSADD Physical Line Pointer Memory Physical Axis (0,0) TFA 1 1 TFA Display Axis (0,0) 2 3 VSCRSADD 3 2 1 1 TFA Frame Memory TFA Display Figure 5.15: Vertical scroll example 2 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.69October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.5.3 Tearing effect output line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: tvdl tvdh Figure 5.16: Tearing effect output line–mode 1 tvdh=The LCD display is not updated from the Frame Memory tvdl=The LCD display is updated from the Frame Memory (except Invisible Line – see below) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and N H-sync pulses per field. N: If RES_SEL [2:0] set to = 3’b000, the resolution is 480 RGB X 864, the N=864. Figure 5.17: Tearing effect output line–mode 2 thdh=The LCD display is not updated from the Frame Memory thdl=The LCD display is updated from the Frame Memory (except Invisible Line – see above) Bottom Line Top Line 2nd Line TE (Mode 2) TE (Mode 1) tvdh Note: During Sleep In Mode, the Tearing Output Pin is active Low. Figure 5.18: Tearing effect output line–timing diagrm Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.70October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.5.3.1 Tearing effect line timing The Tearing Effect signal is described below: tvdl tvdh Vertical Timing Horizontal Timing thdl thdh Figure 5.19: Tearing effect output line –tearing effect line timing Idle Mode Off (Resolution 480x800 RGB, Frame Rate = 60.5 Hz) Symbol tvdl tvdh thdl thdh tr tf Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing High Duration Rise time Fall time Min. 15 1000 18 0.13 - Max. 500 15 15 Unit ms us us us ns ns Note: The timings in Table 5.13 apply when MADCTL ML=0 and ML=1 Table 5.14: AC characteristics of tearing effect signal The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. tr tf 0.8*VDD1 0.2*VDD1 0.8*VDD1 0.2*VDD1 Figure 5.20: Tearing effect output line–definition of tf, tr Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.71October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect. Example 1: MPU write is faster than panel read. Figure 5.21: Tearing effect output line–example 1 (Timing) Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: Data to be sent a b c d Image on LCD Figure 5.22: Tearing effect output line–example 1 (Image) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.72October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Example 2: MPU write is slower than panel read. MCU to Memory 1st Time 864th TE output signal Time Memory to LCD Time 1st a Image on LCD 864th b c d e f Figure 5.23: Tearing effect output line–example 2 (Timing) The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. Data to be sent a b c d e f Image on LCD Figure 5.24: Tearing effect output line–example 2 (Image) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.73October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.6 Color depth conversion 5.6.1 Color depth conversion Look-up tables R input (5-bit) 16-bit / pixel mode 65,536 colours 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 R input (6-bit) R output (8-bit) 18-bit / pixel 24-bit / pixel mode mode 262,144 16,777,216 colours colours 000000 R007 R006R005 R004R003R002R001R000 000001 R017R016R015R014R013R012R011R010 000010 R027R026R025R024R023R022R021R020 000011 R037R036R035R034R033R032R031R030 000100 R047R046R045R044R043R042R041R040 000101 R057R056R055R054R053R052R051R050 000110 R067R066R065R064R063R062R061R060 000111 R077R076R075R074R073R072R071R070 001000 R087R086R085R084R083R082R081R080 001001 R097R096R095R094R093R092R091R090 001010 R107R106R105R104R103R102R101R100 001011 R117R116R115R114R113R112R111R110 001100 R127R126R125R124R123R122R121R120 001101 R137R136R135R134R133R132R131R130 001110 R147R146R145R144R143R142R141R140 001111 R157R156R155R154R153R152R151R150 010000 R167 R166R165 R164R163R162R161R160 010001 R177R176R175R174R173R172R171R170 010010 R187R186R185R184R183R182R181R180 010011 R197R196R195R194R193R192R191R190 010100 R207R206R205R204R203R202R201R200 010101 R217R216R215R214R213R212R211R210 010110 R227R226R225R224R223R222R221R220 010111 R237R236R235R234R233R232R231R230 011000 R247R246R245R244R243R242R241R240 011001 R257R256R255R254R253R252R251R250 011010 R267R266R265R264R263R262R261R260 011011 R277R276R275R274R273R272R271R270 011100 R287R286R285R284R283R282R281R280 011101 R297R296R295R294R293R292R291R290 011110 R307R306R305R304R303R302R301R300 011111 R317R316R315R314R313R312R311R310 Table 5.15: Look-up tables-1 RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.74October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 R input (5-bit) 16-bit / pixel mode 65,536 colours No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input R input (6-bit) R output (8-bit) 18-bit / pixel 24-bit / pixel mode mode 262,144 16,777,216 colours colours 100000 R327 R326R325 R324R323R322R321R320 100001 R337R336R335R334R333R332R331R330 100010 R347R346R345R344R343R342R341R340 100011 R357R356R355R354R353R352R351R350 100100 R367R366R365R364R363R362R361R360 100101 R377R376R375R374R373R372R371R370 100110 R387R386R385R384R383R382R381R380 100111 R397R396R395R394R393R392R391R390 101000 R407R406R405R404R403R402R401R400 101001 R417R416R415R414R413R412R411R410 101010 R427R426R425R424R423R422R421R420 101011 R437R436R435R434R433R432R431R430 101100 R447R446R445R444R443R442R441R440 101101 R457R456R455R454R453R452R451R450 101110 R467R466R465R464R463R462R461R460 101111 R477R476R475R474R473R472R471R470 110000 R487 R486R485 R484R483R482R481R480 110001 R497R496R495R494R493R492R491R490 110010 R507R506R505R504R503R502R501R500 110011 R517R516R515R514R513R512R511R510 110100 R527R526R525R524R523R522R521R520 110101 R537R536R535R534R533R532R531R530 110110 R547R546R545R544R543R542R541R540 110111 R557R556R555R554R553R552R551R550 111000 R567R566R565R564R563R562R561R560 111001 R577R576R575R574R573R572R571R570 111010 R587R586R585R584R583R582R581R580 111011 R597R596R595R594R593R592R591R590 111100 R607R606R605R604R603R602R601R600 111101 R617R616R615R614R613R612R611R610 111110 R627R626R625R624R623R622R621R620 111111 R637R636R635R634R633R632R631R630 Table 5.16: Look-up tables-2 RGBSET Parameter 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.75October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 G input (5-bit) 16-bit / pixel mode 65,536 colours 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 G input (6-bit) G output (8-bit) 18-bit / pixel 24-bit / pixel mode mode 262,144 16,777,216 colours colours 000000 G007 G006G005 G004G003G002G001G000 000001 G017G016G015G014G013G012G011G010 000010 G027G026G025G024G023G022G021G020 000011 G037G036G035G034G033G032G031G030 000100 G047G046G045G044G043G042G041G040 000101 G057G056G055G054G053G052G051G050 000110 G067G066G065G064G063G062G061G060 000111 G077G076G075G074G073G072G071G070 001000 G087G086G085G084G083G082G081G080 001001 G097G096G095G094G093G092G091G090 001010 G107G106G105G104G103G102G101G100 001011 G117G116G115G114G113G112G111G110 001100 G127G126G125G124G123G122G121G120 001101 G137G136G135G134G133G132G131G130 001110 G147G146G145G144G143G142G141G140 001111 G157G156G155G154G153G152G151G150 010000 G167 G166G165 G164G163G162G161G160 010001 G177G176G175G174G173G172G171G170 010010 G187G186G185G184G183G182G181G180 010011 G197G196G195G194G193G192G191G190 010100 G207G206G205G204G203G202G201G200 010101 G217G216G215G214G213G212G211G210 010110 G227G226G225G224G223G222G221G220 010111 G237G236G235G234G233G232G231G230 011000 G247G246G245G244G243G242G241G240 011001 G257G256G255G254G253G252G251G250 011010 G267G266G265G264G263G262G261G260 011011 G277G276G275G274G273G272G271G270 011100 G287G286G285G284G283G282G281G280 011101 G297G296G295G294G293G292G291G290 011110 G307G306G305G304G303G302G301G300 011111 G317G316G315G314G313G312G311G310 Table 5.17: Look-up tables-3 RGBSET Parameter 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.76October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 G input (5-bit) 16-bit / pixel mode 65,536 colours 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 G input (6-bit) G output (8-bit) 18-bit / pixel 24-bit / pixel mode mode 262,144 16,777,216 colours colours 100000 G327 G326G325 G324G323G322G321G320 100001 G337G336G335G334G333G332G331G330 100010 G347G346G345G344G343G342G341G340 100011 G357G356G355G354G353G352G351G350 100100 G367G366G365G364G363G362G361G360 100101 G377G376G375G374G373G372G371G370 100110 G387G386G385G384G383G382G381G380 100111 G397G396G395G394G393G392G391G390 101000 G407G406G405G404G403G402G401G400 101001 G417G416G415G414G413G412G411G410 101010 G427G426G425G424G423G422G421G420 101011 G437G436G435G434G433G432G431G430 101100 G447G446G445G444G443G442G441G440 101101 G457G456G455G454G453G452G451G450 101110 G467G466G465G464G463G462G461G460 101111 G477G476G475G474G473G472G471G470 110000 G487 G486G485 G484G483G482G481G480 110001 G497G496G495G494G493G492G491G490 110010 G507G506G505G504G503G502G501G500 110011 G517G516G515G514G513G512G511G510 110100 G527G526G525G524G523G522G521G520 110101 G537G536G535G534G533G532G531G530 110110 G547G546G545G544G543G542G541G540 110111 G557G556G555G554G553G552G551G550 111000 G567G566G565G564G563G562G561G560 111001 G577G576G575G574G573G572G571G570 111010 G587G586G585G584G583G582G581G580 111011 G597G596G595G594G593G592G591G590 111100 G607G606G605G604G603G602G601G600 111101 G617G616G615G614G613G612G611G610 111110 G627G626G625G624G623G622G621G620 111111 G637G636G635G634G633G632G631G630 Table 5.18: Look-up tables-4 RGBSET Parameter 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.77October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 B input (5-bit) 16-bit / pixel mode 65,536 colours 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 B input (6-bit) B output (8-bit) 18-bit / pixel 24-bit / pixel mode mode 262,144 16,777,216 colours colours 000000 B007 B006B005 B004B003B002B001B000 000001 B017B016B015B014B013B012B011B010 000010 B027B026B025B024B023B022B021B020 000011 B037B036B035B034B033B032B031B030 000100 B047B046B045B044B043B042B041B040 000101 B057B056B055B054B053B052B051B050 000110 B067B066B065B064B063B062B061B060 000111 B077B076B075B074B073B072B071B070 001000 B087B086B085B084B083B082B081B080 001001 B097B096B095B094B093B092B091B090 001010 B107B106B105B104B103B102B101B100 001011 B117B116B115B114B113B112B111B110 001100 B127B126B125B124B123B122B121B120 001101 B137B136B135B134B133B132B131B130 001110 B147B146B145B144B143B142B141B140 001111 B157B156B155B154B153B152B151B150 010000 B167 B166B165 B164B163B162B161B160 010001 B177B176B175B174B173B172B171B170 010010 B187B186B185B184B183B182B181B180 010011 B197B196B195B194B193B192B191B190 010100 B207B206B205B204B203B202B201B200 010101 B217B216B215B214B213B212B211B210 010110 B227B226B225B224B223B222B221B220 010111 B237B236B235B234B233B232B231B230 011000 B247B246B245B244B243B242B241B240 011001 B257B256B255B254B253B252B251B250 011010 B267B266B265B264B263B262B261B260 011011 B277B276B275B274B273B272B271B270 011100 B287B286B285B284B283B282B281B280 011101 B297B296B295B294B293B292B291B290 011110 B307B306B305B304B303B302B301B300 011111 B317B316B315B314B313B312B311B310 Table 5.19: Look-up tables-5 RGBSET Parameter 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.78October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 B input (5-bit) 16-bit / pixel mode 65,536 colours No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input No Input B input (6-bit) B output (8-bit) 18-bit / pixel 24-bit / pixel mode mode 262,144 16,777,216 colours colours 100000 B327 B326B325 B324B323B322B321B320 100001 B337B336B335B334B333B332B331B330 100010 B347B346B345B344B343B342B341B340 100011 B357B356B355B354B353B352B351B350 100100 B367B366B365B364B363B362B361B360 100101 B377B376B375B374B373B372B371B370 100110 B387B386B385B384B383B382B381B380 100111 B397B396B395B394B393B392B391B390 101000 B407B406B405B404B403B402B401B400 101001 B417B416B415B414B413B412B411B410 101010 B427B426B425B424B423B422B421B420 101011 B437B436B435B434B433B432B431B430 101100 B447B446B445B444B443B442B441B440 101101 B457B456B455B454B453B452B451B450 101110 B467B466B465B464B463B462B461B460 101111 B477B476B475B474B473B472B471B470 110000 B487 B486B485 B484B483B482B481B480 110001 B497B496B495B494B493B492B491B490 110010 B507B506B505B504B503B502B501B500 110011 B517B516B515B514B513B512B511B510 110100 B527B526B525B524B523B522B521B520 110101 B537B536B535B534B533B532B531B530 110110 B547B546B545B544B543B542B541B540 110111 B557B556B555B554B553B552B551B550 111000 B567B566B565B564B563B562B561B560 111001 B577B576B575B574B573B572B571B570 111010 B587B586B585B584B583B582B581B580 111011 B597B596B595B594B593B592B591B590 111100 B607B606B605B604B603B602B601B600 111101 B617B616B615B614B613B612B611B610 111110 B627B626B625B624B623B622B621B620 111111 B637B636B635B634B633B632B631B630 Table 5.20: Look-up tables-6 RGBSET Parameter 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.79October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.7 Oscillator The HX8369-A00 can oscillate an internal R-C oscillator with an internal oscillation resistor (Rf). The oscillation frequency is changed according to the UADJ[3:0] internal register. Please refer to OSC control register (RB0h). The default frequency is 15MHz. RGB Display Mode PCLK Display Controller Internal Display Mode Oscillator Clock 15MHz 15MHz fosc UADJ[ UADJ[3:0] Frequency Divider 2 FS1 FS1[1:0] Step up Circuit ( for VGH, VGH,VGL) VGL) PCLK RGB Display Mode CABC_ CABC_PWM_ PWM_CLK (for Backlight CABC) CABC) Figure 5.25: OSC aritecture Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.80October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.8 Source driver The HX8369-A00 contains a 1440 channels of source driver (normal S1~S1440; Zig-zag S1~S1441) which is used for driving the source line of TFT LCD panel. The source driver converts the digital data from GRAM into the analog voltage for 1440 channels and generates corresponding gray scale voltage output, which can realize a 16.7M colors display simultaneously. Since the output circuit of this source driver incorporates an operational amplifier, a positive and a negative voltage can be alternately outputted from each channel. Column inversion Normal type Date Line #1 Date Line #2 Date Line #3 1 Date Line #1438 3 2 ... Date Line #1439 1438 Date Line #1 Date Line #1440 1439 ZigZag type Date Line #2 1 1440 Gate#1 Date Line #3 Date Line #1438 3 2 2 3 1 2 3 1 2 3 ... 1438 1439 Date Line #1440 Date Line #1441 1438 1439 1440 1439 1440 1441 1438 1439 1440 1439 1440 1441 ... Gate#1 1 Date Line #1439 1440 2 3 4 1 2 3 2 3 4 ... Gate#2 ... 1438 1439 1438 1439 Gate#2 1440 Gate#3 ... Gate#3 ... 1440 ... Gate#4 Date Line #1 Date Line #2 + Date Line #3 - Date Line #1438 + ... Date Line #1439 - Gate#4 Date Line #1 Date Line #1440 + - Gate#1 Date Line #2 Date Line #3 Date Line #1438 + - + - + - + - + - + - Date Line #1439 Date Line #1440 Date Line #1441 - + - + - + - + - + - + ... Gate#1 + - + ... - + - ... Gate#2 + - + ... - + Gate#2 - Gate#3 ... Gate#3 + - + ... - + - ... Gate#4 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Gate#4 -P.81October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.9 LCD power generation scheme VGH (+14V~ +20V) VSP, VSPC (4.7V ~ 5.5V) VSPR(3.5V ~ (VSP-0.5V)) VDD2, VDD3 (2.3V ~ 3.3V) VDD1 (1.65V ~ 3.3V) DC/DC converter DSI_VCC (1.65V ~ 3.3V) VREF (1.8V) VDDD (1.6V ~ 2.0V) DSI_LDO (1.2V ~ 1.3V) VSSD,VSSA VCOM(-2V ~ 0V) VDDDN (-2.5V) DC/DC converter VSNR (-3.5V ~ (VSN+0.5V)) VSN, VSNC (-4.7V ~ -5.5V) VGL(-7V~ -13.5V) Figure 5.26: LCD power generation scheme Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.82October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.10 DC/DC converter circuit 5.10.1 Use PFM DC/DC converter The PFM DC-DC converter generates the high voltage level VSP/VSN required for source drivers. HX8369-A00 contains sub-circuits of the PFM boost converter, including a precision 1.8V reference voltage, comparator, PFM controlling logic, and the output buffer. The boost converter uses a external power transistor to provide maximum efficiency and to minimize the number of external components. The output voltage of the boost converter can be set from 4.7 to 5.5 (VSP) and -4.7 to -5.5V (VSN) VDD3 o VCSW2 VSNC PFM Controller VREF VSN D2 L1 D1 VSP VSPC VCSW1 D3 SW1 Figure 5.27: DC/DC converter circuit (PFM Type C)–PCCS=10 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.83October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.10.2 Use HX5186-A The HX5186-A is highly efficient switching voltage generator circuits that generate the high voltage level VSP/VSN required for source drivers. HX8369-A00 contains Charge Pump Controller for HX5186-A, including a comparator for VSP/VSN feedback control. HX5186-A can provide maximum efficiency and use minimum number of external components. The output voltage of the boost converter can be set from 4.7 to 5.5 (VSP) and -4.7 to -5.5V (VSN) Figure 5.28: DC/DC converter circuit (HX5186-A) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.84October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.11 Idle display The HX8369-A00 supports an idle display mode. The grayscale level to be used is V0 and V64 with R7, G7, B7 decoding, and the other levels (V1-V63) are halted to reduce power consumption. In idle display mode, the Gamma-micro-adjustment registers are invalid and only the upper bits of RGB are used for display. Positive Polarity Register Graphics (Input data) G1_VRP0[5:0] G1_VRP1[5:0] G1_VRP2[5:0] G1_VRP3[5:0] R R R R R R R R G G G G G G GG B B B B B B B B 76543210 76543210 76 543210 G1_VRP4[5:0] G1_VRP5[5:0] G1_PRP0[6:0] G1_PRP1[6:0] 1 1 1 G1_CGMP0[1:0] G1_ PKP0[4:0] G1_CGMP1[1:0] G1_PKP1[4:0] G1_CGMP2[1:0] G1_PKP2[4:0] G1_CGMP3[1:0] G1_PKP3[4:0] G1_CGMP5 G1_CGMP4 G1_PKP4[4:0] G1_PKP5[4:0] G1_PKP6[4:0] G1_PKP7[4:0] G1_PKP8[4:0] V0P/V0N 8- bit Grayscale 8- bit Grayscale 8- bit Grayscale D/ A Converter D/ A Converter D/ A Converter < R> < G> < B> V1P/V1N Grayscale Voltage V255P/V255N Generator Output Driver Output Driver Output Driver Negative Polarity Register G1_VRN0[5:0] G1_VRN1[5:0] G1_VRN2[5:0] G1_VRN3[5:0] G1_VRN4[5:0] R G LCD G1_VRN5[5:0] B G1_PRN0[6:0] G1_PRN1[6:0] G1_CGMN0[1:0] G1_ PKN0[4:0] G1_CGMN1[1:0] G1_PKN1[4:0] G1_CGMN2[1:0] G1_PKN2[4:0] G1_CGMN3[1:0] G1_PKN3[4:0] G1_CGMN5 G1_CGMN4 G1_PKN4[4:0] G1_PKN5[4:0] G1_PKN6[4:0] G1_PKN7[4:0] G1_PKN8[4:0] Figure 5.29: Idle mode grayscale control Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.85October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.12 Gamma characteristic correction function The HX8369-A00 incorporates gamma adjustment function for the 16,777,216-color display (256 grayscale for each R, G, B color). Gamma adjustment operation is implemented by deciding the16 grayscale levels firstly in gamma adjustment control registers to match the LCD panel. Then total 512 grayscale levels are generated in grayscale voltage generator. These registers are available for both polarities. Positive Polarity Register Graphics (Input data) G1_VRP0[5:0] G1_VRP1[5:0] G1_VRP2[5:0] G1_VRP3[5:0] R R R R R R R R G G G G G G GG B B B B B B B B 76543210 76543210 76 543210 G1_VRP4[5:0] G1_VRP5[5:0] G1_PRP0[6:0] G1_PRP1[6:0] 8 8 8 G1_CGMP0[1:0] G1_ PKP0[4:0] G1_CGMP1[1:0] G1_PKP1[4:0] G1_CGMP2[1:0] G1_PKP2[4:0] G1_CGMP3[1:0] G1_PKP3[4:0] G1_CGMP5 G1_CGMP4 G1_PKP4[4:0] G1_PKP5[4:0] G1_PKP6[4:0] G1_PKP7[4:0] G1_PKP8[4:0] V0P/V0N 8- bit Grayscale 8- bit Grayscale 8- bit Grayscale D/ A Converter D/ A Converter D/ A Converter < R> < G> < B> V1P/V1N Grayscale Voltage V255P/V255N Generator Output Driver Output Driver Negative Polarity Register Output Driver G1_VRN0[5:0] G1_VRN1[5:0] G1_VRN2[5:0] G1_VRN3[5:0] G1_VRN4[5:0] R G LCD G1_VRN5[5:0] B G1_PRN0[6:0] G1_PRN1[6:0] G1_CGMN0[1:0] G1_ PKN0[4:0] G1_CGMN1[1:0] G1_PKN1[4:0] G1_CGMN2[1:0] G1_PKN2[4:0] G1_CGMN3[1:0] G1_PKN3[4:0] G1_CGMN5 G1_CGMN4 G1_PKN4[4:0] G1_PKN5[4:0] G1_PKN6[4:0] G1_PKN7[4:0] G1_PKN8[4:0] Figure 5.30: Grayscale control Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.86October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Gamma-Characteristics adjustment register This HX8369-A00 has register groups for specifying a series grayscale voltage that meets the Gamma-characteristics for the LCD panel used. These registers are divided into two groups, which correspond to the gradient, amplitude, and macro adjustment of the voltage for the grayscale characteristics. The polarity of each register can be specified independently. (1) Offset adjustment registers The offset adjustment variable registers are used to adjust the amplitude of the grayscale voltage. This function is implemented by controlling these variable resisters in the top and bottom of the gamma resister stream for reference gamma voltage generation. These registers are available for both positive and negative polarities. (2) Gamma center adjustment registers The gamma center adjustment registers are used to adjust the reference gamma voltage in the middle level of grayscale without changing the dynamic range. This function is implemented by choosing one input of 88 to 1 selector in the gamma resister stream for reference gamma voltage generation. These registers are available for both positive and negative polarities. (3) Gamma macro adjustment registers The gamma macro adjustment registers can be used for fine adjustment of the reference gamma voltage. This function is implemented by controlling the 32-to-1 selectors (PKP/N0~5), each of which has 5 inputs and generates one reference voltage output (Vg(P/N)3, 7, 19, 25, 32, 38, 44, 56, 60). Register Groups Center Adjustment Macro Adjustment Offset Adjustment Positive Polarity PRP0 6-0 PRP1 6-0 PKP0 4-0 PKP1 4-0 PKP2 4-0 PKP3 4-0 PKP4 4-0 PKP5 4-0 PKP6 4-0 PKP7 4-0 PKP8 4-0 VRP0 5-0 VRP1 5-0 VRP2 5-0 VRP3 5-0 VRP4 5-0 VRP5 5-0 Negative Polarity PRN0 6-0 PRN1 6-0 PKN0 4-0 PKN1 4-0 PKN2 4-0 PKN3 4-0 Description Variable resistor (PRP/N0) for center adjustment Variable resistor (PRP/N1)for center adjustment 32-to-1 selector (voltage level of grayscale 3) 32-to-1 selector (voltage level of grayscale 7) 32-to-1 selector (voltage level of grayscale 19) 32-to-1 selector (voltage level of grayscale 25) 32-to-1 selector (voltage level of grayscale 32 for positive PKN4 4-0 polarity and grayscale 31 for negative polarity) PKN5 4-0 32-to-1 selector (voltage level of grayscale 38) PKN6 4-0 32-to-1 selector (voltage level of grayscale 44) PKN7 4-0 32-to-1 selector (voltage level of grayscale 56) PKN8 4-0 32-to-1 selector (voltage level of grayscale 60) VRN0 5-0 Variable resistor (VRP/N0)for offset adjustment VRN1 5-0 Variable resistor (VRP/N1)for offset adjustment VRN2 5-0 Variable resistor (VRP/N2)for offset adjustment VRN3 5-0 Variable resistor (VRP/N3)for offset adjustment VRN4 5-0 Variable resistor (VRP/N4)for offset adjustment VRN5 5-0 Variable resistor (VRP/N5)for offset adjustment Table 5.21: Gamma-Adjustment registers Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.87October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Gamma resister stream and 8 to 1 selector Figure 5.31: Gamma resister stream and gamma reference voltage Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.88October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 CGMP/N0 0 1 2 3 1R 3R 3.5R 3.5R 1R 2.5R 2.5R 2.5R 1R 2R 1.8R 2R 1R 2R 1.5R 2R V3 CGMP/N1 V4 V5 V6 0 1 2 3 1R 2R 1.5R 2R 1R 2R 1.8R 2R 1R 2.5R 2.5R 2.5R 1R 3R 3.5R 3.5R V56 V57 V7 CGMP/N2 CGMP/N4 0 1 2 3 1R 3R 4R 4.5R 1R 3R 3R 4R 1R 2.5R 3R 3R 1R 2.5R 3R 3R 1R 2.5R 2.5R 2.5R 1R 2.5R 2.5R 2.5R 0 1 1R 1.5R 1R 1R 1R 1R 1R 1R 1R 1R 1R 1R V13 V14 V15 V16 V17 V18 V19 V7 V58 V59 V60 CGMP/N3 V8 V9 V10 V11 V12 V13 0 1 2 3 1R 2.5R 2.5R 2.5R 1R 2.5R 2.5R 2.5R 1R 2.5R 3R 3R 1R 2.5R 3R 3R 1R 3R 3R 4R 1R 3R 4R 4.5R 0 1 1R 1R 1R 1R 1R 1R 1R 1R CGMP/N5 1R 1R 1R 1.5R V50 V51 V52 V53 V54 V55 V56 V44 V45 V46 V47 V48 V49 V50 Figure 5.32: Gamma resister stream Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.89October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Variable resister There are two types of variable resistors, one is for center adjustment and the other is for offset adjustment. The resistances are decided by setting values in the center adjustment, offset adjustment registers. Their relationships are shown below. Value in Register VR(P/N)0 5-0 000000 000001 000010 000011 • • 011101 011110 011111 100000 100001 100010 • • 111101 111110 111111 Value in Register VR(P/N)3 5-0 000000 000001 000010 • • 011101 011110 011111 100000 100001 100010 • • 111100 111101 111110 111111 Resistance VR(P/N)0 Value in Register VR(P/N)1 5-0 Resistance VR(P/N)1 0R 20R 22R 24R • • 76R 78R 80R 82R 84R 86R • • 140R 142R 144R 000000 000001 000010 000011 • • 011101 011110 011111 100000 100001 100010 • • 111101 111110 111111 0R 2R 4R 6R • • 58R 60R 62R 64R 66R 68R • • 122R 124R 126R Resistance VR(P/N)3 Value in Register VR(P/N)4 5-0 Resistance VR(P/N)4 0R 2R 4R • • 58R 60R 62R 64R 66R 68R • • 120R 122R 124R 126R 000000 000001 000010 • • 011101 011110 011111 100000 100001 100010 • • 111100 111101 111110 111111 0R 2R 4R • • 58R 60R 62R 64R 66R 68R • • 120R 122R 124R 126R Value in Register VR(P/N)2 5-0 000000 000001 000010 000011 • • 011101 011110 011111 100000 100001 100010 • • 111101 111110 111111 Value in Register VR(P/N)5 5-0 000000 000001 000010 • • 011101 011110 011111 100000 100001 100010 • • 111100 111101 111110 111111 Resistance VR(P/N)2 0R 2R 4R 6R • • 58R 60R 62R 64R 66R 68R • • 122R 124R 126R Resistance VR(P/N)2 0R 2R 4R • • 58R 60R 62R 64R 66R 68R • • 120R 122R 124R 144R Table 5.22: Offset adjustment 0~5 Value in Register PR(P/N)0 6-0 0000000 0000001 0000010 • • 1010101 1010110 1010111 Resistance PR(P/N)0 0R 2R 4R • • 170R 172R 174R Value in Register PR(P/N)1 6-0 0000000 0000001 0000010 • • 1010101 1010110 1010111 Resistance PR(P/N)1 0R 2R 4R • • 170R 172R 174R Table 5.23: Center adjustment Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.90October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 The grayscale levels are determined by the following formulas: Reference voltage Macro adjustment value VinP0 formula VinP0 VRP0 5-0 = 000000 VRP0 5-0 = 000001 VRP0 5-0 = 000010 VRP0 5-0 = 000011 VRP0 5-0 = 000100 VRP0 5-0 = 000101 VRP0 5-0 = 000110 VRP0 5-0 = 000111 VRP0 5-0 = 001000 VRP0 5-0 = 001001 VRP0 5-0 = 001010 VRP0 5-0 = 001011 VRP0 5-0 = 001100 VRP0 5-0 = 001101 VRP0 5-0 = 001110 VRP0 5-0 = 001111 VRP0 5-0 = 010000 VRP0 5-0 = 010001 VRP0 5-0 = 010010 VRP0 5-0 = 010011 VRP0 5-0 = 010100 VRP0 5-0 = 010101 VRP0 5-0 = 010110 VRP0 5-0 = 010111 VRP0 5-0 = 011000 VRP0 5-0 = 011001 VRP0 5-0 = 011010 VRP0 5-0 = 011011 VRP0 5-0 = 011100 VRP0 5-0 = 011101 VRP0 5-0 = 011110 VRP0 5-0 = 011111 VRP0 5-0 = 100000 VRP0 5-0 = 100001 VRP0 5-0 = 100010 VRP0 5-0 = 100011 VRP0 5-0 = 100100 VRP0 5-0 = 100101 VRP0 5-0 = 100110 VRP0 5-0 = 100111 VRP0 5-0 = 101000 VRP0 5-0 = 101001 VRP0 5-0 = 101010 VRP0 5-0 = 101011 VRP0 5-0 = 101100 VRP0 5-0 = 101101 VRP0 5-0 = 101110 VRP0 5-0 = 101111 VRP0 5-0 = 110000 VRP0 5-0 = 110001 VRP0 5-0 = 110010 VRP0 5-0 = 110011 VRP0 5-0 = 110100 VRP0 5-0 = 110101 VRP0 5-0 = 110110 VRP0 5-0 = 110111 VRP0 5-0 = 111000 VRP0 5-0 = 111001 VRP0 5-0 = 111010 VRP0 5-0 = 111011 VRP0 5-0 = 111100 VRP0 5-0 = 111101 VRP0 5-0 = 111110 VRP0 5-0 = 111111 VSPR ((450R - 20R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 22R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 24R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 26R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 28R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 30R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 32R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 34R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 36R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 38R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 40R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 42R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 44R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 46R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 48R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 50R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 52R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 54R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 56R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 58R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 60R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 62R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 64R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 66R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 68R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 70R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 72R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 74R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 76R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 78R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 80R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 82R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 84R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 86R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 88R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 90R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 92R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 94R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 96R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 98R ) / 450R) * (VSPR - VGSP) + VGSP ((450R - 100R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 102R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 104R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 106R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 108R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 110R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 112R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 114R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 116R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 118R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 120R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 122R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 126R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 128R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 130R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 132R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 134R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 136R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 138R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 140R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 142R) / 450R) * (VSPR - VGSP) + VGSP ((450R - 144R) / 450R) * (VSPR - VGSP) + VGSP Table 5.24: VinP0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.91October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP1 formula VinP1 VRP1 5-0 = 000000 VRP1 5-0 = 000001 VRP1 5-0 = 000010 VRP1 5-0 = 000011 VRP1 5-0 = 000100 VRP1 5-0 = 000101 VRP1 5-0 = 000110 VRP1 5-0 = 000111 VRP1 5-0 = 001000 VRP1 5-0 = 001001 VRP1 5-0 = 001010 VRP1 5-0 = 001011 VRP1 5-0 = 001100 VRP1 5-0 = 001101 VRP1 5-0 = 001110 VRP1 5-0 = 001111 VRP1 5-0 = 010000 VRP1 5-0 = 010001 VRP1 5-0 = 010010 VRP1 5-0 = 010011 VRP1 5-0 = 010100 VRP1 5-0 = 010101 VRP1 5-0 = 010110 VRP1 5-0 = 010111 VRP1 5-0 = 011000 VRP1 5-0 = 011001 VRP1 5-0 = 011010 VRP1 5-0 = 011011 VRP1 5-0 = 011100 VRP1 5-0 = 011101 VRP1 5-0 = 011110 VRP1 5-0 = 011111 VRP1 5-0 = 100000 VRP1 5-0 = 100001 VRP1 5-0 = 100010 VRP1 5-0 = 100011 VRP1 5-0 = 100100 VRP1 5-0 = 100101 VRP1 5-0 = 100110 VRP1 5-0 = 100111 VRP1 5-0 = 101000 VRP1 5-0 = 101001 VRP1 5-0 = 101010 VRP1 5-0 = 101011 VRP1 5-0 = 101100 VRP1 5-0 = 101101 VRP1 5-0 = 101110 VRP1 5-0 = 101111 VRP1 5-0 = 110000 VRP1 5-0 = 110001 VRP1 5-0 = 110010 VRP1 5-0 = 110011 VRP1 5-0 = 110100 VRP1 5-0 = 110101 VRP1 5-0 = 110110 VRP1 5-0 = 110111 VRP1 5-0 = 111000 VRP1 5-0 = 111001 VRP1 5-0 = 111010 VRP1 5-0 = 111011 VRP1 5-0 = 111100 VRP1 5-0 = 111101 VRP1 5-0 = 111110 VRP1 5-0 = 111111 (430R / 450R) * (VSPR - VGSP) + VGSP ((430R - 2R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 4R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 6R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 8R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 10R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 12R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 14R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 16R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 18R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 20R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 22R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 24R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 26R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 28R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 30R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 32R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 34R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 36R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 38R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 40R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 42R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 44R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 46R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 48R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 50R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 52R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 54R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 56R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 58R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 60R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 62R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 64R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 66R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 68R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 70R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 72R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 74R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 76R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 78R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 80R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 82R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 84R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 86R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 88R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 90R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 92R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 94R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 96R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 98R ) / 450R) * (VSPR - VGSP) + VGSP ((430R - 100R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 102R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 104R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 106R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 108R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 110R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 112R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 114R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 116R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 118R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 120R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 122R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((430R - 126R) / 450R) * (VSPR - VGSP) + VGSP Table 5.25: VinP1 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.92October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP2 formula VinP2 VRP2 5-0 = 000000 VRP2 5-0 = 000001 VRP2 5-0 = 000010 VRP2 5-0 = 000011 VRP2 5-0 = 000100 VRP2 5-0 = 000101 VRP2 5-0 = 000110 VRP2 5-0 = 000111 VRP2 5-0 = 001000 VRP2 5-0 = 001001 VRP2 5-0 = 001010 VRP2 5-0 = 001011 VRP2 5-0 = 001100 VRP2 5-0 = 001101 VRP2 5-0 = 001110 VRP2 5-0 = 001111 VRP2 5-0 = 010000 VRP2 5-0 = 010001 VRP2 5-0 = 010010 VRP2 5-0 = 010011 VRP2 5-0 = 010100 VRP2 5-0 = 010101 VRP2 5-0 = 010110 VRP2 5-0 = 010111 VRP2 5-0 = 011000 VRP2 5-0 = 011001 VRP2 5-0 = 011010 VRP2 5-0 = 011011 VRP2 5-0 = 011100 VRP2 5-0 = 011101 VRP2 5-0 = 011110 VRP2 5-0 = 011111 VRP2 5-0 = 100000 VRP2 5-0 = 100001 VRP2 5-0 = 100010 VRP2 5-0 = 100011 VRP2 5-0 = 100100 VRP2 5-0 = 100101 VRP2 5-0 = 100110 VRP2 5-0 = 100111 VRP2 5-0 = 101000 VRP2 5-0 = 101001 VRP2 5-0 = 101010 VRP2 5-0 = 101011 VRP2 5-0 = 101100 VRP2 5-0 = 101101 VRP2 5-0 = 101110 VRP2 5-0 = 101111 VRP2 5-0 = 110000 VRP2 5-0 = 110001 VRP2 5-0 = 110010 VRP2 5-0 = 110011 VRP2 5-0 = 110100 VRP2 5-0 = 110101 VRP2 5-0 = 110110 VRP2 5-0 = 110111 VRP2 5-0 = 111000 VRP2 5-0 = 111001 VRP2 5-0 = 111010 VRP2 5-0 = 111011 VRP2 5-0 = 111100 VRP2 5-0 = 111101 VRP2 5-0 = 111110 VRP2 5-0 = 111111 (420R / 450R) * (VSPR - VGSP) + VGSP ((420R - 2R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 4R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 6R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 8R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 10R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 12R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 14R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 16R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 18R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 20R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 22R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 24R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 26R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 28R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 30R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 32R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 34R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 36R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 38R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 40R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 42R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 44R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 46R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 48R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 50R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 52R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 54R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 56R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 58R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 60R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 62R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 64R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 66R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 68R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 70R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 72R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 74R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 76R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 78R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 80R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 82R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 84R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 86R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 88R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 90R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 92R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 94R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 96R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 98R ) / 450R) * (VSPR - VGSP) + VGSP ((420R - 100R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 102R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 104R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 106R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 108R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 110R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 112R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 114R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 116R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 118R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 120R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 122R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((420R - 126R) / 450R) * (VSPR - VGSP) + VGSP Table 5.26: VinP2 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.93October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP14 formula VinP14 VRP3 5-0 = 000000 VRP3 5-0 = 000001 VRP3 5-0 = 000010 VRP3 5-0 = 000011 VRP3 5-0 = 000100 VRP3 5-0 = 000101 VRP3 5-0 = 000110 VRP3 5-0 = 000111 VRP3 5-0 = 001000 VRP3 5-0 = 001001 VRP3 5-0 = 001010 VRP3 5-0 = 001011 VRP3 5-0 = 001100 VRP3 5-0 = 001101 VRP3 5-0 = 001110 VRP3 5-0 = 001111 VRP3 5-0 = 010000 VRP3 5-0 = 010001 VRP3 5-0 = 010010 VRP3 5-0 = 010011 VRP3 5-0 = 010100 VRP3 5-0 = 010101 VRP3 5-0 = 010110 VRP3 5-0 = 010111 VRP3 5-0 = 011000 VRP3 5-0 = 011001 VRP3 5-0 = 011010 VRP3 5-0 = 011011 VRP3 5-0 = 011100 VRP3 5-0 = 011101 VRP3 5-0 = 011110 VRP3 5-0 = 011111 VRP3 5-0 = 100000 VRP3 5-0 = 100001 VRP3 5-0 = 100010 VRP3 5-0 = 100011 VRP3 5-0 = 100100 VRP3 5-0 = 100101 VRP3 5-0 = 100110 VRP3 5-0 = 100111 VRP3 5-0 = 101000 VRP3 5-0 = 101001 VRP3 5-0 = 101010 VRP3 5-0 = 101011 VRP3 5-0 = 101100 VRP3 5-0 = 101101 VRP3 5-0 = 101110 VRP3 5-0 = 101111 VRP3 5-0 = 110000 VRP3 5-0 = 110001 VRP3 5-0 = 110010 VRP3 5-0 = 110011 VRP3 5-0 = 110100 VRP3 5-0 = 110101 VRP3 5-0 = 110110 VRP3 5-0 = 110111 VRP3 5-0 = 111000 VRP3 5-0 = 111001 VRP3 5-0 = 111010 VRP3 5-0 = 111011 VRP3 5-0 = 111100 VRP3 5-0 = 111101 VRP3 5-0 = 111110 VRP3 5-0 = 111111 (156R / 450R) * (VSPR - VGSP) + VGSP ((156R - 2R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 4R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 6R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 8R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 10R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 12R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 14R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 16R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 18R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 20R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 22R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 24R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 26R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 28R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 30R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 32R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 34R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 36R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 38R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 40R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 42R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 44R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 46R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 48R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 50R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 52R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 54R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 56R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 58R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 60R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 62R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 64R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 66R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 68R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 70R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 72R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 74R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 76R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 78R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 80R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 82R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 84R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 86R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 88R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 90R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 92R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 94R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 96R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 98R ) / 450R) * (VSPR - VGSP) + VGSP ((156R - 100R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 102R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 104R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 106R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 108R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 110R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 112R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 114R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 116R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 118R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 120R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 122R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((156R - 126R) / 450R) * (VSPR - VGSP) + VGSP Table 5.27: VinP14 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.94October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP15 formula VinP15 VRP4 5-0 = 000000 VRP4 5-0 = 000001 VRP4 5-0 = 000010 VRP4 5-0 = 000011 VRP4 5-0 = 000100 VRP4 5-0 = 000101 VRP4 5-0 = 000110 VRP4 5-0 = 000111 VRP4 5-0 = 001000 VRP4 5-0 = 001001 VRP4 5-0 = 001010 VRP4 5-0 = 001011 VRP4 5-0 = 001100 VRP4 5-0 = 001101 VRP4 5-0 = 001110 VRP4 5-0 = 001111 VRP4 5-0 = 010000 VRP4 5-0 = 010001 VRP4 5-0 = 010010 VRP4 5-0 = 010011 VRP4 5-0 = 010100 VRP4 5-0 = 010101 VRP4 5-0 = 010110 VRP4 5-0 = 010111 VRP4 5-0 = 011000 VRP4 5-0 = 011001 VRP4 5-0 = 011010 VRP4 5-0 = 011011 VRP4 5-0 = 011100 VRP4 5-0 = 011101 VRP4 5-0 = 011110 VRP4 5-0 = 011111 VRP4 5-0 = 100000 VRP4 5-0 = 100001 VRP4 5-0 = 100010 VRP4 5-0 = 100011 VRP4 5-0 = 100100 VRP4 5-0 = 100101 VRP4 5-0 = 100110 VRP4 5-0 = 100111 VRP4 5-0 = 101000 VRP4 5-0 = 101001 VRP4 5-0 = 101010 VRP4 5-0 = 101011 VRP4 5-0 = 101100 VRP4 5-0 = 101101 VRP4 5-0 = 101110 VRP4 5-0 = 101111 VRP4 5-0 = 110000 VRP4 5-0 = 110001 VRP4 5-0 = 110010 VRP4 5-0 = 110011 VRP4 5-0 = 110100 VRP4 5-0 = 110101 VRP4 5-0 = 110110 VRP4 5-0 = 110111 VRP4 5-0 = 111000 VRP4 5-0 = 111001 VRP4 5-0 = 111010 VRP4 5-0 = 111011 VRP4 5-0 = 111100 VRP4 5-0 = 111101 VRP4 5-0 = 111110 VRP4 5-0 = 111111 (146R / 450R) * (VSPR - VGSP) + VGSP ((146R - 2R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 4R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 6R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 8R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 10R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 12R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 14R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 16R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 18R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 20R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 22R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 24R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 26R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 28R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 30R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 32R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 34R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 36R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 38R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 40R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 42R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 44R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 46R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 48R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 50R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 52R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 54R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 56R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 58R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 60R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 62R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 64R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 66R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 68R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 70R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 72R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 74R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 76R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 78R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 80R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 82R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 84R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 86R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 88R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 90R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 92R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 94R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 96R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 98R ) / 450R) * (VSPR - VGSP) + VGSP ((146R - 100R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 102R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 104R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 106R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 108R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 110R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 112R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 114R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 116R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 118R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 120R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 122R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((146R - 126R) / 450R) * (VSPR - VGSP) + VGSP Table 5.28: VinP15 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.95October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP16 formula VinP16 VRP5 5-0 = 000000 VRP5 5-0 = 000001 VRP5 5-0 = 000010 VRP5 5-0 = 000011 VRP5 5-0 = 000100 VRP5 5-0 = 000101 VRP5 5-0 = 000110 VRP5 5-0 = 000111 VRP5 5-0 = 001000 VRP5 5-0 = 001001 VRP5 5-0 = 001010 VRP5 5-0 = 001011 VRP5 5-0 = 001100 VRP5 5-0 = 001101 VRP5 5-0 = 001110 VRP5 5-0 = 001111 VRP5 5-0 = 010000 VRP5 5-0 = 010001 VRP5 5-0 = 010010 VRP5 5-0 = 010011 VRP5 5-0 = 010100 VRP5 5-0 = 010101 VRP5 5-0 = 010110 VRP5 5-0 = 010111 VRP5 5-0 = 011000 VRP5 5-0 = 011001 VRP5 5-0 = 011010 VRP5 5-0 = 011011 VRP5 5-0 = 011100 VRP5 5-0 = 011101 VRP5 5-0 = 011110 VRP5 5-0 = 011111 VRP5 5-0 = 100000 VRP5 5-0 = 100001 VRP5 5-0 = 100010 VRP5 5-0 = 100011 VRP5 5-0 = 100100 VRP5 5-0 = 100101 VRP5 5-0 = 100110 VRP5 5-0 = 100111 VRP5 5-0 = 101000 VRP5 5-0 = 101001 VRP5 5-0 = 101010 VRP5 5-0 = 101011 VRP5 5-0 = 101100 VRP5 5-0 = 101101 VRP5 5-0 = 101110 VRP5 5-0 = 101111 VRP5 5-0 = 110000 VRP5 5-0 = 110001 VRP5 5-0 = 110010 VRP5 5-0 = 110011 VRP5 5-0 = 110100 VRP5 5-0 = 110101 VRP5 5-0 = 110110 VRP5 5-0 = 110111 VRP5 5-0 = 111000 VRP5 5-0 = 111001 VRP5 5-0 = 111010 VRP5 5-0 = 111011 VRP5 5-0 = 111100 VRP5 5-0 = 111101 VRP5 5-0 = 111110 VRP5 5-0 = 111111 (144R / 450R) * (VSPR - VGSP) + VGSP ((144R - 2R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 4R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 6R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 8R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 10R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 12R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 14R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 16R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 18R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 20R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 22R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 24R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 26R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 28R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 30R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 32R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 34R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 36R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 38R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 40R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 42R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 44R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 46R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 48R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 50R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 52R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 54R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 56R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 58R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 60R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 62R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 64R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 66R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 68R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 70R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 72R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 74R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 76R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 78R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 80R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 82R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 84R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 86R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 88R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 90R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 92R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 94R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 96R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 98R ) / 450R) * (VSPR - VGSP) + VGSP ((144R - 100R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 102R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 104R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 106R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 108R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 110R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 112R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 114R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 116R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 118R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 120R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 122R) / 450R) * (VSPR - VGSP) + VGSP ((144R - 124R) / 450R) * (VSPR - VGSP) + VGSP VGSP Table 5.29: VinP16 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.96October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage VinP5 Macro adjustment value VinP5 formula PRP0 6-0 = 0000000 PRP0 6-0 = 0000001 PRP0 6-0 = 0000010 PRP0 6-0 = 0000011 PRP0 6-0 = 0000100 PRP0 6-0 = 0000101 PRP0 6-0 = 0000110 PRP0 6-0 = 0000111 PRP0 6-0 = 0001000 PRP0 6-0 = 0001001 PRP0 6-0 = 0001010 PRP0 6-0 = 0001011 PRP0 6-0 = 0001100 PRP0 6-0 = 0001101 PRP0 6-0 = 0001110 PRP0 6-0 = 0001111 PRP0 6-0 = 0010000 PRP0 6-0 = 0010001 PRP0 6-0 = 0010010 PRP0 6-0 = 0010011 PRP0 6-0 = 0010100 PRP0 6-0 = 0010101 PRP0 6-0 = 0010110 PRP0 6-0 = 0010111 PRP0 6-0 = 0011000 PRP0 6-0 = 0011001 PRP0 6-0 = 0011010 PRP0 6-0 = 0011011 PRP0 6-0 = 0011100 PRP0 6-0 = 0011101 PRP0 6-0 = 0011110 PRP0 6-0 = 0011111 PRP0 6-0 = 0100000 PRP0 6-0 = 0100001 PRP0 6-0 = 0100010 PRP0 6-0 = 0100011 PRP0 6-0 = 0100100 PRP0 6-0 = 0100101 PRP0 6-0 = 0100110 PRP0 6-0 = 0100111 PRP0 6-0 = 0101000 PRP0 6-0 = 0101001 PRP0 6-0 = 0101010 PRP0 6-0 = 0101011 PRP0 6-0 = 0101100 PRP0 6-0 = 0101101 PRP0 6-0 = 0101110 PRP0 6-0 = 0101111 PRP0 6-0 = 0110000 PRP0 6-0 = 0110001 PRP0 6-0 = 0110010 PRP0 6-0 = 0110011 PRP0 6-0 = 0110100 PRP0 6-0 = 0110101 PRP0 6-0 = 0110110 PRP0 6-0 = 0110111 PRP0 6-0 = 0111000 PRP0 6-0 = 0111001 PRP0 6-0 = 0111010 PRP0 6-0 = 0111011 PRP0 6-0 = 0111100 PRP0 6-0 = 0111101 PRP0 6-0 = 0111110 PRP0 6-0 = 0111111 PRP0 6-0 = 1000000 PRP0 6-0 = 1000001 PRP0 6-0 = 1000010 PRP0 6-0 = 1000011 PRP0 6-0 = 1000100 (350R / 450R) (VSPR - VGSP) + VGSP ((350R - 2R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 4R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 6R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 8R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 10R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 12R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 14R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 16R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 18R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 20R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 22R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 24R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 26R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 28R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 30R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 32R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 34R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 36R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 38R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 40R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 42R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 44R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 46R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 48R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 50R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 52R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 54R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 56R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 58R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 60R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 62R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 64R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 66R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 68R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 70R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 72R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 74R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 76R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 78R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 80R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 82R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 84R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 86R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 88R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 90R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 92R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 94R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 96R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 98R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 100R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 102R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 104R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 106R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 108R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 110R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 112R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 114R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 116R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 118R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 120R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 122R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 126R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 128R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 130R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 132R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 134R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 136R) / 450R) * (VSPR - VGSP) + VGSP Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.97October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 PRP0 6-0 = 1000101 PRP0 6-0 = 1000110 PRP0 6-0 = 1000111 PRP0 6-0 = 1001000 PRP0 6-0 = 1001001 PRP0 6-0 = 1001010 PRP0 6-0 = 1001011 PRP0 6-0 = 1001100 PRP0 6-0 = 1001101 PRP0 6-0 = 1001110 PRP0 6-0 = 1001111 PRP0 6-0 = 1010000 PRP0 6-0 = 1010001 PRP0 6-0 = 1010010 PRP0 6-0 = 1010011 PRP0 6-0 = 1010100 PRP0 6-0 = 1010101 PRP0 6-0 = 1010110 PRP0 6-0 = 1010111 PRP0 6-0 = 1011000 PRP0 6-0 = 1011001 PRP0 6-0 = 1011010 PRP0 6-0 = 1011011 PRP0 6-0 = 1011100 PRP0 6-0 = 1011101 PRP0 6-0 = 1011110 PRP0 6-0 = 1011111 PRP0 6-0 = 1100000 PRP0 6-0 = 1100001 PRP0 6-0 = 1100010 PRP0 6-0 = 1100011 PRP0 6-0 = 1100100 PRP0 6-0 = 1100101 PRP0 6-0 = 1100110 PRP0 6-0 = 1100111 PRP0 6-0 = 1101000 PRP0 6-0 = 1101001 PRP0 6-0 = 1101010 PRP0 6-0 = 1101011 PRP0 6-0 = 1101100 PRP0 6-0 = 1101101 PRP0 6-0 = 1101110 PRP0 6-0 = 1101111 PRP0 6-0 = 1110000 PRP0 6-0 = 1110001 PRP0 6-0 = 1110010 PRP0 6-0 = 1110011 PRP0 6-0 = 1110100 PRP0 6-0 = 1110101 PRP0 6-0 = 1110110 PRP0 6-0 = 1110111 PRP0 6-0 = 1111000 PRP0 6-0 = 1111001 PRP0 6-0 = 1111010 PRP0 6-0 = 1111011 PRP0 6-0 = 1111100 PRP0 6-0 = 1111101 PRP0 6-0 = 1111110 PRP0 6-0 = 1111111 ((350R – 138R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 140R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 142R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 144R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 146R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 148R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 150R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 152R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 154R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 156R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 158R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 160R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 162R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 164R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 166R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 168R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 170R) / 450R) * (VSPR - VGSP) + VGSP ((350R – 172R) / 450R) * (VSPR - VGSP) + VGSP ((350R - 174R) / 450R) * (VSPR - VGSP) + VGSP inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit Table 5.30: VinP5 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.98October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage VinP11 Macro adjustment value VinP11 formula PRP1 6-0 = 0000000 PRP1 6-0 = 0000001 PRP1 6-0 = 0000010 PRP1 6-0 = 0000011 PRP1 6-0 = 0000100 PRP1 6-0 = 0000101 PRP1 6-0 = 0000110 PRP1 6-0 = 0000111 PRP1 6-0 = 0001000 PRP1 6-0 = 0001001 PRP1 6-0 = 0001010 PRP1 6-0 = 0001011 PRP1 6-0 = 0001100 PRP1 6-0 = 0001101 PRP1 6-0 = 0001110 PRP1 6-0 = 0001111 PRP1 6-0 = 0010000 PRP1 6-0 = 0010001 PRP1 6-0 = 0010010 PRP1 6-0 = 0010011 PRP1 6-0 = 0010100 PRP1 6-0 = 0010101 PRP1 6-0 = 0010110 PRP1 6-0 = 0010111 PRP1 6-0 = 0011000 PRP1 6-0 = 0011001 PRP1 6-0 = 0011010 PRP1 6-0 = 0011011 PRP1 6-0 = 0011100 PRP1 6-0 = 0011101 PRP1 6-0 = 0011110 PRP1 6-0 = 0011111 PRP1 6-0 = 0100000 PRP1 6-0 = 0100001 PRP1 6-0 = 0100010 PRP1 6-0 = 0100011 PRP1 6-0 = 0100100 PRP1 6-0 = 0100101 PRP1 6-0 = 0100110 PRP1 6-0 = 0100111 PRP1 6-0 = 0101000 PRP1 6-0 = 0101001 PRP1 6-0 = 0101010 PRP1 6-0 = 0101011 PRP1 6-0 = 0101100 PRP1 6-0 = 0101101 PRP1 6-0 = 0101110 PRP1 6-0 = 0101111 PRP1 6-0 = 0110000 PRP1 6-0 = 0110001 PRP1 6-0 = 0110010 PRP1 6-0 = 0110011 PRP1 6-0 = 0110100 PRP1 6-0 = 0110101 PRP1 6-0 = 0110110 PRP1 6-0 = 0110111 PRP1 6-0 = 0111000 PRP1 6-0 = 0111001 PRP1 6-0 = 0111010 PRP1 6-0 = 0111011 PRP1 6-0 = 0111100 PRP1 6-0 = 0111101 PRP1 6-0 = 0111110 PRP1 6-0 = 0111111 PRP1 6-0 = 1000000 PRP1 6-0 = 1000001 PRP1 6-0 = 1000010 PRP1 6-0 = 1000011 PRP1 6-0 = 1000100 (274R / 450R) (VSPR - VGSP) + VGSP ((274R - 2R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 4R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 6R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 8R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 10R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 12R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 14R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 16R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 18R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 20R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 22R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 24R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 26R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 28R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 30R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 32R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 34R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 36R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 38R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 40R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 42R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 44R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 46R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 48R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 50R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 52R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 54R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 56R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 58R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 60R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 62R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 64R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 66R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 68R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 70R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 72R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 74R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 76R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 78R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 80R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 82R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 84R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 86R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 88R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 90R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 92R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 94R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 96R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 98R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 100R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 102R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 104R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 106R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 108R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 110R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 112R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 114R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 116R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 118R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 120R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 122R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 124R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 126R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 128R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 130R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 132R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 134R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 136R) / 450R) * (VSPR - VGSP) + VGSP Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.99October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 PRP1 6-0 = 1000101 PRP1 6-0 = 1000110 PRP1 6-0 = 1000111 PRP1 6-0 = 1001000 PRP1 6-0 = 1001001 PRP1 6-0 = 1001010 PRP1 6-0 = 1001011 PRP1 6-0 = 1001100 PRP1 6-0 = 1001101 PRP1 6-0 = 1001110 PRP1 6-0 = 1001111 PRP1 6-0 = 1010000 PRP1 6-0 = 1010001 PRP1 6-0 = 1010010 PRP1 6-0 = 1010011 PRP1 6-0 = 1010100 PRP1 6-0 = 1010101 PRP1 6-0 = 1010110 PRP1 6-0 = 1010111 PRP1 6-0 = 1011000 PRP1 6-0 = 1011001 PRP1 6-0 = 1011010 PRP1 6-0 = 1011011 PRP1 6-0 = 1011100 PRP1 6-0 = 1011101 PRP1 6-0 = 1011110 PRP1 6-0 = 1011111 PRP1 6-0 = 1100000 PRP1 6-0 = 1100001 PRP1 6-0 = 1100010 PRP1 6-0 = 1100011 PRP1 6-0 = 1100100 PRP1 6-0 = 1100101 PRP1 6-0 = 1100110 PRP1 6-0 = 1100111 PRP1 6-0 = 1101000 PRP1 6-0 = 1101001 PRP1 6-0 = 1101010 PRP1 6-0 = 1101011 PRP1 6-0 = 1101100 PRP1 6-0 = 1101101 PRP1 6-0 = 1101110 PRP1 6-0 = 1101111 PRP1 6-0 = 1110000 PRP1 6-0 = 1110001 PRP1 6-0 = 1110010 PRP1 6-0 = 1110011 PRP1 6-0 = 1110100 PRP1 6-0 = 1110101 PRP1 6-0 = 1110110 PRP1 6-0 = 1110111 PRP1 6-0 = 1111000 PRP1 6-0 = 1111001 PRP1 6-0 = 1111010 PRP1 6-0 = 1111011 PRP1 6-0 = 1111100 PRP1 6-0 = 1111101 PRP1 6-0 = 1111110 PRP1 6-0 = 1111111 ((274R – 138R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 140R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 142R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 144R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 146R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 148R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 150R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 152R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 154R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 156R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 158R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 160R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 162R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 164R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 166R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 168R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 170R) / 450R) * (VSPR - VGSP) + VGSP ((274R – 172R) / 450R) * (VSPR - VGSP) + VGSP ((274R - 174R) / 450R) * (VSPR - VGSP) + VGSP inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit Table 5.31: VinP11 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.100October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP3 formula VinP3 PKP0 4-0 = 00000 PKP0 4-0 = 00001 PKP0 4-0 = 00010 PKP0 4-0 = 00011 PKP0 4-0 = 00100 PKP0 4-0 = 00101 PKP0 4-0 = 00110 PKP0 4-0 = 00111 PKP0 4-0 = 01000 PKP0 4-0 = 01001 PKP0 4-0 = 01010 PKP0 4-0 = 01011 PKP0 4-0 = 01100 PKP0 4-0 = 01101 PKP0 4-0 = 01110 PKP0 4-0 = 01111 PKP0 4-0 = 10000 PKP0 4-0 = 10001 PKP0 4-0 = 10010 PKP0 4-0 = 10011 PKP0 4-0 = 10100 PKP0 4-0 = 10101 PKP0 4-0 = 10110 PKP0 4-0 = 10111 PKP0 4-0 = 11000 PKP0 4-0 = 11001 PKP0 4-0 = 11010 PKP0 4-0 = 11011 PKP0 4-0 = 11100 PKP0 4-0 = 11101 PKP0 4-0 = 11110 PKP0 4-0 = 11111 (47R / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 1R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 2R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 3R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 4R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 5R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 6R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 7R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 8R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R – 9R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 10R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 11R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 12R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 13R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 14R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 15R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 16R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 17R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 18R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 19R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 20R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 21R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 22R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 23R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 24R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 25R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 26R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 27R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 28R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 29R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 30R) / 48R) * (VinP2 - VinP5) + VinP5 ((47R - 31R) / 48R) * (VinP2 - VinP5) + VinP5 Table 5.32: VinP3 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.101October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP4 formula VinP4 PKP1 4-0 = 00000 PKP1 4-0 = 00001 PKP1 4-0 = 00010 PKP1 4-0 = 00011 PKP1 4-0 = 00100 PKP1 4-0 = 00101 PKP1 4-0 = 00110 PKP1 4-0 = 00111 PKP1 4-0 = 01000 PKP1 4-0 = 01001 PKP1 4-0 = 01010 PKP1 4-0 = 01011 PKP1 4-0 = 01100 PKP1 4-0 = 01101 PKP1 4-0 = 01110 PKP1 4-0 = 01111 PKP1 4-0 = 10000 PKP1 4-0 = 10001 PKP1 4-0 = 10010 PKP1 4-0 = 10011 PKP1 4-0 = 10100 PKP1 4-0 = 10101 PKP1 4-0 = 10110 PKP1 4-0 = 10111 PKP1 4-0 = 11000 PKP1 4-0 = 11001 PKP1 4-0 = 11010 PKP1 4-0 = 11011 PKP1 4-0 = 11100 PKP1 4-0 = 11101 PKP1 4-0 = 11110 PKP1 4-0 = 11111 (32R / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 1R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 2R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 3R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 4R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 5R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 6R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 7R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 8R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 9R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 10R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 11R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 12R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 13R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 14R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 15R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 16R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 17R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 18R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 19R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 20R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 21R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 22R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 23R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 24R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 25R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 26R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 27R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 28R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 29R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 30R) / 48R) * (VinP2 - VinP5) + VinP5 ((32R - 31R) / 48R) * (VinP2 - VinP5) + VinP5 Table 5.33: VinP4 Reference voltage Macro adjustment value VinP6 formula VinP6 PKP2 4-0 = 00000 PKP2 4-0 = 00001 PKP2 4-0 = 00010 PKP2 4-0 = 00011 PKP2 4-0 = 00100 PKP2 4-0 = 00101 PKP2 4-0 = 00110 PKP2 4-0 = 00111 PKP2 4-0 = 01000 PKP2 4-0 = 01001 PKP2 4-0 = 01010 PKP2 4-0 = 01011 PKP2 4-0 = 01100 PKP2 4-0 = 01101 PKP2 4-0 = 01110 PKP2 4-0 = 01111 PKP2 4-0 = 10000 PKP2 4-0 = 10001 PKP2 4-0 = 10010 PKP2 4-0 = 10011 PKP2 4-0 = 10100 PKP2 4-0 = 10101 PKP2 4-0 = 10110 PKP2 4-0 = 10111 PKP2 4-0 = 11000 PKP2 4-0 = 11001 PKP2 4-0 = 11010 PKP2 4-0 = 11011 PKP2 4-0 = 11100 PKP2 4-0 = 11101 PKP2 4-0 = 11110 PKP2 4-0 = 11111 (220R / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 3R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 6R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 9R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 12R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 15R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 18R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 21R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 24R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 27R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 30R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 33R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 36R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 39R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 42R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 45R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 48R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 51R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 54R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 57R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 60R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 63R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 66R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 69R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 72R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 75R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 78R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 81R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 84R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 87R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 90R) / 223R) * (VinP5 - VinP11) + VinP11 ((220R - 93R) / 223R) * (VinP5 - VinP11) + VinP11 Table 5.34: VinP6 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.102October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP7 formula VinP7 PKP3 4-0 = 00000 PKP3 4-0 = 00001 PKP3 4-0 = 00010 PKP3 4-0 = 00011 PKP3 4-0 = 00100 PKP3 4-0 = 00101 PKP3 4-0 = 00110 PKP3 4-0 = 00111 PKP3 4-0 = 01000 PKP3 4-0 = 01001 PKP3 4-0 = 01010 PKP3 4-0 = 01011 PKP3 4-0 = 01100 PKP3 4-0 = 01101 PKP3 4-0 = 01110 PKP3 4-0 = 01111 PKP3 4-0 = 10000 PKP3 4-0 = 10001 PKP3 4-0 = 10010 PKP3 4-0 = 10011 PKP3 4-0 = 10100 PKP3 4-0 = 10101 PKP3 4-0 = 10110 PKP3 4-0 = 10111 PKP3 4-0 = 11000 PKP3 4-0 = 11001 PKP3 4-0 = 11010 PKP3 4-0 = 11011 PKP3 4-0 = 11100 PKP3 4-0 = 11101 PKP3 4-0 = 11110 PKP3 4-0 = 11111 (193R / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 3R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 6R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 9R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 12R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 15R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 18R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 21R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 24R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 27R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 30R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 33R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 36R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 39R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 42R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 45R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 48R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 51R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 54R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 57R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 60R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 63R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 66R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 69R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 72R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 75R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 78R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 81R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 84R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 87R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 90R) / 223R) * (VinP5 - VinP11) + VinP11 ((193R - 93R) / 223R) * (VinP5 - VinP11) + VinP11 Table 5.35: VinP7 Reference voltage Macro adjustment value VinP8 formula VinP8 PKP4 4-0 = 00000 PKP4 4-0 = 00001 PKP4 4-0 = 00010 PKP4 4-0 = 00011 PKP4 4-0 = 00100 PKP4 4-0 = 00101 PKP4 4-0 = 00110 PKP4 4-0 = 00111 PKP4 4-0 = 01000 PKP4 4-0 = 01001 PKP4 4-0 = 01010 PKP4 4-0 = 01011 PKP4 4-0 = 01100 PKP4 4-0 = 01101 PKP4 4-0 = 01110 PKP4 4-0 = 01111 PKP4 4-0 = 10000 PKP4 4-0 = 10001 PKP4 4-0 = 10010 PKP4 4-0 = 10011 PKP4 4-0 = 10100 PKP4 4-0 = 10101 PKP4 4-0 = 10110 PKP4 4-0 = 10111 PKP4 4-0 = 11000 PKP4 4-0 = 11001 PKP4 4-0 = 11010 PKP4 4-0 = 11011 PKP4 4-0 = 11100 PKP4 4-0 = 11101 PKP4 4-0 = 11110 PKP4 4-0 = 11111 (158R / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 3R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 6R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 9R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 12R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 15R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 18R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 21R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 24R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 27R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 30R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 33R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 36R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 39R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 42R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 45R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 48R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 51R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 54R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 57R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 60R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 63R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 66R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 69R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 72R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 75R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 78R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 81R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 84R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 87R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 90R) / 223R) * (VinP5 - VinP11) + VinP11 ((158R - 93R) / 223R) * (VinP5 - VinP11) + VinP11 Table 5.36: VinP8 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.103October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP9 formula VinP9 PKP5 4-0 = 00000 PKP5 4-0 = 00001 PKP5 4-0 = 00010 PKP5 4-0 = 00011 PKP5 4-0 = 00100 PKP5 4-0 = 00101 PKP5 4-0 = 00110 PKP5 4-0 = 00111 PKP5 4-0 = 01000 PKP5 4-0 = 01001 PKP5 4-0 = 01010 PKP5 4-0 = 01011 PKP5 4-0 = 01100 PKP5 4-0 = 01101 PKP5 4-0 = 01110 PKP5 4-0 = 01111 PKP5 4-0 = 10000 PKP5 4-0 = 10001 PKP5 4-0 = 10010 PKP5 4-0 = 10011 PKP5 4-0 = 10100 PKP5 4-0 = 10101 PKP5 4-0 = 10110 PKP5 4-0 = 10111 PKP5 4-0 = 11000 PKP5 4-0 = 11001 PKP5 4-0 = 11010 PKP5 4-0 = 11011 PKP5 4-0 = 11100 PKP5 4-0 = 11101 PKP5 4-0 = 11110 PKP5 4-0 = 11111 (123R / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 3R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 6R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 9R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 12R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 15R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 18R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 21R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 24R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 27R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 30R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 33R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 36R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 39R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 42R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 45R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 48R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 51R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 54R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 57R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 60R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 63R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 66R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 69R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 72R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 75R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 78R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 81R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 84R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 87R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 90R) / 223R) * (VinP5 - VinP11) + VinP11 ((123R - 93R) / 223R) * (VinP5 - VinP11) + VinP11 Table 5.37: VinP9 Reference voltage Macro adjustment value VinP10 formula VinP10 PKP6 4-0 = 00000 PKP6 4-0 = 00001 PKP6 4-0 = 00010 PKP6 4-0 = 00011 PKP6 4-0 = 00100 PKP6 4-0 = 00101 PKP6 4-0 = 00110 PKP6 4-0 = 00111 PKP6 4-0 = 01000 PKP6 4-0 = 01001 PKP6 4-0 = 01010 PKP6 4-0 = 01011 PKP6 4-0 = 01100 PKP6 4-0 = 01101 PKP6 4-0 = 01110 PKP6 4-0 = 01111 PKP6 4-0 = 10000 PKP6 4-0 = 10001 PKP6 4-0 = 10010 PKP6 4-0 = 10011 PKP6 4-0 = 10100 PKP6 4-0 = 10101 PKP6 4-0 = 10110 PKP6 4-0 = 10111 PKP6 4-0 = 11000 PKP6 4-0 = 11001 PKP6 4-0 = 11010 PKP6 4-0 = 11011 PKP6 4-0 = 11100 PKP6 4-0 = 11101 PKP6 4-0 = 11110 PKP6 4-0 = 11111 (96R / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 3R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 6R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 9R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 12R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 15R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 18R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 21R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 24R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 27R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 30R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 33R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 36R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 39R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 42R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 45R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 48R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 51R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 54R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 57R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 60R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 63R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 66R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 69R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 72R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 75R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 78R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 81R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 84R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 87R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 90R) / 223R) * (VinP5 - VinP11) + VinP11 ((96R - 93R) / 223R) * (VinP5 - VinP11) + VinP11 Table 5.38: VinP10 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.104October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinP12 formula VinP12 PKP7 4-0 = 00000 PKP7 4-0 = 00001 PKP7 4-0 = 00010 PKP7 4-0 = 00011 PKP7 4-0 = 00100 PKP7 4-0 = 00101 PKP7 4-0 = 00110 PKP7 4-0 = 00111 PKP7 4-0 = 01000 PKP7 4-0 = 01001 PKP7 4-0 = 01010 PKP7 4-0 = 01011 PKP7 4-0 = 01100 PKP7 4-0 = 01101 PKP7 4-0 = 01110 PKP7 4-0 = 01111 PKP7 4-0 = 10000 PKP7 4-0 = 10001 PKP7 4-0 = 10010 PKP7 4-0 = 10011 PKP7 4-0 = 10100 PKP7 4-0 = 10101 PKP7 4-0 = 10110 PKP7 4-0 = 10111 PKP7 4-0 = 11000 PKP7 4-0 = 11001 PKP7 4-0 = 11010 PKP7 4-0 = 11011 PKP7 4-0 = 11100 PKP7 4-0 = 11101 PKP7 4-0 = 11110 PKP7 4-0 = 11111 (47R / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 1R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 2R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 3R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 4R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 5R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 6R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 7R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 8R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 9R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 10R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 11R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 12R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 13R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 14R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 15R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 16R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 17R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 18R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 19R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 20R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 21R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 22R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 23R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 24R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 25R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 26R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 27R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 28R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 29R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 30R) / 48R) * (VinP11 - VinP14) + VinP14 ((47R - 31R) / 48R) * (VinP11 - VinP14) + VinP14 Table 5.39: VinP12 Reference voltage Macro adjustment value VinP13 formula VinP13 PKP8 4-0 = 00000 PKP8 4-0 = 00001 PKP8 4-0 = 00010 PKP8 4-0 = 00011 PKP8 4-0 = 00100 PKP8 4-0 = 00101 PKP8 4-0 = 00110 PKP8 4-0 = 00111 PKP8 4-0 = 01000 PKP8 4-0 = 01001 PKP8 4-0 = 01010 PKP8 4-0 = 01011 PKP8 4-0 = 01100 PKP8 4-0 = 01101 PKP8 4-0 = 01110 PKP8 4-0 = 01111 PKP8 4-0 = 10000 PKP8 4-0 = 10001 PKP8 4-0 = 10010 PKP8 4-0 = 10011 PKP8 4-0 = 10100 PKP8 4-0 = 10101 PKP8 4-0 = 10110 PKP8 4-0 = 10111 PKP8 4-0 = 11000 PKP8 4-0 = 11001 PKP8 4-0 = 11010 PKP8 4-0 = 11011 PKP8 4-0 = 11100 PKP8 4-0 = 11101 PKP8 4-0 = 11110 PKP8 4-0 = 11111 (32R / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 1R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 2R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 3R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 4R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 5R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 6R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 7R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 8R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 9R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 10R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 11R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 12R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 13R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 14R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 15R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 16R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 17R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 18R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 19R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 20R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 21R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 22R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 23R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 24R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 25R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 26R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 27R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 28R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 29R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 30R) / 48R) * (VinP11 - VinP14) + VinP14 ((32R - 31R) / 48R) * (VinP11 - VinP14) + VinP14 Table 5.40: VinP13 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.105October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN0 formula VinN0 VRN0 5-0 = 000000 VRN0 5-0 = 000001 VRN0 5-0 = 000010 VRN0 5-0 = 000011 VRN0 5-0 = 000100 VRN0 5-0 = 000101 VRN0 5-0 = 000110 VRN0 5-0 = 000111 VRN0 5-0 = 001000 VRN0 5-0 = 001001 VRN0 5-0 = 001010 VRN0 5-0 = 001011 VRN0 5-0 = 001100 VRN0 5-0 = 001101 VRN0 5-0 = 001110 VRN0 5-0 = 001111 VRN0 5-0 = 010000 VRN0 5-0 = 010001 VRN0 5-0 = 010010 VRN0 5-0 = 010011 VRN0 5-0 = 010100 VRN0 5-0 = 010101 VRN0 5-0 = 010110 VRN0 5-0 = 010111 VRN0 5-0 = 011000 VRN0 5-0 = 011001 VRN0 5-0 = 011010 VRN0 5-0 = 011011 VRN0 5-0 = 011100 VRN0 5-0 = 011101 VRN0 5-0 = 011110 VRN0 5-0 = 011111 VRN0 5-0 = 100000 VRN0 5-0 = 100001 VRN0 5-0 = 100010 VRN0 5-0 = 100011 VRN0 5-0 = 100100 VRN0 5-0 = 100101 VRN0 5-0 = 100110 VRN0 5-0 = 100111 VRN0 5-0 = 101000 VRN0 5-0 = 101001 VRN0 5-0 = 101010 VRN0 5-0 = 101011 VRN0 5-0 = 101100 VRN0 5-0 = 101101 VRN0 5-0 = 101110 VRN0 5-0 = 101111 VRN0 5-0 = 110000 VRN0 5-0 = 110001 VRN0 5-0 = 110010 VRN0 5-0 = 110011 VRN0 5-0 = 110100 VRN0 5-0 = 110101 VRN0 5-0 = 110110 VRN0 5-0 = 110111 VRN0 5-0 = 111000 VRN0 5-0 = 111001 VRN0 5-0 = 111010 VRN0 5-0 = 111011 VRN0 5-0 = 111100 VRN0 5-0 = 111101 VRN0 5-0 = 111110 VRN0 5-0 = 111111 VSNR ((450R - 20R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 22R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 24R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 26R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 28R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 30R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 32R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 34R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 36R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 38R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 40R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 42R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 44R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 46R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 48R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 50R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 52R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 54R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 56R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 58R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 60R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 62R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 64R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 66R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 68R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 70R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 72R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 74R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 76R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 78R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 80R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 82R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 84R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 86R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 88R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 90R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 92R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 94R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 96R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 98R ) / 450R) * (VSNR - VGSN) + VGSN ((450R - 100R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 102R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 104R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 106R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 108R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 110R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 112R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 114R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 116R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 118R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 120R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 122R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 126R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 128R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 130R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 132R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 134R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 136R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 138R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 140R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 142R) / 450R) * (VSNR - VGSN) + VGSN ((450R - 144R) / 450R) * (VSNR - VGSN) + VGSN Table 5.41: VinN0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.106October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN1 formula VinN1 VRN1 5-0 = 000000 VRN1 5-0 = 000001 VRN1 5-0 = 000010 VRN1 5-0 = 000011 VRN1 5-0 = 000100 VRN1 5-0 = 000101 VRN1 5-0 = 000110 VRN1 5-0 = 000111 VRN1 5-0 = 001000 VRN1 5-0 = 001001 VRN1 5-0 = 001010 VRN1 5-0 = 001011 VRN1 5-0 = 001100 VRN1 5-0 = 001101 VRN1 5-0 = 001110 VRN1 5-0 = 001111 VRN1 5-0 = 010000 VRN1 5-0 = 010001 VRN1 5-0 = 010010 VRN1 5-0 = 010011 VRN1 5-0 = 010100 VRN1 5-0 = 010101 VRN1 5-0 = 010110 VRN1 5-0 = 010111 VRN1 5-0 = 011000 VRN1 5-0 = 011001 VRN1 5-0 = 011010 VRN1 5-0 = 011011 VRN1 5-0 = 011100 VRN1 5-0 = 011101 VRN1 5-0 = 011110 VRN1 5-0 = 011111 VRN1 5-0 = 100000 VRN1 5-0 = 100001 VRN1 5-0 = 100010 VRN1 5-0 = 100011 VRN1 5-0 = 100100 VRN1 5-0 = 100101 VRN1 5-0 = 100110 VRN1 5-0 = 100111 VRN1 5-0 = 101000 VRN1 5-0 = 101001 VRN1 5-0 = 101010 VRN1 5-0 = 101011 VRN1 5-0 = 101100 VRN1 5-0 = 101101 VRN1 5-0 = 101110 VRN1 5-0 = 101111 VRN1 5-0 = 110000 VRN1 5-0 = 110001 VRN1 5-0 = 110010 VRN1 5-0 = 110011 VRN1 5-0 = 110100 VRN1 5-0 = 110101 VRN1 5-0 = 110110 VRN1 5-0 = 110111 VRN1 5-0 = 111000 VRN1 5-0 = 111001 VRN1 5-0 = 111010 VRN1 5-0 = 111011 VRN1 5-0 = 111100 VRN1 5-0 = 111101 VRN1 5-0 = 111110 VRN1 5-0 = 111111 (430R / 450R) * (VSNR - VGSN) + VGSN ((430R - 2R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 4R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 6R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 8R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 10R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 12R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 14R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 16R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 18R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 20R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 22R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 24R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 26R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 28R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 30R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 32R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 34R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 36R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 38R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 40R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 42R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 44R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 46R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 48R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 50R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 52R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 54R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 56R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 58R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 60R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 62R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 64R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 66R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 68R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 70R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 72R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 74R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 76R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 78R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 80R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 82R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 84R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 86R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 88R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 90R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 92R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 94R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 96R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 98R ) / 450R) * (VSNR - VGSN) + VGSN ((430R - 100R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 102R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 104R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 106R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 108R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 110R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 112R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 114R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 116R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 118R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 120R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 122R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((430R - 126R) / 450R) * (VSNR - VGSN) + VGSN Table 5.42: VinN1 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.107October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN2 formula VinN2 VRN2 5-0 = 000000 VRN2 5-0 = 000001 VRN2 5-0 = 000010 VRN2 5-0 = 000011 VRN2 5-0 = 000100 VRN2 5-0 = 000101 VRN2 5-0 = 000110 VRN2 5-0 = 000111 VRN2 5-0 = 001000 VRN2 5-0 = 001001 VRN2 5-0 = 001010 VRN2 5-0 = 001011 VRN2 5-0 = 001100 VRN2 5-0 = 001101 VRN2 5-0 = 001110 VRN2 5-0 = 001111 VRN2 5-0 = 010000 VRN2 5-0 = 010001 VRN2 5-0 = 010010 VRN2 5-0 = 010011 VRN2 5-0 = 010100 VRN2 5-0 = 010101 VRN2 5-0 = 010110 VRN2 5-0 = 010111 VRN2 5-0 = 011000 VRN2 5-0 = 011001 VRN2 5-0 = 011010 VRN2 5-0 = 011011 VRN2 5-0 = 011100 VRN2 5-0 = 011101 VRN2 5-0 = 011110 VRN2 5-0 = 011111 VRN2 5-0 = 100000 VRN2 5-0 = 100001 VRN2 5-0 = 100010 VRN2 5-0 = 100011 VRN2 5-0 = 100100 VRN2 5-0 = 100101 VRN2 5-0 = 100110 VRN2 5-0 = 100111 VRN2 5-0 = 101000 VRN2 5-0 = 101001 VRN2 5-0 = 101010 VRN2 5-0 = 101011 VRN2 5-0 = 101100 VRN2 5-0 = 101101 VRN2 5-0 = 101110 VRN2 5-0 = 101111 VRN2 5-0 = 110000 VRN2 5-0 = 110001 VRN2 5-0 = 110010 VRN2 5-0 = 110011 VRN2 5-0 = 110100 VRN2 5-0 = 110101 VRN2 5-0 = 110110 VRN2 5-0 = 110111 VRN2 5-0 = 111000 VRN2 5-0 = 111001 VRN2 5-0 = 111010 VRN2 5-0 = 111011 VRN2 5-0 = 111100 VRN2 5-0 = 111101 VRN2 5-0 = 111110 VRN2 5-0 = 111111 (420R / 450R) * (VSNR - VGSN) + VGSN ((420R - 2R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 4R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 6R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 8R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 10R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 12R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 14R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 16R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 18R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 20R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 22R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 24R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 26R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 28R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 30R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 32R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 34R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 36R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 38R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 40R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 42R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 44R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 46R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 48R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 50R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 52R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 54R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 56R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 58R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 60R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 62R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 64R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 66R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 68R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 70R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 72R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 74R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 76R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 78R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 80R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 82R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 84R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 86R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 88R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 90R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 92R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 94R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 96R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 98R ) / 450R) * (VSNR - VGSN) + VGSN ((420R - 100R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 102R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 104R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 106R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 108R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 110R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 112R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 114R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 116R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 118R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 120R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 122R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((420R - 126R) / 450R) * (VSNR - VGSN) + VGSN Table 5.43: VinN2 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.108October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN14 formula VinN14 VRN3 5-0 = 000000 VRN3 5-0 = 000001 VRN3 5-0 = 000010 VRN3 5-0 = 000011 VRN3 5-0 = 000100 VRN3 5-0 = 000101 VRN3 5-0 = 000110 VRN3 5-0 = 000111 VRN3 5-0 = 001000 VRN3 5-0 = 001001 VRN3 5-0 = 001010 VRN3 5-0 = 001011 VRN3 5-0 = 001100 VRN3 5-0 = 001101 VRN3 5-0 = 001110 VRN3 5-0 = 001111 VRN3 5-0 = 010000 VRN3 5-0 = 010001 VRN3 5-0 = 010010 VRN3 5-0 = 010011 VRN3 5-0 = 010100 VRN3 5-0 = 010101 VRN3 5-0 = 010110 VRN3 5-0 = 010111 VRN3 5-0 = 011000 VRN3 5-0 = 011001 VRN3 5-0 = 011010 VRN3 5-0 = 011011 VRN3 5-0 = 011100 VRN3 5-0 = 011101 VRN3 5-0 = 011110 VRN3 5-0 = 011111 VRN3 5-0 = 100000 VRN3 5-0 = 100001 VRN3 5-0 = 100010 VRN3 5-0 = 100011 VRN3 5-0 = 100100 VRN3 5-0 = 100101 VRN3 5-0 = 100110 VRN3 5-0 = 100111 VRN3 5-0 = 101000 VRN3 5-0 = 101001 VRN3 5-0 = 101010 VRN3 5-0 = 101011 VRN3 5-0 = 101100 VRN3 5-0 = 101101 VRN3 5-0 = 101110 VRN3 5-0 = 101111 VRN3 5-0 = 110000 VRN3 5-0 = 110001 VRN3 5-0 = 110010 VRN3 5-0 = 110011 VRN3 5-0 = 110100 VRN3 5-0 = 110101 VRN3 5-0 = 110110 VRN3 5-0 = 110111 VRN3 5-0 = 111000 VRN3 5-0 = 111001 VRN3 5-0 = 111010 VRN3 5-0 = 111011 VRN3 5-0 = 111100 VRN3 5-0 = 111101 VRN3 5-0 = 111110 VRN3 5-0 = 111111 (156R / 450R) * (VSNR - VGSN) + VGSN ((156R - 2R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 4R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 6R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 8R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 10R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 12R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 14R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 16R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 18R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 20R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 22R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 24R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 26R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 28R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 30R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 32R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 34R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 36R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 38R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 40R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 42R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 44R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 46R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 48R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 50R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 52R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 54R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 56R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 58R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 60R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 62R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 64R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 66R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 68R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 70R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 72R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 74R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 76R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 78R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 80R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 82R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 84R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 86R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 88R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 90R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 92R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 94R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 96R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 98R ) / 450R) * (VSNR - VGSN) + VGSN ((156R - 100R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 102R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 104R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 106R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 108R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 110R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 112R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 114R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 116R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 118R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 120R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 122R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((156R - 126R) / 450R) * (VSNR - VGSN) + VGSN Table 5.44: VinN14 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.109October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN15 formula VinN15 VRN4 5-0 = 000000 VRN4 5-0 = 000001 VRN4 5-0 = 000010 VRN4 5-0 = 000011 VRN4 5-0 = 000100 VRN4 5-0 = 000101 VRN4 5-0 = 000110 VRN4 5-0 = 000111 VRN4 5-0 = 001000 VRN4 5-0 = 001001 VRN4 5-0 = 001010 VRN4 5-0 = 001011 VRN4 5-0 = 001100 VRN4 5-0 = 001101 VRN4 5-0 = 001110 VRN4 5-0 = 001111 VRN4 5-0 = 010000 VRN4 5-0 = 010001 VRN4 5-0 = 010010 VRN4 5-0 = 010011 VRN4 5-0 = 010100 VRN4 5-0 = 010101 VRN4 5-0 = 010110 VRN4 5-0 = 010111 VRN4 5-0 = 011000 VRN4 5-0 = 011001 VRN4 5-0 = 011010 VRN4 5-0 = 011011 VRN4 5-0 = 011100 VRN4 5-0 = 011101 VRN4 5-0 = 011110 VRN4 5-0 = 011111 VRN4 5-0 = 100000 VRN4 5-0 = 100001 VRN4 5-0 = 100010 VRN4 5-0 = 100011 VRN4 5-0 = 100100 VRN4 5-0 = 100101 VRN4 5-0 = 100110 VRN4 5-0 = 100111 VRN4 5-0 = 101000 VRN4 5-0 = 101001 VRN4 5-0 = 101010 VRN4 5-0 = 101011 VRN4 5-0 = 101100 VRN4 5-0 = 101101 VRN4 5-0 = 101110 VRN4 5-0 = 101111 VRN4 5-0 = 110000 VRN4 5-0 = 110001 VRN4 5-0 = 110010 VRN4 5-0 = 110011 VRN4 5-0 = 110100 VRN4 5-0 = 110101 VRN4 5-0 = 110110 VRN4 5-0 = 110111 VRN4 5-0 = 111000 VRN4 5-0 = 111001 VRN4 5-0 = 111010 VRN4 5-0 = 111011 VRN4 5-0 = 111100 VRN4 5-0 = 111101 VRN4 5-0 = 111110 VRN4 5-0 = 111111 (146R / 450R) * (VSNR - VGSN) + VGSN ((146R - 2R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 4R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 6R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 8R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 10R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 12R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 14R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 16R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 18R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 20R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 22R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 24R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 26R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 28R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 30R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 32R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 34R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 36R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 38R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 40R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 42R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 44R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 46R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 48R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 50R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 52R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 54R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 56R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 58R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 60R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 62R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 64R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 66R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 68R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 70R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 72R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 74R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 76R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 78R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 80R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 82R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 84R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 86R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 88R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 90R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 92R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 94R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 96R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 98R ) / 450R) * (VSNR - VGSN) + VGSN ((146R - 100R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 102R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 104R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 106R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 108R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 110R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 112R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 114R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 116R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 118R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 120R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 122R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((146R - 126R) / 450R) * (VSNR - VGSN) + VGSN Table 5.45: VinN15 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.110October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN16 formula VinN16 VRN5 5-0 = 000000 VRN5 5-0 = 000001 VRN5 5-0 = 000010 VRN5 5-0 = 000011 VRN5 5-0 = 000100 VRN5 5-0 = 000101 VRN5 5-0 = 000110 VRN5 5-0 = 000111 VRN5 5-0 = 001000 VRN5 5-0 = 001001 VRN5 5-0 = 001010 VRN5 5-0 = 001011 VRN5 5-0 = 001100 VRN5 5-0 = 001101 VRN5 5-0 = 001110 VRN5 5-0 = 001111 VRN5 5-0 = 010000 VRN5 5-0 = 010001 VRN5 5-0 = 010010 VRN5 5-0 = 010011 VRN5 5-0 = 010100 VRN5 5-0 = 010101 VRN5 5-0 = 010110 VRN5 5-0 = 010111 VRN5 5-0 = 011000 VRN5 5-0 = 011001 VRN5 5-0 = 011010 VRN5 5-0 = 011011 VRN5 5-0 = 011100 VRN5 5-0 = 011101 VRN5 5-0 = 011110 VRN5 5-0 = 011111 VRN5 5-0 = 100000 VRN5 5-0 = 100001 VRN5 5-0 = 100010 VRN5 5-0 = 100011 VRN5 5-0 = 100100 VRN5 5-0 = 100101 VRN5 5-0 = 100110 VRN5 5-0 = 100111 VRN5 5-0 = 101000 VRN5 5-0 = 101001 VRN5 5-0 = 101010 VRN5 5-0 = 101011 VRN5 5-0 = 101100 VRN5 5-0 = 101101 VRN5 5-0 = 101110 VRN5 5-0 = 101111 VRN5 5-0 = 110000 VRN5 5-0 = 110001 VRN5 5-0 = 110010 VRN5 5-0 = 110011 VRN5 5-0 = 110100 VRN5 5-0 = 110101 VRN5 5-0 = 110110 VRN5 5-0 = 110111 VRN5 5-0 = 111000 VRN5 5-0 = 111001 VRN5 5-0 = 111010 VRN5 5-0 = 111011 VRN5 5-0 = 111100 VRN5 5-0 = 111101 VRN5 5-0 = 111110 VRN5 5-0 = 111111 (144R / 450R) * (VSNR - VGSN) + VGSN ((144R - 2R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 4R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 6R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 8R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 10R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 12R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 14R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 16R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 18R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 20R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 22R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 24R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 26R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 28R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 30R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 32R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 34R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 36R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 38R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 40R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 42R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 44R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 46R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 48R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 50R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 52R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 54R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 56R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 58R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 60R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 62R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 64R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 66R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 68R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 70R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 72R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 74R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 76R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 78R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 80R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 82R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 84R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 86R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 88R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 90R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 92R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 94R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 96R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 98R ) / 450R) * (VSNR - VGSN) + VGSN ((144R - 100R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 102R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 104R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 106R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 108R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 110R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 112R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 114R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 116R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 118R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 120R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 122R) / 450R) * (VSNR - VGSN) + VGSN ((144R - 124R) / 450R) * (VSNR - VGSN) + VGSN VGSN Table 5.46: VinN16 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.111October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage VinN5 Macro adjustment value VinN5 formula PRN0 6-0 = 0000000 PRN0 6-0 = 0000001 PRN0 6-0 = 0000010 PRN0 6-0 = 0000011 PRN0 6-0 = 0000100 PRN0 6-0 = 0000101 PRN0 6-0 = 0000110 PRN0 6-0 = 0000111 PRN0 6-0 = 0001000 PRN0 6-0 = 0001001 PRN0 6-0 = 0001010 PRN0 6-0 = 0001011 PRN0 6-0 = 0001100 PRN0 6-0 = 0001101 PRN0 6-0 = 0001110 PRN0 6-0 = 0001111 PRN0 6-0 = 0010000 PRN0 6-0 = 0010001 PRN0 6-0 = 0010010 PRN0 6-0 = 0010011 PRN0 6-0 = 0010100 PRN0 6-0 = 0010101 PRN0 6-0 = 0010110 PRN0 6-0 = 0010111 PRN0 6-0 = 0011000 PRN0 6-0 = 0011001 PRN0 6-0 = 0011010 PRN0 6-0 = 0011011 PRN0 6-0 = 0011100 PRN0 6-0 = 0011101 PRN0 6-0 = 0011110 PRN0 6-0 = 0011111 PRN0 6-0 = 0100000 PRN0 6-0 = 0100001 PRN0 6-0 = 0100010 PRN0 6-0 = 0100011 PRN0 6-0 = 0100100 PRN0 6-0 = 0100101 PRN0 6-0 = 0100110 PRN0 6-0 = 0100111 PRN0 6-0 = 0101000 PRN0 6-0 = 0101001 PRN0 6-0 = 0101010 PRN0 6-0 = 0101011 PRN0 6-0 = 0101100 PRN0 6-0 = 0101101 PRN0 6-0 = 0101110 PRN0 6-0 = 0101111 PRN0 6-0 = 0110000 PRN0 6-0 = 0110001 PRN0 6-0 = 0110010 PRN0 6-0 = 0110011 PRN0 6-0 = 0110100 PRN0 6-0 = 0110101 PRN0 6-0 = 0110110 PRN0 6-0 = 0110111 PRN0 6-0 = 0111000 PRN0 6-0 = 0111001 PRN0 6-0 = 0111010 PRN0 6-0 = 0111011 PRN0 6-0 = 0111100 PRN0 6-0 = 0111101 PRN0 6-0 = 0111110 PRN0 6-0 = 0111111 PRN0 6-0 = 1000000 PRN0 6-0 = 1000001 PRN0 6-0 = 1000010 PRN0 6-0 = 1000011 PRN0 6-0 = 1000100 (350R / 450R) (VSNR - VGSN) + VGSN ((350R - 2R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 4R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 6R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 8R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 10R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 12R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 14R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 16R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 18R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 20R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 22R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 24R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 26R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 28R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 30R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 32R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 34R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 36R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 38R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 40R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 42R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 44R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 46R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 48R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 50R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 52R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 54R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 56R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 58R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 60R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 62R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 64R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 66R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 68R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 70R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 72R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 74R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 76R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 78R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 80R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 82R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 84R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 86R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 88R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 90R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 92R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 94R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 96R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 98R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 100R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 102R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 104R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 106R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 108R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 110R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 112R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 114R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 116R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 118R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 120R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 122R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 126R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 128R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 130R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 132R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 134R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 136R) / 450R) * (VSNR - VGSN) + VGSN Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.112October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 PRN0 6-0 = 1000101 PRN0 6-0 = 1000110 PRN0 6-0 = 1000111 PRN0 6-0 = 1001000 PRN0 6-0 = 1001001 PRN0 6-0 = 1001010 PRN0 6-0 = 1001011 PRN0 6-0 = 1001100 PRN0 6-0 = 1001101 PRN0 6-0 = 1001110 PRN0 6-0 = 1001111 PRN0 6-0 = 1010000 PRN0 6-0 = 1010001 PRN0 6-0 = 1010010 PRN0 6-0 = 1010011 PRN0 6-0 = 1010100 PRN0 6-0 = 1010101 PRN0 6-0 = 1010110 PRN0 6-0 = 1010111 PRN0 6-0 = 1011000 PRN0 6-0 = 1011001 PRN0 6-0 = 1011010 PRN0 6-0 = 1011011 PRN0 6-0 = 1011100 PRN0 6-0 = 1011101 PRN0 6-0 = 1011110 PRN0 6-0 = 1011111 PRN0 6-0 = 1100000 PRN0 6-0 = 1100001 PRN0 6-0 = 1100010 PRN0 6-0 = 1100011 PRN0 6-0 = 1100100 PRN0 6-0 = 1100101 PRN0 6-0 = 1100110 PRN0 6-0 = 1100111 PRN0 6-0 = 1101000 PRN0 6-0 = 1101001 PRN0 6-0 = 1101010 PRN0 6-0 = 1101011 PRN0 6-0 = 1101100 PRN0 6-0 = 1101101 PRN0 6-0 = 1101110 PRN0 6-0 = 1101111 PRN0 6-0 = 1110000 PRN0 6-0 = 1110001 PRN0 6-0 = 1110010 PRN0 6-0 = 1110011 PRN0 6-0 = 1110100 PRN0 6-0 = 1110101 PRN0 6-0 = 1110110 PRN0 6-0 = 1110111 PRN0 6-0 = 1111000 PRN0 6-0 = 1111001 PRN0 6-0 = 1111010 PRN0 6-0 = 1111011 PRN0 6-0 = 1111100 PRN0 6-0 = 1111101 PRN0 6-0 = 1111110 PRN0 6-0 = 1111111 ((350R – 138R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 140R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 142R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 144R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 146R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 148R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 150R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 152R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 154R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 156R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 158R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 160R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 162R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 164R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 166R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 168R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 170R) / 450R) * (VSNR - VGSN) + VGSN ((350R – 172R) / 450R) * (VSNR - VGSN) + VGSN ((350R - 174R) / 450R) * (VSNR - VGSN) + VGSN inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit Table 5.47: VinN5 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.113October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage VinN11 Macro adjustment value VinN11 formula PRN1 6-0 = 0000000 PRN1 6-0 = 0000001 PRN1 6-0 = 0000010 PRN1 6-0 = 0000011 PRN1 6-0 = 0000100 PRN1 6-0 = 0000101 PRN1 6-0 = 0000110 PRN1 6-0 = 0000111 PRN1 6-0 = 0001000 PRN1 6-0 = 0001001 PRN1 6-0 = 0001010 PRN1 6-0 = 0001011 PRN1 6-0 = 0001100 PRN1 6-0 = 0001101 PRN1 6-0 = 0001110 PRN1 6-0 = 0001111 PRN1 6-0 = 0010000 PRN1 6-0 = 0010001 PRN1 6-0 = 0010010 PRN1 6-0 = 0010011 PRN1 6-0 = 0010100 PRN1 6-0 = 0010101 PRN1 6-0 = 0010110 PRN1 6-0 = 0010111 PRN1 6-0 = 0011000 PRN1 6-0 = 0011001 PRN1 6-0 = 0011010 PRN1 6-0 = 0011011 PRN1 6-0 = 0011100 PRN1 6-0 = 0011101 PRN1 6-0 = 0011110 PRN1 6-0 = 0011111 PRN1 6-0 = 0100000 PRN1 6-0 = 0100001 PRN1 6-0 = 0100010 PRN1 6-0 = 0100011 PRN1 6-0 = 0100100 PRN1 6-0 = 0100101 PRN1 6-0 = 0100110 PRN1 6-0 = 0100111 PRN1 6-0 = 0101000 PRN1 6-0 = 0101001 PRN1 6-0 = 0101010 PRN1 6-0 = 0101011 PRN1 6-0 = 0101100 PRN1 6-0 = 0101101 PRN1 6-0 = 0101110 PRN1 6-0 = 0101111 PRN1 6-0 = 0110000 PRN1 6-0 = 0110001 PRN1 6-0 = 0110010 PRN1 6-0 = 0110011 PRN1 6-0 = 0110100 PRN1 6-0 = 0110101 PRN1 6-0 = 0110110 PRN1 6-0 = 0110111 PRN1 6-0 = 0111000 PRN1 6-0 = 0111001 PRN1 6-0 = 0111010 PRN1 6-0 = 0111011 PRN1 6-0 = 0111100 PRN1 6-0 = 0111101 PRN1 6-0 = 0111110 PRN1 6-0 = 0111111 PRN1 6-0 = 1000000 PRN1 6-0 = 1000001 PRN1 6-0 = 1000010 PRN1 6-0 = 1000011 PRN1 6-0 = 1000100 (274R / 450R) (VSNR - VGSN) + VGSN ((274R - 2R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 4R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 6R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 8R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 10R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 12R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 14R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 16R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 18R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 20R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 22R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 24R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 26R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 28R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 30R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 32R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 34R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 36R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 38R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 40R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 42R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 44R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 46R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 48R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 50R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 52R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 54R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 56R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 58R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 60R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 62R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 64R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 66R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 68R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 70R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 72R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 74R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 76R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 78R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 80R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 82R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 84R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 86R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 88R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 90R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 92R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 94R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 96R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 98R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 100R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 102R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 104R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 106R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 108R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 110R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 112R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 114R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 116R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 118R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 120R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 122R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 124R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 126R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 128R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 130R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 132R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 134R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 136R) / 450R) * (VSNR - VGSN) + VGSN Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.114October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 PRN1 6-0 = 1000101 PRN1 6-0 = 1000110 PRN1 6-0 = 1000111 PRN1 6-0 = 1001000 PRN1 6-0 = 1001001 PRN1 6-0 = 1001010 PRN1 6-0 = 1001011 PRN1 6-0 = 1001100 PRN1 6-0 = 1001101 PRN1 6-0 = 1001110 PRN1 6-0 = 1001111 PRN1 6-0 = 1010000 PRN1 6-0 = 1010001 PRN1 6-0 = 1010010 PRN1 6-0 = 1010011 PRN1 6-0 = 1010100 PRN1 6-0 = 1010101 PRN1 6-0 = 1010110 PRN1 6-0 = 1010111 PRN1 6-0 = 1011000 PRN1 6-0 = 1011001 PRN1 6-0 = 1011010 PRN1 6-0 = 1011011 PRN1 6-0 = 1011100 PRN1 6-0 = 1011101 PRN1 6-0 = 1011110 PRN1 6-0 = 1011111 PRN1 6-0 = 1100000 PRN1 6-0 = 1100001 PRN1 6-0 = 1100010 PRN1 6-0 = 1100011 PRN1 6-0 = 1100100 PRN1 6-0 = 1100101 PRN1 6-0 = 1100110 PRN1 6-0 = 1100111 PRN1 6-0 = 1101000 PRN1 6-0 = 1101001 PRN1 6-0 = 1101010 PRN1 6-0 = 1101011 PRN1 6-0 = 1101100 PRN1 6-0 = 1101101 PRN1 6-0 = 1101110 PRN1 6-0 = 1101111 PRN1 6-0 = 1110000 PRN1 6-0 = 1110001 PRN1 6-0 = 1110010 PRN1 6-0 = 1110011 PRN1 6-0 = 1110100 PRN1 6-0 = 1110101 PRN1 6-0 = 1110110 PRN1 6-0 = 1110111 PRN1 6-0 = 1111000 PRN1 6-0 = 1111001 PRN1 6-0 = 1111010 PRN1 6-0 = 1111011 PRN1 6-0 = 1111100 PRN1 6-0 = 1111101 PRN1 6-0 = 1111110 PRN1 6-0 = 1111111 ((274R – 138R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 140R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 142R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 144R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 146R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 148R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 150R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 152R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 154R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 156R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 158R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 160R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 162R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 164R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 166R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 168R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 170R) / 450R) * (VSNR - VGSN) + VGSN ((274R – 172R) / 450R) * (VSNR - VGSN) + VGSN ((274R - 174R) / 450R) * (VSNR - VGSN) + VGSN inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit inhibit Table 5.48: VinN11 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.115October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN3 formula VinN3 PKN0 4-0 = 00000 PKN0 4-0 = 00001 PKN0 4-0 = 00010 PKN0 4-0 = 00011 PKN0 4-0 = 00100 PKN0 4-0 = 00101 PKN0 4-0 = 00110 PKN0 4-0 = 00111 PKN0 4-0 = 01000 PKN0 4-0 = 01001 PKN0 4-0 = 01010 PKN0 4-0 = 01011 PKN0 4-0 = 01100 PKN0 4-0 = 01101 PKN0 4-0 = 01110 PKN0 4-0 = 01111 PKN0 4-0 = 10000 PKN0 4-0 = 10001 PKN0 4-0 = 10010 PKN0 4-0 = 10011 PKN0 4-0 = 10100 PKN0 4-0 = 10101 PKN0 4-0 = 10110 PKN0 4-0 = 10111 PKN0 4-0 = 11000 PKN0 4-0 = 11001 PKN0 4-0 = 11010 PKN0 4-0 = 11011 PKN0 4-0 = 11100 PKN0 4-0 = 11101 PKN0 4-0 = 11110 PKN0 4-0 = 11111 (47R / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 1R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 2R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 3R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 4R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 5R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 6R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 7R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 8R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R – 9R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 10R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 11R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 12R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 13R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 14R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 15R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 16R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 17R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 18R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 19R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 20R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 21R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 22R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 23R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 24R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 25R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 26R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 27R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 28R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 29R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 30R) / 48R) * (VinN2 - VinN5) + VinN5 ((47R - 31R) / 48R) * (VinN2 - VinN5) + VinN5 Table 5.49: VinN3 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.116October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN4 formula VinN4 PKN1 4-0 = 00000 PKN1 4-0 = 00001 PKN1 4-0 = 00010 PKN1 4-0 = 00011 PKN1 4-0 = 00100 PKN1 4-0 = 00101 PKN1 4-0 = 00110 PKN1 4-0 = 00111 PKN1 4-0 = 01000 PKN1 4-0 = 01001 PKN1 4-0 = 01010 PKN1 4-0 = 01011 PKN1 4-0 = 01100 PKN1 4-0 = 01101 PKN1 4-0 = 01110 PKN1 4-0 = 01111 PKN1 4-0 = 10000 PKN1 4-0 = 10001 PKN1 4-0 = 10010 PKN1 4-0 = 10011 PKN1 4-0 = 10100 PKN1 4-0 = 10101 PKN1 4-0 = 10110 PKN1 4-0 = 10111 PKN1 4-0 = 11000 PKN1 4-0 = 11001 PKN1 4-0 = 11010 PKN1 4-0 = 11011 PKN1 4-0 = 11100 PKN1 4-0 = 11101 PKN1 4-0 = 11110 PKN1 4-0 = 11111 (32R / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 1R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 2R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 3R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 4R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 5R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 6R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 7R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 8R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 9R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 10R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 11R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 12R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 13R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 14R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 15R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 16R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 17R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 18R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 19R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 20R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 21R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 22R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 23R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 24R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 25R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 26R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 27R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 28R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 29R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 30R) / 48R) * (VinN2 - VinN5) + VinN5 ((32R - 31R) / 48R) * (VinN2 - VinN5) + VinN5 Table 5.50: VinN4 Reference voltage Macro adjustment value VinN6 formula VinN6 PKN2 4-0 = 00000 PKN2 4-0 = 00001 PKN2 4-0 = 00010 PKN2 4-0 = 00011 PKN2 4-0 = 00100 PKN2 4-0 = 00101 PKN2 4-0 = 00110 PKN2 4-0 = 00111 PKN2 4-0 = 01000 PKN2 4-0 = 01001 PKN2 4-0 = 01010 PKN2 4-0 = 01011 PKN2 4-0 = 01100 PKN2 4-0 = 01101 PKN2 4-0 = 01110 PKN2 4-0 = 01111 PKN2 4-0 = 10000 PKN2 4-0 = 10001 PKN2 4-0 = 10010 PKN2 4-0 = 10011 PKN2 4-0 = 10100 PKN2 4-0 = 10101 PKN2 4-0 = 10110 PKN2 4-0 = 10111 PKN2 4-0 = 11000 PKN2 4-0 = 11001 PKN2 4-0 = 11010 PKN2 4-0 = 11011 PKN2 4-0 = 11100 PKN2 4-0 = 11101 PKN2 4-0 = 11110 PKN2 4-0 = 11111 (220R / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 3R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 6R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 9R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 12R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 15R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 18R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 21R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 24R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 27R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 30R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 33R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 36R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 39R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 42R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 45R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 48R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 51R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 54R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 57R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 60R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 63R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 66R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 69R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 72R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 75R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 78R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 81R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 84R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 87R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 90R) / 223R) * (VinN5 - VinN11) + VinN11 ((220R - 93R) / 223R) * (VinN5 - VinN11) + VinN11 Table 5.51: VinN6 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.117October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN7 formula VinN7 PKN3 4-0 = 00000 PKN3 4-0 = 00001 PKN3 4-0 = 00010 PKN3 4-0 = 00011 PKN3 4-0 = 00100 PKN3 4-0 = 00101 PKN3 4-0 = 00110 PKN3 4-0 = 00111 PKN3 4-0 = 01000 PKN3 4-0 = 01001 PKN3 4-0 = 01010 PKN3 4-0 = 01011 PKN3 4-0 = 01100 PKN3 4-0 = 01101 PKN3 4-0 = 01110 PKN3 4-0 = 01111 PKN3 4-0 = 10000 PKN3 4-0 = 10001 PKN3 4-0 = 10010 PKN3 4-0 = 10011 PKN3 4-0 = 10100 PKN3 4-0 = 10101 PKN3 4-0 = 10110 PKN3 4-0 = 10111 PKN3 4-0 = 11000 PKN3 4-0 = 11001 PKN3 4-0 = 11010 PKN3 4-0 = 11011 PKN3 4-0 = 11100 PKN3 4-0 = 11101 PKN3 4-0 = 11110 PKN3 4-0 = 11111 (193R / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 3R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 6R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 9R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 12R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 15R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 18R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 21R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 24R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 27R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 30R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 33R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 36R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 39R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 42R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 45R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 48R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 51R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 54R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 57R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 60R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 63R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 66R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 69R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 72R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 75R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 78R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 81R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 84R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 87R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 90R) / 223R) * (VinN5 - VinN11) + VinN11 ((193R - 93R) / 223R) * (VinN5 - VinN11) + VinN11 Table 5.52: VinN7 Reference voltage Macro adjustment value VinN8 formula VinN8 PKN4 4-0 = 00000 PKN4 4-0 = 00001 PKN4 4-0 = 00010 PKN4 4-0 = 00011 PKN4 4-0 = 00100 PKN4 4-0 = 00101 PKN4 4-0 = 00110 PKN4 4-0 = 00111 PKN4 4-0 = 01000 PKN4 4-0 = 01001 PKN4 4-0 = 01010 PKN4 4-0 = 01011 PKN4 4-0 = 01100 PKN4 4-0 = 01101 PKN4 4-0 = 01110 PKN4 4-0 = 01111 PKN4 4-0 = 10000 PKN4 4-0 = 10001 PKN4 4-0 = 10010 PKN4 4-0 = 10011 PKN4 4-0 = 10100 PKN4 4-0 = 10101 PKN4 4-0 = 10110 PKN4 4-0 = 10111 PKN4 4-0 = 11000 PKN4 4-0 = 11001 PKN4 4-0 = 11010 PKN4 4-0 = 11011 PKN4 4-0 = 11100 PKN4 4-0 = 11101 PKN4 4-0 = 11110 PKN4 4-0 = 11111 (158R / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 3R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 6R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 9R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 12R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 15R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 18R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 21R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 24R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 27R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 30R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 33R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 36R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 39R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 42R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 45R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 48R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 51R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 54R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 57R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 60R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 63R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 66R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 69R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 72R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 75R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 78R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 81R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 84R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 87R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 90R) / 223R) * (VinN5 - VinN11) + VinN11 ((158R - 93R) / 223R) * (VinN5 - VinN11) + VinN11 Table 5.53: VinN8 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.118October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN9 formula VinN9 PKN5 4-0 = 00000 PKN5 4-0 = 00001 PKN5 4-0 = 00010 PKN5 4-0 = 00011 PKN5 4-0 = 00100 PKN5 4-0 = 00101 PKN5 4-0 = 00110 PKN5 4-0 = 00111 PKN5 4-0 = 01000 PKN5 4-0 = 01001 PKN5 4-0 = 01010 PKN5 4-0 = 01011 PKN5 4-0 = 01100 PKN5 4-0 = 01101 PKN5 4-0 = 01110 PKN5 4-0 = 01111 PKN5 4-0 = 10000 PKN5 4-0 = 10001 PKN5 4-0 = 10010 PKN5 4-0 = 10011 PKN5 4-0 = 10100 PKN5 4-0 = 10101 PKN5 4-0 = 10110 PKN5 4-0 = 10111 PKN5 4-0 = 11000 PKN5 4-0 = 11001 PKN5 4-0 = 11010 PKN5 4-0 = 11011 PKN5 4-0 = 11100 PKN5 4-0 = 11101 PKN5 4-0 = 11110 PKN5 4-0 = 11111 (123R / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 3R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 6R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 9R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 12R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 15R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 18R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 21R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 24R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 27R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 30R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 33R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 36R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 39R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 42R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 45R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 48R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 51R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 54R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 57R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 60R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 63R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 66R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 69R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 72R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 75R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 78R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 81R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 84R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 87R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 90R) / 223R) * (VinN5 - VinN11) + VinN11 ((123R - 93R) / 223R) * (VinN5 - VinN11) + VinN11 Table 5.54: VinN9 Reference voltage Macro adjustment value VinN10 formula VinN10 PKN6 4-0 = 00000 PKN6 4-0 = 00001 PKN6 4-0 = 00010 PKN6 4-0 = 00011 PKN6 4-0 = 00100 PKN6 4-0 = 00101 PKN6 4-0 = 00110 PKN6 4-0 = 00111 PKN6 4-0 = 01000 PKN6 4-0 = 01001 PKN6 4-0 = 01010 PKN6 4-0 = 01011 PKN6 4-0 = 01100 PKN6 4-0 = 01101 PKN6 4-0 = 01110 PKN6 4-0 = 01111 PKN6 4-0 = 10000 PKN6 4-0 = 10001 PKN6 4-0 = 10010 PKN6 4-0 = 10011 PKN6 4-0 = 10100 PKN6 4-0 = 10101 PKN6 4-0 = 10110 PKN6 4-0 = 10111 PKN6 4-0 = 11000 PKN6 4-0 = 11001 PKN6 4-0 = 11010 PKN6 4-0 = 11011 PKN6 4-0 = 11100 PKN6 4-0 = 11101 PKN6 4-0 = 11110 PKN6 4-0 = 11111 (96R / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 3R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 6R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 9R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 12R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 15R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 18R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 21R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 24R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 27R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 30R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 33R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 36R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 39R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 42R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 45R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 48R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 51R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 54R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 57R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 60R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 63R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 66R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 69R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 72R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 75R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 78R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 81R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 84R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 87R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 90R) / 223R) * (VinN5 - VinN11) + VinN11 ((96R - 93R) / 223R) * (VinN5 - VinN11) + VinN11 Table 5.55: VinN10 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.119October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Reference voltage Macro adjustment value VinN12 formula VinN12 PKN7 4-0 = 00000 PKN7 4-0 = 00001 PKN7 4-0 = 00010 PKN7 4-0 = 00011 PKN7 4-0 = 00100 PKN7 4-0 = 00101 PKN7 4-0 = 00110 PKN7 4-0 = 00111 PKN7 4-0 = 01000 PKN7 4-0 = 01001 PKN7 4-0 = 01010 PKN7 4-0 = 01011 PKN7 4-0 = 01100 PKN7 4-0 = 01101 PKN7 4-0 = 01110 PKN7 4-0 = 01111 PKN7 4-0 = 10000 PKN7 4-0 = 10001 PKN7 4-0 = 10010 PKN7 4-0 = 10011 PKN7 4-0 = 10100 PKN7 4-0 = 10101 PKN7 4-0 = 10110 PKN7 4-0 = 10111 PKN7 4-0 = 11000 PKN7 4-0 = 11001 PKN7 4-0 = 11010 PKN7 4-0 = 11011 PKN7 4-0 = 11100 PKN7 4-0 = 11101 PKN7 4-0 = 11110 PKN7 4-0 = 11111 (47R / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 1R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 2R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 3R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 4R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 5R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 6R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 7R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 8R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 9R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 10R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 11R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 12R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 13R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 14R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 15R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 16R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 17R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 18R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 19R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 20R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 21R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 22R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 23R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 24R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 25R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 26R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 27R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 28R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 29R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 30R) / 48R) * (VinN11 - VinN14) + VinN14 ((47R - 31R) / 48R) * (VinN11 - VinN14) + VinN14 Table 5.56: VinN12 Reference voltage Macro adjustment value VinN13 formula VinN13 PKN8 4-0 = 00000 PKN8 4-0 = 00001 PKN8 4-0 = 00010 PKN8 4-0 = 00011 PKN8 4-0 = 00100 PKN8 4-0 = 00101 PKN8 4-0 = 00110 PKN8 4-0 = 00111 PKN8 4-0 = 01000 PKN8 4-0 = 01001 PKN8 4-0 = 01010 PKN8 4-0 = 01011 PKN8 4-0 = 01100 PKN8 4-0 = 01101 PKN8 4-0 = 01110 PKN8 4-0 = 01111 PKN8 4-0 = 10000 PKN8 4-0 = 10001 PKN8 4-0 = 10010 PKN8 4-0 = 10011 PKN8 4-0 = 10100 PKN8 4-0 = 10101 PKN8 4-0 = 10110 PKN8 4-0 = 10111 PKN8 4-0 = 11000 PKN8 4-0 = 11001 PKN8 4-0 = 11010 PKN8 4-0 = 11011 PKN8 4-0 = 11100 PKN8 4-0 = 11101 PKN8 4-0 = 11110 PKN8 4-0 = 11111 (32R / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 1R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 2R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 3R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 4R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 5R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 6R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 7R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 8R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 9R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 10R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 11R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 12R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 13R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 14R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 15R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 16R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 17R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 18R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 19R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 20R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 21R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 22R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 23R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 24R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 25R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 26R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 27R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 28R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 29R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 30R) / 48R) * (VinN11 - VinN14) + VinN14 ((32R - 31R) / 48R) * (VinN11 - VinN14) + VinN14 Table 5.57: VinN13 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.120October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage Formula V0 VinP0 V1 VinP1 V2 VinP2 V3 VinP3 CGMP0=0 = VinP3 - (VinP3 - VinP4)*(1R/4R) V4 V5 V6 V7 V8 V9 V10 V11 Grayscale voltage V16 V17 V18 CGMP4=1 =VinP5 - (VinP5 - VinP6)*(5.5R/6.5R) V19 VinP6 CGMP0=3 = VinP3 - (VinP3 - VinP4)*(3.5R/10R) V20 VinP6 - (VinP6 - VinP7)*(1R/6R) CGMP0=0 = VinP3 - (VinP3 - VinP4)*(2R/4R) V21 VinP6 - (VinP6 - VinP7)*(2R/6R) CGMP0=1 = VinP3 - (VinP3 - VinP4)*(5.5R/9.5R) V22 VinP6 - (VinP6 - VinP7)*(3R/6R) CGMP0=2 = VinP3 - (VinP3 - VinP4)*(6R/9.3R) V23 VinP6 - (VinP6 - VinP7)*(4R/6R) CGMP0=3 = VinP3 - (VinP3 - VinP4)*(6R/10R) V24 VinP6 - (VinP6 - VinP7)*(5R/6R) CGMP0=0 = VinP3 - (VinP3 - VinP4)*(3R/4R) V25 VinP7 CGMP0=1 = VinP3 - (VinP3 - VinP4)*(7.5R/9.5R) V26 VinP7 - (VinP7 - VinP8)*(1R/7.5R) CGMP0=2 = VinP3 - (VinP3 - VinP4)*(7.8R/9.3R) V27 VinP7 - (VinP7 - VinP8)*(2R/7.5R) CGMP0=3= VinP3 - (VinP3 - VinP4)*(8R/10R) V28 VinP7 - (VinP7 - VinP8)*(3R/7.5R) VinP4 V29 VinP7 - (VinP7 - VinP8)*(4R/7.5R) CGMP2=0 = VinP4 - (VinP4 - VinP5)*(1R/6R) V30 VinP7 - (VinP7 - VinP8)*(5R/7.5R) CGMP2=1 = VinP4 - (VinP4 - VinP5)*(3R/16R) V31 VinP7 - (VinP7 - VinP8)*(6R/7.5R) CGMP2=2 = VinP4 - (VinP4 - VinP5)*(4R/18R) V32 VinP8 CGMP2=3 = VinP4 - (VinP4 - VinP5)*(4.5R/19.5R) V33 VinP8 - (VinP8 - VinP9)*(1R/6R) CGMP2=0 = VinP4 - (VinP4 - VinP5)*(2R/6R) V34 VinP8 - (VinP8 - VinP9)*(2R/6R) CGMP2=1 = VinP4 - (VinP4 - VinP5)*(6R/16R) V35 VinP8 - (VinP8 - VinP9)*(3R/6R) CGMP2=2 = VinP4 - (VinP4 - VinP5)*(7R/18R) V36 VinP8 - (VinP8 - VinP9)*(4R/6R) CGMP2=3 = VinP4 - (VinP4 - VinP5)*(8.5R/19.5R) V37 VinP8 - (VinP8 - VinP9)*(5R/6R) CGMP2=0 = VinP4 - (VinP4 - VinP5)*(3R/6R) V38 VinP9 CGMP2=1 = VinP4 - (VinP4 - VinP5)*(8.5R/16R) V39 VinP9 - (VinP9 - VinP10)*(1R/6R) CGMP2=2 = VinP4 - (VinP4 - VinP5)*(10R/18R) V40 VinP9 - (VinP9 - VinP10)*(2R/6R) CGMP2=3 = VinP4 - (VinP4 - VinP5)*(11.5R/19.5R) V41 VinP9 - (VinP9 - VinP10)*(3R/6R) CGMP2=0 = VinP4 - (VinP4 - VinP5)*(4R/6R) V42 VinP9 - (VinP9 - VinP10)*(4R/6R) CGMP2=1 = VinP4 - (VinP4 - VinP5)*(11R/16R) V43 VinP9 - (VinP9 - VinP10)*(5R/6R) CGMP2=2 = VinP4 - (VinP4 - VinP5)*(13R/18R) V44 CGMP2=1 = VinP4 - (VinP4 - VinP5)*(13.5R/16R) CGMP2=3 = VinP4 - (VinP4 - VinP5)*(17R/19.5R) V45 V46 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(2R/6R) CGMP4=1 =VinP5 - (VinP5 - VinP6)*(2.5R/6.5R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(2R/6R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(2R/6.5R) V47 VinP5 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(1R/6R) VinP10 CGMP5=0 =VinP10 - (VinP10 - VinP11)*(1R/6R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(1R/6.5R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(3R/6R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(3R/6.5R) V48 CGMP4=1 =VinP5 - (VinP5 - VinP6)*(1.5R/6.5R) V15 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(5R/6R) CGMP0=2 = VinP3 - (VinP3 - VinP4)*(3.5R/9.3R) CGMP2=2 = VinP4 - (VinP4 - VinP5)*(15.5R/18R) V14 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(4R/6R) CGMP4=1 =VinP5 - (VinP5 - VinP6)*(4.5R/6.5R) CGMP2=0 = VinP4 - (VinP4 - VinP5)*(5R/6R) V13 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(3R/6R) CGMP4=1 =VinP5 - (VinP5 - VinP6)*(3.5R/6.5R) CGMP0=1 = VinP3 - (VinP3 - VinP4)*(3R/9.5R) CGMP2=3 = VinP4 - (VinP4 - VinP5)*(14.5R/19.5R) V12 Formula CGMP5=0 =VinP10 - (VinP10 - VinP11)*(4R/6R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(4R/6.5R) V49 CGMP5=0 =VinP10 - (VinP10 - VinP11)*(5R/6R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(5R/6.5R) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.121October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage V50 Formula VinP11 Grayscale voltage V56 CGMP3=0 = VinP11 - (VinP11 - VinP12)*(1R/6R) CGMP3=2 = VinP11 - (VinP11 - VinP12)*(2.5R/18R) VinP12 CGMP1=0 = VinP12 - (VinP12 – VinP13)*(1R/4R) CGMP3=1 = VinP11 - (VinP11 - VinP12)*(2.5R/16R) V51 Formula CGMP1=1 = VinP12 - (VinP12 – VinP13)*(2R/9.5R) V57 CGMP1=2 = VinP12 - (VinP12 – VinP13)*(1.5R/9.3R) CGMP3=3 = VinP11 - (VinP11 - VinP12)* (2.5R/19.5R) CGMP1=3 = VinP12 - (VinP12 – VinP13)*(2R/10R) CGMP3=0 = VinP11 - (VinP11- VinP12)*(2R/6R) CGMP1=0 = VinP12 - (VinP12 – VinP13)*(2R/4R) CGMP3=1 = VinP11 - (VinP11 - VinP12)*(5R/16R) V52 CGMP1=1 = VinP12 - (VinP12 – VinP13)*(4R/9.5R) V58 CGMP3=2 = VinP11 - (VinP11 - VinP12)*(5R/18R) CGMP1=2 = VinP12 - (VinP12 – VinP13)*(3.3R/9.3R) CGMP3=3 = VinP11 - (VinP11 - VinP12)*(5R/19.5R) CGMP1=3 = VinP12 - (VinP12 – VinP13)*(4R/10R) CGMP3=0 = VinP11 - (VinP11 - VinP12)*(3R/6R) CGMP1=0 = VinP12 - (VinP12 – VinP13)*(3R/4R) CGMP3=1 = VinP11 - (VinP11 - VinP12)*(7.5R/16R) V53 CGMP1=1 = VinP12 - (VinP12 – VinP13)*(6.5R/9.5R) V59 CGMP3=2 = VinP11 - (VinP11 - VinP12)*(8R/18R) CGMP1=2 = VinP12 - (VinP12 – VinP13)*(5.8R/9.3R) CGMP3=3 = VinP11 - (VinP11 - VinP12)*(8R/19.5R) CGMP1=3= VinP12 - (VinP12 – VinP13)*(6.5R/10R) CGMP3=0 = VinP11 - (VinP11 - VinP12)*(4R/6R) V60 VinP13 CGMP3=1 = VinP11 - (VinP11 - VinP12)*(10R/16R) V61 VinP14 CGMP3=2 = VinP11 - (VinP11 - VinP12)*(11R/18R) V62 VinP15 CGMP3=3 = VinP11 - (VinP11 - VinP12)* (11R/19.5R) V63 VinP16 V54 CGMP3=0 = VinP11 - (VinP11- VinP12)*(5R/6R) CGMP3=1 = VinP11 - (VinP11 - VinP12)*(13R/16R) V55 CGMP3=2 = VinP11 - (VinP11 - VinP12)*(14R/18R) CGMP3=3 = VinP11 - (VinP11 - VinP12)* (15R/19.5R) Table 5.58: Voltage calculation formula of 64-grayscale voltage (positive polarity) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.122October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage Formula V0 VinN0 V1 VinN1 V2 VinN2 V3 VinN3 CGMN0=0 = VinN3 - (VinN3 - VinN4)*(1R/4R) V4 V5 V6 V7 V8 V9 V10 V11 Grayscale voltage V16 V17 V18 CGMN0=1 = VinN3 - (VinN3 - VinN4)*(3R/9.5R) CGMN4=1 =VinN5 - (VinN5 - VinN6)*(5.5R/6.5R) V19 VinN6 CGMN0=3 = VinN3 - (VinN3 - VinN4)*(3.5R/10R) V20 VinN6 - (VinN6 - VinN7)*(1R/6R) CGMN0=0 = VinN3 - (VinN3 - VinN4)*(2R/4R) V21 VinN6 - (VinN6 - VinN7)*(2R/6R) CGMN0=1 = VinN3 - (VinN3 - VinN4)*(5.5R/9.5R) V22 VinN6 - (VinN6 - VinN7)*(3R/6R) CGMN0=2 = VinN3 - (VinN3 - VinN4)*(6R/9.3R) V23 VinN6 - (VinN6 - VinN7)*(4R/6R) CGMN0=3 = VinN3 - (VinN3 - VinN4)*(6R/10R) V24 VinN6 - (VinN6 - VinN7)*(5R/6R) CGMN0=0 = VinN3 - (VinN3 - VinN4)*(3R/4R) V25 VinP7 CGMN0=1 = VinN3 - (VinN3 - VinN4)*(7.5R/9.5R) V26 VinP7 - (VinP7 - VinP8)*(1R/7.5R) CGMN0=2 = VinN3 - (VinN3 - VinN4)*(7.8R/9.3R) V27 VinP7 - (VinP7 - VinP8)*(2R/7.5R) CGMN0=3= VinN3 - (VinN3 - VinN4)*(8R/10R) V28 VinP7 - (VinP7 - VinP8)*(3R/7.5R) VinN4 V29 VinP7 - (VinP7 - VinP8)*(4R/7.5R) CGMN2=0 = VinN4 - (VinN4 - VinN5)*(1R/6R) V30 VinP7 - (VinP7 - VinP8)*(5R/7.5R) CGMN2=1 = VinN4 - (VinN4 - VinN5)*(3R/16R) V31 VinP7 - (VinP7 - VinP8)*(6R/7.5R) CGMN2=2 = VinN4 - (VinN4 - VinN5)*(4R/18R) V32 VinP8 CGMN2=3 = VinN4 - (VinN4 - VinN5)*(4.5R/19.5R) V33 VinP8 - (VinP8 - VinP9)*(1R/6R) CGMN2=0 = VinN4 - (VinN4 - VinN5)*(2R/6R) V34 VinP8 - (VinP8 - VinP9)*(2R/6R) CGMN2=1 = VinN4 - (VinN4 - VinN5)*(6R/16R) V35 VinP8 - (VinP8 - VinP9)*(3R/6R) CGMN2=2 = VinN4 - (VinN4 - VinN5)*(7R/18R) V36 VinP8 - (VinP8 - VinP9)*(4R/6R) CGMN2=3 = VinN4 - (VinN4 - VinN5)*(8.5R/19.5R) V37 VinP8 - (VinP8 - VinP9)*(5R/6R) CGMN2=0 = VinN4 - (VinN4 - VinN5)*(3R/6R) V38 VinN9 CGMN2=1 = VinN4 - (VinN4 - VinN5)*(8.5R/16R) V39 VinN9 - (VinN9 - VinN10)*(1R/6R) CGMN2=2 = VinN4 - (VinN4 - VinN5)*(10R/18R) V40 VinN9 - (VinN9 - VinN10)*(2R/6R) CGMN2=3 = VinN4 - (VinN4 VinN5)*(11.5R/19.5R) V41 VinN9 - (VinN9 - VinN10)*(3R/6R) CGMN2=0 = VinN4 - (VinN4 - VinN5)*(4R/6R) V42 VinN9 - (VinN9 - VinN10)*(4R/6R) CGMN2=1 = VinN4 - (VinN4 - VinN5)*(11R/16R) V43 VinN9 - (VinN9 - VinN10)*(5R/6R) CGMN2=2 = VinN4 - (VinN4 - VinN5)*(13R/18R) V44 VinN10 CGMN2=3 = VinN4 - (VinN4 VinN5)*(14.5R/19.5R) V45 CGMN2=1 = VinN4 - (VinN4 - VinN5)*(13.5R/16R) V46 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(2R/6R) CGMN4=1 =VinN5 - (VinN5 - VinN6)*(2.5R/6.5R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(2R/6R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(2R/6.5R) V47 VinN5 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(1R/6R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(1R/6R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(1R/6.5R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(3R/6R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(3R/6.5R) V48 CGMN4=1 =VinN5 - (VinN5 - VinN6)*(1.5R/6.5R) V15 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(5R/6R) CGMN0=2 = VinN3 - (VinN3 - VinN4)*(3.5R/9.3R) CGMN2=3 = VinN4 - (VinN4 - VinN5)*(17R/19.5R) V14 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(4R/6R) CGMN4=1 =VinN5 - (VinN5 - VinN6)*(4.5R/6.5R) CGMN2=2 = VinN4 - (VinN4 - VinN5)*(15.5R/18R) V13 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(3R/6R) CGMN4=1 =VinN5 - (VinN5 - VinN6)*(3.5R/6.5R) CGMN2=0 = VinN4 - (VinN4 - VinN5)*(5R/6R) V12 Formula CGMN5=0 =VinN10 - (VinN10 - VinN11)*(4R/6R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(4R/6.5R) V49 CGMN5=0 =VinN10 - (VinN10 - VinN11)*(5R/6R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(5R/6.5R) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.123October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage V50 Formula VinN11 Grayscale voltage V56 CGMN3=0 = VinN11 - (VinN11 - VinN12)*(1R/6R) VinN12 CGMN1=0 = VinN12 - (VinN12 – VinN13)*(1R/4R) CGMN3=1 = VinN11 - (VinN11 - VinN12)*(2.5R/16R) V51 Formula CGMN1=1 = VinN12 - (VinN12 – VinN13)*(2R/9.5R) V57 CGMN3=2 = VinN11 - (VinN11 - VinN12)*(2.5R/18R) CGMN1=2 = VinN12 - (VinN12 – VinN13)*(1.5R/9.3R) CGMN3=3 = VinN11 - (VinN11 VinN12)*(2.5R/19.5R) CGMN1=3 = VinN12 - (VinN12 – VinN13)*(2R/10R) CGMN3=0 = VinN11 - (VinN11- VinN12)*(2R/6R) CGMN1=0 = VinN12 - (VinN12 – VinN13)*(2R/4R) CGMN3=1 = VinN11 - (VinN11 - VinN12)*(5R/16R) V52 CGMN1=1 = VinN12 - (VinN12 – VinN13)*(4R/9.5R) V58 CGMN3=2 = VinN11 - (VinN11 - VinN12)*(5R/18R) CGMN1=2 = VinN12 - (VinN12 – VinN13)*(3.3R/9.3R) CGMN3=3 = VinN11 - (VinN11 - VinN12)*(5R/19.5R) CGMN1=3 = VinN12 - (VinN12 – VinN13)*(4R/10R) CGMN3=0 = VinN11 - (VinN11 - VinN12)*(3R/6R) CGMN1=0 = VinN12 - (VinN12 – VinN13)*(3R/4R) CGMN3=1 = VinN11 - (VinN11 - VinN12)*(7.5R/16R) V53 CGMN1=1 = VinN12 - (VinN12 – VinN13)*(6.5R/9.5R) V59 CGMN3=2 = VinN11 - (VinN11 - VinN12)*(8R/18R) CGMN1=2 = VinN12 - (VinN12 – VinN13)*(5.8R/9.3R) CGMN3=3 = VinN11 - (VinN11 - VinN12)*(8R/19.5R) CGMN1=3= VinN12 - (VinN12 – VinN13)*(6.5R/10R) CGMN3=0 = VinN11 - (VinN11 - VinN12)*(4R/6R) V60 VinN13 CGMN3=1 = VinN11 - (VinN11 - VinN12)*(10R/16R) V61 VinN14 CGMN3=2 = VinN11 - (VinN11 - VinN12)*(11R/18R) V62 VinN15 CGMN3=3 = VinN11 - (VinN11 - VinN12)*(11R/19.5R) V63 VinN16 V54 CGMN3=0 = VinN11 - (VinN11- VinN12)*(5R/6R) CGMN3=1 = VinN11 - (VinN11 - VinN12)*(13R/16R) V55 CGMN3=2 = VinN11 - (VinN11 - VinN12)*(14R/18R) CGMN3=3 = VinN11 - (VinN11 - VinN12)*(15R/19.5R) Table 5.59: Voltage calculation formula of 64-grayscale voltage (negative polarity) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.124October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage Formula Grayscale voltage Formula VV0 V0 VV44 V11 VV1 V0 - (V0 - V1)*(4R/16R) VV45 V11 - (V11 - V12)*(1.6R/6.4R) VV2 V0 - (V0 - V1)*(8R/16R) VV46 V11 - (V11 - V12)*(3.2R/6.4R) VV3 V0 - (V0 - V1)*(12R/16R) VV47 V11 - (V11 - V12)*(4.8R/6.4R) VV4 V1 VV48 V12 VV5 V1 - (V1 - V2)*(4R/16R) VV49 V12 - (V12 - V13)*(1.6R/6.4R) VV6 V1 - (V1 - V2)*(8R/16R) VV50 V12 - (V12 - V13)*(3.2R/6.4R) VV7 V1 - (V1 - V2)*(12R/16R) VV51 V12 - (V12 - V13)*(4.8R/6.4R) VV8 V2 VV52 V13 VV9 V2 - (V2 - V3)*(4R/16R) VV53 V13 - (V13 - V14)*(1.6R/6.4R) VV10 V2 - (V2 - V3)*(8R/16R) VV54 V13 - (V13 - V14)*(3.2R/6.4R) VV11 V2 - (V2 - V3)*(12R/16R) VV55 V13 - (V13 - V14)*(4.8R/6.4R) VV12 V3 VV56 V14 VV13 V3 - (V3 - V4)*(2R/8R) VV57 V14 - (V14 - V15)*(1.6R/6.4R) VV14 V3 - (V3 - V4)*(4R/8R) VV58 V14 - (V14 - V15)*(3.2R/6.4R) VV15 V3 - (V3 - V4)*(6R/8R) VV59 V14 - (V14 - V15)*(4.8R/6.4R) VV16 V4 VV60 V15 VV17 V4 - (V4 - V5)*(2R/8R) VV61 V15 - (V15 - V16)*(1.6R/6.4R) VV18 V4 - (V4 - V5)*(4R/8R) VV62 V15 - (V15 - V16)*(3.2R/6.4R) VV19 V4 - (V4 - V5)*(6R/8R) VV63 V15 - (V15 - V16)*(4.8R/6.4R) VV20 V5 VV64 V16 VV21 V5 - (V5 - V6)*(2R/8R) VV65 V16 - (V16 - V17)*(1.6R/6.4R) VV22 V5 - (V5 - V6)*(4R/8R) VV66 V16 - (V16 - V17)*(3.2R/6.4R) VV23 V5 - (V5 - V6)*(6R/8R) VV67 V16 - (V16 - V17)*(4.8R/6.4R) VV24 V6 VV68 V17 VV25 V6 - (V6 - V7)*(2R/8R) VV69 V17 - (V17 - V18)*(1.6R/6.4R) VV26 V6 - (V6 - V7)*(4R/8R) VV70 V17 - (V17 - V18)*(3.2R/6.4R) VV27 V6 - (V6 - V7)*(6R/8R) VV71 V17 - (V17 - V18)*(4.8R/6.4R) VV28 V7 VV72 V18 VV73 V18 - (V18 - V19)*(1.6R/6.4R) VV29 V7 - (V7 - V8)*(1.6R/6.4R) VV30 V7 - (V7 - V8)*(3.2R/6.4R) VV74 V18 - (V18 - V19)*(3.2R/6.4R) VV31 V7 - (V7 - V8)*(4.8R/6.4R) VV75 V18 - (V18 - V19)*(4.8R/6.4R) VV32 V8 VV76 V19 VV33 V8 - (V8 - V9)*(1.6R/6.4R) VV77 V19 - (V19 - V20)*(1.6R/6.4R) VV34 V8 - (V8 - V9)*(3.2R/6.4R) VV78 V19 - (V19 - V20)*(3.2R/6.4R) VV35 V8 - (V8 - V9)*(4.8R/6.4R) VV79 V19 - (V19 - V20)*(4.8R/6.4R) VV36 V9 VV80 V20 VV37 V9 - (V9 - V10)*(1.6R/6.4R) VV81 V20 - (V20 - V21)*(1.6R/6.4R) VV38 V9 - (V9 - V10)*(3.2R/6.4R) VV82 V20 - (V20 - V21)*(3.2R/6.4R) VV39 V9 - (V9 - V10)*(4.8R/6.4R) VV83 V20 - (V20 - V21)*(4.8R/6.4R) VV40 V10 VV84 V21 VV41 V10 - (V10 - V11)*(1.6R/6.4R) VV85 V21 - (V21 - V22)*(1.6R/6.4R) VV42 V10 - (V10 - V11)*(3.2R/6.4R) VV86 V21 - (V21 - V22)*(3.2R/6.4R) VV43 V10 - (V10 - V11)*(4.8R/6.4R) VV87 V21 - (V21 - V22)*(4.8R/6.4R) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.125October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage Formula Grayscale voltage Formula VV88 V22 VV132 V32 - (V32 - V33)*(1.6R/6.4R) VV89 V22 - (V22 - V23)*(1.6R/6.4R) VV133 V32 - (V32 - V33)*(3.2R/6.4R) VV90 V22 - (V22 - V23)*(3.2R/6.4R) VV134 V32 - (V32 - V33)*(4.8R/6.4R) VV91 V22 - (V22 - V23)*(4.8R/6.4R) VV135 V33 VV92 V23 VV136 V33 - (V33 - V34)*(1.6R/6.4R) VV93 V23 - (V23 - V24)*(1.6R/6.4R) VV137 V33 - (V33 - V34)*(3.2R/6.4R) VV94 V23 - (V23 - V24)*(3.2R/6.4R) VV138 V33 - (V33 - V34)*(4.8R/6.4R) VV95 V23 - (V23 - V24)*(4.8R/6.4R) VV139 V34 VV96 V24 VV140 V34 - (V34 - V35)*(1.6R/6.4R) VV97 V24 - (V24 - V25)*(1.6R/6.4R) VV141 V34 - (V34 - V35)*(3.2R/6.4R) VV98 V24 - (V24 - V25)*(3.2R/6.4R) VV142 V34 - (V34 - V35)*(4.8R/6.4R) VV99 V24 - (V24 - V25)*(4.8R/6.4R) VV143 V35 VV100 V25 VV144 V35 - (V35 - V36)*(1.6R/6.4R) VV101 V25 - (V25 - V26)*(1.6R/6.4R) VV145 V35 - (V35 - V36)*(3.2R/6.4R) VV102 V25 - (V25 - V26)*(3.2R/6.4R) VV146 V35 - (V35 - V36)*(4.8R/6.4R) VV103 V25 - (V25 - V26)*(4.8R/6.4R) VV147 V36 VV104 V26 VV148 V36 - (V36 - V37)*(1.6R/6.4R) VV105 V26 - (V26 - V27)*(1.6R/6.4R) VV149 V36 - (V36 - V37)*(3.2R/6.4R) VV106 V26 - (V26 - V27)*(3.2R/6.4R) VV150 V36 - (V36 - V37)*(4.8R/6.4R) VV107 V26 - (V26 - V27)*(4.8R/6.4R) VV151 V37 VV108 V27 VV152 V37 - (V37 - V38)*(1.6R/6.4R) VV109 V27 - (V27 - V28)*(1.6R/6.4R) VV153 V37 - (V37 - V38)*(3.2R/6.4R) VV110 V27 - (V27 - V28)*(3.2R/6.4R) VV154 V37 - (V37 - V38)*(4.8R/6.4R) VV111 V27 - (V27 - V28)*(4.8R/6.4R) VV155 V38 VV112 V28 VV156 V38 - (V38 - V39)*(1.6R/6.4R) VV113 V28 - (V28 - V29)*(1.6R/6.4R) VV157 V38 - (V38 - V39)*(3.2R/6.4R) VV114 V28 - (V28 - V29)*(3.2R/6.4R) VV158 V38 - (V38 - V39)*(4.8R/6.4R) VV115 V28 - (V28 - V29)*(4.8R/6.4R) VV159 V39 VV116 V29 VV160 V39 - (V39 - V40)*(1.6R/6.4R) VV117 V29 - (V29 - V30)*(1.6R/6.4R) VV161 V39 - (V39 - V40)*(3.2R/6.4R) VV118 V29 - (V29 - V30)*(3.2R/6.4R) VV162 V39 - (V39 - V40)*(4.8R/6.4R) VV119 V29 - (V29 - V30)*(4.8R/6.4R) VV163 V40 VV120 V30 VV164 V40 - (V40 - V41)*(1.6R/6.4R) VV121 V30 - (V30 - V31)*(1.6R/6.4R) VV165 V40 - (V40 - V41)*(3.2R/6.4R) VV122 V30 - (V30 - V31)*(3.2R/6.4R) VV166 V40 - (V40 - V41)*(4.8R/6.4R) VV123 V30 - (V30 - V31)*(4.8R/6.4R) VV167 V41 VV124 V31 VV168 V41 - (V41 - V42)*(1.6R/6.4R) VV125 V31 - (V31 - V32)*(1.6R/11.2R) VV169 V41 - (V41 - V42)*(3.2R/6.4R) VV126 V31 - (V31 - V32)*(3.2R/11.2R) VV170 V41 - (V41 - V42)*(4.8R/6.4R) VV127 V31 - (V31 - V32)*(4.8R/11.2R) VV171 V42 VV128 V31 - (V31 - V32)*(6.4R/11.2R) VV172 V42 - (V42 - V43)*(1.6R/6.4R) VV129 V31 - (V31 - V32)*(8R/11.2R) VV173 V42 - (V42 - V43)*(3.2R/6.4R) VV130 V31 - (V31 - V32)*(9.6R/11.2R) VV174 V42 - (V42 - V43)*(4.8R/6.4R) VV131 V32 VV175 V43 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.126October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Grayscale voltage VV176 VV177 VV178 VV179 VV180 VV181 VV182 VV183 VV184 VV185 VV186 VV187 VV188 VV189 VV190 VV191 VV192 VV193 VV194 VV195 VV196 VV197 VV198 VV199 VV200 VV201 VV202 VV203 VV204 VV205 VV206 VV207 VV208 VV209 VV210 VV211 VV212 VV213 VV214 VV215 Formula V43 - (V43 - V44)*(1.6R/6.4R) V43 - (V43 - V44)*(3.2R/6.4R) V43 - (V43 - V44)*(4.8R/6.4R) V44 V44 - (V44 - V45)*(1.6R/6.4R) V44 - (V44 - V45)*(3.2R/6.4R) V44 - (V44 - V45)*(4.8R/6.4R) V45 V45 - (V45 - V46)*(1.6R/6.4R) V45 - (V45 - V46)*(3.2R/6.4R) V45 - (V45 - V46)*(4.8R/6.4R) V46 V46 - (V46 - V47)*(1.6R/6.4R) V46 - (V46 - V47)*(3.2R/6.4R) V46 - (V46 - V47)*(4.8R/6.4R) V47 V47 - (V47 - V48)*(1.6R/6.4R) V47 - (V47 - V48)*(3.2R/6.4R) V47 - (V47 - V48)*(4.8R/6.4R) V48 V48 - (V48 - V49)*(1.6R/6.4R) V48 - (V48 - V49)*(3.2R/6.4R) V48 - (V48 - V49)*(4.8R/6.4R) V49 V49 - (V49 - V50)*(1.6R/6.4R) V49 - (V49 - V50)*(3.2R/6.4R) V49 - (V49 - V50)*(4.8R/6.4R) V50 V50 - (V50 - V51)*(1.6R/6.4R) V50 - (V50 - V51)*(3.2R/6.4R) V50 - (V50 - V51)*(4.8R/6.4R) V51 V51 - (V51 - V52)*(1.6R/6.4R) V51 - (V51 - V52)*(3.2R/6.4R) V51 - (V51 - V52)*(4.8R/6.4R) V52 V52 - (V52 - V53)*(1.6R/6.4R) V52 - (V52 - V53)*(3.2R/6.4R) V52 - (V52 - V53)*(4.8R/6.4R) V53 Grayscale voltage VV216 VV217 VV218 VV219 VV220 VV221 VV222 VV223 VV224 VV225 VV226 VV227 VV228 VV229 VV230 VV231 VV232 VV233 VV234 VV235 VV236 VV237 VV238 VV239 VV240 VV241 VV242 VV243 VV244 VV245 VV246 VV247 VV248 VV249 VV250 VV251 VV252 VV253 VV254 VV255 Formula V53 - (V53 - V54)*(1.6R/6.4R) V53 - (V53 - V54)*(3.2R/6.4R) V53 - (V53 - V54)*(4.8R/6.4R) V54 V54 - (V54 - V55)*(1.6R/6.4R) V54 - (V54 - V55)*(3.2R/6.4R) V54 - (V54 - V55)*(4.8R/6.4R) V55 V55 - (V55 - V56)*(1.6R/6.4R) V55 - (V55 - V56)*(3.2R/6.4R) V55 - (V55 - V56)*(4.8R/6.4R) V56 V56 - (V56 - V57)*(2R/8R) V56 - (V56 - V57)*(4R/8R) V56 - (V56 - V57)*(6R/8R) V57 V57 - (V57 - V58)*(2R/8R) V57 - (V57 - V58)*(4R/8R) V57 - (V57 - V58)*(6R/8R) V58 V58 - (V58 - V59)*(2R/8R) V58 - (V58 - V59)*(4R/8R) V58 - (V58 - V59)*(6R/8R) V59 V59 - (V59 - V60)*(2R/8R) V59 - (V59 - V60)*(4R/8R) V59 - (V59 - V60)*(6R/8R) V60 V60 - (V60 - V61)*(4R/16R) V60 - (V60 - V61)*(8R/16R) V60 - (V60 - V61)*(12R/16R) V61 V61 - (V61 - V62)*(4R/16R) V61 - (V61 - V62)*(8R/16R) V61 - (V61 - V62)*(12R/16R) V62 V62 - (V62 - V63)*(4R/16R) V62 - (V62 - V63)*(8R/16R) V62 - (V62 - V63)*(12R/16R) V63 Table 5.60: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.127October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.13 Characteristics of I/O 5.13.1 Output or bi-directional (I/O) pins Output or bi-directional pins TE DB23 to DB0 (Output driver) SDO CABC_PWM_OUT After power on After hardware reset After software reset Low Low Low High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) Low High-Z (Inactive) Low High-Z (Inactive) Low Table 5.61 Characteristics of output or bi-directional (I/O) pins 5.13.2 Input pins Input pins RESX CSX DCX_SCL WRX_DCX RDX_E DB23 to DB0 SDI HSYNC VSYNC PCLK DE OSC, BS3, BS2, BS1, BS0, TEST2-1 Input valid Input valid Input valid Input valid Input valid After hardware reset Input valid Input valid Input valid Input valid Input valid After software reset Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Input valid Low Low During power on process After power on Setion.5.18 Input valid Input valid Input valid Input valid Low Low Low Table 5.62 Characteristics of input pins During power off process Setion.5.18 Input valid Input valid Input valid Input valid Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.128October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.14 GIP control singal HX8369-A00 is a single chip solution for a WVGA GIP (Gate In Panel) type TFT LCD display. There are many GIP/ASG type TFT panels that correspond to different GIP timing. Therefore, the GIP setting must be setup to the correct GIP/ASG timing for the normal display. The GIP timing adjustment is related to register 0xD5h SETGIP. The GIP control signals (GOUT[1~10]_L and GOUT[1~10]_R) is for panel used. The assignment of each panel type is specified on the application note. Regarding the GIP/ASG timing, please refer to HX8369-A00 application note. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.129October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.15 Sleep Out –command and self-diagnostic functions of the display module 5.15.1 Register loading detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from OTP (or similar device) to registers of the display controller is working properly. There are compared factory values of the OTP and register values of the display controller by the display controller. If those both values (OTP and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (=increased by 1). The flow chart for this internal function is following: Figure 5.33: Sleep out flow chart–command and self-diagnostic functions Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.130October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.15.2 Functionality detection Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (=the display controller) is comparing, if the display module still meets functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirement is met, 1 bit will be inverted (=increased by 1), which is defined in command “Read Display Self- Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this command is D6). If functionality requirement is not the same, this bit (D6) is not inverted (=increased by 1). The flow chart for this internal function is shown as below. Power on sequence HW reset SW reset Sleep In (10h) Sleep Out Mode Sleep In Mode RDDSDR`s D6=0 Sleep Out (11h) Checks timings, voltage levels and other functionalities NO Is functionality requirement meet ? YES D6 inverted Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In–mode toSleep Out -mode, before there is possible to check if Customer’s functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode. Figure 5.34: Sleep out flow chart internal function detection Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.131October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.16 Power on/off sequence VDD1, VDD2 and VDD3 can be applied in any order. VDD1, VDD2 and VDD3 can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD1 and VDD2 must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDD1, VDD2 and VDD3 can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. There will be no damage to the display module if the power sequences are not met. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. If RESX line is not held stable by host during Power On Sequence as defined in Sections 5.16.1 and 5.16.2, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.132October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.16.1 Case 1: RESX line is held high or unstable by host at power on If RESX line is held high or unstable by the host during power on, then a Hardware Reset must be applied after both VDD1, VDD2 and VDD3 have been appliedotherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. tRPW= +/- no limit tFPW= +/- no limit VDD1 VDD2 VDD3 Time when the latter signal rises up to 90% of its typical value. Ex. When VCI comes latter. This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V. Time when the former signal falls down to 90% of its typical value. Ex. When VCI falls earilier. This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V. tRPWICS= +/- no limit CSX tFPWICS= +/- no limit H or L tRPWIRES= + no limit tFPWIRES1= min 120ms RESX (Power down in sleep out mode) tRPWIRES= + no limit RESX (Power down in sleep in mode) tFPWIRES2= min 0ns tFPWIRES1 is applied to NRESET falling in the Sleep Out Mode tFPWIRES2 is applied to NRESET falling in the Sleep In Mode Figure 5.35: Case 1: RESX line is held high or unstable by host at power on Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.133October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.16.2 Case 2: RESX line is held low by host at power on If RESX line is held low (and stable) by the host during power on, then the RESX must be held low for minimum 10µsec after both VDD1, VDD2 and VDD3 have been applied. tRPW= +/- no limit tFPW= +/- no limit VDD1 VDD2 VDD3 Time when the latter signal rises up to 90% of its typical value. Ex. When VCI comes latter. This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V. Time when the former signal falls down to 90% of its typical value. Ex. When VCI falls earilier. This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V. tRPWICS= +/- no limit CSX tFPWICS= +/- no limit H or L tFPWIRES1= min 120ms tRPWIRES= min 10us RESX (Power down in sleep out mode) tRPWIRES= min 10us RESX tFPWIRES2= min 0ns (Power down in sleep in mode) tFPWIRES1 is applied to NREST falling in the Sleep Out Mode tFPWIRES2 is applied to NREST falling in the Figure 5.36: Case 2: RESX line is held low by host at power on 5.17 Uncontrolled power off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until “Power On Sequence” powers it up. Note: HX8369-A00 is support the noise reject filter (20ns) to reject spike or noise. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.134October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.18 Content adaptive brightness control (CABC) function The general block diagram of the CABC and the brightness control is illustrated below: External VSYNC, HSYNC, ENABLE, DCK (RGB interface) Display Control Signal Generator Display Data Generator Image data Display Data Contents Analysis C[1:0]= ‘00’ à off C[1:0]= ‘01’, ‘10’, ‘11’ à off CABC Gain / Duty CABC Block DBV[7:0] (R52h) (BL=0) PWM_CLK (FoscD) PWM Clock Devider Brightness Control Block PWM_OUT (BL=1) CABC[1:0] (R55h) SAVEPOWER[6:0] (RC9h) DBG0~8[6:0] (RCAh) SEL_PWMCLK[2:0] C9h) DBV[7:0] (R51h) BCTRL, BL(R53h) CMB[7:0](R5Eh) INVPLUS SEL_BLDUTY PWM_PERIOD (RC9h) Figure 5.37: CABC block diagram Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.135October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.18.1 Module architectures HX8369-A00 can support two module architectures for CABC operation. The BL bit setting of R53h can be used to select used display module architecture. White LED driver circuit for display backlight is located on the main PWB, not in the display module both in architecture I and II. • Architecture I CABC_ PWM_OUT 1. BL =`1` of R53h 2. LED backlight brightness for the dis play i s c ontrol led by external output “CABC_PWM_OUT”. • Architecture II 1. BL =`0` of R53h 2. LED backlight brightness data for the display is read with DBV[7:0] bits of R52h. 3. Read commands R53h should be synchronized with V-sync. Figure 5.38: Module architecture Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.136October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.18.2 CABC block There are DBG0~8[6:0] register bits in CABC block to define the “CABC gain”/ “CABC duty” table. Every DBGx[6:0] has 33 gain/duty value setting. After one-frame display data content analysis, LSI will generate one CABC gain / CABC duty value calculated from DBG0~8[6:0] register bits setting (by using interpolated method) for display data generating and for backlight PWM pulse generating. Please note that the CABC gain / CABC duty value calculated by the LSI is one of the 33 gain/duty value setting in DBGxx[6:0]. Please note that : Duty ( valid level period (LED on) / one complete period)=1/ gain. DBG0 Gain curve DBG1 DBG2 DBG3 DBG4 Gain DBG5 SAVEPOWER DBG6 DBG7 DBG8 0 32 64 96 128 160 192 224 256 One frame display data content analysis Figure 5.39: CABC gain / CABC duty generation For power saving of backlight module, there are SAVEPOWER[6:0] bits to define the “minimum gain”/ “maximum duty” of CABC block output. If the CABC gain / duty after one-frame display data contents analysis is smaller(gain) / larger(duty) than SAVEPOWER[6:0] bits setting, the CABC block will output CABC gain / duty equal to SAVEPOWER[6:0] and ignore the result of display data contents analysis. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.137October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.18.3 Brightness control block There is an external output signal from brightness block, CABC_PWM_OUT, to control the LED driver IC in order to control display brightness. There are resister bits, DBV[7:0] of R51h, for display brightness of manual brightness setting. The CABC_PWM_OUT duty is calculated as (DBV[7:0])/255 x CABC duty (generated after one-frame display data content analysis). For ex: CABC_PWM_OUT period=2.95 ms, and DBV[7:0](R51h)=‘228DEC’ and CABC duty is 74%. Then CABC_PWM_OUT duty=(228) / 255 x 74.42%≡66.54%. Correspond to the CABC_PWM_OUT period=2.95 ms, the high-level of CABC_PWM_OUT (high effective) = 1.96ms, and the low-level of CABC_PWM_OUT =0.99ms. One Period (tpw) ON CABC_ PWM_OUT (INVPLUS=`1`) Display Brightness OFF Duty = 100% OFF Duty = 100% Maximum Duty = 33% Duty = 66.57% Figure 5.40: CABC_PWM_OUT output duty Symbol tpw Parameter Pulse width Min. 0.0333 Max. 8.33 Unit ms Description - Table 5.63 CABC timing table Note1: The signal rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. Note2: The pulse width range by setting CABC related registers is locate between 0.0333ms to 8.33ms. When Architecture II module is used (BL=’0’) with the example below, the CABC_PWM_OUT is always output low and the DBV[7:0](R51h) will be read a value as 169DEC ((169)/255≡ 66.27%). Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.138October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.18.4 Minimum brightness setting of CABC function CABC function is automatically reduced backlight brightness based on image contents. In the case of the combination with the CABC or manual brightness setting, display brightness is too dark. It must affect to image quality degradation. CABC minimum brightness setting (CMB[7:0] bits of R5Eh) is to avoid too much brightness reduction. When CABC is active, CABC can not reduce the display brightness to less than CABC minimum brightness setting. Image processing function is worked as normal, even if the brightness can not be changed. This function does not affect to the other function, manual brightness setting. Manual brightness can be set the display brightness to less than CABC minimum brightness. Smooth transition and dimming function can be worked as normal. When display brightness is turned off (BCTRL=’0’ of R53h), CABC minimum brightness setting is ignored. “CMB[7:0], Read CABC minimum brightness (R5Fh)“ always read the setting value of “CMB[7:0], Write CABC minimum brightness (R5Eh)” Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.139October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19 OTP programing 5.19.1 OTP table OTP_INDEX (HEX) Ref. Command 00 SETOSC (B0h) 1B B7 B6 B5 B4 NVALID0 - - - B0 - - UADJ[3:0] VCMC_B1[7:0] SETVCOM (B6h) VCMC_F2[7:0] 1F VCMC_B2[7:0] 20 VCMC_F3[7:0] 21 VCMC_B3[7:0] 22 ID1_1[7:0] 23 NVALID_ID1 ID2_1[6:0] 24 ID3_1[7:0] 25 ID1_2[7:0] 26 NVALID_ID2 ID2_2[6:0] 27 ID3_2[7:0] 28 ID1_3[7:0] SETID (C3h) NVALID_ID3 ID2_3[6:0] 2A ID3_3[7:0] 2B ID1_4[7:0] 2C NVALID_ID4 ID2_4[6:0] 2D ID3_4[7:0] 2E ID1_5[7:0] 2F NVALID_ID5 ID2_5[6:0] 30 ID3_5[7:0] 31 NVALID8 32 - 33 FS1[2:0] - DT[1:0] - - - - - 34 - - - 35 - - - AP[2:0] BT[3:0] DCDIV[3:0] BTP[4:0] BTN[4:0] 36 VRHP[7:0] 37 VRHN[7:0] 38 39 B1 VCMC_F1[7:0] 1D 29 B2 NVALID_VCMF1 NVALID_VCMF2 NVALID_VCMF3 NVALID_VCMB1 NVALID_VCMB2 NVALID_VCMB3 1C 1E B3 SETPOWER (B1h) - - VRMP[5:0] - - VRMN[5:0] 3A - - DD_TU VPNL_EN - 3B - DC86_DIV3 DC86_DIV2 DC86_DIV1 DC86_DIV0 3C - DTPS[2:0] VBS[2:0] XDK1 - XDK0 AUTO_XDK DTNS[2:0] 3D A_DC[1:0] A_DTP[2:0] A_DTN[2:0] 3E B_DC[1:0] B_DTP[2:0] B_DTN[2:0] 3F C_DC[1:0] C_DTP[2:0] C_DTN[2:0] 40 D_DC[1:0] D_DTP[2:0] D_DTN[2:0] 41 E_DC[1:0] E_DTP[2:0] 42 NVALID9 - - NW_PE[1:0] 43 44 E_DTN[2:0] - NW[1:0] SON[7:0] SETCYC (B4h) SOFF[7:0] 45 EQS[7:0] 46 EQON[7:0] 47 SETPANEL (CCh) NVALID10 48 SETDISP (B2h) NVALID11 VPL HPL EPL SS_PANEL DPL RM DFR - - RES_SEL[2:0] 49 BGR_PANEL DM[1:0] BP [7:0] 4A FP [7:0] 4B SAP[3:0] 4C GEN_ON[7:0] 4D GEN_OFF[7:0] 4E 4F REV_PANEL - - RTN[7:0] - - - - TEI[3:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.140October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 50 - - - - - 51 TEP[7:0] 52 BP_PE [7:0] 53 FP_PE [7:0] 54 RTN_PE[7:0] - 78 NVALID_GV0 - G1_VRP0[5:0] 79 - - G1_VRP1[5:0] TEP[9:8] 7A - - G1_VRP2[5:0] 7B - - G1_VRP3[5:0] 7C - - G1_VRP4[5:0] 7D - - 7E - 7F - 80 G1_CGMP0[1:0] - G1_ PKP0[4:0] 81 G1_CGMP1[1:0] - G1_PKP1[4:0] 82 G1_CGMP2[1:0] - G1_PKP2[4:0] 83 G1_CGMP3[1:0] - G1_PKP3[4:0] G1_VRP5[5:0] G1_PRP0[6:0] G1_PRP1[6:0] 84 G1_CGMP5 G1_CGMP4 - G1_PKP4[4:0] 85 - - - G1_PKP5[4:0] 86 - - - G1_PKP6[4:0] 87 - - - G1_PKP7[4:0] - - - - - G1_VRN0[5:0] 88 89 SETGAMMA (E0h) (GC0) G1_PKP8[4:0] 8A - - G1_VRN1[5:0] 8B - - G1_VRN2[5:0] 8C - - G1_VRN3[5:0] 8D - - G1_VRN4[5:0] 8E - - 8F - 90 - 91 G1_CGMN0[1:0] - G1_PKN0[4:0] 92 G1_CGMN1[1:0] - G1_PKN1[4:0] 93 G1_CGMN2[1:0] - G1_PKN2[4:0] 94 G1_CGMN3[1:0] - G1_PKN3[4:0] G1_VRN5[5:0] G1_PRN0[6:0] G1_PRN1[6:0] 95 G1_CGMN5 G1_CGMN4 - G1_PKN4[4:0] 96 - - - G1_PKN5[4:0] 97 - - - G1_PKN6[4:0] 98 - - - G1_PKN7[4:0] 99 - - - NVALID13 - - 9A SETGIP(D5h) G1_PKN8[4:0] - 9B 9C SHR_0[11:8] SHR_0[7:0] - - - 9D - SHR_1[11:8] SHR_1[7:0] 9E SPD[7:0] 9F CHR[7:0] A0 CON[7:0] A1 COFF[7:0] A2 SHP[3:0] SCP[3:0] A3 CHP[3:0] CCP[3:0] A4 SOS_1[3:0] SOS_0[3:0] A5 SOS_3[3:0] SOS_2[3:0] A6 COS_1[3:0] COS_0[3:0] A7 COS_3[3:0] COS_2[3:0] A8 COS_5[3:0] COS_4[3:0] A9 COS_7[3:0] COS_6[3:0] AA SOS_1_ML[3:0] SOS_0_ML[3:0] AB SOS_3_ML[3:0] SOS_2_ML[3:0] AC COS_1_ML[3:0] COS_0_ML[3:0] AD COS_3_ML[3:0] COS_2_ML[3:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.141October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 AE COS_5_ML[3:0] AF COS_4_ML[3:0] COS_7_ML[3:0] B0 - COS_6_ML[3:0] - GTO[5:0] B1 GNO[7:0] B2 EQ_DELAY[7:0] B3 GIP_OPT[7:0] 100 NVALID16 101 102 ‧ ‧‧ - - - - - DITH_OPT DGC_EN D1[7:0] SETDGCLUT (C1h) D2[7:0] Dn[7:0] 17D D125[7:0] 17E D126[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.142October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19.2 OTP programming flow OTP_KEY0[7:0] OTP_KEY1[7:0] OTP_KEY0[7:0] = 0xAAh OTP_KEY1[7:0] = 0x55h OTP_KEY0[7:0] = 0x00h OTP_KEY1[7:0] = 0x00h Description Note Enter OTP program mode Leave OTP program mode 1. If HX8369-A01 operate on OTP program mode, then keep on OTP Other value Invalid program mode. 2. If HX8369-A01 operate on non-OTP program mode, then keep on non-OTP program mode. Figure 5.41: OTP programming sequence Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.143October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19.3 Programming sequence Step 1 2 3 4 5 6 7 8 9 10 11 Operation Power on and reset the module. SLPOUT and set 0xB9h = 0xFFh, 0x83h, 0x69h to access the extension commands. Set VGH power to 7.5V for OTP programming state for using internal power mode. Or using the external power 7.5V to VPP. Write optimized values to related registers. Set OTP_KEY1[7:0] (RE9h)=0xAAh and OTP_KEY1[7:0] (RE9h)=0x55h to enter OTP program mode. Specify OTP_index, please refer to the OTP table. Set OTP_Mask=0x00h, programming the entire bit of one parameter. Set OTP_PROG=1, Internal register begin write to OTP according to OTP_index. Wait 5 ms (Note 1) Set OTP_PROG=0, OTP_index programming action done. Complete programming one parameter to OTP. If continue to programming other parameter, return to step (5). Otherwise, set OTP_KEY1[7:0] (RE9h)=0x00h and OTP_KEY1[7:0] (RE9h)=0x00h to leave OTP program mode and power off the module and remove the external power on VPP pin. Note1: When do the OTP programming process, it must be added 5ms delay time after setting OTP_PROG=1. Table 5.64: OTP Programming sequence Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.144October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19.4 OTP Programming example of VCOM setting VCMC_F and VCMC_B OTP Program Flow H/W Reset + SLPOUT Set extension commands Set CMD 0xB9h 1st parameter 0xFFh 2nd parameter 0x83h 3rd parameter 0x69h Using External power 7.5V to VPP Write optimized VCOM value of Register Set CMD 0xB6h 1st parameter 0x##h(VCMC_F) 2nd parameter0x##h(VCMC_B) Set OTP_KEY0[7:0] = 0xAAh OTP_KEY1[7:0] = 0x55h Set CMD 0xE9h 1st parameter 0xAAh 2nd parameter0x55h Set OTP index 0x1Ch for VCMC_F1[7:0] Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x1Ch 4th parameter 0x00h Set OTP_PROG=1 for programming action Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x1Ch 4th parameter 0x01h Set OTP index 0x1Dh for VCMC_B1[7:0] Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x1Dh 4th parameter 0x00h Set OTP_PROG=1 for programming action Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x1Dh 4th parameter 0x01h Delay 5ms OTP programming action done Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x1Dh 4th parameter 0x00h OTP_KEY0[7:0] = 0x00h OTP_KEY1[7:0] = 0x00h Set CMD 0xE9h 1st parameter 0x00h 2nd parameter0x00h Reset IC for OTP relaod END Delay 5ms OTP programming action done Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x1Ch 4th parameter 0x00h Figure 5.42: OTP programming sequence example 1. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.145October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19.5 OTP Programming example of ID1, ID2 and ID3 OTP Program Flow H/W Reset + SLPOUT (command 0x11h) Set extension commands Set CMD 0xB9h 1st parameter 0xFFh 2nd parameter 0x83h 3rd parameter 0x69h OTP_KEY0[7:0] = 0x00h OTP_KEY1[7:0] = 0x00h Set CMD 0xE9h 1st parameter 0x00h 2nd parameter0x00h Reset IC for OTP relaod Using External power 7.5V to VPP END Set ID1, ID2 and ID3 values Set CMD 0xC3h 1st parameter 0x##h (ID1) 2nd parameter0x##h (ID2) 2nd parameter0x##h (ID3) Set OTP_KEY0[7:0] = 0xAAh OTP_KEY1[7:0] = 0x55h Set CMD 0xE9h 1st parameter 0xAAh 2nd parameter0x55h Set OTP index 0x22h for ID1[7:0], ID2[6:0] and ID3[7:0] Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x22h 4th parameter 0x00h Set OTP_PROG=1 for programming action Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x22h 4th parameter 0x01h Delay 5ms OTP index 0x22h, 0x23h and 0x24h OTP programming action done Set CMD 0xBBh 1st parameter 0x00h 2nd parameter 0x00h 3rd parameter 0x22h 4th parameter 0x00h Figure 5.43: OTP programming sequence example 2. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.146October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19.6 OTP read example of 0x1Bh (VCOM setting re-load) OTP_index 0x1Bh D7 NVALID_VCMF1 D6 NVALID_VCMF2 D5 NVALID_VCMF3 D4 NVALID_VCMB1 D3 NVALID_VCMB2 D2 NVALID_VCMB3 0x1Bh value Reload OTP index value 1 1 1 1 1 1 0xFFh Default 1st VCOM OTP 0 1 1 0 1 1 0x6Fh 0x1Ch and 0x1Dh 2nd VCOM OTP 0 0 1 0 0 1 0x27h 0x1Eh and 0x1Fh 3rd VCOM OTP 0 0 0 0 0 0 0x03h 0x20h and 0x21h Figure 5.44: OTP programming sequence index 0x1Bh read flow. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.147October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.19.7 OTP read example of VCMC_F1 Figure 5.45: OTP programming sequence read flow. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.148October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 5.20 Temperature sensor control The HX8369-A00 has the calibration scheme that including Gain and Offset Control to compensate the Temperature Sensor. The temperature sensor control block diagram as below. Figure 5.46: Temperature sensor Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.149October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6. Command 6.1 Command list 6.1.1 Standard command (Hex) Operation code 00 NOP 0 1 01 SWRESET 0 05 RDNUMPE 06 RDRED 07 RDGREEN 08 RDBLUE 0A RDDPM 0B RDDMADCTL 0C RDDCOLMOD 0D RDDIM 0E RDDSM 0F RDDSDR D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function ↑ 0 0 0 0 0 0 0 0 1 ↑ 0 0 0 0 0 0 0 1 0 1 ↑ 0 0 0 0 0 1 0 1 1 1 ↑ ↑ 1 1 x x x x x P[7:0] x x x 0 1 ↑ 0 0 0 0 0 1 1 0 1 1 ↑ ↑ 1 1 x R7 x R6 x R5 x R4 x R3 x R2 x R1 x R0 0 1 ↑ 0 0 0 0 0 1 1 1 1 1 ↑ ↑ 1 1 x G7 x G6 x G5 x G4 x G3 x G2 x G1 x G0 0 1 ↑ 0 0 0 0 1 0 0 0 1 1 ↑ ↑ 1 1 x B7 x B6 x B5 x B4 x B3 x B2 x B1 x B0 0 1 ↑ 0 0 0 0 1 0 1 0 1 1 ↑ ↑ 1 1 x D7 x D6 x D5 x D4 x D3 x D2 x 0 x 0 0 1 ↑ 0 0 0 0 1 0 1 1 1 1 ↑ ↑ 1 1 x D7 x D6 x D5 x D4 x D3 x D2 x 0 x 0 0 1 ↑ 0 0 0 0 1 1 0 0 1 1 ↑ ↑ 1 1 x - x D6 x D5 x D4 x - x D2 x D1 x D0 0 1 ↑ 0 0 0 0 1 1 0 1 1 1 ↑ ↑ 1 1 x D7 x D6 x D5 x 0 x 0 x D2 x D1 x D0 0 1 ↑ 0 0 0 0 1 1 1 0 1 1 ↑ ↑ 1 1 x D7 x D6 x 0 x 0 x 0 x 0 x 0 x 0 0 1 ↑ 0 0 0 0 1 1 1 1 1 1 ↑ ↑ 1 1 x D7 x D6 x D5 x D4 x 0 x 0 x 0 x 0 No Operation Software Reset Read Number of DSI Parity Error Dummy read Read Red Colour Dummy read xx Read Green Colour Dummy read xx Read Blue Colour Dummy read xx Read display power mode Dummy read Read display MADCTL Dummy read Read display pixel format Dummy read Read display image mode Dummy read Read display signal mode Dummy read Read display self-diagnostic result Dummy read - Default RGB (Hex) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. - Yes - Yes - - - - - Yes - - - Yes - - - Yes - - - Yes - - - Yes - - - Yes - - - Yes - - - Yes - - - Yes - - -P.150October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 10 11 12 Operation Code SLPIN SLPOUT PTLON 13 (Hex) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 ↑ ↑ ↑ 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 NORON 0 1 ↑ 0 0 0 1 0 0 1 1 20 INVOFF 0 1 ↑ 0 0 1 0 0 0 0 0 21 INVON 0 1 ↑ 0 0 1 0 0 0 0 1 0 1 0 0 1 1 1 1 ↑ ↑ ↑ ↑ 0 1 ↑ 1 1 ↑ SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 1 1 ↑ SC7 SC6 1 1 ↑ EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 1 1 ↑ EC7 EC6 0 1 ↑ 1 1 ↑ SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 1 1 ↑ SP7 SP6 1 1 ↑ EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 1 1 ↑ EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 ↑ ↑ ↑ ↑ ↑ 0 D17 Dx7 Dn7 0 R007 Rnn7 R637 G007 Gnn7 G637 B007 Bnn7 B637 0 X D17 Dx7 Dn7 0 SR15 SR7 ER15 ER7 1 D15 Dx5 Dn5 1 R005 Rnn5 R635 G005 Gnn5 G635 B005 Bnn5 B635 1 X D15 Dx5 Dn5 1 SR13 SR5 ER13 ER5 0 D14 Dx4 Dn4 0 R004 Rnn4 R634 G004 Gnn4 G634 B004 Bnn4 B634 0 X D14 Dx4 Dn4 1 SR12 SR4 ER12 ER4 26 GAMSET 28 29 DISPOFF DISPON 2A 2B 2C CASET PASET RAMWR 2D RGBSET 2E RAMRD 30 PLTAR 0 0 GC7 GC6 0 0 0 0 0 0 0 0 0 D16 Dx6 Dn6 0 R006 Rnn6 R636 G006 Gnn6 G636 B006 Bnn6 B636 0 X D16 Dx6 Dn6 0 SR14 SR6 ER14 ER6 1 GC5 1 1 1 SC5 EC5 1 SP5 0 0 1 1 0 GC4 GC3 GC2 GC1 GC0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 SC4 SC3 SC2 SC1 SC0 EC4 EC3 EC2 EC1 EC0 0 1 0 1 1 SP4 SP3 SP2 SP1 SP0 1 D13 Dx3 Dn3 1 R003 Rnn3 R633 G003 Gnn3 G633 B003 Bnn3 B633 1 X D13 Dx3 Dn3 0 SR11 SR3 ER11 ER3 1 D12 Dx2 Dn2 1 R002 Rnn2 R632 G002 Gnn2 G632 B002 Bnn2 B632 1 X D12 Dx2 Dn2 0 SR10 SR2 ER10 ER2 0 D11 Dx1 Dn1 0 R001 Rnn1 R631 G001 Gnn1 G631 B001 Bnn1 B631 1 X D11 Dx1 Dn1 0 SR9 SR1 ER9 ER1 0 D10 Dx0 Dn0 1 R000 Rnn0 R630 G000 Gnn0 G630 B000 Bnn0 B630 0 X D10 Dx0 Dn0 0 SR8 SR0 ER8 ER0 Default (Hex) Sleep In Sleep Out Partial Mode On Normal display mode on Display inversion off Display inversion on Gamma set Display off Display on Column Address Set Column address start Column address start Column address end Column address end Row address set Row address start Row address start Row address end Row address end Memory Write Write data Write data Write data Color Set Red tone Red tone Red tone Green tone Green tone Green tone Blue tone Blue tone Blue tone Memory read Dummy read Read data Read data Partial Area Start row Start row End row End row Function Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. RGB Yes Yes No No No No Yes Yes Yes No No No Yes No No - -P.151October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 (Hex) Operation Code 33 VSCRDEF 34 TEOFF 35 TEON 36 MADCTL 37 VSCRSADD 38 39 IDMOFF IDMON 3A COLMOD 3C RAMWRCON 3E RAMRDCON 44 TESL 45 GETSCAN 51 WRDISBV 52 RDDISBV 53 WRCTRLD 54 RDCTRLD 55 WRCABC 56 D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 1 0 1 ↑ 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ 0 1 ↑ 0 0 1 1 0 1 0 0 0 1 ↑ 0 0 1 1 0 1 0 1 1 1 ↑ X X X X X X X M 0 1 ↑ 0 0 1 1 0 1 1 0 1 1 ↑ B7 B6 B5 B4 B3 B2 X X 0 1 ↑ 0 0 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 ↑ ↑ ↑ 0 0 0 X 0 D17 Dx7 Dn7 0 X D17 Dx7 Dn7 0 0 0 0 D6 0 D16 Dx6 Dn6 0 X D16 Dx6 Dn6 1 0 1 ↑ 0 1 1 1 1 1 ↑ ↑ 0 1 ↑ 1 1 ↑ 0 1 ↑ 0 1 0 1 1 0 1 ↑ ↑ 1 1 1 1 ↑ ↑ xx xx xx 0 xx xx xx DBV[7:0] 1 0 1 0 xx BCTRL xx DD 0 1 ↑ 0 1 1 1 ↑ ↑ 1 1 xx 0 xx xx xx 0 BCTRL 0 0 1 ↑ 0 1 0 1 1 ↑ xx xx 0 1 ↑ 0 1 1 ↑ ↑ 1 1 XX 0 TFA[15:8] TFA[7:0] VSA[15:8] VSA[7:0] BFA[15:8] BFA[7:0] VSP[15:8] VSP[7:0] 1 1 1 0 1 1 1 0 1 1 1 0 D5 D4 X D2 1 1 1 1 D15 D14 D13 D12 Dx5 Dx4 Dx3 Dx2 Dn5 Dn4 Dn3 Dn2 1 1 1 1 X X X X D15 D14 D13 D12 Dx5 Dx4 Dx3 Dx2 Dn5 Dn4 Dn3 Dn2 0 0 0 1 TELINE[15:8](8’b0) TELINE[7:0](8’b0) 0 0 0 1 0 0 1 D1 0 D11 Dx1 Dn1 1 X D11 Dx1 Dn1 0 0 1 0 D0 0 D10 Dx0 Dn0 0 X D10 Dx0 Dn0 0 0 1 SLN[15:8] SLN[7:0] 0 1 0 1 0 0 0 1 DBV[7:0] 0 1 0 xx xx xx 0 BL 1 xx 1 xx 0 0 1 1 xx DD xx BL xx 0 xx 0 1 0 1 0 1 xx xx xx xx CABC[1:0] 1 0 1 0 1 1 0 XX 0 XX 0 XX 0 XX 0 XX 0 XX C1 XX C0 0 1 1 0 RDCABC Function Default RGB (Hex) Vertical scrolling definition Tearing Effect Line OFF Tearing Effect Line ON Memory Access Control Vertical scrolling start address Idle mode off Idle mode on Memory write Memory read Dummy read TESL Reture the current scanline SLN[15:0] Write Display Brightness Read Display Brightness Value Dummy read Write CTRL Display Read Control Value Display Dummy read Write Adaptive Brightness Control Read Adaptive Brightness Control Content Dummy read - Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. - No - - - No - No - - - Yes - - - No - No No Yes No No Yes - - No - - - Yes - - - Yes - Yes - - Yes - - - Yes - - - Yes - - -P.152October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 (Hex) Operation Code 5E WRCABCMB 5F 68 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1 1 0 0 1 ↑ 1 1 ↑ 0 1 ↑ 0 1 0 1 1 ↑ ↑ 1 1 - XX XX 0 1 ↑ 0 1 1 1 1 0 1 1 0 1 1 0 1 1 ↑ ↑ ↑ 1 1 ↑ 1 1 ↑ 1 1 1 1 1 ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ 0 1 ↑ 1 0 1 0 0 0 0 1 1 1 1 1 ↑ ↑ ↑ ↑ 1 1 1 1 XX x x x XX x x x XX x x x XX x x x XX x x x XX x x x XX x x x XX x x x 0 1 ↑ 1 0 1 0 1 0 0 0 1 1 1 1 ↑ ↑ ↑ ↑ 1 1 1 1 XX x x x XX x x x XX x x x XX x x x XX x x x XX x x x XX x x x XX x x x 0 CMB[7:0] 1 1 1 1 1 XX XX XX 0 0 0 RDCABCMB XX XX CMB[7:0] 0 1 RDABCSDR DA RDID1 DB RDID2 DC RDID3 A1 D/CX RDX WRX D7 Read_DDB_start A8 Read_DDB_continue XX XX XX XX XX XX XX XX D[7:6] 0 0 0 0 0 0 1 1 0 1 1 0 1 0 XX XX XX XX XX XX XX XX module’s manufacturer[7:0] 1 1 0 1 1 0 1 1 XX XX XX XX XX XX XX XX 1 LCD module/driver version [6:0] 1 1 0 1 1 1 0 0 XX XX XX XX XX XX XX XX LCD module/driver ID[7:0] Function Default RGB (Hex) Write CABC minimum brightness Read CABC minimum brightness Dummy read Read Automatic Brightness Control Self-Diagnostic Result Read ID1 Dummy read Read ID2 Dummy read Read ID3 Dummy read Read the DDB from the provided location. Dummy read Continue reading the DDB from the last read location. Dummy read - - Yes - - - Yes - - - Yes - Yes Yes Yes - - Yes - - - Yes - - Note: (1) Undefined commands are treated as NOP (00h) command. (2) B0h to D8h and E0h to FFh are for factory use of display supplier. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.153October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.1.2 User define command list table User define command list is available only set “SETEXC” command. (Hex) Operation DCX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function Code B0 B1 B2 - B3 B4 (Hex) 0 1 ↑ 1 0 1 1 0 0 1 1 1 1 ↑ ↑ - - - - - - - - - - 0 1 ↑ 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ VBIAS_EN VSN_EN VSP_EN VGL_EN VGH_EN LVGL_EN VDDDN_HZ - - - - - - - 0 0 - OSC_EN SETOSC SETPOWER SETDISP - SETRGBIF SETCYC Default - UADJ[3:0] DT[1:0] (00h) - (0Bh) - STB Set power related setting - (01h) DSTB - (00h) 1 - - (34h) - - BT[3:0] - (07h) - - DCDIV[3:0] - (00h) - (0Eh) - (0Eh) FS1[2:0] - Set Internal oscillator - - - - - - - - AP[2:0] BTP[4:0] BTN[4:0] VRHP[7:0] - (21h) VRHN[7:0] - (29h) (19h) - - VRMP[5:0] - - - VRMN[5:0] - (19h) - - - (07h) - DD_TU VPNL_EN - VBS[2:0] DC86_DIV3 DC86_DIV2 DC86_DIV1 DC86_DIV0 - DTPS[2:0] - (22h) DTNS[2:0] - (01h) (E6h) XDK1 XDK0 - AUTO_XDK A_DC[1:0] A_DTP[2:0] A_DTN[2:0] - B_DC[1:0] B_DTP[2:0] B_DTN[2:0] - (E6h) C_DC[1:0] C_DTP[2:0] C_DTN[2:0] - (E6h) D_DC[1:0] D_DTP[2:0] D_DTN[2:0] - (E6h) E_DC[1:0] E_DTP[2:0] E_DTN[2:0] - (E6h) 0 1 ↑ 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - - - - - - 1 1 - - - - D[1:0] Set display related register - RM DFR DM[1:0](1) - (10h) BP [7:0] - (03h) FP [7:0] - (03h) - (70h) 0 RES_SEL[2:0] SAP[3:0] 0 - 1 - 0 - - GEN_ON[7:0] - (00h) - (FFh) RTN[7:0] - - - - - - - - (00h) GEN_OFF[7:0] - - - TEI[3:0] - (00h) - (00h) - (00h) TEP[7:0] - (00h) BP_PE [7:0] - (03h) FP_PE [7:0] - (03h) RTN_PE[7:0] - (03h) - - Note: (1) When BS[3:0]=1101, 1110, 1111 DM[1:0] default =11 Other condition, DM[1:0] default =00 TEP[9:8] - GON 0 1 ↑ 1 0 1 1 0 0 1 1 1 1 ↑ - - - - DPL HSPL VSPL EPL 0 1 ↑ 1 0 1 0 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ - - - - - (01h) - - Set RGB interface related register) (01h) Set Display waveform cycles - (00h) SON[7:0] - (0Fh) SOFF[7:0] - (82h) EQS[7:0] - (0Ch) EQON[7:0] - (03h) 0 1 NW_PE[1:0] 0 0 NW[1:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. - -P.154October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 B6 B9 BB C1 C3 C9 CC D5 SETVCOM (OTPx3) SETEXTC SETOTP SETDGCLUT SETID (OTPx5) SETCABC 0 1 ↑ 1 1 1 1 ↑ ↑ 0 1 ↑ 1 1 1 0 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 ↑ 1 0 1 1 0 1 1 Set VCOM Voltage - 0 VCMC_F[7:0] (5Eh) VCMC_B[7:0] 1 0 1 1 1 0 0 Set extended command set (00h/FFh) - 1 EXTC1[7:0] 1 0 1 EXTC2[7:0] - (00h/83h) EXTC3[7:0] - (00h/69h) 1 1 0 1 1 OTP_MASK[7:0] - - - - - - - OTP_INDEX[8] OTP_INDEX[7:0] OTP_LOAD_ OTP_TEST DISABLE OTP_POR OTP_PWE 1 1 ↑ 0 1 ↑ 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - - - - 0 1 ↑ OTP_PTM[1:0] VPP_SEL OTP_PROG OTP_DATA[7:0] 1 1 0 0 0 0 1 - - DITH_OPT DGC_EN 1 1 ↑ - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ CABC_DD - (01h) (FFh) - (00h) OTP read / write Set DGC LUT - - - - 0 0 1 - 0 1 1 0 0 1 - - (00h) - (00h) Set CABC Control (00h) (3Eh) EN_TEMP (00h) (00h) (01h) SEL_GAIN[1:0] (2Fh) INVPULS SEL_BLDUTY (2Bh) PWM_PERIOD[7:0] (1Eh) DIM_FRAME[6:0] (1Eh) CABC_STEP[7:0] (00h) CABC_CLKEN[7:0] Set panel related register 0 1 ↑ 1 1 0 0 1 1 0 0 1 1 ↑ - - - - SS_PANEL - REV_PANE BGR_PANE L 0 1 ↑ 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - - - - 0 1 0 SHR_0[11:8] SHR_0[7:0] - - - - - Set ID CABC_FLM[3:0] SEL_PWMCLK[2:0] - - - EN_DIM_MI EN_COST_ EN_NLN_G EN_COST EN_JUDGE X MEAN AIN SAVEPOWER[6:0] - - - MEAN_OFFSET[7:0] - (xxh) D126[7:0] SETPANEL SETGIP - - ID2[6:0] 0 (00h) Dn[7:0] ID3[7:0] 1 - - - ID1[7:0] 1 Set OTP D1[7:0] 0 0 (5Eh) 1 SET GIP control - SHR_1[11:8] SHR_1[7:0] (02h) (00h) (02h) - (00h) - (01h) SPD[7:0] - (02h) CHR[7:0] - (03h) CON[7:0] - (20h) COFF[7:0] - (6Ch) (03h) SHP[3:0] SCP[3:0] - CHP[3:0] CCP[3:0] - (03h) SOS_1[3:0] SOS_0[3:0] - (00h) SOS_3[3:0] SOS_2[3:0] - (00h) COS_1[3:0] COS_0[3:0] - (60h) COS_3[3:0] COS_2[3:0] - (04h) COS_5[3:0] COS_4[3:0] - (71h) COS_7[3:0] COS_6[3:0] - (75h) SOS_1_ML[3:0] SOS_0_ML[3:0] - (00h) SOS_3_ML[3:0] SOS_2_ML[3:0] - (00h) COS_1_ML[3:0] COS_0_ML[3:0] - (51h) COS_3_ML[3:0] COS_2_ML[3:0] - (57h) COS_5_ML[3:0] COS_4_ML[3:0] - (40h) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.155October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 D8 E0 E9 SETTPSNR SETGAMMA (OTPx1) SETOTPKEY F4 GETHXID FD SETCNCD/ GETCNCD 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ 0 1 ↑ 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - - - TSRAW[4:0] - - - TS_OS2[4:0] COS_7_ML[3:0] - COS_6_ML[3:0] (01h) - (0Ch) EQ_DELAY[7:0] - (0Ch) GIP_OPT[7:0] Set the Temp Senor control (read only) (00h) 1 1 0 BT_P4[3:0] - - TS_G[2:0] - TS_OS1[4:3] TS_OS1[2:0] PORE - RER[1:0] TF_ON (46h) GNO[7:0] GTO[5:0] TSON 0 1 - (12h) BT_P1[3:0] - (74h) BT_P3[3:0] D0[4:0] - (A7h) - (0Ch) I0[4:0] - (6Ah) BT_P2[3:0] - - - D1[4:0] - (57h) I1[4:0] - (55h) D2[4:0] - (17h) I2[4:0] - (55h) 0 1 ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 - - G1_VRP0[5:0] Set Gamma Curve Related Setting - - - G1_VRP1[5:0] - (18h) - - G1_VRP2[5:0] - (1Fh) - - G1_VRP3[5:0] - (3Fh) - - G1_VRP4[5:0] - (3Fh) - - G1_VRP5[5:0] - (3Fh) (33h) 0 1 ↑ 1 0 0 0 0 0 - (00h) - G1_PRP0[6:0] - - G1_PRP1[6:0] - (57h) G1_CGMP0[1:0] - G1_ PKP0[4:0] - (07h) G1_CGMP1[1:0] - G1_PKP1[4:0] - (0Dh) G1_CGMP2[1:0] - G1_PKP2[4:0] - (0Fh) G1_CGMP3[1:0] - G1_PKP3[4:0] - (13h) G1_CGMP5 G1_CGMP4 - G1_PKP4[4:0] - (16h) - - - G1_PKP5[4:0] - (14h) - - - G1_PKP6[4:0] - (16h) - - - G1_PKP7[4:0] - (18h) - - - G1_PKP8[4:0] - (1Fh) - - G1_VRN0[5:0] - (00h) - - G1_VRN1[5:0] - (18h) - - G1_VRN2[5:0] - (1Fh) - - G1_VRN3[5:0] - (3Fh) - - G1_VRN4[5:0] - (3Fh) - - G1_VRN5[5:0] - (3Fh) (33h) - G1_PRN0[6:0] - - G1_PRN1[6:0] - (57h) G1_CGMN0[1:0] - G1_PKN0[4:0] - (07h) G1_CGMN1[1:0] - G1_PKN1[4:0] - (0Dh) G1_CGMN2[1:0] - G1_PKN2[4:0] - (0Fh) G1_CGMN3[1:0] - G1_PKN3[4:0] - (13h) G1_CGMN5 G1_CGMN4 - G1_PKN4[4:0] - (16h) - - - G1_PKN5[4:0] - (14h) - - - G1_PKN6[4:0] - (16h) - - - G1_PKN7[4:0] - (18h) - - - G1_PKN8[4:0] - (1Fh) 1 1 1 0 1 0 0 1 OTP_KEY0[7:0] OTP_KEY1[7:0] 1 1 1 1 0 1 0 0 Himax ID[7:0] 1 1 1 1 1 1 0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. 1 - - - (00h/AAh) - (00h/55h) - - - (69h) Set/Get Continue Command - -P.156October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 FE FF SET READ INDEX GETSPIREAD 1 1 ↑ 0 1 ↑ 1 1 ↑ 0 1 ↑ 1 1 1 ↑ ↑ ↑ 1 1 1 WR_CMD_CN[7:0] 1 1 1 CMD_DATA1[7:0] SET READ Command Address Read Command Data - : - - CMD_DATAN[7:0] - - 1 1 1 1 0 CMD_ADD[7:0] 1 1 1 1 1 1 1 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. 1 (00h) - -P.157October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2 Command description 6.2.1 NOP (00h) 00H Command Parameter Description Restriction Register Availability Default Flow Chart NOP (No Operation) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 0 0 0 0 00 NO PARAMETER This command is an empty command; it does not have any effect on the display module. However it can be used to terminate Frame Memory Write or Read as described in RAMWR (Memory Write) and RAMRD (Memory Read) Commands. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes N/A - Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.158October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.2 Software reset (01h) 01H Command Parameter Description Restriction Register Availability Default SWRESET (Software Reset) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 0 0 0 0 0 0 0 1 01 NO PARAMETER When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values. (See default tables in each command description.) Note: The Frame Memory contents are unaffected by this command It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display supplier’s factory default values to the registers during this 5msec. If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep out command. Software Reset Command cannot be sent during Sleep Out sequence. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes N/A Legend SWRESET Red and Blue Display whole blank screen Parameter Display Flow Chart Set Commands to S/W Default Value Action Mode Sleep In Mode Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.159October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.3 05H Command st 1 parameter nd 2 parameter Description RDNUMPE: Read number of the parity errors (05h) D/CX 0 1 1 RDX 1 ↑ ↑ WRX ↑ 1 1 RDNUMPE (Read Number of the Parity Errors) D7 D6 D5 D4 D3 D2 D1 D15-D8 0 0 0 0 0 1 0 x x x x x x x P7 P6 P5 P4 P3 P2 P1 - D0 HEX 1 05 x Dummy read P0 xx The first parameter is telling a number of the errors on DSI. The more detailed description of the bits is below. P[6..0] bits are telling a number of the errors. P[7] is set to ‘1’ if there is overflow with P[6..0] bits. P[7..0] bits are set to ‘0’s (as well as RDDSM(0Eh)’s D0 is set ‘0’ at the same time) after there is sent the second parameter information (The read function is completed). Restriction SETEXTC turn on to enable this command Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Default Availability Yes Yes Yes Yes P[7:0] = 0x00h Legend DSI I/F Mode Command RDNUMPE (R05h) Host Parameter Driver Send 1st parameter Display Flow Chart Action RDDSM (R0Eh) 's D0 = '0' P[7:0] = "00"h Mode Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.160October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.4 Get_red_channel (06h) 06H Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default RDRED (Read Red Colour) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 0 1 ↑ 0 0 0 0 0 1 1 1 ↑ 1 x x x x x x x 1 ↑ 1 R7 R6 R5 R4 R3 R2 R1 The first parameter is telling red colour value of the first pixel of the frame when there is used DPI I/F. 16 bit format: R5 is MSB and R1 is LSB. R7, R6 and R0 are set to ‘0’. 18 bit format: R5 is MSB and R0 is LSB. R7 and R6 are set to ‘0’. Status Availability Sleep Out Yes D0 0 x R0 HEX 06 Dummy read xx R[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.161October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.5 Get_green_channel (07h) 07H Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default RDGREEN (Read Green Colour) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 0 1 ↑ 0 0 0 0 0 1 1 1 ↑ 1 x x x x x x x 1 ↑ 1 G7 G6 G5 G4 G3 G2 G1 The first parameter is telling green colour value of the first pixel of the frame when there is used DPI I/F. 16 and 18 bit formats: G5 is MSB and G0 is LSB. G7 and G6 are set to ‘0’. Status Availability Sleep Out Yes D0 1 x G0 HEX 07 Dummy read xx G[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.162October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.6 Get_blue_channel (08h) 08H Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default RDBLUE (Read Blue Colour) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 1 0 0 0 08 1 ↑ 1 x x x x x x x x Dummy read 1 ↑ 1 B7 B6 B5 B4 B3 B2 B1 B0 xx The first parameter is telling blue colour value of the first pixel of the frame when there is used DPI I/F. 16 bit format: B5 is MSB and B1 is LSB. B7, B6 and B0 are set to ‘0’. 18 bit format: B5 is MSB and B0 is LSB. B7 and B6 are set to ‘0’. Status Availability Sleep Out Yes Sleep In Yes B[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.163October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.7 Get_power_mode (0Ah) RDDPM (Read Display Power Mode) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 1 0 1 0 0A 1 ↑ 1 x x x x x x x x Dummy read 1 ↑ 1 D7 D6 D5 D4 D3 D2 0 0 xx This command indicates the current status of the display as described in the table below: Bit Description Comment D7 Not Defined Set to ‘0’ D6 Idle Mode On/Off D5 Partial Mode On/Off D4 Sleep In/Out D3 Display Normal Mode On/Off D2 Display On/Off D1 Not Defined Set to ‘0’ D0 Not Defined Set to ‘0’ 0AH Command st 1 parameter nd 2 parameter Description Restrictions Bits D7 for future use and are set to ‘0’. Bit D6 – Idle Mode On/Off ‘0’ = Idle Mode Off. ‘1’ = Idle Mode On. Bit D5 – Partial Mode On/Off ‘0’ = Partial Mode Off. ‘1’ = Partial Mode On. Bit D4 – Sleep In/Out ‘0’ = Sleep In Mode. ‘1’ = Sleep Out Mode. Bit D3 – Display Normal Mode On/Off ‘0’ = Display Normal Mode Off. ‘1’ = Display Normal Mode On. Bit D2 – Display On/Off ‘0’ = Display is Off. ‘1’ = Display is On. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Register Availability Default Availability Yes Yes Yes Yes D[7:0] = 0x08h Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.164October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.8 Read display MADCTL (0Bh) 0BH Command st 1 parameter nd 2 parameter Description Restrictions Register Availability Default RDDMADCTL (Read Display MADCTL) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 ↑ 0 0 0 0 1 0 1 1 1 ↑ 1 x x x x x x x x 1 ↑ 1 D7 D6 D5 D4 D3 D2 0 0 This command indicates the current status of the display as described in the table below: Bit Description Comment D7 Page Address Order D6 Column Address Order D5 Page/Column Order D4 Line Address Order D3 RGB/BGR Order D2 Display Data Latch Order D1 Reserved Set to ‘0’ D0 Reserved Set to ‘0’ HEX 0B Dummy read xx Bit D7 – Page Address Order ‘0’ = Top to Bottom (When MADCTL B7=’0’). ‘1’ = Bottom to Top (When MADCTL B7=’1’). Bit D6 – Column Address Order ‘0’ = Left to Right (When MADCTL B6=’0’). ‘1’ = Right to Left (When MADCTL B6=’1’). Bit D5 – Page/Column Order ‘0’ = Normal (When MADCTL B5=’0’). ‘1’ = Roration (When MADCTL B5=’1’). Note: For Bits D7 to D5, also refer to Section 5.3 MCU to memory write/read direction. Bit D4 – Line Address Order ‘0’ = LCD Refresh Top to Bottom (When MADCTL B4=’0’). ‘1’ = LCD Refresh Bottom to Top (When MADCTL B4=’1’). Bit D3 – RGB/BGR Order ‘0’ = RGB (When MADCTL B3=’0’). ‘1’ = BGR (When MADCTL B3=’1’). Note: For Bits D4 and D3 also refer to Section 6.2.31 Set_address_mode (36h). Bit D2 – Display Data Latch Data Order ‘0’ = LCD Refresh Left to Right (When MADCTL B2=’0’). ‘1’ = LCD Refresh Right to Left (When MADCTL B2=’1’). Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off D[7:0] = 0x00h Availability Yes Yes Yes Yes Yes Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.165October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.166October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.9 Get_pixel_format (0Ch) 0CH Command st 1 parameter nd 2 parameter Description RDDCOLMOD (Read Display COLMOD) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 1 1 0 0 0C 1 ↑ 1 x x x x x x x x Dummy read 1 ↑ 1 D6 D5 D4 D2 D1 D0 xx This command indicates the current status of the display as described in the table below: Bit Description Comment D7 Reserved Set to ‘0’ D6 DPI Interface Pixel format D5 D4 D3 Reserved Set to ‘0’ D2 DBI Interface Pixel format D1 D0 Bits D6, D5, D4 – DPI Interface Colour Pixel Format Definition Bits D2, D1, D0 – DBI Interface Colour Pixel Format Definition. For Setting pixel format, see section 6.2.35 Set_pixel_format (3Ah)”. D6 D5 D4 D2 D1 D0 Not Defined 0 0 0 Not Defined 0 0 1 Not Defined 0 1 0 Not Defined 0 1 1 Not Defined 1 0 0 16 bit/pixel 1 0 1 18 bit/pixel 1 1 0 24 bit/pixel 1 1 1 If a particular interface, either DBI or DPI, is not used then the corresponding bits in the parameter returned from the display module are undefined. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes D[7:0] = 0x07h Interface Colour Format Restrictions Register Availability Default Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.167October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.168October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.10 Get_display_mode (0Dh) 0DH Command st 1 parameter nd 2 parameter Description Restrictions Register Availability Default RDDIM (Read Display Image Mode) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 1 1 0 1 0D 1 ↑ 1 x x x x x x x x Dummy read 1 ↑ 1 D7 D6 D5 0 0 D2 D1 D0 xx This command indicates the current status of the display as described in the table below: Bit D7 – Vertical Scrolling On/Off ‘0’ = Vertical Scrolling is Off. ‘1’ = Vertical Scrolling is On. Bit D6 – Horizontal Scrolling Status This bit is not applicable for this project, so it is set to ‘0’ Bit D5 – Inversion On/Off ‘0’ = Inversion is Off. ‘1’ = Inversion is On. Bit D4, D4 – Reserved Bits D2, D1, D0 – Gamma Curve Selection Gamma Curve Gamma Set (26h) D2 D1 D0 Selected Parameter Gamma Curve 1 0 0 0 GC0 Gamma Curve 2 0 0 1 GC1 Gamma Curve 3 0 1 0 GC2 Gamma Curve 4 0 1 1 GC3 Not Defined 1 0 0 Not Defined Not Defined 1 0 1 Not Defined Not Defined 1 1 0 Not Defined Not Defined 1 1 1 Not Defined Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes D[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.169October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.11 Get_signal_mode (0Eh) 0EH Command st 1 parameter nd 2 parameter Description Restrictions Register Availability Default RDDSM (Read Display Signal Mode) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 1 1 1 0 0E 1 ↑ 1 x x x x x x x x Dummy read 1 ↑ 1 D7 D6 0 0 0 0 0 0 xx This command indicates the current status of the display as described in the table below: Bit D7 – Tearing Effect Line On/Off ‘0’ = Tearing Effect Line Off. ‘1’ = Tearing Effect On. Bit D6 – Tearing Effect Line Output Mode, see section 5.5.3 for mode definitions. ‘0’ = Mode 1. ‘1’ = Mode 2. D5 are D0 – are for future use and are set to ‘0’. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes D[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.170October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.12 Get_diagnostic_result (0Fh) 0FH Command st 1 parameter nd 2 parameter Description Restrictions Register Availability Default RDDSDR (Read Display Self-Diagnostic Result) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 0 1 1 1 1 0F 1 ↑ 1 x x x x x x x x Dummy read 1 1 1 D7 D6 D5 D4 0 0 0 0 xx The display module returns the self-diagnostic results following a Sleep Out command. See section 5.15 for a description of the status results. Bit D7 – Register Loading Detection Bit D6 – Functionality Detection Bit D5 – Chip Attachment Detection Set to ‘0’ if feature unimplemented. Bit D4 – Display Glass Break Detection Set to ‘0’ if feature unimplemented. Bits D[3:0] – Reserved Set to ‘0’. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes D[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.171October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.13 Enter_sleep_mode (10h) 10H Command Parameter SLPIN (Sleep In) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 1 0 0 0 0 10 NO PARAMETER This command causes the LCD module to enter the minimum power consumption mode. In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and panel scanning is stopped. Description MCU interface and memory are still working and the memory keeps its contents. Restriction Register Availability Default This command has no effect when module is already in sleep in mode. Sleep In Mode can only be left by the Sleep Out Command (11h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A It takes 120msec to get into Sleep In mode after SLPIN command issued. Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.172October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.14 Exit_sleep_omde (11h) 11H Command Parameter SLPOUT (Sleep Out) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 1 0 0 0 1 11 NO PARAMETER This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal oscillator is started, and panel scanning is started. Out[1:960] Blank STOP Memory contents VST etc.(V scanner control logic) Description DC charge in the capacitor DC:DC converter 0V DC:DC converter 0V DC:DC converter 0V Reset pulse for circuit inside panel Internal Oscillator Restriction Register Availability Default 0V CHARGE RESET STOP START This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be left by the Sleep In Command (10h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. The display module loads all display supplier’s factory default values to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the display module is already Sleep Out –mode. The display module is doing self-diagnostic functions during this 5msec. It will be necessary to alit 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes N/A It takes 120msec to become Sleep Out mode after SLPOUT command issued. Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.173October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.15 Enter_partial_mode (12h) 12H Command Parameter Description Restrictions Register Availability Default Flow Chart PTLON (Partial Mode On) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 1 0 0 1 0 12 NO PARAMETER This command turns on partial mode The partial mode window is described by the “Set_partial_area” command (30H). To leave Partial mode, the “Enter_norma_mode” command (13H) should be written. This command has no effect when Partial mode is active. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A See Partial Area (30h) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.174October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.16 Enter_normal_mode (13h) 13H Command Parameter Description Restriction Register Availability Default Flow Chart NORON (Normal Display Mode On) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 0 1 0 0 1 1 13 NO PARAMETER This command returns the display to normal mode. Normal display mode is means Partial mode off, Scroll mode Off. This command has no effect when Normal Display mode is active. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.175October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.17 Exit_inversion_mode (20h) 20H Command Parameter Description Restriction Register Availability Default INVOFF (Display Inversion Off) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 0 1 ↑ 0 0 1 0 0 0 No parameter This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status. (Example) Memory D1 0 D0 0 HEX 20 (Example) Display This command has no effect when module is already in inversion off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.176October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.18 Enter_inversion_mode (21h) 21H Command Parameter INVON (Display Inversion On) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 0 0 0 0 1 21 NO PARAMETER This command is used to enter into display inversion mode. This command makes no change of contents of frame memory. Every bit is inverted from the frame memory to the display. This command does not change any other status. (Example) Description Restriction Register Availability Default memory display This command has no effect when module is already in inversion on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.177October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.19 Set_gamma_curve (26h) 26H Command Parameter Description GAMSET (Gamma Set) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 0 0 1 1 0 26 1 1 ↑ GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 1..08 This command is used to select the desired Gamma curve for the current display. A maximum of 4 fixed gamma curves can be selected. The curves are defined in Curve Correction Power Supply Circuit. The curve is selected by setting the appropriate bit in the parameter as described in the Table: GC[7..0] Parameter Curve selected 01h GC0 Gamma Curve 1 02h GC1 Gamma Curve 2 04h GC2 Gamma Curve 3 08h GC3 Gamma Curve 4 Note: All other values are undefined. Restriction Register Availability Default Values of GC[7..0] not shown in table above are invalid and will not change the current selected Gamma curve until valid value is received. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes GC[7:0] = 0x01h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.178October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.20 Set_display_off (28h) 28H Command Parameter DISPOFF (Display Off) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 0 1 0 0 0 28 NO PARAMETER This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. Description Restriction Register Availability Default This command has no effect when module is already in display off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A Legend Display On Mode Command Parameter Display Flow Chart DISPOFF Action Mode Display Off Mode Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.179October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.21 Set_display_on (29h) 29H Command Parameter DISPON (Display On) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 0 1 0 0 1 29 NO PARAMETER This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory. This command does not change any other status. Description Restriction Register Availability Default This command has no effect when module is already in display on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes N/A Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.180October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.22 Set_clumn_address (2Ah) 2AH Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter CASET (Column Address Set) D7 D6 D5 D4 D3 0 0 1 0 1 D/CX 0 RDX 1 WRX ↑ D15-D8 - D2 0 D1 1 D0 0 1 1 ↑ - SC15 SC14 SC13 SC12 1 1 ↑ - SC7 SC6 SC5 SC4 1 1 ↑ - EC15 EC14 EC13 1 1 ↑ - EC7 EC6 EC5 HEX 2A SC11 SC10 SC9 SC8 00.. SC3 SC2 SC1 SC0 Note 1 EC12 EC11 EC10 EC9 EC8 00 .. EC4 EC3 EC2 EC1 EC0 Note 1 This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The values of SC[15:0] and EC[15:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. (Example) SC[15:0] Description Restriction Register Availability Default EC[15:0] SC[15:0] always must be equal to or less than EC[15:0] Note 1: When SC[15:0] or EC[15:0] is greater than horizontal line (when MADCTL’s B5=0) or vertical line (when MADCTL’s B5=1), data of out of range will be ignored. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Availability Yes Yes Yes Yes Yes RES_SEL[2:0]=000, Resoultion 480RGBx864: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh RES_SEL[2:0]=001, Resoultion 480RGBx854: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh RES_SEL[2:0]=010, Resoultion 480RGBx800: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh RES_SEL[2:0]=011, Resoultion 480RGBx640: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh RES_SEL[2:0]=100, Resoultion 360RGBx640: SC[15:0] = 0x0000h, EC[15:0] = 0x0167h RES_SEL[2:0]=101, Resoultion 480RGBx720: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh Legend CASET Command 1st & 2nd parameter SC[15:0] 3rd & 4th parameter EC[15:0] Parameter Display PASET Action Flow Chart 1st & 2nd parameter SP[15:0] 3rd & 4th parameter EP[15:0] If needed RAMWR Mode Sequential transfer Image Data D1[15:0],D2[15:0], ¡K.,Dn[15:0] Any Command Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.181October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.23 Set_page_address (2Bh) 2BH Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter PASET (Page Address Set) D7 D6 D5 D4 D3 0 0 1 0 1 SP15 SP14 SP13 SP12 SP11 SP7 SP6 SP5 SP4 SP3 D2 0 SP10 SP2 D1 1 SP9 SP1 D0 1 SP8 SP0 EP15 EP10 EP9 EP8 1 1 ↑ EP7 EP6 EP5 EP4 EP3 EP2 EP1 This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The values of SP[15:0] and EP[15:0] are referred when RAMWR command comes. Each value represents one Page line in the Frame Memory. EP0 D/CX 0 1 1 RDX 1 1 1 WRX ↑ ↑ ↑ D15-D8 - 1 1 ↑ - EP14 EP13 EP12 EP11 HEX 2B 00 .. Note 1 00 .. Note 1 Description Restriction Register Availability Default SP[15:0] always must be equal to or less than EP[15:0] Note 1: When SP[15:0] or EP[15:0] is greater than vertical line (When MADCTL’s B5=0) or horizontal line (When MADCTL’s B5=1), data of out of range will be ignored. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes RES_SEL[2:0]=000, Resoultion 480RGBx864: SP[15:0] = 0x0000h, EP[15:0] = 0x035Fh RES_SEL[2:0]=001, Resoultion 480RGBx854: SP[15:0] = 0x0000h, EP[15:0] = 0x0355h RES_SEL[2:0]=010, Resoultion 480RGBx800: SP[15:0] = 0x0000h, EP[15:0] = 0x031Fh RES_SEL[2:0]=011, Resoultion 480RGBx640: SP[15:0] = 0x0000h, EP[15:0] = 0x027Fh RES_SEL[2:0]=100, Resoultion 360RGBx640: SP[15:0] = 0x0000h, EP[15:0] = 0x027Fh RES_SEL[2:0]=101, Resoultion 480RGBx720: SP[15:0] = 0x0000h, EP[15:0] = 0x02CFh IF Needed Flow Chart IF Needed Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.182October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.24 Write_memory_start (2Ch) 2CH Command st 1 parameter : th N parameter Description Restriction Register Availability Default RAMWR (Memory Write) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 0 1 1 0 0 2C 1 1 ↑ D17 D16 D15 D14 D13 D12 D11 D10 00..FF 1 1 ↑ Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF 1 1 ↑ Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF This command transfers image data from the host processor to the display module’s frame memory starting at the pixel location specified by preceding set_column_address and set_page_address commands. The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixel Data 1 is stored in frame memory at (SC, SP). The column register is then incremented and pixels are written to the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are written to the frame memory until the page register equals the End Page (EP) value or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. In all colour modes, there is no restriction on length of parameters. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Contents of memory is set randomly and not cleared. Legend RAMWR Command Parameter Flow Chart Image Data D1[7:0],D2[7:0], ...,Dn[7:0] Display Action Any Command Mode Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.183October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.25 Colour Set (2Dh) 2DH COLSET (Colour Set) DNC NRD NWR D8~D15 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - 0 R007 Rnn7 R637 G007 Gnn7 G637 B007 Bnn7 B637 0 R006 Rnn6 R636 G006 Gnn6 G636 B006 Bnn6 B636 1 R005 Rnn5 R635 G005 Gnn5 G635 B005 Bnn5 B635 0 R004 Rnn4 R634 G004 Gnn4 G634 B004 Bnn4 B634 1 R003 Rnn3 R633 G003 Gnn3 G633 B003 Bnn3 B633 1 R002 Rnn2 R632 G002 Gnn2 G632 B002 Bnn2 B632 0 R001 Rnn1 R631 G001 Gnn1 G631 B001 Bnn1 B631 1 R000 Rnn0 R630 G000 Gnn0 G630 B000 Bnn0 B630 2D 00..FF 00..FF 00..FF 00..FF 00..FF 00..FF 00..FF 00..FF 00..FF Command st 1 parameter : th 64 parameter th 65 parameter : th 128 parameter th 129 parameter : nd 192 parameter Description This command is used to define the LUT for 18bit to 24bit, 16bit-to-24bit colour depth conversions colour depth conversions. 192bytes must be written to the LUT regardless of the colour mode. This command has no effect on other commands/parameters and Contents of frame memory. Visible change takes effect next time the Frame Memory is written to. This command is needed to be set in write_data for RGB 5-6-5 (65K colours) and RGB 6-6-6 (262K colours) pixel format. The default for command Colour Set (2Dh) is 0x00h. The colour depth conversion must be followed the below tables. Once write data is RGB 5-6-5 (65K colours), the set pixel format 0x3A=0x05h command must be set and using the 16bit-to-24bit colour depth conversion. R-G-B=5-6-5 R Restriction G B RGBSET parameter 1 2 3 .. .. 30 31 32 33 34 35 .. .. 62 63 64 65 66 67 .. .. 126 127 128 129 130 131 .. .. 158 159 160 161 162 163 24- bit /pixel mode R00[7:0] R01[7:0] R02[7:0] .. .. R29[7:0] R30[7:0] R31[7:0] LUT 24-bit /pixel value 00000000 00001000 00010000 .. .. 11101111 11110111 11111111 Input 16-bit /pixel 00000 00001 00010 .. .. 11101 11110 11111 Not Used Not Used Not Used G00[7:0] G01[7:0] G02[7:0] .. .. G61[7:0] G62[7:0] G63[7:0] B00[7:0] B01[7:0] B02[7:0] .. .. B29[7:0] B30[7:0] B31[7:0] 00000000 00000100 00001000 .. .. 11110111 11111011 11111111 00000000 00001000 00010000 .. .. 11101111 11110111 11111111 000000 000001 000010 .. .. 111101 111110 111111 00000 00001 00010 .. .. 11101 11110 11111 Not Used Not Used Not Used Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.184October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 .. .. 190 191 192 Once write data is RGB 5-6-5 (65K colours), the set pixel format 0x3A=0x06h command must be set and using the 18bit-to-24bit colour depth conversion. R-G-B=6-6-6 R G B Register Availability RGBSET parameter 1 2 3 .. .. 62 63 64 65 66 67 .. .. 126 127 128 129 130 131 .. .. 190 191 192 24- bit /pixel mode R00[7:0] R01[7:0] R02[7:0] .. .. R61[7:0] R62[7:0] R63[7:0] G00[7:0] G01[7:0] G02[7:0] .. .. G61[7:0] G62[7:0] G63[7:0] B00[7:0] B01[7:0] B02[7:0] .. .. B61[7:0] B62[7:0] B63[7:0] Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Status S/W Reset Default H/W Reset LUT 24-bit /pixel value 00000000 00000100 00001000 .. .. 11110111 11111011 11111111 00000000 00000100 00001000 .. .. 11110111 11111011 11111111 00000000 00000100 00001000 .. .. 11110111 11111011 11111111 Input 18-bit /pixel 000000 000001 000010 .. .. 111101 111110 111111 000000 000001 000010 .. .. 111101 111110 111111 000000 000001 000010 .. .. 111101 111110 111111 Availability Yes Yes Yes Yes Yes Default value Contents of the look-up table protected R00[7:0]~R63[7:0] =0x00h G00[7:0]~G63[7:0] =0x00h B00[7:0]~B63[7:0] =0x00h Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.185October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.186October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.26 Raed_memory_start (2Eh) 2EH Command st 1 parameter nd 2 parameter : th (n+1) parameter Description Restriction Register Availability Default D/CX 0 1 1 1 RDX 1 ↑ ↑ ↑ WRX ↑ 1 1 1 D15-D8 - 1 ↑ 1 - RAMRD (Memory Read) D7 D6 D5 D4 D3 0 0 1 0 1 X X X X X D17 D16 D15 D14 D13 Dx7 Dx6 Dx5 Dx4 Dx3 D2 1 X D12 Dx2 D1 1 X D11 Dx1 D0 0 X D10 Dx0 HEX 2E Dummy read 00..FF 00..FF Dn7 Dn2 Dn1 Dn0 00..FF Dn6 Dn5 Dn4 Dn3 This command transfers image data from the display module’s frame memory to the host processor starting at the pixel location specified by preceding set_column_address and set_page_address commands. The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels are read from frame memory at (SC, SP). The column register is then incremented and pixels read from the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are read from the frame memory until the page register equals the End Page (EP) value or the host processor sends another command. In all colour modes, the Frame Read is always 24bit so there is no restriction on length of parameters. Note – Memory Read is only possible via the Parallel Interface. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes Contents of memory is set randomly and not cleared. Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.187October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.27 Set_partial_area (30h) 30H Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter PLTAR (Partial Area) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 1 0 0 0 0 30 1 1 ↑ SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 xx 1 1 ↑ SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 xx 1 1 ↑ ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 xx 1 1 ↑ ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 xx This command defines the partial mode’s display area. There are 4 parameters associated with this command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in the figures below. SR and ER refer to the Frame Memory Line Pointer. If End Row>Start Row when MADCTL B4=0:- If End Row>Start Row when MADCTL B4=1:End Row Description ER[15:0] Partial Area SR[15:0] Start Row If End Row<Start Row when MADCTL B4=0:End Row ER[15:0] Partial Area SR[15:0] Start Row Restriction Register Availability If End Row = Start Row then the Partial Area will be one row deep. SR[15..0] and ER[15..0] cannot be greater than horizontal line number. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.188October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Default RES_SEL[2:0]=000, Resoultion 480RGBx864: SR[15:0] = 0x0000h, ER[15:0] = 0x035Fh RES_SEL[2:0]=001, Resoultion 480RGBx854: SR[15:0] = 0x0000h, ER[15:0] = 0x0355h RES_SEL[2:0]=010, Resoultion 480RGBx800: SR[15:0] = 0x0000h, ER[15:0] = 0x031Fh RES_SEL[2:0]=011, Resoultion 480RGBx640: SR[15:0] = 0x0000h, ER[15:0] = 0x027Fh RES_SEL[2:0]=100, Resoultion 360RGBx640: SR[15:0] = 0x0000h, ER[15:0] = 0x027Fh RES_SEL[2:0]=101, Resoultion 480RGBx720: SR[15:0] = 0x0000h, ER[15:0] = 0x02CFh 1. To Enter Partial Mode:PLTAR Legend Command SR[15...0] Parameter Display ER[15...0] PTLON Partial Mode Action Mode Sequential transfer 2. To Leave Partial Mode Flow Chart Partial Mode DISPOFF (Optional) To prevent Tearing Effect Image displayed NORON Partial Mode OFF RAMRW Image Data D1[17:0],D2[17:0], ..., Dn[15:0] DISPON Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.189October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.28 Set_scroll_area (33h) 33H Command 1 parameter nd 2 parameter rd 3 parameter th 4 parameter th 5 parameter th 6 parameter st VSCRDEF (Vertical Scrolling Definition) D15-D8 D7 D6 D5 D4 D3 D/CX RDX WRX D2 D1 D0 HEX 0 1 ↑ - 0 0 1 1 0 0 1 1 33 1 1 ↑ - TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8 xx 1 1 ↑ - TFA7 TFA 6 TFA 5 TFA 4 TFA 3 TFA 2 TFA1 TFA0 xx 1 1 ↑ - VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8 xx 1 1 ↑ - VSA7 VSA 6 VSA 5 VSA 4 VSA 3 VSA 2 VSA1 VSA0 xx 1 1 ↑ - BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8 xx 1 1 ↑ - BFA7 BFA 6 BFA 5 BFA 4 BFA 3 BFA 2 BFA1 BFA0 xx st nd This command defines the Vertical Scrolling Area of the display. When MADCTL B4=0, the 1 & 2 parameter TFA[15..0] describes the Top Fixed Area (in No. of lines from top of the Frame Memory rd th and Display). The 3 & 4 parameter VSA[15..0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first line read from Frame Memory appears immediately after the bottom most line of the Top Fixed Area. th th The 5 & 6 parameter BFA[15..0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer. Top Fixed Area (0 ,0 ) TFA [ 15:0 ] First line read from frame memory Scroll Area BFA [15:0] Description Bottom Fixed Area When MADCTL B4=1 st nd The 1 & 2 parameter TFA[15..0] describes the Top Fixed Area (in No. of lines from bottom of the rd th Frame Memory and Display). The 3 & 4 parameter VSA[15..0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first line read from Frame Memory appears immediately after the top most line of the th th Top Fixed Area. The 5 & 6 parameter BFA[15..0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display). Bottom Fixed Area (0 ,0 ) BFA [15:0] Scroll Area TFA [ 15:0 ] Top Fixed Area Restriction Register Availability First line read from frame memory The condition is (TFA+VSA+BFA)= Vertical line number, otherwise Scrolling mode is undefined. In Vertical Scroll Mode, MADCTL B5 should be set to ‘0’ – this only affects the Frame Memory Write. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Availability Yes Yes Yes Yes Yes Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.190October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Status Default RES_SEL[2:0]=000, 480RGBx864 RES_SEL[2:0]=001, 480RGBx854 RES_SEL[2:0]=010, 480RGBx800 RES_SEL[2:0]=011, 480RGBx640 RES_SEL[2:0]=100, 360RGBx640 RES_SEL[2:0]=101, Default value TFA[15..0]= 0x0000h VSA[15..0]= 0x0360h BFA[15..0]= 0x0000h TFA[15..0]= 0x0000h VSA[15..0]= 0x0356h BFA[15..0]= 0x0000h TFA[15..0]= 0x0000h VSA[15..0]= 0x0320h BFA[15..0]= 0x0000h TFA[15..0]= 0x0000h VSA[15..0]= 0x0280h BFA[15..0]= 0x0000h TFA[15..0]= 0x0000h VSA[15..0]= 0x0280h BFA[15..0]= 0x0000h TFA[15..0]= 0x0000h VSA[15..0]= 0x02D0h BFA[15..0]= 0x0000h 1.To enter Vertical Scroll Mode: Normal Mode Legend Command VSCRDEF Parameter 1st & 2nd Parameter TFA[15...0] Display 3rd & 4th Parameter VSA[15...0] Action 5th & 6th Parameter BFA[15...0] Mode CASET Sequential transfer 1st & 2nd Parameter SC[15...0] 3rd & 4th Parameter EC[15...0] PASET Flow Charts Only required for nonrolling scrolling Redefines the Frame Memory Window that the scroll data will be written to. See Note 1 1st & 2nd Parameter SP[15...0] 3rd & 4th Parameter EP[15..0] MADCTL Parameter Optional ¡V It may be necessary to redefine the Frame Memory Write Direction. RAMRW Scroll Image Data VSCRSADD 1st & 2nd Parameter VSP[15...0] Scroll Mode Note: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed. 2. Continuous Scroll: Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.191October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Legend Scroll Mode CASET 1st & 2nd Parameter SC[15..0] Command Parameter Display Action 3rd & 4th Parameter EC[15..0] Mode PASET 1st & 2nd Parameter SP[15..0] Sequential transfer 3rd & 4th Parameter EP[15..0] RAMRW Scroll Image Data VSCRSADD 1st & 2nd Parameter VSP[15..0] 3. To Leave Vertical Scroll Mode: Note: Scroll Mode can be left by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.192October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.29 Tearing effect line off (34h) 34H Command Parameter Description Restriction Register Availability Default TEOFF (Tearing Effect Line OFF) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 1 0 1 0 0 34 NO PARAMETER This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. This command has no effect when Tearing Effect output is already OFF. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes OFF Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.193October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.30 Set_tear_on (35h) 35H Command Parameter TEON (Tearing Effect Line ON) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 1 0 1 0 1 35 1 1 ↑ X X X X X X X M xx This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit B4. The Tearing Effect Line On has one parameter which describes the mode of the Tearing Effect Output Line. (X=Don’t Care). When M=0: The Tearing Effect Output line consists of V-Blanking information only: tvdl Description tvdh Vertical Time Scale When M=1: The Tearing Effect Output Line consists of both V-Blanking and H-Blanking information: tvdl tvdh Vertical Time Scale Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Restriction Register Availability Default This command has no effect when Tearing Effect output is already ON. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes OFF Legend TE Line Output OFF Command Parameter TEON Flow Chart M Display Action Mode TE Line Output ON Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.194October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.31 Set_address_mode (36h) 36H Command st 1 parameter D/CX 0 1 RDX 1 1 MADCTL (Memory Access Control) D15-D8 D7 D6 D5 D4 D3 0 0 1 1 0 B7 B6 B5 B4 B3 WRX ↑ ↑ D2 1 B2 D1 1 X D0 0 X HEX 36 XX This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Bit Assignment BIT B7 B6 B5 B4 NAME PAGE ADDRESS ORDER (MY) COLUMN ADDRESS ORDER (MX) PAGE/COLUMN SELECTION (MV) Vertical ORDER (ML) B3 RGB-BGR ORDER (BGR) B2 Horizontal ORDER (SS) DESCRIPTION These 3 bits controls MCU to memory write/read direction. LCD vertical refresh direction control Colour selector switch control (0=RGB colour filter panel, 1=BGR colour filter panel) LCD horizontal refresh direction control RGB-BGR Order B3= 0 Description SIG1 Driver IC SIG2 ………… SIG1 SIG2 ………… RGB RG B RG B RG B RG B B3= 1 RG B SIG480 SIG1 Driver IC SIG2 ………… SIG480 SIG1 SIG2 ………… RG B B GR B GR B GR B GR RGB RG B LCD panel RGB SIG480 SIG480 B GR B GR LCD panel Sent 2nd Sent 3rd Sent First (1) Sent last (480) Sent last (480) Sent 2nd Sent 3rd Sent First (1) Note: Top-Left (0,0) means a physical memory location. Bit D1 – Switching Between Segment Output and RAM Bit D0 – Switching Between Common Output and RAM Restriction - Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.195October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Default Status Power On Sequence S/W Reset Availability Yes Yes Yes Yes Yes Default value B7=0,B6=0,B5=0,B4=0,B3=0,B2=0,B1=0,B0=0 No Change Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.196October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.32 Set_scroll_start (37h) 37H VSCRSADD (Vertical Scrolling Start Address) D15-D8 D7 D6 D5 D4 D3 D2 0 0 1 1 0 1 D/CX 0 RDX 1 WRX ↑ st 1 1 ↑ - nd 1 1 ↑ - Command 1 parameter 2 parameter VSP 15 VSP 7 VSP 14 VSP 6 VSP 13 VSP 5 VSP 12 VSP 4 VSP 11 VSP 3 VSP 10 VSP 2 D1 1 D0 1 HEX 37 VSP 9 VSP 1 VSP 8 VSP 0 00. 13F This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter which describes the address of the line in the Frame Memory that will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:When MADCTL B4=0 Example: When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 864(DM=10) and Description When MADCTL B4=1 Example: When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 320(DM=10) and Restriction Register Availability Default Flow Chart When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. VSP refers to the Frame Memory line Pointer. Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h) – otherwise undesirable image will be displayed on the Panel. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No VSP[15:0]= 0x0000h See Vertical Scrolling Definition (33h) description. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.197October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.33 Idle mode off (38h) 38H Command Parameter Description Restriction Register Availability Default IDMOFF (Idle mode off) D15-D8 D7 D6 D5 D4 D3 0 0 1 1 1 D/CX RDX WRX D2 D1 D0 HEX 0 1 ↑ 0 0 0 38 NO PARAMETER This command is used to recover from Idle mode on. In the idle off mode, LCD can display maximum 16.7M colours. This command has no effect when module is already in idle off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Idle mode is OFF. Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.198October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.34 Enter_Idle_mode (39h) 39H Command Parameter IDMON (Idle mode on) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 0 1 ↑ 0 0 1 1 1 0 0 NO PARAMETER This command is used to enter into Idle mode on. In the idle on mode, colour reduced. The primary and the secondary colours using MSB of each R, G Frame Memory, 8 colour depth data is displayed. D0 1 HEX 39 expression is and B in the (Example) Memory Description Restriction Register Availability Default Display Memory contents vs. Display Colour R7 - R0 G7 - G0 Black 0XXXXX 0XXXXX Blue 0XXXXX 0XXXXX Red 1XXXXX 0XXXXX Magent 1XXXXX 0XXXXX Green 0XXXXX 1XXXXX Cyan 0XXXXX 1XXXXX Yellow 1XXXXX 1XXXXX White 1XXXXX 1XXXXX X=don’t care This command has no effect when module is already in idle on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes Idle mode is OFF. B7 - B0 0XXXXX 1XXXXX 0XXXXX 1XXXXX 0XXXXX 1XXXXX 0XXXXX 1XXXXX Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.199October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.35 Set_pixel_format (3Ah) 3A H Command st 1 parameter Description Restriction Register Availability Default COLMOD (Interface Pixel Format) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 1 1 0 1 0 3A 1 1 ↑ X D6 D5 D4 X D2 D1 D0 XX This command is used to define the format of RGB picture data. D6~D4 : DPI Pixel format Definition. D2~D0 : DBI Pixel format Definition. The formats are shown in the table: Pixel Format D6/D2 D5/D1 D4/D0 Not Defined 0 0 0 Not Defined 0 0 1 Not Defined 0 1 0 Not Defined 0 1 1 Not Defined 1 0 0 16 Bit/Pixel 1 0 1 18 Bit/Pixel 1 1 0 24 Bit/Pixel 1 1 1 If a particular interface, enter DBI or DPI, is not used then the correspondind bits in the parameter returned from the display module undefined. There is no visible effect until the Frame Memory is written to. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Status Power On Sequence Default value 24 Bit/Pixel Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.200October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.36 Write_memory_contiune (3Ch) 3CH Command st 1 parameter : th N parameter Description Restriction Register Availability Default Write_memory_contiune D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 0 1 1 1 1 0 0 3C 1 1 ↑ D17 D16 D15 D14 D13 D12 D11 D10 00..FF 1 1 ↑ Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF 1 1 ↑ Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF This command transfers image data from the host processor to the display module’s frame memory continuing from the pixel location following the previous write_memory_continue or write_memory_start command. Sending any other command can stop frame Write. If set_address_mode B5 = 0: Data is written continuing from the pixel location after the write range of the previous write_memory_start or write_memory_continue. The column register is then incremented and pixels are written to the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are written to the frame memory until the page register equals the End Page (EP) value or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. If set_address_mode B5 = 1: Data is written continuing from the pixel location after the write range of the previous write_memory_start or write_memory_continue. The page register is then incremented and pixels are written to the frame memory until the page register equals the End Page (EP) value. The page register is then reset to SP and the column register is incremented. Pixels are written to the frame memory until the column register equals the End column (EC) value or the host processor sends another command. If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored. In all colour modes, there is no restriction on length of parameters. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Status Power On Sequence S/W Reset Default value Contents of memory is set randomly Contents of memory is set randomly Legend RAMWR Command Parameter Flow Chart Image Data D1[7:0],D2[7:0], ...,Dn[7:0] Display Action Any Command Mode Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.201October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.37 Raed_memory_continue (3Eh) 3EH Raed_memory_continue D7 D6 D5 D4 D3 0 0 1 1 1 D/CX 0 RDX 1 WRX ↑ D15-D8 - st 1 ↑ 1 - X X X X nd 1 1 ↑ ↑ 1 1 - D17 D16 D15 Dx7 Dx6 Dx5 1 ↑ 1 - Dn7 Dn6 Dn5 Command 1 parameter 2 parameter : th (n+1) parameter Description Restriction Register Availability D2 1 D1 1 D0 0 HEX 3E X X X X D14 D13 D12 D11 D10 Dummy read 00..FF Dx4 Dx3 Dx2 Dx1 Dx0 00..FF Dn4 Dn3 Dn2 Dn1 Dn0 00..FF This command transfers image data from the display module’s frame memory to the host processor continuing from the location following the previous read_memory_continue or read_memory_start command. If set_address_mode B5=0: Pixels are read continuing from the pixel location after the read range of the previous read_memory_start or read_memory_continue. The column register is then incremented and pixels are read from the frame memory until the column register equals the End Column (EC) value. The column register is then reset to SC and the page register is incremented. Pixels are read from the frame memory until the page register equals the End Page (EP) value or the host processor sends another command. If set_address_mode B5=1: Pixels are read continuing from the pixel location after the read range of the previous read_memory_start or read_memory_continue. The page register is then incremented and pixels are read from the frame memory until the page register equals the End Page (EP) value. The page register is then reset to SP and the column register is incremented. Pixels are read from the frame memory until the column register equals the End Column (EC) value or the host processor sends another command. Regardless of the color mode set in set_pixel_format, the pixel format returned by read_memory_continue is always 24-bit so there is no restriction on the length of data. A read_memory_start should follow a set_column_address, set_page_address or set_address_mode to define the read location. Otherwise, data read with read_memory_continue is undefined. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Default Status Power On Sequence Default value Contents of memory is set randomly Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.202October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.38 Set tear scan lines (44h) 44H Command st 1 parameter nd 2 parameter Description TESL (Tear Effect Scan Lines) D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 0 1 0 0 0 1 0 0 44 1 1 ↑ TELINE[15:8](8’b0) 00..FF 1 1 ↑ TELINE[7:0](8’b0) 00..FF This command is turns on the display module’s Tearing Effect output signal on the TE signal Line when the display module reacfes line TELINE. The TE signal is not affected by changing MADCTL bit B4. The Tearing Effect Line On has one parameter which describes the mode of the Tearing Effect Output Line. The Tearing Effect Output line consists of V-Blanking information only: tvdl tvdh Vertical Time Scale Restriction Register Availability Default Note: That TELINE=0 is equivalent to TEMODE=0. The Tearing Effect Output Line shall be active low when the display module is in Sleep mode. The command has no effect when Tearing Effect output is already ON. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes TELINE[15:0]=0x0000h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.203October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.39 Get the current scanline(45h) 45H D/CX RDX WRX 0 1 1 1 1 1 ↑ ↑ ↑ Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default GETSCAN (Get the current scanline) D15-D8 D7 D6 D5 D4 D3 D2 - 0 1 0 0 0 1 SLN[15:8](8’b0) SLN[7:0](8’b0) D1 D0 HEX 0 1 45 00..FF 00..FF The display module returns the current scanline, N, used to update the display device. The total number of scanlines on a display device is defined as VSYNC + VBP + VACT + VFP. The first scanline is defined as the first line of V Sync and is denoted as Line 0. When in Sleep Mode, the value returned by get_scanline is undefined. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes SLN[15:0]= 0x0000h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.204October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.40 Write display brightness (51h) 51H Command st 1 parameter Description Restriction Register Availability Default WRDISBV (Write Display Brightness) D/CX 0 1 RDX 1 1 WRX ↑ ↑ D15-D8 - D7 0 D6 1 D5 0 D4 D3 1 0 DBV[7:0] D2 0 D1 0 D0 1 HEX 51 00 .. FF This command is used to adjust the brightness value of the display. It should be checked what the relationship between this written value and output brightness of the display is. This relationship is defined on the display module specification. In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. See chapter “5.18.3 Brightness Control Block”. Status Availability Sleep Out Yes Sleep In Yes DBV[7:0]= 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.205October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.41 Read display brightness value (52h) RDDISBV (Read Display Brightness Value) 52H D/CX 0 1 1 Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default RDX 1 ↑ ↑ WRX ↑ 1 1 D15-D8 - D7 0 xx D6 1 xx D5 0 xx D4 D3 1 0 xx xx DBV[7:0] D2 0 xx D1 1 xx D0 0 xx HEX 52 Dummy read xx This command returns the brightness value of the display. It should be checked what the relationship between this returned value and output brightness of the display. This relationship is defined on the display modulespecification is. In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. See chapters: “5.18.3 Brightness Control Block”, and “6.2.40 Write Display Brightness (51h)” DBV[7:0] is reset when display is in sleep-in mode. DBV[7:0] is ‘0’ when bit BCTRL of “6.2.42 Write CTRL Display (53h)” command is ‘0’. DBV[7:0] is manual set brightness specified with “6.2.42 Write CTRL Display (53h)” command when bit BCTRL is ‘1’. When bit BCTRL of “6.2.42 Write CTRL Display (53h)” command is ‘1’ and bit C1/C0 of “6.2.44 Write Content Adaptive Brightness Control (55h)” are ‘0’, DBV[7:0] output is the brightness value specified with “6.2.40 Write Display Brightness (51h)” command. Status Sleep Out Sleep In DBV[7:0]= 0x00h Availability Yes Yes Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.206October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.42 Write CTRL display (53h) 53H Command st 1 parameter Description Restriction Register Availability Default WRCTRLD (Write Control Display) D/CX 0 1 RDX 1 1 WRX ↑ ↑ D15-D8 - D7 0 xx D6 1 xx D5 0 BCTRL D4 1 xx D3 0 DD D2 0 BL D1 1 xx D0 1 xx HEX 53 00 .. FF This command is used to control display brightness. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display. 0 = Off (Brightness registers are 00h, DBV[7..0]) 1 = On (Brightness registers are active, according to the other parameters.) Display Dimming (DD): (Only for manual brightness setting) DD = 0: Display Dimming is off DD = 1: Display Dimming is on BL: Backlight Control On/Off 0 = Off (Completely turn off backlight circuit. Control lines must be low. ) 1 = On Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0. When BL bit change from “On” to “Off”, backlight is turned off without gradual dimming, even if dimming-on (DD=1) are selected. X = Don’t care. Status Availability Sleep Out Yes Sleep In Yes D[7:0]= 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.207October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.43 Read CTRL value display (54h) 54H Command st 1 parameter nd 2 arameter Description Restriction Register Availability Default RDCTRLD (Read Control Value Display) D/CX 0 1 1 RDX 1 ↑ ↑ WRX ↑ 1 1 D15-D8 - D7 0 xx 0 D6 1 xx 0 D5 0 xx BCTRL D4 1 xx 0 D3 0 xx DD D2 1 xx BL D1 0 xx 0 D0 0 xx 0 HEX 54 xx xx This command returns ambient light and brightness control values, see chapter: “6.2.42 Write CTRL Display (53h)”. BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display. 0 = Off 1 = On Display Dimming (DD): DD = 0: Display Dimming is off DD = 1: Display Dimming is on BL: Backlight Control On/Off 0 = Off (completely turn off backlight circuit) 1 = On Status Availability Sleep Out Yes Sleep In Yes D[7:0]= 0x00h Legend Serial I/F Mode Flow Chart Command Parallel I/F Mode Read RDCTRLD Read RDCTRLD Send 2nd Parameter Dummy Read Host Display Parameter Displa y Action Mode Send 2nd Parameter Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.208October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.44 Write content adaptive brightness control (55h) 55 H Command st 1 parameter WRCABC (Write Content Adaptive Brightness Control) D/CX 0 1 RDX 1 1 WRX ↑ ↑ D15-D8 - D7 0 xx D6 1 xx D5 0 xx D4 1 xx D3 0 xx D2 1 xx D1 D0 0 1 CABC[1:0] HEX 55 xx This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. See chapter “5.18 Content Adaptive Brightness Control (CABC)”. Description C1 0 0 1 1 X = Don’t care. C0 0 1 0 1 Function Off User Interface Image Still Picture Moving Image Restriction Register Availability Default Status Sleep Out Sleep In CABC[1:0] = 00 Availability Yes Yes Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.209October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.45 Read content adaptive brightness control (56h) 56H Command st 1 parameter nd 2 parameter Description RDCABC (Read Content Adaptive Brightness Control) D/CX 0 1 1 RDX 1 ↑ ↑ WRX ↑ 1 1 D15-D8 - D7 0 XX 0 D6 1 XX 0 D5 0 XX 0 D4 1 XX 0 D3 0 XX 0 D2 1 XX 0 D1 1 XX C1 D0 0 XX C0 HEX 56 Dummy read xx This command is used to set parameters for image content based adaptive brightness control functionality. There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below. See chapter “5.18 Content Adaptive Brightness Control (CABC)”. C1 C0 Function 0 0 Off 0 1 User Interface Image 1 0 Still Picture 1 1 Moving Image Restriction Register Availability Default Status Sleep Out Sleep In C[1:0] = 00 Availability Yes Yes Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.210October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.46 Write CABC minimum brightness (5Eh) 5E H Command st 1 parameter Description Restriction Register Availability Default WRCABCMB (Write CABC minimum brightness) D/CX 0 1 RDX 1 1 WRX ↑ 1 D15-D8 - D7 0 D6 1 D5 0 D4 D3 1 1 CMB[7:0] D2 1 D1 1 D0 0 HEX 5E 00 .. FF This command is used to set the minimum brightness value of the display for CABC function. In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest brightness for CABC. See chapter “5.18.4 Minimum brightness setting of CABC function”. Status Availability Sleep Out Yes Sleep In Yes CMB[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.211October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.47 Read CABC minimum brightness (5Fh) 5FH Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default D/CX RDX 0 1 1 1 ↑ ↑ RDCABCMB (Read CABC minimum brightness) WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 ↑ 1 1 - 0 XX 1 XX 0 XX 1 1 XX XX CMB[7:0] 1 XX 1 XX D0 HEX 1 XX 5F XX XX This command returns the minimum brightness value of CABC function. In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness. See chapter “5.18.4 Minimum brightness setting of CABC function”. CMB[7:0] is CABC minimum brightness specified with “6.2.46 Write CABC minimum brightness (5Eh)” command. Status Availability Sleep Out Yes Sleep In Yes CMB[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.212October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.48 Read automatic brightness control self-diagnostic result (68h) 68H Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default RDABCSDR (Read Automatic Brightness Control Self-Diagnostic Result) D/CX 0 1 1 RDX 1 ↑ ↑ WRX ↑ 1 1 D15-D8 - D7 D6 0 1 xx xx D[7:6] D5 1 xx 0 D4 0 xx 0 D3 1 xx 0 D2 0 xx 0 D1 0 xx 0 D0 0 xx 0 HEX 68 xx xx This command indicates the status of the display self-diagnostic results for automatic brightness control after Sleep Out -command as described in the table below: Bit D7 – Register Loading Detection See section “5.15.1 Register loading Detection”. Bit D6 – Functionality Detection See section “5.15.2 Functionality Detection “. Bits D5, D4, D3, D2, D1 and D0 are for future use and are set to ‘0’. Status Availability Sleep Out Yes Sleep In Yes D[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.213October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.49 Read_DDB_start (A1h) A1H Command st 1 parameter nd 2 parameter : th N parameter Description Restrictions Register Availability Default Read_DDB_start D/CX 0 1 1 1 1 RDX 1 ↑ ↑ ↑ ↑ WRX ↑ 1 1 1 1 D15-D8 - D7 1 x x x x D6 0 x x x x D5 1 x x x x D4 0 x x x x D3 0 x x x x D2 0 x x x x D1 0 x x x x D0 1 X x x x HEX A1 Dummy read xx xx xx This command reads identifying and descriptive information from the peripheral. This information is organized in the Device Descriptor Block (DDB) stored on the peripheral. The response to this command returns a sequence of bytes that may be any length up to 64K bytes. Note that the returned sequence of bytes does not necessarily correspond to the entire DDB; it may be a portion of a larger block of data. The format of returned data is as follows: Parameter 2: LS (least significant) byte of Supplier ID. Supplier ID is a unique value assigned to each peripheral supplier by the MIPI organization. Parameter 3: MS (most significant) byte of Supplier ID. Parameter 4: LS (least significant) byte of Supplier Elective Data. This is a byte of information that is determined by the supplier. It could include model number or revision information, for example. Parameter 5: MS (most significant) byte of Supplier Elective Data Parameter 6: single-byte Escape or Exit Code (EEC). The code is interpreted as follows: - FFh - Exit code – there is no more data in the Descriptor Block - 00h - Escape code – there is supplier-proprietary data in the Descriptor Block (does not conform to any MIPI standard) - Any other value – there is DDB data in the Descriptor Block. The format and interpretation of this data is documented in MIPI Alliance Standard for Device Descriptor Block (DDB). DDBs may contain many more data fields providing information about the peripheral. In a DSI system, read activity takes the form of two separate transactions across the bus: first the read command read_DDB_start from host processor to peripheral, which includes the bus turn-around token. The peripheral then takes control of the bus and returns the requested data. The peripheral response to read_DDB_start is a Long Packet type, so its length may be up to 64K bytes unless limited by a previous set_max_return_size command. The response to a read_DDB_start command always starts at the beginning of the Device Descriptor Block. After receiving the first packet and processing the returned DDB data, the host processor may initiate a read_DDB_continue command to access the next portion of the DDB. A read_DDB_continue command begins the next read at the location following the last byte of the previous data read from the DDB. Subsequent read_DDB_continue commands can be used to read a DDB or supplier-proprietary block of arbitrary size. There is, however, no obligation to read the entire block. The host processor may choose to stop reading after completion of any read_DDB_xxx command. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes D[7:0] = 0x00h Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.214October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.215October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.50 Read_DDB_continue (A8h) A8H Command st 1 parameter nd 2 parameter : th N parameter Description Restrictions Register Availability Default Read_DDB_continue D/CX 0 1 1 1 1 RDX 1 ↑ ↑ ↑ ↑ WRX ↑ 1 1 1 1 D15-D8 - D7 1 x x x x D6 0 x x x x D5 1 x x x x D4 0 x x x x D3 1 x x x x D2 0 x x x x D1 0 x x x x D0 0 x x x x HEX A8 Dummy read xx xx xx A read_DDB_start command should be executed at least once before a read_DDB_continue command to define the read location. Otherwise, data read with a read_DDB_continue command is undefined. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes D[7:0] = 0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.216October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.51 Read ID1 (DAh) DAH Command st 1 parameter nd 2 parameter Description Restriction Register Availability Default RDID1 (Read ID1) DNC 0 1 1 NRD 1 ↑ ↑ NWR ↑ 1 1 D15~D8 - D7 1 - D6 1 - D5 D4 D3 D2 D1 D0 HEX 0 1 1 0 1 0 DA module’s manufacturer[7:0] xx This read byte identifies the LCD module’s manufacturer. It is specified by display supplier and for xx is defined as xxHEX. - Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Availability Yes Yes Yes Yes Yes Default value OTP value Define by customer ID1[7:0]=0x00h Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.217October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.52 Read ID2 (DBh) DBH Command st 1 parameter nd 2 parameter Description Restrictions Register Availability Default RDID2 (Read ID2) DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 1 0 1 1 0 1 1 DB 1 ↑ 1 xx xx xx xx xx xx xx xx xx 1 ↑ 1 LCD module/driver version [6:0] This read byte is used to track the LCD module/driver version. It is defined by display supplier and changes each time a revision is made to the display, material or construction specifications. See Table: ID Byte Value V[7:0] Version Changes 80h 81h 82h 83h 84h 85h X= Don't care Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes Default value OTP value Define by customer ID2[6:0]=0x00h Serial I/F Mode (P/SX=Low) Parallel I/F Mode (P/SX=High) Legend Command Read ID2 Flow Chart Send 2 nd p arameter Read ID2 Dummy Read Host Display Parameter Display Action Mode Send 2 nd parameter Sequential transfer Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.218October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.53 Read ID3 (DCh) DCH Command st 1 parameter nd 2 parameter Description Restrictions RDID3 (Read ID3) DNC 0 1 1 NRD 1 ↑ ↑ NWR ↑ 1 1 D15~D8 - D7 1 xx D6 1 xx D5 D4 D3 D2 D1 D0 HEX 0 1 1 1 0 0 DC xx xx xx xx xx xx xx LCD module/driver ID[7:0] xx This read byte identifies the LCD module/driver. It is specified by display supplier and for this LCD project module is defined as xxHEX. - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Default Default value ID3[7:0]=0x00h Availability Yes Yes Yes Yes Yes OTP value Define by customer Flow Chart Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.219October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.54 SETOSC: Set internal oscillator (B0h) B0H Command SETOSC( Set Internal Oscillator) DNC 0 NRD 1 NWR ↑ D15~D8 - D7 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 1 1 ↑ - - - - - - - - 1 1 ↑ - - - - - st 1 parameter 2 nd parameter UADJ[3:0] D0 0 OSC _EN HEX DC - This command is used to set internal oscillator related setting OSC_EN: Enable internal oscillator, High active. UADJ[3:0]: For User to adjust OSC frequency, default is 15 MHZ. Description Restrictions Register Availability Default UADJ Internal oscillator frequency 0 0 0 0 28.0% 0 0 0 1 34.8% 0 0 1 0 41.5% 0 0 1 1 48.1% 0 1 0 0 54.7% 0 1 0 1 61.3% 0 1 1 0 67.8% 0 1 1 1 74.4% 1 0 0 0 80.6% 1 0 0 1 87.2% 1 0 1 0 93.5% 100.0% 1 0 1 1 1 1 0 0 106.4% 1 1 0 1 112.7% 1 1 1 0 119.4% 1 1 1 1 125.8% SETEXTC turn on to enable this command. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Status Power On Sequence S/W Reset H/W Reset Default value OSC_EN=0, UADJ[3:0]= 1011 OTP value UADJ[3:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.220October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.55 SETPOWER: Set power (B1h) B1H SETPOWER( Set power related setting) DNC NRD NWR D15~D8 Command 0 1 ↑ - st 1 1 ↑ - nd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - 1 1 ↑ - 1 parameter 2 parameter rd 3 parameter th 4 parameter th 5 parameter th 6 parameter th 7 parameter th 8 parameter th 9 parameter th 10 parameter th 11 parameter th 12 parameter D7 D6 - - - - th 1 1 ↑ - - th 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ - A_DC[1:0] B_DC[1:0] C_DC[1:0] D_DC[1:0] E_DC[1:0] 13 parameter 14 parameter th 15 parameter th 16 parameter th 17 parameter th 18 parameter th 19 parameter D5 1 0 1 VBIA VSN_ VSP_ S_EN EN EN FS1[2:0] DT[1:0] - DD_TU D4 D3 D2 1 VGL_ EN - 0 VGH_ EN - 0 LVGL _EN - - 0 VDDD N_HZ AP[2:0] BT[3:0] DCDIV[3:0] BTP[4:0] BTN[4:0] VRHP[7:0] VRHN[7:0] VRMP[5:0] VRMN[5:0] VPNL _EN DC86_DIV[3:0] DTPS[2:0] A_DTP[2:0] B_DTP[2:0] C_DTP[2:0] D_DTP[2:0] E_DTP[2:0] D1 HEX 1 B1 STB - DSTB - VBS[2:0] XDK1 - D0 XDK0 DTNS[2:0] A_DTN[2:0] B_DTN[2:0] C_DTN[2:0] D_DTN[2:0] E_DTN[2:0] AUTO _XDK - This command is used to set related setting of power. DSTB: When DSTB = “1”, the HX8369-A into the deep_standby mode, where all display operation stops, suspend all the internal operations including the internal R-C oscillator. During the standby mode, only the following process can be executed. 1. Exit the Standby mode (DSTB = “0”) In the deep standby mode, the GRAM data and register content may be lost. For preventing this, they have to reset again after the deep standby mode cancel. STB: When SLP = “1”, the HX8369-A00 enters the standby mode, where all display operation stops, suspend all the internal operations. But the internal R-C oscillator stop or not is determined by OSC_EN bit. To minimize the standby power, please set OSC_EN to 0. During the standby mode, only the following process can be executed. a. Exit the Standby (Sleep) mode (SLP = “0”) b. Enable or disable the oscillation c. Software reset Description VSP_EN: ON/OFF the operation of VSP circuit. VSP_EN Operation of VSP DC/DC circuit 0 OFF 1 ON VSN_EN: ON/OFF the operation of VSN circuit. VSN_EN Operation of VSN DC/DC circuit 0 OFF 1 ON VGH_EN: ON/OFF the operation of VGH charge bump circuit. VGH_EN Operation of VGH charge bump circuit 0 OFF 1 ON Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.221October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 VGL_EN 0 1 Operation of VGL charge bump circuit OFF ON LVGL_EN : ON/OFF the operation of LVGL charge bump circuit. LVGL_EN Operation of LVGL charge bump circuit 0 OFF 1 ON BT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VGH 2*(VSP-VSN) 2*(VSP-VSN) 2*(VSP-VSN) (VSP-VSN)+(VDD3-VSN) (VSP-VSN)+(VDD3-VSN) (VSP-VSN)+(VDD3-VSN) (VSP-VSN)+(VSP-VSSD) (VSP-VSN)+(VSP-VSSD) (VSP-VSN)+(VSP-VSSD) (VDD3-VSN)+(VSP-VSSD) (VDD3-VSN)+(VSP-VSSD) (VDD3-VSN)+(VSP-VSSD) (VSP-VSN) (VSP-VSN) (VSP-VSN) 2*(VSP-VSSD) VGL VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) -2*(VSP-VSSD) FS1[2:0]: Set the operating frequency of the step-up circuit for VGH and VGL voltage generation. FS12 FS11 FS10 Operation Frequency of Step-up Circuit 0 0 0 Inhibit 0 0 1 Fosc/64 0 1 0 Fosc/128 0 1 1 Fosc/256 1 0 0 Fosc/512 1 0 1 Fosc/1024 1 1 0 Fosc/2048 1 1 1 Fosc/4096 VDDDN_HZ: Choose external or internal VDDDN power. VDDDN_HZ=0, VDDDN= -2.5V. VDDDN_HZ=1, VDDDN output HZ. (For external VDDDN.) DCDIV[3:0]: Set the normal operate frequency of DC/DC converter circuit during normal mode. For PFM circuit: Set the operate frequency of DC/DC converter circuit for PFM design. (PCCS[1:0]=00, PCCS[1:0]=01, PCCS[1:0]=10) Normal operate frequency of DC/DC DCDIV3 DCDIV2 DCDIV1 DCDIV0 converter 0 0 0 0 Fosc / 1 0 0 0 1 Fosc / 2 0 0 1 0 Fosc / 3 0 0 1 1 Fosc / 4 0 1 0 0 Fosc / 5 0 1 0 1 Fosc / 6 0 1 1 0 Fosc / 7 0 1 1 1 Fosc / 8 1 0 0 0 Fosc / 1 1 0 0 1 Fosc / 2 1 0 1 0 Fosc / 3 1 0 1 1 Fosc / 4 1 1 0 0 Fosc / 5 1 1 0 1 Fosc / 6 1 1 1 0 Fosc / 7 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.222October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 1 1 1 1 Fosc / 8 DT[1:0]:Delay time of power on and power off sequence. DT1 DT0 Delay time of power on and power off sequence on (ms) 0 0 5ms 0 1 10ms 1 0 15ms 1 1 20ms DTPS[2:0]: Set the soft start operating duty cycle of DC/DC circuit. (PFM DC/DC circuit). 1 duty cycle = 1 M clock DTPS2 DTPS1 DTPS0 soft start operating duty cycle of DC/DC circuit circuit 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 DTNS[2:0]: Set the soft start operating duty cycle of DC/DC circuit. (PFM DC/DC circuit). 1 duty cycle = 1 M clock DTNS2 DTNS1 DTNS0 soft start operating duty cycle of DC/DC circuit circuit 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 BTP[4:0]: Switch the output factor for DC/DC circuit for VSP voltage generation. The LCD drive voltage level VSP can be selected according to the characteristic of liquid crystal which panel used. BTP4 BTP3 BTP2 BTP1 BTP0 VSP 3.01 0 0 0 0 0 3.15 0 0 0 0 1 3.29 0 0 0 1 0 3.46 0 0 0 1 1 3.60 0 0 1 0 0 1 3.74 0 0 1 0 3.91 0 0 1 1 0 4.05 0 0 1 1 1 4.19 0 1 0 0 0 4.36 0 1 0 0 1 4.50 0 1 0 1 0 4.64 0 1 0 1 1 4.81 0 1 1 0 0 4.95 0 1 1 0 1 5.09 0 1 1 1 0 5.26 0 1 1 1 1 5.40 1 0 0 0 0 5.54 1 0 0 0 1 5.71 1 0 0 1 0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.223October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 1 0 1 1 0 ‧‧‧‧‧ 1 1 1 1 1 Inhibit Inhibit Inhibit BTN[4:0]: Switch the output factor of DC/DC circuit for VSN voltage generation. The LCD drive voltage level VSN can be selected according to the characteristic of liquid crystal which panel used. While using PFM type-C or HX5186-A mode (PCCS1-0 = 10, PCCS1-0 = 11), VSN is followed the BTP[4:0] setting. PFM mode type-C : VSN = -VSP + 0.6V Using HX5186-A charge Pump mode : VSN = -VSP AP[2:0]: Adjust the amount of fixed current from the fixed current source for the operational amplifier in the power supply circuit. When the amount of fixed current is increased, the LCD driving capacity and the display quality are high, but the current consumption is increased. This is a tradeoff, Adjust the fixed current by considering both the display quality and the current consumption. During no display operation, when AP[2:0] = 000, the current consumption can be reduced by stopping the operations of operational amplifier and step-up circuit. AP2 AP1 AP0 Constant Current of Operational Amplifier 0 0 0 Stop (inhibit) 0 0 1 0.5µA 0 1 0 1µA 0 1 1 1.5µA 1 0 0 2µA 1 0 1 2.5µA 1 1 0 3µA 1 1 1 3.5µA VRHP[7:0]: VSPR regulator output control setting for source data output driving. VRHP[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. VSPR 3.488 3.516 3.544 3.572 3.600 3.628 3.656 3.684 3.713 3.741 3.769 3.797 3.825 3.853 3.881 3.909 3.938 3.966 3.994 4.022 4.050 4.078 4.106 4.134 4.163 4.191 4.219 4.247 4.275 4.303 4.331 4.359 4.388 -P.224October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 00111011 ~ 01111110 1 1 10000000 ~ 11111110 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 VRHN[7:0]: VSNR regulator output control setting for source data output driving. VRHN[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. 4.416 4.444 4.472 4.500 4.528 4.556 4.584 4.613 4.641 4.669 4.697 4.725 4.753 4.781 4.809 4.838 4.866 4.894 4.922 4.950 4.978 5.006 5.034 5.063 5.091 5.119 Inhibit VSP Inhibit HZ VSNR -3.263 -3.291 -3.319 -3.347 -3.375 -3.403 -3.431 -3.459 -3.488 -3.516 -3.544 -3.572 -3.600 -3.628 -3.656 -3.684 -3.713 -3.741 -3.769 -3.797 -3.825 -3.853 -3.881 -3.909 -3.938 -3.966 -3.994 -4.022 -4.050 -4.078 -4.106 -P.225October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 01000011 ~ 01111110 1 1 10000000 ~ 11111110 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 -4.134 -4.163 -4.191 -4.219 -4.247 -4.275 -4.303 -4.331 -4.359 -4.388 -4.416 -4.444 -4.472 -4.500 -4.528 -4.556 -4.584 -4.613 -4.641 -4.669 -4.697 -4.725 -4.753 -4.781 -4.809 -4.838 -4.866 -4.894 -4.922 -4.950 -4.978 -5.006 -5.034 -5.063 -5.091 -5.119 Inhibit VSN Inhibit HZ VRMP[5:0]: The positive polarity gamma amplitude voltage setting (VSPR-VGSP). VRMP[5:0] VSPR-VGSP 0 0 0 0 0 0 2.588 0 0 0 0 0 1 2.644 0 0 0 0 1 0 2.700 0 0 0 0 1 1 2.756 0 0 0 1 0 0 2.813 0 0 0 1 0 1 2.869 0 0 0 1 1 0 2.925 0 0 0 1 1 1 2.981 0 0 1 0 0 0 3.038 0 0 1 0 0 1 3.094 0 0 1 0 1 0 3.150 0 0 1 0 1 1 3.206 0 0 1 1 0 0 3.263 0 0 1 1 0 1 3.319 0 0 1 1 1 0 3.375 0 0 1 1 1 1 3.431 0 1 0 0 0 0 3.488 0 1 0 0 0 1 3.544 0 1 0 0 1 0 3.600 0 1 0 0 1 1 3.656 0 1 0 1 0 0 3.713 0 1 0 1 0 1 3.769 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.226October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 ‧‧‧‧‧ 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 3.825 3.881 3.938 3.994 4.050 4.106 4.163 4.219 4.275 4.331 4.388 4.444 4.500 4.556 4.613 4.669 4.725 4.781 4.838 4.894 4.950 5.006 5.063 5.119 Inhibit Inhibit Inhibit VSPR(VGSP=VSSA) VRMN[5:0]: The negitive polarity gamma amplitude voltage setting (VSNR-VGSN). VRMN[5:0] VSNR-VGSN 0 0 0 0 0 0 -2.588 0 0 0 0 0 1 -2.644 0 0 0 0 1 0 -2.700 0 0 0 0 1 1 -2.756 0 0 0 1 0 0 -2.813 0 0 0 1 0 1 -2.869 0 0 0 1 1 0 -2.925 0 0 0 1 1 1 -2.981 0 0 1 0 0 0 -3.038 0 0 1 0 0 1 -3.094 0 0 1 0 1 0 -3.150 0 0 1 0 1 1 -3.206 0 0 1 1 0 0 -3.263 0 0 1 1 0 1 -3.319 0 0 1 1 1 0 -3.375 0 0 1 1 1 1 -3.431 0 1 0 0 0 0 -3.488 0 1 0 0 0 1 -3.544 0 1 0 0 1 0 -3.600 0 1 0 0 1 1 -3.656 0 1 0 1 0 0 -3.713 0 1 0 1 0 1 -3.769 0 1 0 1 1 0 -3.825 0 1 0 1 1 1 -3.881 0 1 1 0 0 0 -3.938 0 1 1 0 0 1 -3.994 0 1 1 0 1 0 -4.050 0 1 1 0 1 1 -4.106 0 1 1 1 0 0 -4.163 0 1 1 1 0 1 -4.219 0 1 1 1 1 0 -4.275 0 1 1 1 1 1 -4.331 1 0 0 0 0 0 -4.388 1 0 0 0 0 1 -4.444 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.227October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 ‧‧‧‧‧ 1 1 1 1 VBS[2:0]: Set the VBIAS level. VBS2 VBS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 VBS0 0 1 0 1 0 1 0 1 -4.500 -4.556 -4.613 -4.669 -4.725 -4.781 -4.838 -4.894 -4.950 -5.006 -5.063 -5.119 Inhibit Inhibit Inhibit VSNR(VGSN=VSSA) VBIAS Inhibit 4.68 4.50 4.32 4.14 3.96 3.78 3.60 DC86_DIV[3:0]: Frequency for Charge Pump Mode (HX5186-A) DC86_DIV[3:0] Frequency - Charge Pump Mode (HX5186-A) 0000 Fosc/2 0001 Fosc/4 0010 Fosc/8 0011 Fosc/16 0100 Fosc/24 0101 Fosc/32 0110 Fosc/40 0111 Fosc/48 1000 Fosc/56 1001 Fosc/64 1010 Fosc/72 1011 Fosc/80 1100 Fosc/88 1101 Fosc/96 1110 Fosc/104 1111 Fosc/112 XDK[1:0]: Setting HX5186-A XDK[1] 0 0 1 1 XDK[0] 0 1 0 1 HX5186-A or Internal-Charge Pump X1.5 Pump x2 Pump X3 Pump Inhibited AUTO_XDK: Auto XDK function enable, when using HX5186-A. Auto_XDK=1 VDD3 x 1.5 > VSPtarget VDD3 x 2 > VSPtarget VDD3 x 2 < VSPtarget Auto_XDK=0 Hx5186-A X1.5 X2 X3 Depend on XDK[2:0] DD_TU: In-house function, and not open. VPNL_EN: Enable VPNL function. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.228October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Restriction Register Availability Default SETEXTC turn on to enable this command. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes Status Default value OTP value Power On Sequence FS1[2:0], AP[2:0], BT[3:0], S/W Reset DT[1:0], DCDIV[3:0], VBIAS_EN=0, VSN_EN=0, H/W Reset BTP[4:0], BTN[4:0], VSP_EN=0, VRHP[7:0], VRHN[7:0], VGL_EN=0, VGH_EN=0, LVGL_EN=0, VRMP[5:0], VRMN[5:0], VDDDN_HZ=0, STB=1, DSTB=0, DD_TU, VPNL_EN, FS1[2:0]=011, AP[2:0]=100, VBS[2:0], DC86_DIV[3:0], BT[3:0]=111, DT[1:0] =00, XDK1, XDK0, AUTO_XDK, DCDIV[3:0]=0000, BTP[4:0]=01110, DTPS[2:0], DTNS[2:0], BTN[4:0]=01110, VRHP[7:0]=0x21h, A_DC[1:0], A_DTP[2:0], VRHN[7:0]=0x29h, VRMP[5:0]=0x19h, A_DTN[2:0]. VRMN[5:0]=0x19h, B_DC[1:0], B_DTP[2:0], DD_TU= 0, VPNL_EN=0, B_DTN[2:0], VBS[2:0]=111, DC86_DIV[3:0]=0111, C_DC[1:0], C_DTP[2:0], XDK1=0, XDK0=1, AUTO_XDK=0, C_DTN[2:0], DTPS[2:0]=000, DTNS[2:0]=001, D_DC[1:0], D_DTP[2:0], A_DC[1:0]=11, A_DTP[2:0]=100, D_DTN[2:0], A_DTN[2:0]=110, E_DC[1:0], E_DTP[2:0], B_DC[1:0]=11, B_DTP[2:0]=100, E_DTN[2:0], B_DTN[2:0]=110, C_DC[1:0]=11, C_DTP[2:0]=100, C_DTN[2:0]=110, D_DC[1:0]=11, D_DTP[2:0]=100, D_DTN[2:0]=110, E_DC[1:0]=11, E_DTP[2:0]=100, E_DTN[2:0]=110, Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.229October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.56 SETDISP: Set display related register (B2h) B2H SETDISP( Set display related register) DNC NRD NWR D15~D8 D7 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - 1 - 0 - Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter th 5 parameter th 6 parameter th 7 parameter th 8 parameter th 9 parameter th 10 parameter th 11 parameter th 12 parameter th 13 parameter th 14 parameter th 15 parameter - - - D5 D4 D3 1 1 0 RES_SEL[2:0] RM BP [7:0] FP [7:0] SAP[3:0] GEN_ON[7:0] GEN_OFF[7:0] RTN[7:0] TEP[7:0] BP_PE[7:0] FP_PE[7:0] RTN_PE[7:0] - - - - D2 D1 D0 HEX 0 DFR 1 0 B2 - - D[1:0] DM[1:0] - TEI[3:0] - TEP[9:8] - - GON This command is used to set display related register D1–0: HX8369-A00 Internal Display Operations D1 D0 Source Output 0 0 VSSD Halt 0 1 Inhibit Inhibit 1 0 V255 Operate 1 1 Display Operate RES_SEL[2:0]: Resolution selection. RES_SEL 2 RES_SEL 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Description RES_SEL 0 0 1 0 1 0 1 0 1 Resolution 480RGBX864 480RGBX854 480RGBX800 480RGBX640 360 RGBX640 480RGBX720 Setting disable Setting disable DFR The bit is used in the Frame Memory access and Display operation. In-house function and not open. RM The bit is used to select an interface for the Frame Memory access operation. The Frame Memory is accessed only via the interface defined by RM bit. Because the interface can be selected separately from display operation mode, writing data to the Frame Memory is possible via system interface when RM = 0, even in the DPI display operation. RM setting is enabled from the next frame. Wait 1 frame to transfer data after setting. RM Interface for RAM Access 0 DBI Interface (CPU) 1 DPI Interface (RGB) DM[1:0] The bit is used to select display operation mode. The setting allows switching between display operation in synchronization with internal oscillation clock, VSYNC, or DPI signal (VSYNC+HSYNC). Note that switching between VSYNC and DPI operation is prohibited. DM 1 DM 0 Display Mode Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.230October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 0 1 DPI signal (VSYNC+HSYNC) 1 0 VSYNC signal 1 1 RGB data bypass GRAM mode FP[7:0]: Specify the amount of scan line for front porch (FP). BP[7:0] : Specify the amount of scan line for back porch(BP). FP_PE[7:0]: Specify the amount of scan line for front porch (FP) on partial idle mode. BP_PE[7:0] : Specify the amount of scan line for back porch(BP) on partial idle mode. FP[7:0] / FP_PE[7:0] Number of FP Line BP[7:0] / BP_PE[7:0] 8h’00 8h’01 8h’02 8h’03 8h’04 8h’05 ‧‧‧ 8h’FB 8h’FC 8h’FD 8h’FE 8h’FF Number of BP Line Inhibited 3 lines 4 lines 5 lines 6 lines 7 lines ‧‧‧ 253 lines 254 lines 255 lines 256 lines 257 lines SAP3 0 0 0 0 0 0 0 0 SAP2 0 0 0 0 1 1 1 1 SAP1 0 0 1 1 0 0 1 1 1 1 1 SAP0 0 1 0 1 0 1 0 1 Fixed Current of Operational Amplifier 0.5u 1u 1.5u 2u 2.5u 3u 3.5u 4u ‧‧‧‧‧‧‧‧‧‧‧‧ 1 8u GEN_ON[7:0]: Gamma OP turned on timing and in-house function not open. GEN_OFF[7:0]: Gamma OP turned off timing and in-house function not open. RTN[7:0]: A cycle time of line width, in-house function not open. RTN_PE[7:0]: A cycle time of line width on partial idle mode, in-house function not open. RTN[7:0]/ RTN_PE[7:0] 8h’00 8h’01 8h’02 8h’03 ‧‧‧ 8’hFD 8’hFE 8’hFF Clock per Line 275 clocks (275 + 1x2) 277 clocks (275 + 2x2) 279 clocks (275 + 3x2) 281 clocks ‧‧‧ (275 + 253x2) 781 clocks (275 + 254x2) 783 clocks (275 + 255x2) 785 clocks TEI[3:0]: Sets the output interval of TE signal according to the display data rewrite cycle and data transfer rate. TEI3 TEI2 TEI1 TEI0 Output Interval 0 0 0 0 1 frame 0 0 0 1 2 frames 0 0 1 0 3 frames Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.231October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver 1 1 ‧‧‧‧‧‧‧ 1 1 1 1 0 1 DATA SHEET V02 ‧‧ 15 frames 16 frames TEP[9:0]: Sets the output position of frame cycle signal. TE can be used as the trigger signal for frame synchronous write operation. Make sure the setting restriction 9’h000 ≤ TEP[9:0] ≤ BP+Number of Line +FP. TEP[9:0] Output position 10’h000 0th line 10’h001 1st line 10’h002 2nd line 10’h003 3rd line ‧‧‧ ‧‧‧ 10’h35D 861th line 10’h35E 862th line 10’h35F 863th line GON: Controlling the GIP signals On/Off register. GON =1, the GIP signals are On for normal operation. GON =0, the GIP signals are OFF and set as GND. Restrictions Register Availability SETEXTC turn on to enable this command Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Status Power On Sequence S/W Reset H/W Reset Default Default value D[1:0]=00, RES_SEL[2:0]=001, RM=0, DFR=0, DM[1:0]=00 BP[7:0]=0x03h, FP[7:0]=0x03h, SAP[3:0]=0111, GEN_ON=0x00h, GEN_OFF=0xFFh, RTN[7:0]=0x00h, TEI[3:0] =0000,TEP[9:0] =0x000h, BP_PE[7:0]=0x03h, FP_PE[7:0]=0x03h, RTN_PE[7:0]=0x00h, GON=1 Availability Yes Yes Yes Yes OTP value RES_SEL[2:0], RM, DFR, DM[1:0] BP[7:0], FP[7:0], SAP[3:0], GEN_ON, GEN_OFF, RTN[7:0], TEI[3:0], TEP[9:0], BP_PE[7:0], FP_PE[7:0], RTN_PE[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.232October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.57 SETRGBIF: Set RGB interface related register (B3h) B3H Command st 1 parameter SETRGBIF( Set RGB interface related register) DNC 0 1 NRD 1 1 NWR ↑ ↑ D15~D8 - D7 1 - D6 0 - D5 1 - D4 1 - D3 0 DPL D2 0 HSPL D1 1 VSPL D0 1 EPL HEX B3 - This command is used to set RGB interface related register. EPL: Specify the polarity of DE pin in RGB interface mode. EPL DE pin Display 0 0 Enable 0 1 Disable 1 0 Disable 1 1 Enable Description VSPL: The polarity of VS pin. When VSPL=0, the VS pin is Low active. When VSPL=1, the VS pin is High active. HSPL: The polarity of HS pin. When HSPL=0, the HS pin is Low active. When HSPL=1, the HS pin is High active. DPL: The polarity of PCLK pin. When DPL=0, the data is read on the rising edge of PCLK signal. When DPL=1, the data is read on the falling edge of PCLK signal. Restrictions SETEXTC turn on to enable this command. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Availability Yes Yes Yes Yes Default value OTP value Default Status Power On Sequence S/W Reset H/W Reset DPL=0,HSPL=0,VSPL=0,EPL=1 DPL,HSPL,VSPL,EPL Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.233October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.58 SETCYC: Set display waveform cycle (B4h) B4H Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter th 5 parameter SETCYC( Set display waveform cycles) DNC 0 1 1 1 1 1 NRD 1 1 1 1 1 1 NWR ↑ ↑ ↑ ↑ ↑ ↑ D15~D8 - D7 1 - D6 0 - D5 1 - D4 D3 D2 0 0 1 NW_PE[1:0] SON[7:0] SOFF[7:0] EQS[7:0] EQON[7:0] D1 D0 0 0 NW[1:0] HEX B4 - This command is used to get setting of display waveform cycles. NW[1:0]: Inversion type setting. NW1 NW0 0 0 0 1 1 0 1 1 Inversion type Column inversion 1-dot inversion 2-dot inversion Zig-zag inversion NW_PE[1:0]: Inversion type setting on partial idle mode. NW_PE1 NW_PE0 Inversion type 0 0 Column inversion 0 1 1-dot inversion 1 0 2-dot inversion 1 1 Zig-zag inversion Description SON[7:0]: Specify the valid source output start time. SON [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 Source output start time Inhibit 1 OSC clock cycle 2 OSC clock cycle 3 OSC clock cycle 4 OSC clock cycle Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.234October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ‧‧‧‧‧ 0 1 ‧‧‧‧‧ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 SOFF[7:0]: Specify the valid source output end time. SOFF [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 ‧‧‧‧‧ 1 0 0 0 0 0 1 ‧‧‧‧‧ 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 1 0 1 0 1 EQON[7:0]: Specify the valid Equalize output start time. (Please note that the EQON[7:0] ≤ EQS[7:0]-1) EQON [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 ‧‧‧‧‧ 0 0 0 0 1 1 0 0 ‧‧‧‧‧ 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 DATA SHEET V02 ‧‧‧‧‧ 15 OSC clock cycle ‧‧‧‧‧ 250 OSC clock cycle 251 OSC clock cycle 252 OSC clock cycle 253 OSC clock cycle 254 OSC clock cycle 255 OSC clock cycle Source output end time Inhibit 1 OSC clock cycle 2 OSC clock cycle 3 OSC clock cycle 4 OSC clock cycle ‧‧‧‧‧ 130 OSC clock cycle ‧‧‧‧‧ 250 OSC clock cycle 251 OSC clock cycle 252 OSC clock cycle 253 OSC clock cycle 254 OSC clock cycle 255 OSC clock cycle Gate output start time Inhibit 1 OSC clock cycle 2 OSC clock cycle 3 OSC clock cycle 4 OSC clock cycle ‧‧‧‧‧ 12 OSC clock cycle ‧‧‧‧‧ 250 OSC clock cycle 251 OSC clock cycle 252 OSC clock cycle 253 OSC clock cycle 254 OSC clock cycle 255 OSC clock cycle EQS[7:0]: Specify the Equalize time of source output. (Please note that the EQS[7:0] ≤ SON-1). EQS [7:0] Equalize time of source output 0 0 0 0 0 0 0 0 Equalize function off 0 0 0 0 0 0 0 1 1 OSC clock cycle 0 0 0 0 0 0 1 0 2 OSC clock cycle 0 0 0 0 0 0 1 1 3 OSC clock cycle 0 0 0 0 0 1 0 0 4 OSC clock cycle 0 0 0 0 0 1 0 1 5 OSC clock cycle 0 0 0 0 0 1 1 0 6 OSC clock cycle ‧‧‧‧‧ ‧‧‧‧‧ 1 1 1 1 1 0 1 0 250 OSC clock cycle 1 1 1 1 1 0 1 1 251 OSC clock cycle Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.235October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver Restrictions Register Availability 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Status Default Power On Sequence S/W Reset H/W Reset 0 0 1 1 0 1 0 1 Default value NW_PE[1:0]=00,NW[1:0]=00, SON[7:0]=0x0Fh,SOFF[7:0]=0x82h, EQS[7:0]=0x0Ch, EQON[7:0]=0x03h DATA SHEET V02 252 OSC clock cycle 253 OSC clock cycle 254 OSC clock cycle 255 OSC clock cycle Availability Yes Yes Yes Yes Yes OTP value NW_PE[1:0], NW[1:0], SON[7:0], SOFF[7:0], EQS[7:0], EQON[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.236October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.59 SETVCOM: Set VCOM voltage (B6h) B6 H Command st 1 parameter nd 2 parameter SETVCOM ( Set VCOM Voltage) DNC 0 1 1 NRD 1 1 1 NWR ↑ ↑ ↑ D15~D8 - D7 1 D6 0 D5 1 D4 D3 1 0 VCMC_F[7:0] VCMC_B[7:0] D2 1 D1 1 D0 0 HEX B6 - This command is used to set VCOM Voltage include VCOM Low and VCOM High Voltage. VCMC_F[7:0]: DC VCOM voltage setting for forward scan. VCMC_B[7:0]: DC VCOM voltage setting for backward scan. VCMC_F[7:0] / VCMC_B[7:0] Description D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. VCOM (V) -2 -1.984 -1.968 -1.952 -1.936 -1.92 -1.904 -1.888 -1.872 -1.856 -1.84 -1.824 -1.808 -1.792 -1.776 -1.76 -1.744 -1.728 -1.712 -1.696 -1.68 -1.664 -1.648 -1.632 -1.616 -1.6 -1.584 -1.568 -1.552 -1.536 -1.52 -1.504 -1.488 -1.472 -1.456 -1.44 -1.424 -1.408 -1.392 -1.376 -1.36 -1.344 -1.328 -1.312 -1.296 -P.237October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DATA SHEET V02 -1.28 -1.264 -1.248 -1.232 -1.216 -1.2 -1.184 -1.168 -1.152 -1.136 -1.12 -1.104 -1.088 -1.072 -1.056 -1.04 -1.024 -1.008 -0.992 -0.976 -0.96 -0.944 -0.928 -0.912 -0.896 -0.88 -0.864 -0.848 -0.832 -0.816 -0.8 -0.784 -0.768 -0.752 -0.736 -0.72 -0.704 -0.688 -0.672 -0.656 -0.64 -0.624 -0.608 -0.592 -0.576 -0.56 -0.544 -0.528 -0.512 -0.496 -0.48 -0.464 -0.448 -0.432 -0.416 -0.4 -0.384 -0.368 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.238October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver Restrictions Register Availability Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 01111101 ~ 01111101 1 1 1 1 1 1 10000000 ~ 11111110 1 1 1 SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Status Power On Sequence S/W Reset H/W Reset Default value VCMC_F[7:0]=0x5Eh, VCMC_B[7:0]=0x5Eh 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 DATA SHEET V02 -0.352 -0.336 -0.32 -0.304 -0.288 -0.272 -0.256 -0.24 -0.224 -0.208 -0.192 -0.176 -0.16 -0.144 -0.128 -0.112 -0.096 -0.08 -0.064 -0.048 -0.032 -0.016 Inhibit VCOMR VSSA Inhibit HZ Availability Yes Yes Yes Yes Yes OTP value VCMC_F[7:0], VCMC_B[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.239October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.60 SETEXTC: Set extension command (B9h) B9H Command st 1 parameter nd 2 parameter rd 3 parameter SETEXTC ( Set extended command set) DNC 0 1 1 1 NRD 1 1 1 1 NWR ↑ ↑ ↑ ↑ D15~D8 - D7 1 D6 0 D5 1 D4 D3 1 1 EXTC1[7:0](FFh) EXTC2[7:0](83h) EXTC3[7:0](69h) D2 0 D1 0 D0 1 HEX B9 - This command is used to set extended command set access enable. Extend cmd Description Enable Disable(default) Restrictions Command description After command (B0h), must write 3 parameters (ffh,83h,69h) by order After command(B0h), write 3 parameters (xxh,xxh,xxh) any value is all right, but can not be (ffh,83h,69h) - Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off Default Status Power On Sequence S/W Reset H/W Reset Default value EXTC1[7:0]=0x00h, EXTC2[7:0]=0x00h, EXTC3[7:0]=0x00h, Availability Yes Yes Yes Yes Yes OTP value N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.240October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.61 SETOTP: Set OTP (BBh) BBH Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter th 5 parameter Description Restrictions Register Availability SETOTP( Set OTP Related Setting) DNC NRD NWR D15-D8 0 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ - 1 1 ↑ - D6 0 D5 1 - - - OTP_LOAD_ DISABLE OTP_TEST D4 D3 D2 1 1 0 OTP_MASK[7:0] (8'b0) OTP_INDEX[7:0] OTP_POR OTP_PWE OTP_PTM[1:0] D1 1 D0 1 - OTP_INDEX[8] VPP_SEL OTP_PROG HEX BB - OTP_DATA[7:0] - This command is used to set OTP Related Setting. OTP_MASK[7:0]: Bit programming mask, if 1, means this bit can’t be programmed. OTP_INDEX[8:0]: Set index of OTP table for programming. OTP_PWE: OTP program write enable, if 1, means OTP is able to be programmed. OTP_PROG: When set to 1, the register content of OTP index is programmed. OTP_LOAD_DISABLE: Normally the internal registers are auto-loaded from OTP when the SLPOUT command is received. Nevertheless, if this bit is set to 1, it will disable the auto loading function when the SLPOUT command was received. In general, this bit is used when OTP is not yet programmed. OTP_PTM[1:0]: Not open, internal use. VPP_SEL: When written to 1, VPP voltage is fed to OTP OTP_DATA[7:0]: Read back the OTP index data. SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default D7 1 Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default value OTP_MASK[7:0]=0x00h, OTP_INDEX[8:0]=0x1FFh, OTP_LOAD_ DISABLE=0, OTP_TEST=0, OTP_POR=0, OTP_PWE=0, OTP_PTM[1:0]=00, VPP_SEL=0, OTP_PROG=0, OTP_DATA[7:0]=xxh OTP value N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.241October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.62 SETDGCLUT: Set DGC LUT (C1h) C1H Command st 1 parameter nd 2 parameter : th 127 parameter SETDGCLUT ( Set DGC LUT) DNC 0 1 1 1 1 NRD 1 1 1 1 1 NWR ↑ ↑ ↑ ↑ ↑ D15-D8 - D7 1 - D6 1 - D5 0 - D4 0 - D4 R006 R016 R026 : : R316 R326 R010 R050 : : R290 0 G006 G016 G026 : : G316 G326 G010 G050 : : G290 0 B006 B016 B026 : : B316 B326 B010 B050 : : B290 0 D3 R005 R015 R025 : : R315 R325 R021 R061 : : R301 0 G005 G015 G025 : : G315 G325 G021 G061 : : G301 0 B005 B015 B025 : : B315 B325 B021 B061 : : B301 0 D3 D2 0 0 D1[7:0] Dn[7:0] D126[7:0] D1 0 DITH_OPT D0 1 DGC_EN HEX C1 - This command is used to set DGC LUT. DITH_OPT: Not open, internal use. DGC_EN: Enable the DGC function D1[7:0] ~ D126[7:0]: LUT 1st 2nd 3rd : : 32rd 33rd 34th 35th : : 41st 42nd 43rd 44th 45th : : 74th 75th 76th 77th : : 83rd 84th 85th 86th 87th : : 116th 117th 118th 119th : : 125th 126th Description D7 R009 R019 R029 : : R319 R329 R001 R041 : : R281 R321 G009 G019 G029 : : G319 G329 G001 G041 : : G281 G321 B009 B019 B029 : : B319 B329 B001 B041 : : B281 B321 D6 R008 R018 R028 : : R318 R328 R000 R040 : : R280 R320 G008 G018 G028 : : G318 G328 G000 G040 : : G280 G320 B008 B018 B028 : : B318 B328 B000 B040 : : B280 B320 D5 R007 R017 R027 : : R317 R327 R011 R051 : : R291 0 G007 G017 G027 : : G317 G327 G011 G051 : : G291 0 B007 B017 B027 : : B317 B327 B011 B051 : : B291 0 D2 R004 R014 R024 : : R314 R324 R020 R060 : : R300 0 G004 G014 G024 : : G314 G324 G020 G060 : : G300 0 B004 B014 B024 : : B314 B324 B020 B060 : : B300 0 D1 R003 R013 R023 : : R313 R323 R031 R071 : : R311 0 G003 G013 G023 : : G313 G323 G031 G071 : : G311 0 B003 B013 B023 : : B313 B323 B031 B071 : : B311 0 D0 R002 R012 R022 : : R312 R322 R030 R070 : : R310 0 G002 G012 G022 : : G312 G322 G030 G070 : : G310 0 B002 B012 B022 : : B312 B322 B030 B070 : : B310 0 Default 00h 08h 10h : : F8h FFh 00h 00h : : 00h 00h 00h 08h 10h : : F8h FFh 00h 00h : : 00h 00h 00h 08h 10h : : F8h FFh 00h 00h : : 00h 00h Write D1[7:0] (R 1st), D43[7:0] (G 1st) and D85[7:0] (B 1st), but Read is from D1[7:0], D2[7:0] and D3[7:0] Restrictions Register Availability SETEXTC turn on to enable this command. Status Idle Mode Off, Sleep Out Idle Mode On, Sleep Out Sleep In or Booster Off Availability Yes Yes Yes Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.242October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Status Default Power On Sequence S/W Reset H/W Reset Default value DITH_OPT DGC_EN D1[7:0]~D126[7:0] OTP value DITH_OPT DGC_EN D1[7:0]~D126[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.243October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.63 SETID: Set ID (C3h) C3H Command st 1 parameter nd 2 parameter rd 3 parameter Description Restrictions SETID ( Set ID) DNC 0 NRD 1 NWR ↑ D15-D8 - 1 1 ↑ - 1 1 ↑ - 1 1 ↑ - D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 0 1 1 ID1[7:0] 0 ID2[6:0] ID3[7:0] HEX C3 - This command is used to set ID (RDAh, RDBh, RDCh) value. SETEXTC turn on to enable this command. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes OTP value Default Status Power On Sequence S/W Reset H/W Reset Default value ID1[7:0]=0x00h, ID2[6:0]=0x00h, ID3[7:0]=0x00h, ID1[7:0], ID2[6:0], ID3[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.244October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.64 SETCABC: Set CABC Control (C9h) C9H SETCABC (Set CABC Control) DNC 0 NRD 1 NWR ↑ D15-D8 - D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 1 0 0 1 st 1 1 ↑ - - - EN_DI M_MI X EN_C OST_ MEAN EN_C OST EN_N LN_G AIN EN_J UDGE EN_T EMP nd 1 1 ↑ - CABC _DD rd 1 1 ↑ - 1 1 ↑ - Command 1 parameter 2 parameter 3 parameter th 4 parameter SAVEPOWER[6:0] - - - - MEAN_OFFSET[7:0] - HEX C9 CABC_FLM[3:0] INVP ULS SEL_ BLDU TY th 1 1 ↑ - th 1 1 ↑ - 1 1 ↑ - 1 1 ↑ - CABC_STEP[7:0] - 1 1 ↑ - CABC_CLKEN[7:0] - 5 parameter 6 parameter th 7 parameter th 8 parameter th 9 parameter - SEL_PWMCLK[2:0] SEL_GAIN[1:0] PWM_PERIOD[7:0] - - DIM_FRAME[6:0] - This command is used to set CABC function. INVPULS: The backlight PWM output polarity select. ‘0’, The backlight PWM output is low level active. ‘1’, The backlight PWM output is high level active. SEL_BLDUTY : The backlight PWM output duty on/off control when CABC operated. ‘0’, The backlight PWM output duty is 100%. ‘1’, The backlight PWM output duty is calculated from CABC operation. SEL_PWMCLK[2:0] : Internal PWM_CLK divider for CABC clock. 0 0 0 0 1 1 1 1 Description SEL_PWMCLK[2:0] 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Brightness Control Clock PWM_CLK / 1 PWM_CLK / 2 PWM_CLK / 4 PWM_CLK / 8 PWM_CLK / 16 PWM_CLK / 32 PWM_CLK / 64 PWM_CLK / 128 SEL_GAIN[1:0]: CABC gain select. Internal use and not Open. Please set to “11”. PWM_PERIOD[7:0] : The backlight PWM output period setting. Backlight PWM output period = 1 / (PWM_CLK / clock divider (SEL_PWMCLK[2:0] )) x (255x(PWM_PERIOD[7:0])). SAVEPOWER[6:0] : Minimum CABC gain / maximum CABC duty output select. To define the minimum gain or maximum duty of CABC block output. If not used, please set to”0000000”. CABC_DD: Internal use and not open. MEAN_OFFSET[7:0]: Internal use, not open. CABC_FLM[3:0]: CABC dimming frame number for each step. CABC_STEP[7:0]: Internal use and not open. CABC_CLKEN[7:0]: Internal use and not open. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.245October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 DIM_FRAME[6:0]: Manual brightness setting dimming period. EN_DIM_MIX: Internal use and not open. Please set to”1”. EN_COST_MAIN: Internal use and not open. Please set to”1”. EN_COST: Internal use and not open. Please set to”1”. EN_NLN_GAIN: Internal use and not open. Please set to”1”. EN_JUDGE: Internal use and not open. Please set to”1”. Restrictions Register Availability EN_TEMP: Internal use and not open. Please set to”0”. SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Default value EN_DIM_MIX =1, EN_COST_MEAN =1, EN_COST =1, EN_NLN_GAIN =1, EN_JUDGE =1, EN_TEMP =0, CABC_DD =0, SAVEPOWER[6:0] =0x00h MEAN_OFFSET[7:0] =0x00h CABC_FLM[3:0] = 0001, SEL_PWMCLK[2:0] =010, SEL_GAIN[1:0] =11, INVPULS =1, SEL_BLDUTY =1, PWM_PERIOD[7:0] =0x2Bh, DIM_FRAME[6:0] =0x1Eh, CABC_STEP[7:0] =0x1Eh, CABC_CLKEBN[7:0] =0x00h Availability Yes Yes Yes Yes Yes OTP value SEL_PWMCLK[2:0], SEL_GAIN[1:0], INVPULS, SEL_BLDUTY, PWM_PERIOD[7:0], DIM_FRAME[6:0], CABC_STEP[7:0], CABC_CLKEBN[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.246October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.65 SETPANEL (CCh) CCH Command st 1 parameter SETPANEL( Set panel related register) DNC 0 NRD 1 1 1 NWR D15-D8 ↑ ↑ - D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0 HEX CC - - - - SS_PANEL - REV_PANEL BGR_PANEL - This command is used to set setting of panel related register and make panel module meets below spec from viewpoint of user Description0 Restrictions Register Availability Default BGR_PANEL: The order of <R><G><B> dot color for module supplier, default value is stored in OTP. If color filter of panel is <B><G><R> type, setting BGR_PANEL = 1, if color filter of panel is <R><G><B> type, setting BGR_PANEL = 0. This bit is to make panel module look like a <R><G><B> type panel form the user viewpoint. SS_PANEL: Specify the shift direction of source driver output. When SS_PANEL = 0, the shift direction from S1 to S1440 When SS_PANEL = 1, the shift direction from S1440 to S1. REV_PANEL: Select the inversion of the display of all characters and graphics. This setting allows the display of the same data on both normally-white and normally-black panels. REV_PANEL = 0 normal-white panel REV_PANEL = 1 normal-black panel SETEXTC turn on to enable this command Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Default value SS_PANEL=0, REV_PANE=1, BGR_PANEL=0 Availability Yes Yes Yes Yes Yes OTP value SS_PANEL, REV_PANE, BGR_PANEL Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.247October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.66 SETGIP (D5h) D5H Command st 1 parameter nd 2 parameter rd 3 parameter th 4 parameter th 5 parameter th 6 parameter th 7 parameter th 8 parameter th 9 parameter th 10 parameter th 11 parameter th 12 parameter th 13 parameter th 14 parameter th 15 parameter th 16 parameter th 17 parameter th 18 parameter th 19 parameter th 20 parameter th 21 parameter th 22 parameter th 23 parameter th 24 parameter th 25 parameter th 26 parameter SETGIP DNC NRD NWR D15-D8 D7 D6 D5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - 1 - 1 - 0 - - - - - D4 D3 1 0 SHR_0[7:0] SHR_1[7:0] SPD[7:0] CHR[7:0] CON[7:0] COFF[7:0] SHP[3:0] CHP[3:0] SOS_1[4:0] SOS_3[4:0] COS_1[4:0] COS_3[4:0] COS_5[4:0] COS_7[4:0] SOS_1_ML[3:0] SOS_3_ML[3:0] COS_1_ML[3:0] COS_3_ML[3:0] COS_5_ML[3:0] COS_7_ML[3:0] - D2 D1 1 0 SHR_0[11:8] SHR_1[11:8] SCP[3:0] CCP[3:0] SOS_0[3:0] SOS_2[3:0] COS_0[3:0] COS_2[3:0] COS_4[3:0] COS_6[3:0] SOS_0_ML[3:0] SOS_2_ML[3:0] COS_0_ML[3:0] COS_2_ML[3:0] COS_4_ML[3:0] COS_6_ML[3:0] GTO[5:0] GNO[7:0] EQ_DELAY[7:0] GIP_OPT[7:0] D0 HEX 1 D5 - This command is used for GIP timing output control. Description Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.248October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 STV0 SHP[3:0 ] STV1 SCP[3:0 1xHsync CK0 CHP[3:0 ] CK1 1xHsyn CK2 c CK3 CCP[3:0 ] SHR_0[11:0]:STV_0 Hsync Rise SHR_0[11:0] Start Pulse 0 Output delay 0x000h 0 x HSYNC 0x001h 1 x HSYNC 0x002h 2 x HSYNC 0x003h 3 x HSYNC 0x004h 4 x HSYNC 0x005h 5 x HSYNC ‧‧‧‧‧ 0xFFEh 4094 x HSYNC 0xFFFh 4095 x HSYNC SHR_1[11:0]:STV_1 Hsync Rise SHR_1[11:0] Start Pulse 1 Output delay 0x000h 0 x HSYNC 0x001h 1 x HSYNC 0x002h 2 x HSYNC 0x003h 3 x HSYNC 0x004h 4 x HSYNC 0x005h 5 x HSYNC ‧‧‧‧‧ 0xFFEh 4094 x HSYNC 0xFFFh 4095 x HSYNC SPD[7:0]: STV Pulse Delay SPD[7:0] Start Pulse Output delay 0x00h 0 x OSC CLK 0x01h 1 x OSC CLK 0x02h 2 x OSC CLK 0x03h 3 x OSC CLK 0x04h 4 x OSC CLK 0x05h 5 x OSC CLK ‧‧‧‧‧ 0xFEh 254 x OSC CLK 0xFFh 255 x OSC CLK Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.249October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 CHR[7:0]: CK Hsync Rise CHR[7:0] Start Pulse 1 Output delay 0x00h 0 x HSYNC 0x01h 1 x HSYNC 0x02h 2 x HSYNC 0x03h 3 x HSYNC 0x004h 4 x HSYNC 0x005h 5 x HSYNC ‧‧‧‧‧ 0xFEh 254 x HSYNC 0xFFh 255 x HSYNC CON[7:0]: CK Pulse Delay CON[7:0] CK Pulse Output delay 0x00h 0 x OSC CLK 0x01h 1 x OSC CLK 0x02h 2 x OSC CLK 0x03h 3 x OSC CLK 0x04h 4 x OSC CLK 0x05h 5 x OSC CLK ‧‧‧‧‧ 0xFEh 254 x OSC CLK 0xFFh 255 x OSC CLK Note: Avoid CON[7:0] OSC LCK width > 1-line width COFF[7:0]: CK Pulse width COFF[7:0] CK Pulse Output 0x00h Inhibit 0x01h 1 x OSC CLK 0x02h 2 x OSC CLK 0x03h 3 x OSC CLK 0x04h 4 x OSC CLK 0x05h 5 x OSC CLK ‧‧‧‧‧ 0xFEh 254 x OSC CLK 0xFFh 255 x OSC CLK Note: COFF[7:0] value must bigger than CON[7:0] value SHP[3:0]: Width of STV High pulse SHP3 SHP2 SHP1 SHP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 ‧‧‧‧‧ 1 1 1 0 1 1 1 1 15 x HSYNC 16 x HSYNC SCP[3:0]: A Cycle of STV pulse SCP3 SCP2 SCP1 SCP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 Start Pulse cycle 1 x HSYNC 2 x HSYNC 3 x HSYNC 4 x HSYNC 5 x HSYNC 6 x HSYNC Start Pulse Width 1 x HSYNC 2 x HSYNC 3 x HSYNC 4 x HSYNC 5 x HSYNC 6 x HSYNC Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.250October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 1 1 1 1 ‧‧‧‧‧ 1 0 1 1 CHP[3:0]: Width of CK High pulse CHP3 CHP2 CHP1 CHP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 ‧‧‧‧‧ 1 1 1 0 1 1 1 1 CCP[3:0]: A Cycle of CK pulse CCP3 CCP2 CCP1 CCP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 ‧‧‧‧‧ 1 1 1 0 1 1 1 1 15 x HSYNC 16 x HSYNC CK Pulse Width 1 x HSYNC 2 x HSYNC 3 x HSYNC 4 x HSYNC 5 x HSYNC 6 x HSYNC 15 x HSYNC 16 x HSYNC CK Pulse cycle 1 x HSYNC 2 x HSYNC 3 x HSYNC 4 x HSYNC 5 x HSYNC 6 x HSYNC 15 x HSYNC 16 x HSYNC SOS_0[3:0] for CGOUT9_L pulse selector SOS_1[3:0] for CGOUT10_L pulse selector SOS_2[3:0] for CGOUT9_R pulse selector SOS_3[3:0] for CGOUT10_R pulse selector SOS_0/1/2/3[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SOS_0/1/2/3[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SOS_0/1/2/3[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SOS_0/1/2/3[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Signal Type STV-0 STV-1 STV-2 STV-3 CK-0 CK-1 CK-2 CK-3 CK-4 CK-5 CK-6 CK-7 Inhibit Inhibit Inhibit Inhibit COS_0[3:0] for CGOUT5L pulse selector COS_1[3:0] for CGOUT6L pulse selector COS_2[3:0] for CGOUT7L pulse selector COS_3[3:0] for CGOUT8L pulse selector COS_4[3:0] for CGOUT5R pulse selector COS_5[3:0] for CGOUT6R pulse selector COS_6[3:0] for CGOUT7R pulse selector COS_7[3:0] for CGOUT8R pulse selector Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.251October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 COS_0-7[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 COS_0-7[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 COS_0-7[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 COS_0-7[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Signal Type STV-0 STV-1 STV-2 STV-3 CK-0 CK-1 CK-2 CK-3 CK-4 CK-5 CK-6 CK-7 Inhibit Inhibit Inhibit Inhibit Once the R36h ML=1 the STV gate control signals are refered to the below registers: SOS_0_ML[3:0] for CGOUT9_L pulse selector SOS_1_ML[3:0] for CGOUT10_L pulse selector SOS_2_ML[3:0] for CGOUT9_R pulse selector SOS_3_ML[3:0] for CGOUT10_R pulse selector SOS_0-3_ML[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SOS_0-3_ML[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SOS_0-3_ML[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SOS_0-3_ML[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Signal Type STV-0 STV-1 STV-2 STV-3 CK-0 CK-1 CK-2 CK-3 CK-4 CK-5 CK-6 CK-7 Inhibit Inhibit Inhibit Inhibit Once the R36h ML=1 the CK gate control signals are refered to the below registers: COS_0_ML[3:0] for CGOUT5L pulse selector COS_1_ML[3:0] for CGOUT6L pulse selector COS_2_ML[3:0] for CGOUT7L pulse selector COS_3_ML[3:0] for CGOUT8L pulse selector COS_4_ML[3:0] for CGOUT5R pulse selector COS_5_ML[3:0] for CGOUT6R pulse selector COS_6_ML[3:0] for CGOUT7R pulse selector COS_7_ML[3:0] for CGOUT8R pulse selector COS_0-7_ML[3] 0 0 0 0 0 COS_0-7_ML[2] 0 0 0 0 1 COS_0-7_ML[1] 0 0 1 1 0 COS_0-7_ML[0] 0 1 0 1 0 Signal Type STV-0 STV-1 STV-2 STV-3 CK-0 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.252October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver 0 0 0 1 1 1 1 1 1 1 1 GTO[5:0] 6’h00 6’h01 6’h02 6’h03 ‧‧‧‧‧ 6’h3D 6’h3E 6’h3F GNO[7:0] 8’h00 8’h01 8’h02 8’h03 ‧‧‧‧‧ 8’hFD 8’hFE 8’hFF 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 DATA SHEET V02 CK-1 CK-2 CK-3 CK-4 CK-5 CK-6 CK-7 Inhibit Inhibit Inhibit Inhibit GPWR toggle frequency 64 x Frame 1 x Frame 2 x Frame 3 x Frame ‧‧‧‧‧ 61 x Frame 62 x Frame 63 x Frame GPWR non-overlap timing 0 1 x OSC CLK 2 x OSC CLK 3 x OSC CLK ‧‧‧‧‧ 253 x OSC CLK 254 x OSC CLK 255 x OSC CLK EQ_DELAY[7:0] is in-house function not open. GIP_OPT[7:3] is in-hose function and not open. GIP_OPT[2] is stv_2_time, In order to meet 2 STV pulses for BP and FP separately. It is the function of controlling the STV-0 and STV-1 pulses in the begin of a frame, and controlling the STV-2 and STV-3 pulses in the end of a frame. The pulses STV-2 and STV-3 started in position are determined by SHR_1[11:0]. GIP_OPT[1] is stv_gated, CK will be off while STV on. GIP_OPT[0] is toggle_en, CK will toggle while porch duration. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.253October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Status Default Power On Sequence S/W Reset H/W Reset Default value SHR_0[11:0]= 0x02h SHR_1[11:0]= 0x01h SPD[7:0]= 0x02h CHR[7:0]= 0x03h CON[7:0]= 0x20h COFF[7:0]= 0x6Cg SCP[3:0]= 0x03h SHP[3:0]= 0x00h CCP[3:0]= 0x03h CHP[3:0]= 0x00h SOS_0[3:0]= 0x00h SOS_1[3:0]= 0x00h SOS_2[3:0]= 0x00h SOS_3[3:0]= 0x00h COS_0[3:0]= 0x00h COS_1[3:0]= 0x06h COS_2[3:0]= 0x04h COS_3[3:0]= 0x00h COS_4[3:0]= 0x01h COS_5[3:0]= 0x07h COS_6[3:0]= 0x05h COS_7[3:0]= 0x07h SOS_0_ML[3:0]= 0x00h SOS_1_ML[3:0]= 0x00h SOS_2_ML[3:0]= 0x00h SOS_3_ML[3:0]= 0x00h COS_0_ML[3:0]= 0x01h COS_1_ML[3:0]= 0x05h COS_2_ML[3:0]= 0x07h COS_3_ML[3:0]= 0x05h COS_4_ML[3:0]= 0x00h COS_5_ML[3:0]= 0x04h COS_6_ML[3:0]= 0x06h COS_7_ML[3:0]= 0x04h GTO[5:0]= 0x01h GNO[7:0]= 0x0Ch EQ_DELAY[7:0]= 0x0Ch GIP_OPT[7:0]= 0x00h OTP value SHR_0[11:0], SHR_1[11:0] SPD[7:0], CHR[7:0] CON[7:0], COFF[7:0] SCP[3:0], SHP[3:0] CCP[3:0], CHP[3:0] SOS_0[3:0], SOS_1[3:0] SOS_2[3:0], SOS_3[3:0] COS_0[3:0], COS_1[3:0] COS_2[3:0], COS_3[3:0] COS_4[3:0], COS_5[3:0] COS_6[3:0], COS_7[3:0] SOS_0_ML[3:0] SOS_1_ML[3:0] SOS_2_ML[3:0] SOS_3_ML[3:0] COS_0_ML[3:0] COS_1_ML[3:0] COS_2_ML[3:0] COS_3_ML[3:0] COS_4_ML[3:0] COS_5_ML[3:0] COS_6_ML[3:0] COS_7_ML[3:0] GTO[5:0], GNO[7:0] EQ_DELAY[7:0] GIP_OPT[7:0] Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.254October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.67 SETTPSNR (D8h) D8H SETTPSNR (Set the Temp Senor control) DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ - 1 1 0 1 0 1 0 1 st 1 1 ↑ - - - - nd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - - D5 (read only) - 1 parameter 2 parameter rd 3 parameter th 4 parameter th 5 parameter th 6 parameter th 7 parameter th 8 parameter th 9 parameter th 10 parameter BT_P2[3:0] BT_P4[3:0] TS_G[2:0] TS_OS1[4:3] TS_OS1[2:0] PORE RER[1:0] TF_ON TSON TSRAW[4:0] TS_OS2[4:0] BT_P1[3:0] BT_P3[3:0] D0[4:0] I0[4:0] D1[4:0] I1[4:0] D2[4:0] I2[4:0] This command is used for the temperature senor control. TSON : Temp. sensor on/off function. 1 = On 0 = Off (default); VGH level is controlled by only BT_P1[1:0] TF_ ON : Median filter on/off function. 1 = On (default) 0 = Off Description Temp. sensor variation = Under +/- 3 degree TSRAW[4:0] Temp.(℃) 00000 -18.55 ~ -20.00 00001 -15.65 ~ -18.55 00010 -12.74 ~ -15.65 00011 -9.84 ~ -12.74 00100 -6.94 ~ -9.84 00101 -4.03 ~ -6.94 00110 -1.13 ~ -4.03 00111 1.77 ~ -1.13 01000 4.68 ~ 1.77 01001 7.58 ~ 4.68 01010 10.48 ~ 7.58 01011 13.39 ~ 10.48 01100 16.29 ~ 13.39 01101 19.19 ~ 16.29 01110 22.10 ~ 19.19 01111 25.00 ~ 22.10 Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.255October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 27.90 ~ 25.00 30.81 ~ 27.90 33.71 ~ 30.81 36.61 ~ 33.71 39.52 ~ 36.61 42.42 ~ 39.52 45.32 ~ 42.42 48.23 ~ 45.32 51.13 ~ 48.23 54.03 ~ 51.13 56.93 ~ 54.03 59.84 ~ 56.93 62.74 ~ 59.84 65.64 ~ 62.74 68.55 ~ 65.64 70.00 ~ 68.55 TS_G[2:0] : Gain control of Temp sensor output. TS_G[2:0] 000 001 010 011 100 101 110 111 Gain Range 0.8125 0.8750 0.9375 1 1.0625 1.1250 1.1875 1.2500 (step=0.0625) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.256October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 TS_OS1[4:0] & TS_OS2 [4:0]: Offset control of Temp sensor output TSRAW[4:0] 11111 00000 -20 70 TS_OS1[4:0] / TS_OS2[4:0] 00000 00001 00010 00011 ….. 10010 ….. 11100 11101 11110 11111 Temp. Temp.(℃) -54 -51 -48 -45 .. 0 .. 30 33 36 39 RER[1:0] : Refresh rate of TSRAW[4:0] RER[1:0] 00 01 10 11 Refresh Rate Every 4 vsync Every 6 vsync Every 60 vsync Setting disabled VSYNC TSRAW[3:0] TSRAW1[3:0] S864 TSRAW2[3:0] Porch S1 PORE: The point of refresh rate PORE 0 1 Description Start of vertical porch End of vertical porch Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.257October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 BT : VGH pumping control VGH 4- step x7 Phase 1 Phase 2 x6 Phase 3 x5 Phase 4 x4 I1[4:0] I0[4:0] * I2[4:0] D0[4:0] D1[4:0] D2[4:0] 10 25 40 Temp Sensor Output TSRAW[4:0] I0~2 & D0~2 is needed for hysterisis BT_P1[3:0] : VGH control at Phase 1 BT_P2[3:0] : VGH control at Phase 2 BT_P3[3:0] : VGH control at Phase 3 BT_P4[3:0] : VGH control at Phase 4 BT_P1[3:0]/ BT_P2[3:0]/ BT_P3[3:0]/ BT_P4[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VGH VGL 2*(VSP-VSN) 2*(VSP-VSN) 2*(VSP-VSN) (VSP-VSN)+(VDD3-VSN) (VSP-VSN)+(VDD3-VSN) (VSP-VSN)+(VDD3-VSN) (VSP-VSN)+(VSP-VSSD) (VSP-VSN)+(VSP-VSSD) (VSP-VSN)+(VSP-VSSD) (VDD3-VSN)+(VSP-VSSD) (VDD3-VSN)+(VSP-VSSD) (VDD3-VSN)+(VSP-VSSD) (VSP-VSN) (VSP-VSN) (VSP-VSN) 2*(VSP-VSSD) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) VDDDN-1*(VSP-VSN) -1*(VSP-VSN) VDD3-1*(VSP-VSN) -2*(VSP-VSSD) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.258October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 I0 [4:0] : Set the lower boundary of the phase 1, 2 D0 [4:0] : Set the higher boundary of the phase 1, 2 I1 [4:0] : Set the lower boundary of the phase 2, 3 D1 [4:0] : Set the higher boundary of the phase 2, 3 I2 [4:0] : Set the lower boundary of the phase 3, 4 D2 [4:0] : Set the higher boundary of the phase 3, 4 Boundary of the phase: Temp.(℃) -20 -17 -14 -11 -8 --------64 67 70 Disabled IO,DO,I1,D1,I2,D2[4:0] 00000 00001 00010 00011 00100 --------11100 11101 11110 11111 Restrictions Register Availability SETEXTC turn on to enable this command. Status Idle Mode Off, Sleep Out Idle Mode On, Sleep Out Sleep In or Booster Off Status Default Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Default value TS_OS1[4:0]=0x0Ah, TS_OS2[4:0]=0x12h, BT_P1[3:0]=4b’0100, BT_P2[3:0]=4b’0111, BT_P3[3:0]=4b’0111, BT_P4[3:0]=4b’1010, D0[4:0]=0x0Ch, D1[4:0]= 0x17h, D2[4:0]= 0x17h, I0[4:0]= 0x0Ah, I1[4:0]= 0x15h, I2[4:0]= 0x15h, PORE=0, RER=2b’00, TF_ON=1, TSON=0, OTP value TS_OS1[4:0], TS_OS2[4:0], BT_P1[3:0], BT_P2[3:0], BT_P3[3:0], BT_P4[3:0], D0[4:0], D1[4:0], D2[4:0], I0[4:0], I1[4:0], I2[4:0], PORE, RER, TF_ON, TSON Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.259October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.68 SETGAMMA: Set gamma curve related setting (E0h) E0H SETGAMMAR ( Set Gamma Curve Related Setting ) DNC 0 1 1 1 1 1 1 1 1 NRD 1 1 1 1 1 1 1 1 1 NWR ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ D15-D8 - 1 1 ↑ - th 1 1 ↑ - th 1 1 ↑ - th 1 1 ↑ - th 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ - 1 1 ↑ - Command st 1 parameter nd 2 parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter th 14 Parameter th 15 Parameter th 16 Parameter th 17 Parameter th 18 Parameter th 19 Parameter th 20 Parameter th 21 Parameter th 22 Parameter th 23 Parameter th 24 Parameter th 25 Parameter th 1 1 ↑ - th 1 1 ↑ - th 1 1 ↑ - th 1 1 ↑ - th 1 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ - 26 Parameter 27 Parameter 28 Parameter 29 Parameter 30 Parameter th 31 Parameter th 32 Parameter th 33 Parameter th 34 Parameter Register Positive Groups Polarity G1_PRP0 6-0 Center Adjustment G1_PRP1 6-0 Description G1_PKP0 4-0 G1_PKP1 4-0 G1_PKP2 4-0 G1_PKP3 4-0 D7 1 - G1_CGMP0 [1:0] G1_CGMP1 [1:0] G1_CGMP2 [1:0] G1_CGMP3 [1:0] G1_CGMP5 G1_CGMP4 - D5 1 G1_CGMN0 [1:0] G1_CGMN1 [1:0] G1_CGMN2 [1:0] G1_CGMN3 [1:0] G1_CGMN5 G1_CGMN4 - Negative Polarity G1_PRN0 6-0 G1_PRN1 6-0 G1_PKN0 4-0 G1_PKN1 4-0 G1_PKN2 4-0 G1_PKN3 4-0 G1_PKN4 4-0 G1_PKP5 4-0 G1_PKP6 4-0 G1_PKP7 4-0 G1_PKP8 4-0 G1_VRP0 5-0 G1_VRP1 5-0 G1_VRP2 5-0 G1_PKN5 4-0 G1_PKN6 4-0 G1_PKN7 4-0 G1_PKN8 4-0 G1_VRN0 5-0 G1_VRN1 5-0 G1_VRN2 5-0 D4 0 D3 D2 0 0 G1_VRP0[5:0] G1_VRP1[5:0] G1_VRP2[5:0] G1_VRP3[5:0] G1_VRP4[5:0] G1_VRP5[5:0] G1_PRP0[6:0] G1_PRP1[6:0] D1 0 D0 0 HEX E0 - - G1_ PKP0[4:0] - - G1_PKP1[4:0] - - G1_PKP2[4:0] - - G1_PKP3[4:0] - - G1_PKP4[4:0] G1_PKP5[4:0] G1_PKP6[4:0] G1_PKP7[4:0] G1_PKP8[4:0] G1_VRN0[5:0] G1_VRN1[5:0] G1_VRN2[5:0] G1_VRN3[5:0] G1_VRN4[5:0] G1_VRN5[5:0] G1_PRN0[6:0] - G1_PRN1[6:0] - - Macro G1_PKP4 4-0 Adjustment Offset Adjustment D6 1 - - G1_PKN0[4:0] - - G1_PKN1[4:0] - - G1_PKN2[4:0] - - G1_PKN3[4:0] - - G1_PKN4[4:0] G1_PKN5[4:0] G1_PKN6[4:0] G1_PKN7[4:0] G1_PKN8[4:0] - Description Variable resistor (PRP/N0) for center adjustment Variable resistor (PRP/N1)for center adjustment 32-to-1 selector (voltage level of grayscale 3) 32-to-1 selector (voltage level of grayscale 7) 32-to-1 selector (voltage level of grayscale 19) 32-to-1 selector (voltage level of grayscale 25) 32-to-1 selector (voltage level of grayscale 32 for positive polarity and grayscale 31 for negative polarity) 32-to-1 selector (voltage level of grayscale 38) 32-to-1 selector (voltage level of grayscale 44) 32-to-1 selector (voltage level of grayscale 56) 32-to-1 selector (voltage level of grayscale 60) Variable resistor (VRP/N0)for offset adjustment Variable resistor (VRP/N1)for offset adjustment Variable resistor (VRP/N2)for offset adjustment Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.260October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 G1_ VRP3 5-0 G1_VRP4 5-0 G1_VRP5 5-0 G1_VRN3 5-0 G1_VRN4 5-0 G1_VRN5 5-0 Variable resistor (VRP/N3)for offset adjustment Variable resistor (VRP/N4)for offset adjustment Variable resistor (VRP/N5)for offset adjustment G1_CGMP/N0: Select to change gamma resistor stream. G1_CGMP/N1: Select to change gamma resistor stream. G1_CGMP/N2: Select to change gamma resistor stream. G1_CGMP/N3: Select to change gamma resistor stream. Please refer to Figure 5.31. G1_CGMP/N4: Select to change gamma resistor stream. Please refer to Figure 5.31. G1_CGMP/N5: Select to change gamma resistor stream. Please refer to Figure 5.31. Restriction Register Availability SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Default Default value G1_VRP0[5:0]=0x00h, G1_VRP1[5:0]=0x18h, G1_VRP2[5:0]=0x1Fh, G1_VRP3[5:0]=0x3Fh, G1_VRP4[5:0]=0x3Fh, G1_VRP5[5:0]=0x3Fh, G1_PRP0[6:0]=0x33h, G1_PRP1[6:0]=0x57h, G1_CGMP0[1:0]=00, G1_CGMP1[1:0]=00, G1_CGMP2[1:0]=00, G1_CGMP3[1:0]=00, G1_CGMP4=0, G1_CGMP5=0, G1_ PKP0[4:0]=0x07h, G1_ PKP1[4:0]=0x0Dh, G1_ PKP2[4:0]=0x0Fh, G1_ PKP3[4:0]=0x13h, G1_ PKP4[4:0]=0x16h, G1_ PKP5[4:0]=0x14h, G1_ PKP6[4:0]=0x16h, G1_ PKP7[4:0]=0x18h, G1_ PKP8[4:0]=0x1Fh, G1_VRN0[5:0]=0x00h, G1_VRN1[5:0]=0x18h, G1_VRN2[5:0]=0x1Fh, G1_VRN3[5:0]=0x3Fh, G1_VRN4[5:0]=0x3Fh, G1_VRN5[5:0]=0x3Fh, G1_ PKN0[4:0]=0x07h, G1_ PKN1[4:0]=0x0Dh, G1_ PKN2[4:0]=0x0Fh, G1_ PKN3[4:0]=0x13h, G1_ PKN4[4:0]=0x16h, G1_ PKN5[4:0]=0x14h, G1_ PKN6[4:0]=0x16h, G1_ PKN7[4:0]=0x18h, G1_ PKN8[4:0]=0x1Fh, G1_CGMN0[1:0]=00, G1_CGMN1[1:0]=00, G1_CGMN2[1:0]=00, G1_CGMN3[1:0]=00, G1_CGMN4=0, G1_CGMN5=0, Availability Yes Yes Yes Yes Yes OTP value G1_VRP0[5:0], G1_VRP1[5:0], G1_VRP2[5:0], G1_VRP3[5:0], G1_VRP4[5:0], G1_VRP5[5:0], G1_PRP0[6:0], G1_PRP1[6:0], G1_CGMP0[1:0], G1_CGMP1[1:0], G1_CGMP2[1:0], G1_CGMP3[1:0], G1_CGMP4, G1_CGMP5, G1_ PKP0[4:0], G1_ PKP1[4:0], G1_ PKP2[4:0], G1_ PKP3[4:0], G1_ PKP4[4:0], G1_ PKP5[4:0], G1_ PKP6[4:0], G1_ PKP7[4:0], G1_ PKP8[4:0], G1_VRN0[5:0], G1_VRN1[5:0], G1_VRN2[5:0], G1_VRN3[5:0], G1_VRN4[5:0], G1_VRN5[5:0], G1_ PKN0[4:0], G1_ PKN1[4:0], G1_ PKN2[4:0], G1_ PKN3[4:0], G1_ PKN4[4:0], G1_ PKN5[4:0], G1_ PKN6[4:0], G1_ PKN7[4:0], G1_ PKN8[4:0], G1_CGMN0[1:0], G1_CGMN1[1:0], G1_CGMN2[1:0], G1_CGMN3[1:0], G1_CGMN4, G1_CGMN5. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.261October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.69 SETOTPKEY (E9h) E9H Command st 1 parameter nd 2 parameter SETOTPKEY DNC 0 1 1 NRD 1 1 1 NWR ↑ ↑ ↑ D15-D8 - D7 1 D6 1 D5 1 D4 D3 0 1 OTP_KEY0[7:0] OTP_KEY1[7:0] D2 0 D1 0 D0 1 HEX E9 00h 00h This command is used to set OTP key to enter or leave OTP program mode. Description OTP_KEY0[7:0] OTP_KEY1[7:0] Description OTP_KEY0[7:0] = 0xAAh OTP_KEY1[7:0] = 0x55h Enter OTP program mode OTP_KEY0[7:0] = 0x00h OTP_KEY1[7:0] = 0x00h Leave OTP program mode Other value Restrictions Register Availability Default Invalid SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default value Power On Sequence OTP_KEY0[7:0]=0x00h, S/W Reset OTP_KEY1[7:0]=0x00h H/W Reset Note 1. If HX8369-A00 operate on OTP program mode, Then keep on OTP program mode. 2. If HX8369-A00 operate on non-OTP program mode, Then keep on non-OTP program mode. Availability Yes Yes Yes Yes Yes OTP value N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.262October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.70 GETHXID (F4h) F4H Command st 1 parameter Description Restrictions Register Availability Default GETHXIC DNC 0 1 NRD 1 ↑ NWR ↑ 1 D15-D8 - D7 1 D6 1 D5 1 This command is used to get LCD ID. SETEXTC turn on to enable this command. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default value Power On Sequence S/W Reset Himax ID[7:0] = 0x69h H/W Reset D4 D3 1 0 Himax ID[7:0] D2 1 D1 0 D0 0 HEX F4 - Availability Yes Yes Yes Yes Yes OTP value N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.263October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.71 SETCNCD/GETCNCD (FDh) FDH Command st 1 parameter Description Restrictions Register Availability Default SETCNCD/GETCNCD (Set/Get Continue Command) DNC 0 1 NRD 1 1 NWR ↑ ↑ D15-D8 - D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1 HEX FD - WR_CMD_CN[7:0] This function is use to instead of Register-Content interface mode. The parameter for SETCNCD will continue to read from the last command address automatically. SETEXTC turn on to enable this command Status Availability Idle Mode Off, Sleep Out Yes Idle Mode On, Sleep Out Yes Sleep In or Booster Off Yes Status Power On Sequence S/W Reset H/W Reset OTP value Default value N/A N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.264October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.72 SET SPI READ INDEX (FEh) FEH Command st 1 parameter Description Restrictions Register Availability Default SET SPI READ INDEX (Set SPI READ Command Address) DNC 0 NRD 1 NWR ↑ D15-D8 - D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 1 1 ↑ CMD_ADD[7:0] SET SPI READ Command Address for User Define Command. SETEXTC turn on to enable this command Status Availability Idle Mode Off, Sleep Out Yes Idle Mode On, Sleep Out Yes Status Power On Sequence S/W Reset H/W Reset Default value CMD_ADD[7:0]=0x00h D0 0 HEX FE - OTP value N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.265October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 6.2.73 GETSPIREAD:: Read command data (FFh) FFH Command st 1 parameter : th n parameter Description Restrictions GETMPUREAD (Read Command Data) DNC 0 NRD 1 NWR ↑ D15-D8 - D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 HEX FF 1 ↑ 1 - CMD_DATA1[7:0] - 1 ↑ 1 - : - 1 ↑ 1 - CMD_DATAN[7:0] - Read SPI Command Data for User Define Command. SETEXTC turn on to enable this command. Register Availability Status Idle Mode Off, Sleep Out Idle Mode On, Sleep Out Sleep In or Booster Off Default Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Default value N/A OTP value N/A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.266October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 7. Power Supply 7.1 Power supply setup 7.1.1 Architecture 1 with PFM circuit Note: If not use LVGL, please connect the VGL and LVGL together. Figure 7.1: Power supply with PFM circuit Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.267October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 7.1.2 Architecture 2 with HX5186-A Note: If not use LVGL, please connect the VGL and LVGL together. Figure 7.2: Power supply with HX5186-A Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.268October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 7.2 Voltage configuration The HX8369-A00 has an internal power supply circuit to drive TFTLCD panel. Please set up each voltage output according to the LCD panel. Name VREF VSP VSN VSPC VSNC VSPR VSNR VDDDN VGH VGL LVGL VCOM Function Set up value Note Reference voltage from internal band gap circuit 1.8V DC/DC converter circuit output 4.7V ~ 5.5V Do not exceed 6 V DC/DC converter circuit output -4.7V ~ -5.5V Do not exceed 6V DC/DC converter circuit output 4.7V ~ 5.5V Do not exceed 6 V DC/DC converter circuit output -4.7V ~ -5.5V Do not exceed 6V Reference voltage for gamma circuit 3.5V ~ (VSP – 0.5V) Reference register Reference voltage for gamma circuit -3.5V ~ (VSN + 0.5V) Reference register Logic power supply -2.5V Positive gate driver output voltage level +9V ~ +20V Depend on VSP and VSN Negative gate driver output voltage level -6V ~ -13.5V Depend on VSP and VSN GIP most negative voltage level VGL-VDD3 Depend on VSP and VSN VCOM DC voltage -2V ~ 0V - Pad Name VCOM VGH Connection Connect to Capacitor (Max 6V): VCOM ---(-)----| |--- (+)----- VSSA Connect to Capacitor (Max 25V): VGH ---(+)----| |--- (-)----- VSSA Connect to Capacitor (Max 16V): VGL ---(+)----| |--- (-)----- VSSA VGL Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---- VGL C24AP - C24AN C23AP - C23AN C22AP - C22AN C21AP - C21AN C41AP – C41AN VSPR VSNR VDDD VDDDN VREF VSP VSN VDD3 Connect to Capacitor (Max 16V): C24AP ---(+)----| |--- (-)-----C24AN Connect to Capacitor (Max 16V): C23AP ---(+)----| |--- (-)-----C23AN Connect to Capacitor (Max 16V): C22AP ---(+)----| |--- (-)-----C22AN Connect to Capacitor (Max 16V): C21AP ---(+)----| |--- (-)-----C21AN Connect to Capacitor (Max 16V): C41AP ---(+)----| |--- (-)-----C41AN Connect to Capacitor (Max 10V): VSPR ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 10V): VSNR ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 6V): VDDDN ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 6V): VREF ---(-)----| |--- (+)----- VSSA Connect to Capacitor (Max 10V):VSP ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 10V):VSN ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 10V): VDD3 ---(+)----| |--- (-)-----VSSA Connect to Capacitor (Max 16V): LVGL ---(-)----| |--- (+)----- VSSA LVGL Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---LVGL Typical Component Value 2.2 µF 1.0 µF 1.0 µF VF < 0.4V / 20mA @ 25°C, VR ≥30V (Recommended diode: RB521S-30) 1.0 µF 1.0 µF 1.0 µF 1.0 µF 1.0 µF 1.0 µF 1.0 µF 1.0 µF 1.0 µF 1.0 µF 2.2 µF 2.2 µF 1.0 µF 1.0 µF VF < 0.4V / 20mA @ 25°C, VR ≥30V (Recommended diode: RB521S-30) Table 7.1: Adoptability of component Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.269October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8. Electrical Characteristics 8.1 Absolute maximum ratings The absolute maximum ratings are list on Table 8.1. When used out of the absolute maximum ratings, the LSI may be permanently damaged. Using the LSI within the following electrical characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, the LSI will malfunction and cause poor reliability. Item Power Supply Voltage 1 Power Supply Voltage 2 Power Supply Voltage 3 Power Supply Voltage 4 Power Supply Voltage 5 Power Supply Voltage 6 Power Supply Voltage 7 Power Supply Voltage 8 Operating Temperature Storage Temperature Symbol VDD1~ VSSD VDD2 ~ VSSA VDD3 ~ VSSA DSI_VCC ~ DSI_VSS VSP ~ VSSA VSSA ~ VSN VGH ~ VSSA VSSA ~ VGL Topr Tstg Unit V V V Value -0.3 to +3.6 -0.3 to +5.5 -0.3 to +5.5 Note (1),(2) Note (1),(3) Note (1) (4) Note V -0.3 to +3.6 Note V V V V °C °C -0.3 to +6.6 0 to -6.6 -0.3 to +25 0 to -16 -40 to +85 -55 to +110 (1) (5) (6) Note (7) Note (8) Note (9) Note (10) Note (11) Note Note: (1) VDD1, VSSD must be maintained. (2) To make sure VDD1 ≥ VSSD. (3) To make sure VDD2≥ VSSA. (4) To make sure VDD3≥ VSSA. (5) To make sure DSI_VCC ≥ DSI_VSS. (6) To make sure VSP ≥ VSSA. (7) To make sure VSSA ≥ VSN (8) To make sure VGH ≥ VSSA. (9) To make sure VSSA ≥ VGL VGH +|VGL| < 32V (10) For die and wafer products, specified up to +85℃. (11) This temperature specifications apply to the TCP package. Table 8.1: Absolute maximum rating 8.2 ESD protection level Mode Test condition Criteria Human Body Model C=100 pF, R=1.5 kΩ ±2.0KV Machine Model C=200 pF, R=0.0 Ω ±200V Standard MIL-STD-883F Method 3015.7 EIA/JEDEC JESD22-A115-A Table 8.2: ESD protection level Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.270October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.3 DC characteristics (VDD2=2.3 ~ 4.8V, VDD3=2.3 ~ 4.8V, VDD1=1.65~3.3V, TA=-40 ~ 85 °C) Item Input high voltage Symbol VIH Unit V Input low voltage VIL V VPP VIH VIL V V VOH1 V Output high voltage (SDO, CABC_PWM_OUT) Output low voltage (SDO, CABC_PWM_OUT) VOL1 V IIH uA Logic High level input current IIHD uA IIL uA IILD uA Logic Low level input current Current consumption standby mode (VDD2/VDD3-VSSD) Current consumption standby mode ( VDD1– VSSD ) IST(VDD) µA IST(VDD1) µA Test Condition VDD1= 1.65 ~ 3.3V VDD2= 2.3 ~ 3.3V VDD3= 2.3 ~ 3.3V Min. 0.7 VDD1 Typ. - Max. VDD1 Note V 0 - 0.3 VDD1 V VPP 7.25V 7.5V 7.75V V IOH = -1.0 mA 0.8 VDD1 - VDD1 V 0 - 0.2 VDD1 V - - uA - - 1 1 VDD1= 1.65 ~ 2.4V IOL = 1.0 mA VSYNC, HSYNC RESX, DCX_SCL, CSX, RDX_E, WRX_DCX DB[23…0], SDI, DCX_SCL DB[23…0] VSYNC, HSYNC RESX, DCX_SCL, CSX, RDX_E, WRX_DCX DB[23…0], SDI, DCX_SCL DB[17…0] VDD2/VDD3=2.8V, VDD1=1.8V TA =25°C - - -1 -1 - 1 1 uA uA uA uA - uA - uA -1 - uA - 30 80 - 1 - -1 uA uA Current consumption during Deep-standby mode IDP-ST(VDD) µA 5 VDD2/VDD3=2.8V, (VDD2/VDD3-VSSD) VDD1=1.8V Current consumption TA =25°C during Deep-standby mode IDP-ST(VDD1) µA 1 ( VDD1– VSSD ) Note: 1. The VPP pin is open on normal mode and in used while OTP programming condition. 2. The GRAM data is eliminated under the Deep standby mode. uA uA - Table 8.3: DC characteristic Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.271October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.4 AC characteristics 8.4.1 DBI Type A interface characteristics Figure 8.1: DBI Type A interface characteristics(CLK-E mode) (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Signal Symbol Parameter Min. Max. Unit Description WRX_DCX or DCX_SCL tAST tAHT Address setup time Address hold time (Write/Read) System clock cycle time read register Read GRAM Write register Write GRAM @ SLPOUT Write GRAM @ SLPIN 10 10 - ns - 100 790 ns - 350 100 33 100 15 25 10 10 790 790 790 790 - ns ns ns ns - ns For maximum CL=30pF For minimum CL=8pF CSX or RDX_E tcycle DB23-DB0 tDS tDH tACC tOH Data setup time Data hold time Read access time Output disable time Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. Table 8.4: DBI Type A interface characteristics Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.272October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.4.2 DBI Type B interface characteristics Figure 8.2: DBI Type B interface characteristics (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Signal Symbol DCX_SCL tAST tAHT Address setup time Address hold time (Write/Read) tCS tRCS Chip select setup time (Write) Chip select setup time (Read ID) Chip Select setup time (Read FM) Chip select wait time (Write/Read) CSX WRX_DCX RDX_E DB23-DB0 tRCSFM tCSF Parameter Min. Max. Unit Description 10 10 20 45 355 20 - ns - - ns - ns - ns - ns For maximum CL=30pF For minimum CL=8pF tWC tWC tWC tWRH tWRL tRC tRC tRDH tRDL Write cycle (write register) Write cycle (write GRAM@SLPOUT) Write cycle (write GRAM@SLPIN) Control pulse “H” duration Control pulse “L” duration Read cycle (read register) Read cycle (GRAM) Control pulse “H” duration Control pulse “L” duration 100 33 100 15 15 100 350 30 20 790 790 790 630 160 790 790 630 160 tWDS tWDH tRACC tRDO Data setup time Data hold time Read access time Output disable time 15 25 10 10 - Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. Table 8.5: DBI Type B interface characteristics Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.273October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.4.3 DBI Type C interface characteristics Figure 8.3: DBI Type C interface characteristics (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA = 25°C) Signal Symbol CSX tCSS tCSH Chip select setup time (Write) Chip select setup time (Read) WRX_DCX tAST tAHT Address setup time Address hold time (Write/Read) DCX_SCL (Write) tWC tWRH tWRL Write cycle Control pulse “H” duration Control pulse “L” duration DCX_SCL (Read) tRC tRDH tRDL Read cycle Control pulse “H” duration Control pulse “L” duration SDI/SDO (Input) SDI/SDO (Output) tDS tDT Data setup time Data hold time tRACC tOD Parameter Read access time Output disable time Min. Max. 40 40 10 10 100 40 40 150 60 60 30 30 10 10 50 Unit Description ns - ns - ns - ns - ns ns For maximum CL=30pF For minimum CL=8pF Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals. Table 8.6: DBI Type C interface characteristics Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.274October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.4.4 DPI interface characteristics VSST VSHT VSYNC HSST HSHT HSYNC PCLKCYC PCLKLT PCLKHT PCLK DST DHT DB[15:0], DB[17:0], DB[23:0], DE Figure 8.4: DPI interface characteristics Resolution=480x800 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Parameter Vertical sync. setup time Vertical sync. hold time Horizontal sync. setup time Horizontal sync. hold time Symbol Condition Min. Typ. Max. Unit VSST VSHT HSST HSHT VRR(5) = Min . 50 Hz Max. 70 Hz - 5 5 5 5 - - ns ns ns ns Pixel clock cycle when RGB I/F is running PCLKCYC Pixel clock low time Pixel clock high time Data setup time DB[23:0] Data hold time DB[23:0] PCLKLT PCLKHT DST DHT 31 (3) 5 5 5 5 - 49.2 (4) ns - ns ns ns ns Note: (1) Signal rise and fall times are equal to or less than 20 ns. (2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state. (3) 32.2 MHz (4) 20.3 MHz (5) VRR : Vertical Refresh Rate, equal to VSYNC frequency. Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.275October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Resolution=480x854 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Item Vertical sync. Setup time Vertical sync. Hold time Horizontal sync. Setup time Horizontal sync. Hold time Symbol Condition VSST VSHT HSST HSHT - Min. 5 5 5 5 Typ. - Max. Unit - ns ns ns ns (5) Pixel clock cycle When RGB I/F is running Pixel clock low time Pixel clock high time Data setup time DB[23:0] Data Hold time DB[23:0] VRR = DCKCYC Min . 50 Hz Max. 70 Hz DCKLT DCKHT DST DHT - 29.1 (Note 3) 5 5 5 5 - 46.2 (Note 4) - ns ns ns ns ns Note: (1) Signal rise and fall times are equal to or less than 20 ns. (2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state. (3) 34.3 MHz (4) 21.6 MHz Table 8.7: DPI interface characteristics Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.276October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Vertical Timings for RGB I/F VSYNC VFP DB[23:0] VS VBP VFP Note3 Note3 VDISP VBL DE VP HSYNC Figure 8.5: Vertical Timings for RGB I/F Resolution=480x854 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Item Symbol Condition Min. Typ. Max. Unit Vertical cycle Vertical low pulse width Vertical front porch Vertical back porch Vertical data start point Vertical blanking period Vertical active area Vertical Refresh rate Line Line Line Line Line Line Line Hz VP VS VFP VBP VBL VRR VS+VBP VS+VBP+VFP VDISP - 6 Note(5) - - 854 - 50 - 70 860 Note(5) 2 Note(5) 2 Note(5) 2 Note(5) 4 Note(5) Note(4) Note(4) Note(4) - Note: (1) Signal rise and fall times are equal to or less than 20 ns. (2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for highstate. (3) Data lines can be set to “High” or “Low” during blanking time – Don’t care. (4) The VS and VBP pulse width are related to ASG/GIP STV and CKV timing. The STV and CKV must be set at corresponding position for LCD normal display. Also refer to setion 6.2.66 SETGIP. (5) The VS and VBP and VFP pulse width are related to ASG/GIP STV and CKV timing. The minimum of VS and VBP and VFP must ≧3 Hsync if the STV0~STV3 and CKV0~CKV7 are all in used in corresponding position for LCD normal display. Also refer to setion 6.2.66 SETGIP. Resolution=480x800 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Item Symbol Condition Min. Typ. Max. Unit Vertical cycle Vertical low pulse width Vertical front porch Vertical back porch Vertical data start point Vertical blanking period Vertical active area Vertical Refresh rate Line Line Line Line Line Line Line Hz VP VS VFP VBP VBL VRR VS+VBP VS+VBP+VFP VDISP - 6 Note(5) - - 800 - 50 - 70 806 Note(5) 2 Note(5) 2 Note(5) 2 Note(5) 4 Note(5) Note(4) Note(4) Note(4) - Note: (1) Signal rise and fall times are equal to or less than 20 ns. (2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for highstate. (3) Data lines can be set to “High” or “Low” during blanking time – Don’t care. (4) The VS and VBP pulse width are related to ASG/GIP STV and CKV timing. The STV and CKV must be set at corresponding position for LCD normal display. Also refer to setion 6.2.66 SETGIP. (5) The VS and VBP and VFP pulse width are related to ASG/GIP STV and CKV timing. The minimum of VS and VBP and VFP must ≧3 Hsync if the STV0~STV3 and CKV0~CKV7 are all in used in corresponding position for LCD normal display. Also refer to setion 6.2.66 SETGIP. Table 8.8 Vertical Timings for RGB I/F Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.277October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 Horizontal Timings for RGB I/F Figure 8.6: Horizontal Timing for RGB I/F Resolution=480x854 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Item Symbol Condition Min. Typ. Max. Unit HS cycle HP Note 3 - 568 HS low pulse width HS - 5 - 78 DCK Horizontal back porch HBP - 5 - 78 DCK Horizontal front porch HFP - 5 - 78 DCK Horizontal data start point - HS+HBP DCK Horizontal blanking period HBLK HS+HBP+HFP Horizontal active area HDISP - Pixel clock frequency When RGB I/F is running DCK VRR = Min. 50 Hz – Max. 70 Hz 504 DCK 19 - 83 700 - - 24 - 88 DCK - 480 - DCK 21.6 - 34.3 MHz 29.1 - 46.2 ns ns Note: (1) Signal rise and fall times are equal to or less than 20 ns. (2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state. (3) HP is multiples of eight DCK. (4)Data lines can be set to “High” or “Low” during blanking time – Don’t care. Resolution=480x800 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C) Item Symbol Condition Min. Typ. HS cycle HP Note 3 HS low pulse width HS Horizontal back porch Horizontal front porch Max. Unit 504 - 568 DCK - 5 - 78 DCK HBP - 5 - 78 DCK HFP - Horizontal data start point - HS+HBP Horizontal blanking period HBLK HS+HBP+HFP Horizontal active area HDISP - Pixel clock frequency When RGB I/F is running DCK VRR = Min. 50 Hz – Max. 70 Hz 5 - 78 DCK 19 - 83 DCK 700 - - 24 - 88 DCK - 480 - DCK 20.3 - 32.2 MHz 31 - 49.2 ns ns Note: (1) Signal rise and fall times are equal to or less than 20 ns. (2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state. (3) HP is multiples of eight DCK. (4)Data lines can be set to “High” or “Low” during blanking time – Don’t care. Table 8.9 Horizontal Timings for RGB I/F Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.278October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.4.5 Reset input timing Shorter than 5µs tRESW RESX tREST Internal Status Normal Operation Initial Condition (Default for H/W reset) Resetting Figure 8.7: Reset input timing Symbol Parameter (1) tRESW Reset low pulse width tREST Reset complete time (2) Related pins RESX Min. Typ. Max. Note Unit 10 - - µs - 5 - - - 120 - - When reset is applied during Sleep In mode When reset is applied during Sleep Out mode ms ms Note: (1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. RESX Pulse Action Reset Rejected Shorter than 5 µ Reset Longer than 10 µs Between 5 µs and 10 µs Reset Start (2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then returns to Default condition for H/W reset. (3) During Reset Complete Time, ID2 value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX. (4) Spike Rejection also applies during a valid reset pulse as shown below: (5) When Reset is applied during Sleep In Mode. (6) When Reset is applied during Sleep Out Mode. (7) It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec. Table 8.10: Reset timing Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.279October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 8.4.6 DPI Interface Power On/Off Timing VDD1 VDD2 VDD3 RESX Wait until power stable 10us (min) Effective reset pulse Sleep out command Standard command input (Note1) V synchronous time , max 1 frame Min 120ms 5ms (min) 20ms (min) User Define command input (Note2) Himax Initialize commands Himax Initialize commands Display on command (Note3) 2 frames RGB signals before SLPOUT RGB Interface Mode Function See “Power On Timing - 2” RGB signals Sleep in Not define Load OTP <20ms All power off Sleep out + Display on Sleep out Display off Clear screen Normal display 2 frames (33ms) OSC OFF Driver boost Not defined Operation 67ms (min) Regulator VCOM/ VSPR/ VSNR Normal operation Power sequential turn on Normal operation OFF V0/V255 S[1440:1] Gray Sleep out command Display on command VGH 2ms (min) VGL DT+5ms(min) (Note4) VSP (for PFM) DT+15ms(min) (Note4) VSN (for PFM) DTms (Note4) VSP (for 5186) DTms (Note4) VSN (for 5186) DT+15ms(min) (Note4) VCOM/ VSPR/ VSNR Note1: “Standard” command except “01h” & “10h” command must wait 5ms after “Sleep out” command then can be sent. “01h” & “10h” command must wait 100ms after “Sleep out” command then can be sent. 3DT+15ms(at least) (Note4) Note2: “User Define” command must be sent “B9h” first then other commands can be available. Note3: “Display on” command must send after “User Define” command or at the same time. Note4: Default DT=5ms Figure 8.1 Power On Timing Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.280October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 VDD1 VDD2 VDD3 Sleep in command Min 120ms Display off command V synchronous time , max 1 frame 2 frames after sleep in RGB Interface RGB Signals Mode Sleep out + Display on Sleep out Function Normal display Clear screen OSC Operation Driver boost Normal operation Sleep in Power off sequence Not defined All power off 2 frames (33ms) OFF 60ms (min) Sequential turn off Regulator VCOM/ Normal operation VSPR/ VSNR S[1440:1] Gray Not defined OFF V0/V255 Figure 1.2 Power Off Timing Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.281October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 9. Layout Recommendation Figure 9.1: Layout recommendation Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.282October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 10. Maximum Layout Resistance Name Type Maximum series resistance 10 20 10 10 10 10 10 20 10 50 30 100 VDD1 Power supply VDD2 Power supply VDD3 Power supply VSSD Power supply VSSA Power supply DSI_VCC / MDDI_VCC Power supply DSI_VSS / MDDI_VSS Power supply VSSAC Power supply VPP Input PCCS0, PCCS1 Input VCSW1, VCSW2 Output BS[3:0] Input RDX_E, WRX_DCX, DCX_SCL, CSX, Input RESX HSYNC, VSYNC, DE, PCLK Input SDI Input SDO Output DB[23:0] Output CABC_PWM_OUT Output VCOM Output DSI_D0P / MDDI_D1P Input + Output DSI_D0N / MDDI_D1N Input + Output DSI_CLKP / MDDI_STBP Input DSI_CLKN / MDDI_STBN Input DSI_D1P / MDDI_D0P Input DSI_D1N / MDDI_D0N Input VDDD Capacitor Connection VDDDN Capacitor Connection VSP, VSN Capacitor Connection VSPC, VSNC Capacitor Connection VSPR, VSNR Capacitor Connection VREF Capacitor Connection VGL, LVGL Capacitor Connection VGH Capacitor Connection DSI_LDO/MDDI_LDO Capacitor Connection DSI_LDO_ENB Input OSC Input C21AP,C21AN,C22AP,C22AN, C23AP,C23AN,C24AP,C24AN, Capacitor Connection C41AP,C41AN, TEST[2:1] Input TE Output VTESTOUTP, VTESTOUTN Output VBIAS Output VCOMR Input Table 10.1: Maximum layout resistance Unit Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω 100 Ω 100 100 100 100 100 10 8 8 8 8 8 8 5 50 10 50 50 20 10 10 20 100 100 Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω 10 Ω 100 100 100 50 100 Ω Ω Ω Ω Ω Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.283October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 11. Ordering Information Part No. HX8369-A00 PDxxx Package PD: mean COG xxx: mean chip thickness (µm), (default: 250 µm) 12. Revision History Version 01 Date 2009/08/26 2009/10/27 Description of Changes 1. 1. 2. 3. 4. 2009/10/29 1. 2. 2009/11/6 3. 1. 2. 2009/11/12 2009/11/26 2010/03/08 2010/04/01 3. 1. 1. 1. 2. 1. 2. 3. 4. 2010/04/09 2010/04/23 2010/04/30 1. 1. 2. 3. 1. 2. 3. 4. New setup Update pin assignment (page 19) Update bump arrangement (page 28) Add temperature sensor control register (page 254 ~ 258) Update PFM circuit and HX5186-A application diagrams (page 266~267) Update RTN, RTN_PE, FP_PE and BP_PE setting (page 231) Update absolute maximum rating VDD2 and VDD3 (page 269) Update BT[3:0] setting (page222) Error typing. Update 3Ah interface format table (page 199) Error typing. Update 0Ch interface format table (page 168) Update table7.1 adoptablilty of component. (page269) Update OTP table (page 139-141) Update registers default values (page153~156) Update 0xB2h FP[7:0] and BP[7:0] = 8h’00 definition(page 230). Update 0xB1h BTN[4:0] VSN definition(page 223). Update OTP index 0x47h (page 140) Update command list 0xB1h default (page 220) Error typing PCLKCYC, PCLKLT and PCLKHT (page 275) Adds Gamma resister stream description (page 113 and 114) Error typing I/O pins. (page 26) Update the chip thickness information.(page 17) Update register 2Dh Look Up table description. (page 183-185) Update DC characteristics information. (page270) Error typing, change maximum 256k colours to 16.7M colours.(page 182) Error typing, change SDA to SDI and SDO. (page 40~42) Adds notice for RGB caputer mode only used in RGB 24-bit. (page 46) Add notice for GIP description.(page 247) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.284October, 2010 HX8369-A00 480RGBx864dots, TFT Mobile Single Chip Driver DATA SHEET V02 2010/05/03 1. 2. 3. 4. 2010/05/10 2010/05/19 5. 1. 2. 3. 1. 2. 3. 4. 2010/05/20 1. 2010/05/28 2010/06/02 2010/07/14 1. 1. 1. 2. 2010/08/04 2010/08/20 2010/09/23 2010/10/18 02 2010/10/26 2010/11/11 1. 2. 3. 1. 2. Error typing, change NRESET to RESX.(page17) Error typing section 5.15(page153) Error typing, change PVSS to VPP. (page 144,271 and 283) Add the I/O pin CABC_PWM_OUT in the table 5.22.(page 116) Update the OTP table. (page 139-141) Update figure SDI,SDO and RESX(page 279) Update the revision date(all pages). Error typing, change SDA to SDI and SDO. (page 13) Update Command list table.(page153-156) Update Gamma stream description.(page117-155) Adds register D5hSETGIP description.(page247-253) Adds register D8hSETTPSNR description. (page254-258). Update Vertical RGB I/F timing note(4).(page275-277) Update FS1[2:0]=000 setting is inhibited.(page 222). Update CSX tRCS and tRCSFM (page 273-274) Adds the setion 5.194~ 5.197 OTP programming examples.(page 144 – 147) Update pin assignment scribe line information. (page18) Update DB23-0 description.(page 15) Updae Table 4.20 pin connection.(page 30) Error typing CCh REV_PANEL description.(page 247) Adds page header information.(page 3-9). Adds register C9h Set CABC control description. (page 244-245) Adds power on/off timing chart.(page 280-281) Update regidter 0xF4h.(page 263) Update GIP_OPT[7:0] description.(page 253) 1. 2. 3. 4. Update DFR description.(page 230) 5. Update Rest timing table.(page 279) 1. Update the OTP readback flow dummy read notice. (page 147~148) 1. Update standby mode current consumption max. 80uA. (page 271) 1. Update GIP timing chart. (page 249) Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. -P.285October, 2010