The following document contains information on Cypress products. 32-BIT MICROCONTROLLER FM4 Family GDC Part PERIPHERAL MANUAL For the information for microcontroller supports, see the following web site. http://www.spansion.com/support/microcontrollers/ Publication Number FM4_MN709-00014 CONFIDENTIAL Revision 1.0 Issue Date February 2, 2015 P E R I P H E R A L 2 CONFIDENTIAL M A N U A L FM4_MN709-00014-1v0-E, February 2, 2015 P E R I P H E R A L M A N U A L Preface Thank you for your continued use of Spansion products. Read this manual and data sheet thoroughly before using products in this family. Purpose of This Manual and Intended Readers This manual explains the functions and operations of this family and describes how it is used. The manual is intended for engineers engaged in the actual development of products using this family. For the descriptions on Analog macro, Timer, and Communication Macro, see the respective separate peripheral manual. Note: − This manual explains the configuration and operation of the peripheral functions, but does not cover the specifics of each device in the series. Users should refer to the respective data sheets of devices for device-specific details. Trademark ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Sample Programs and Development Environment Spansion offers sample programs free of charge for using the peripheral functions of the FM4 family. Spansion also makes available descriptions of the development environment required for this family. Feel free to use them to verify the operational specifications and usage of this Spansion microcontroller. Microcontroller Support Information: http://www.spansion.com/support/microcontrollers/ Note: − Note that the sample programs are subject to change without notice. Since they are offered as a way to demonstrate standard operations and usage, evaluate them sufficiently before running them on your system. Spansion assumes no responsibility for any damage that may occur as a result of using a sample program. Overall Organization of This Manual This Peripheral Manual has 4 chapters as shown below. CHAPTER 1 : Overview CHAPTER 2 : Reference Clock Selector CHAPTER 3 : Subsystem Control CHAPTER 4 : Software Interface February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 3 P E R I P H E R A L M A N U A L Related Manuals The manuals related to this family are listed below. See the manual appropriate to the applicable conditions. The contents of these manuals are subject to change without notice. Contact us to check the latest versions available. Peripheral Manual FM4 Family Peripheral Manual Main Part (MN709-00001) (Called PERIPHERAL MANUAL hereafter) FM4 Family Peripheral Manual Timer Part (MN709-00002) (Called Timer part hereafter) FM4 Family Peripheral Manual Analog Macro Part (MN709-00003) (Called Analog Macro part hereafter) FM4 Family Peripheral Manual Communication Macro Part (MN709-00004) (Called Communication Macro part hereafter) FM4 Family Peripheral Manual GDC Part (This manual) (Called GDC part hereafter) FM4 Family Peripheral Manual GDC (Subsystem) Part (MN709-00019) It is necessary to conclude non-disclosure agreement to obtain this manual. Contact us for more information. FM4 Family Peripheral Manual GDC (Core) Part (MN709-00020) It is necessary to conclude non-disclosure agreement to obtain this manual. Contact us for more information. Data Sheet For details about device-specific, electrical characteristics, package dimensions, ordering information etc., see the following document. 32-bit Microcontroller FM4 Family Data Sheet Note: − The data sheets for each series are provided. See the appropriate data sheet for the series that you are using. CPU Programming Manual For details about ARM Cortex-M4 core, see the following documents that can be obtained from http://www.arm.com/. Cortex-M4 Technical Reference Manual ARMv7-M Architecture Application Level Reference Manual Flash Programming Manual For details about the functions and operations of the built-in flash memory, see the following document. FM4 Family Flash Programming Manual Note: − 4 CONFIDENTIAL Flash programming manuals for each series are provided. See the appropriate flash programming manual for the series that you are using. FM4_MN709-00014-1v0-E, February 2, 2015 P E R I P H E R A L M A N U A L How to Use This Manual Finding a Function The following methods can be used to search for the explanation of a desired function in this manual: Search from the table of the contents The table of the contents lists the manual contents in the order of description. Search from the register The address where each register is located is not described in the text. To verify the address of a register, see A. Register Map in Appendixes. About the Chapters Basically, this manual explains 1 peripheral function per chapter. Terminology This manual uses the following terminology. Term Explanation Word Indicates access in units of 32 bits. Half word Indicates access in units of 16 bits. Byte Indicates access in units of 8 bits. Notations The notations in bit configuration of the register explanation of this manual are written as follows. − bit: bit number − Field: bit field name − Attribute : Attributes for read and write of each bit − R: Read only − W: Write only − R/W: Readable/Writable − -: Undefined − Initial value : Initial value of the register after reset − − − 0: 1: Initial value is 0 Initial value is 1 X: Initial value is undefined The multiple bits are written as follows in this manual. Example: bit7:0 indicates the bits from bit7 to bit0 The values such as for addresses are written as follows in this manual. − Hexadecimal number: 0x is attached in the beginning of a value as a prefix (example: 0xFFFF) − Binary number: − Decimal number: February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 0b is attached in the beginning of a value as a prefix (example: 0b1111) Written using numbers only (example : 1000) 5 P E R I P H E R A L M A N U A L The Target Products in This Manual In this manual, the products are classified into the following groups and are described follows. For the descriptions such as TYPE1-M4, see the relevant items of the target product in the list below. Table 4 TYPE4-M4 Product List Flash memory size Description in this 384 Kbytes VRAM 512 Kbytes VRAM size manual TYPE4-M4 6 CONFIDENTIAL + 512 Kbytes 384 Kbytes S6E2D35G0AGB10 S6E2D35GAAGB10 S6E2D35G0AGV20 S6E2D35GAAGV20 S6E2D35G0AGZ20 S6E2D35GAAGZ20 S6E2D35J0AGV20 S6E2D35JAAGV20 VFLASH 2 Mbytes S6E2D35J0AGZ20 S6E2D35JAAGZ20 S6E2D55G0AGB10 S6E2D55GAAGB10 S6E2D55G0AGV20 S6E2D55GAAGV20 S6E2D55G0AGZ20 S6E2D55GAAGZ20 S6E2D55J0AGV20 S6E2D55JAAGV20 S6E2D55J0AGZ20 S6E2D55JAAGZ20 S6E2DF5G0AGB10 S6E2DF5GAAGB10 S6E2DF5G0AGV20 S6E2DF5GAAGV20 S6E2DF5G0AGZ20 S6E2DF5GAAGZ20 S6E2DF5J0AGV20 S6E2DF5JAAGV20 S6E2DF5J0AGZ20 S6E2DF5JAAGZ20 S6E2DH5G0AGB10 S6E2DH5GAAGB10 S6E2DH5G0AGV20 S6E2DH5GAAGV20 S6E2DH5G0AGZ20 S6E2DH5GAAGZ20 S6E2DH5J0AGV20 S6E2DH5JAAGV20 S6E2DH5J0AGZ20 S6E2DH5JAAGZ20 S6E2D35GJAMV20 S6E2D55GJAMV20 S6E2DF5GJAMV20 S6E2DH5GJAMV20 FM4_MN709-00014-1v0-E, February 2, 2015 P E R I P H E R A L M A N U A L Table of Contents CHAPTER 1: Overview ................................................................................................................................ 11 1. Overview ........................................................................................................................................... 12 1.1. Feature Summary ................................................................................................................. 12 1.1.1. General Features .................................................................................................... 12 1.1.2. Display Controller .................................................................................................... 12 1.1.3. Blit Engine ............................................................................................................... 13 2. Block Diagrams ................................................................................................................................. 14 3. Function Summary ............................................................................................................................ 15 3.1. Reference Clock Selector ..................................................................................................... 15 3.1.1. Reference Clock for GDC Clock .............................................................................. 15 3.1.2. Reference Clock for Peripherals.............................................................................. 15 3.1.3. Software Reset ........................................................................................................ 15 3.2. Subsystem Controller (subsysctrl) ........................................................................................ 15 3.3. GDC Core ............................................................................................................................. 15 3.4. HS-SPI External Memory Interface ....................................................................................... 15 3.5. SDRAM External Memory Controller .................................................................................... 16 3.6. HyperBus Interface ............................................................................................................... 16 CHAPTER 2: Reference Clock Selector ..................................................................................................... 17 1. Overview ........................................................................................................................................... 18 1.1. Feature Summary ................................................................................................................. 18 1.1.1. Reference Clock for GDC Clock .............................................................................. 18 1.1.2. Reference Clock for Peripherals.............................................................................. 18 1.1.3. Software Reset ........................................................................................................ 18 2. Block Diagram................................................................................................................................... 19 3. Operation .......................................................................................................................................... 20 3.1. Clock Set up ......................................................................................................................... 20 3.2. Setting the Multiplication Ratio to Generate the GDC Subsystem PLL ................................. 21 3.3. Reset Set up ......................................................................................................................... 22 4. Registers ........................................................................................................................................... 23 4.1. GCCR ................................................................................................................................... 24 4.2. GPCR1 ................................................................................................................................. 25 4.3. GPCR2 ................................................................................................................................. 26 4.4. GPCR3 ................................................................................................................................. 27 4.5. GPCR4 ................................................................................................................................. 28 4.6. GP_STR ............................................................................................................................... 29 4.7. GPINT_ENR ......................................................................................................................... 30 4.8. GPINT_CLR .......................................................................................................................... 31 4.9. GPINT_STR .......................................................................................................................... 32 4.10. GCSR ................................................................................................................................. 33 4.11. GRCR ................................................................................................................................. 35 4.12. GMCR ................................................................................................................................. 36 CHAPTER 3: Subsystem Control ............................................................................................................... 37 1. Overview ........................................................................................................................................... 38 1.1. Feature Summary ................................................................................................................. 38 2. Block Diagram................................................................................................................................... 39 3. Function and Operation .................................................................................................................... 40 3.1. Overview ............................................................................................................................... 40 3.1.1. Reference Clocks .................................................................................................... 40 3.1.2. GDC Clock .............................................................................................................. 40 3.1.3. CONFIG Clock ........................................................................................................ 40 3.1.4. Peripheral Clocks .................................................................................................... 40 February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 7 P E R I P H E R A L M A N U A L 3.2. GDC Clock Set up................................................................................................................. 41 3.3. CONFIG Clock Set up........................................................................................................... 42 3.4. Display Clock Set up ............................................................................................................. 42 3.4.1. Display Clock Generation and Reset Control .......................................................... 42 3.4.2. Display Clock Shift .................................................................................................. 43 3.4.3. How to Set up Display clock .................................................................................... 43 3.5. HyperBus Interface Clock Set up .......................................................................................... 44 3.6. SDRAM Interface Clock Setup .............................................................................................. 44 3.7. QSPI Interface Clock Setup .................................................................................................. 44 3.8. Clock Frequency Setup Example .......................................................................................... 45 3.8.1. Example1 ................................................................................................................ 45 3.8.2. Example2 ................................................................................................................ 46 4. Registers ........................................................................................................................................... 47 4.1. LockUnlock ........................................................................................................................... 49 4.2. LockStatus ............................................................................................................................ 50 4.3. TEST (Reserved) .................................................................................................................. 51 4.4. CnfigClockControl ................................................................................................................. 52 4.5. VRamInterruptEnable ........................................................................................................... 53 4.6. TEST (Reserved) .................................................................................................................. 55 4.7. VramInterruptClear ............................................................................................................... 56 4.8. VRamInterrunptStatus .......................................................................................................... 57 4.9. ExtFlashDevSelect................................................................................................................ 58 4.10. VramRemapDisable ............................................................................................................ 59 4.11. PanicSwitch ........................................................................................................................ 60 4.12. GDC_ClockDivider .............................................................................................................. 61 4.13. WkupTriggerMask ............................................................................................................... 62 4.14. ClockDomainStatus ............................................................................................................ 64 4.15. dsp_LockUnlock.................................................................................................................. 66 4.16. dsp_LockStatus .................................................................................................................. 67 4.17. dsp0_ClockDivider .............................................................................................................. 69 4.18. dsp0_DomainControl .......................................................................................................... 70 4.19. dsp0_ClockShift .................................................................................................................. 71 4.20. TEST (Reserved) ................................................................................................................ 72 4.21. dsp0_PowerEnControl ........................................................................................................ 73 4.22. dsp0_ClockGateModeLock ................................................................................................. 74 4.23. dsp0_ClockGateControl ...................................................................................................... 75 4.24. SDRAMC_ClockDivider ...................................................................................................... 76 4.25. SDRAMC_DomainControl .................................................................................................. 77 4.26. HSSPIC_ClockDivider ........................................................................................................ 79 4.27. HSSPIC_DomainControl ..................................................................................................... 80 4.28. RPCC_ClockDivider............................................................................................................ 81 4.29. RPCC_DomainControl ........................................................................................................ 82 4.30. vram_LockUnlock ............................................................................................................... 83 4.31. vram_LockStatus ................................................................................................................ 84 4.32. vram_sram_select............................................................................................................... 86 4.33. TEST (Reserved) ................................................................................................................ 91 4.34. TEST (Reserved) ................................................................................................................ 92 4.35. TEST (Reserved) ................................................................................................................ 93 4.36. TEST (Reserved) ................................................................................................................ 94 4.37. TEST (Reserved) ................................................................................................................ 95 4.38. TEST (Reserved) ................................................................................................................ 96 4.39. TEST (Reserved) ................................................................................................................ 97 4.40. TEST (Reserved) ................................................................................................................ 98 8 CONFIDENTIAL FM4_MN709-00014-1v0-E, February 2, 2015 P E R I P H E R A L M A N U A L 4.41. vram_sberraddr_s0 ............................................................................................................. 99 4.42. vram_sberraddr_s1 ........................................................................................................... 100 4.43. vram_arbiter_priority ......................................................................................................... 101 CHAPTER 4: Software Interface ............................................................................................................... 103 1. Map Tables ..................................................................................................................................... 104 1.1. Interrupt Map ...................................................................................................................... 104 Appendixes ................................................................................................................................................ 107 A. Register Map .................................................................................................................................. 108 1. Register Map................................................................................................................................... 110 1.1. FLASH_IF ........................................................................................................................... 111 1.1.1. TYPE1-M4, TYPE2-M4 products ............................................................................ 111 1.1.2. TYPE3-M4 product ................................................................................................. 112 1.1.3. TYPE4-M4 product ................................................................................................. 113 1.2. Unique ID ............................................................................................................................ 114 1.3. ECC Capture Address ........................................................................................................ 114 1.4. Clock/Reset ........................................................................................................................ 115 1.5. HW WDT............................................................................................................................. 117 1.6. SW WDT ............................................................................................................................. 117 1.7. Dual_Timer ......................................................................................................................... 118 1.8. MFT .................................................................................................................................... 119 1.8.1. TYPE1-M4, TYPE2-M4 products ............................................................................ 119 1.8.2. TYPE3-M4, TYPE4-M4 products ........................................................................... 122 1.9. PPG .................................................................................................................................... 125 1.10. Base Timer ....................................................................................................................... 128 1.11. IO Selector for Base Timer ............................................................................................... 129 1.12. QPRC ............................................................................................................................... 130 1.12.1. TYPE1-M4, TYPE2-M4 products ......................................................................... 130 1.12.2. TYPE3-M4, TYPE4-M4 products ......................................................................... 131 1.13. QPRC NF .......................................................................................................................... 132 1.14. A/DC ................................................................................................................................. 133 1.15. CR Trim ............................................................................................................................ 134 1.16. EXTI .................................................................................................................................. 134 1.17. INT-Req. READ ................................................................................................................ 135 1.17.1. TYPE1-M4, TYPE2-M4 products ......................................................................... 135 1.17.2. TYPE3-M4 product .............................................................................................. 141 1.17.3. TYPE4-M4 product .............................................................................................. 148 1.18. D/AC ................................................................................................................................. 155 1.19. HDMI-CEC ........................................................................................................................ 156 1.20. GPIO ................................................................................................................................. 157 1.20.1. TYPE1-M4, TYPE2-M4 products ......................................................................... 157 1.20.2. TYPE3-M4 product .............................................................................................. 164 1.20.3. TYPE4-M4 product .............................................................................................. 173 1.21. LVD ................................................................................................................................... 181 1.22. DS_Mode .......................................................................................................................... 181 1.23. USB Clock ........................................................................................................................ 182 1.24. CAN_Prescaler ................................................................................................................. 183 1.25. MFS .................................................................................................................................. 183 1.26. CRC .................................................................................................................................. 185 1.27. Watch Counter .................................................................................................................. 185 1.28. RTC .................................................................................................................................. 186 1.28.1. TYPE1-M4, TYPE2-M4, TYPE3-M4 products ..................................................... 186 1.28.2. TYPE4-M4 product .............................................................................................. 189 1.29. Low-speed CR Prescaler .................................................................................................. 193 February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 9 P E R I P H E R A L M A N U A L 1.30. Peripheral Clock Gating .................................................................................................... 194 1.30.1. TYPE1-M1, TYPE2-M4 products ......................................................................... 194 1.30.2. TYPE3-M4, TYPE4-M4 products ......................................................................... 194 1.31. I2S Prescaler .................................................................................................................... 195 1.31.1. TYPE1-M4, TYPE2-M4, TYPE3-M4 products ..................................................... 195 1.31.2. TYPE4-M4 product .............................................................................................. 196 1.32. GDC_Prescaler ................................................................................................................. 197 1.33. EXT-Bus I/F ...................................................................................................................... 198 1.33.1. TYPE1-M4 product .............................................................................................. 198 1.33.2. TYPE3-M4, TYPE4-M4 products ......................................................................... 201 1.34. USB .................................................................................................................................. 204 1.35. DMAC ............................................................................................................................... 206 1.36. DSTC ................................................................................................................................ 208 1.37. CAN .................................................................................................................................. 210 1.38. Ethernet-MAC ................................................................................................................... 212 1.39. Ethernet-Control................................................................................................................ 212 1.40. I2S .................................................................................................................................... 213 1.41. SD-Card ............................................................................................................................ 213 1.42. CAN FD ............................................................................................................................ 214 1.43. Programmable-CRC ......................................................................................................... 217 1.44. WorkFlash_IF.................................................................................................................... 217 1.45. Hi-Speed Quad SPI controller ........................................................................................... 218 1.45.1. TYPE1-M4, TYPE2-M4, TYPE3-M4 products ..................................................... 218 1.45.2. TYPE4-M4 product .............................................................................................. 221 1.46. HyperBus Interface ........................................................................................................... 224 1.47. GDC Sub system controller .............................................................................................. 225 1.48. GDC Sub system SDRAM controller................................................................................. 228 Major Changes ........................................................................................................................................... 230 10 CONFIDENTIAL FM4_MN709-00014-1v0-E, February 2, 2015 CHAPTER 1: Overview This chapter gives an overview of the GDC subsystem. 1. Overview 2. Block Diagram 3. Function Summary : February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 11 CHAPTER 1: Overview 1. Overview P E R I P H E R A L 1. M A N U A L Overview 1.1 Feature Summary 1.1.1 General Features 1.1.2 Controller for external graphics display. Accelerator for 2D block image transfer (blit) operations. Embedded SRAM video memory. Multilayer GDC bus matrix with master and slave ports. Signature computation for display content (use: data integrity/safety requirements) Command Sequencer for graphic operations. Quad SPI (Serial Peripheral Interface) for external memory extensions. SDRAM interface for external memory extensions. HBI (Hyper Bus Interface) interface for external memory extensions. Two processing pipeline (blit / display). Maximum core system clock frequency: Refer to the Data sheet. Display Controller 1.1.2.1 1.1.2.2 Display Output Stream One display output stream. Up to 24-bit color resolution (RGB). TTL mode. Video modes up to SVGA @ 60 Hz (see Functional Limitations for details). Timing controller with up to 12 signal generators. Spatial and temporal dithering for low resolution panels. Gamma correction. Can select on-the-fly between two independent input streams (content and safety stream). Can overlay both input streams (e.g. for safety HMI). Signature unit (CRC checksum; up to 2 independent windows) for each display. Panic mode (autonomous change of stream configuration in response to system events). 1-bit alpha mask per pixel for one of - Transparent stream overlay. - Masked color correction. - Masked signature computation. 2 Background Plane in Total 1 x constant color. 1.1.2.3 2 Foreground Planes with 9 Layers in Total 1 x integral plane (1 layer; optionally compressed). 1 x fractional plane (composed from up to 8 layers with independent display buffers). 1.1.2.4 Alpha Blending Stage for Each Plane Configurable blending sequence for planes. All layers from 1x1 pixel to max supported frame dimension. 12 CONFIDENTIAL FM4_MN709-00014-1v0-E, February 2, 2015 CHAPTER 1: Overview 1. Overview P E R I P H E R A L 1.1.2.5 1.1.2.6 M A N U A L Display Buffer Formats RGBA, Grayscale. Source alpha, constant alpha, transparent alpha (any combination). Color index (256 x 24 bit palette). Compressed (lossless: RL or RLA; lossy: RLAD). 1, 2, 4, 8, 16, 18, 24, 32 bits per pixel word (packed in memory). All color channels at any bit position in pixel word (configurable). Bit width of all color channels between 0 .. 8 bits (configurable). Configurable scan direction (90/180/270° rotation; horizontal/vertical flip). Other Features All configuration registers shadowed. Individual shadow load for each layer (synchronized to display refresh). 1.1.3 Blit Engine 1.1.3.1 1.1.3.2 1.1.3.3 1.1.3.4 Operations Fill. Copy. Blend (compliant to OpenGL, OpenVG and OpenWF). Rop2/3 (any logic operation). Scale (any factor). Rotate (any angle). Linear color conversion (a programmable 3x3 matrix). Non-linear color conversion (programmable look-up per component). Pixel format conversion (from any to any of all supported formats listed below). Source Pixel Formats RGBA, Grayscale. Source alpha, constant alpha, transparent alpha, mask alpha (any combination). Color index (256 x 24 bit palette). Compressed (lossless: RL or RLA; lossy: RLAD). 1, 2, 4, 8, 16, 18, 24, 32 bits per pixel word (packed in memory). All color channels at any bit position in pixel word (configurable). Bit width of all color channels between 0 .. 8 bits (configurable). Configurable scan direction (90/180/270° rotation; horizontal/vertical flip). Destination Pixel Formats RGBA, Grayscale. Pre-multiplied alpha. 1, 2, 4, 8, 16, 18, 24, 32 bits per pixel word (packed in memory). All color channels at any bit position in pixel word (configurable). Bit width of all color channels between 0 .. 8 bits (configurable). Other Features Any image size from 1x1 pixel to max supported dimension (see Functional Limitations). All operations with 8-bit precision per color channel. Source and destination buffer stride in bytes. Source buffer clip window. Lot of functions can be combined with single-pass blit (e.g. rotate + blend). All configuration registers shadowed (can set up next operation during blit). February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 13 CHAPTER 1: Overview 1. P E R I P H E R A L 2. M A N U A L Block Diagram Figure 2-1 Block Diagram of the GDC Subsystem GDC Sub system HBI I/O PAD SDRAM I/O PAD AHB32L master interface QSPI I/O PAD AHB32L slave interface DDR I/F embedded SRAM Asynchronous FIFO HyperBus I/F SDRAM I/F Ttree Fetch Units One Store Unit Config Two Fetch Units GDC Core Asynchronous FIFO Pixel Engine Core Display engine core Config Write Agent CmdSeq Core AHB32L BUS I/F AXI32W AXI64R AXI Interconnect AXI64R Performance Analyzer AHB32L BUS I/F AXI64W AXI64R AXI64R Bus Monitor BUS I/F Config QSPI I/F AHB32L BUS I/F AXI64R SPI Control core Config Subsysctrl Read Agent Config Clocks / Resets signal Ref. clock for AIX VRAM I/F SDRAM Control core Config Ref. clock for peripherals VRAM I/F core AXI32R HBI core System control Core IRQ Synchonizer reference Clock Selecter Panel I/F IO PAD 14 CONFIDENTIAL Config IRQ Global FM4_MN709-00014-1v0-E, February 2, 2015 CHAPTER 1: Overview 3. Function Summary P E R I P H E R A L 3. M A N U A L Function Summary 3.1 Reference Clock Selector Reference clock selector selects reference clock for GDC clock and reference clock for peripherals. 3.1.1 Reference Clock for GDC Clock Clock source can be selected for GDC clock: GDC PLL output clock. Main PLL output clock. HCLK. 3.1.2 Reference Clock for Peripherals Clock source can be selected for peripherals that are clock for display controller, HyperBus Interface, SDRAM controller, and QSPI controller: GDC PLL output clock. HCLK. 3.1.3 Software Reset Reference clock selector generates software reset signal for the GDC subsystem. Note: − 3.2 Reference clock for GDC clock and reference clock for peripherals should be stopped as negating software reset. Subsystem Controller (subsysctrl) Subsystem controller generates clocks from reference clock for GDC clock: GDC clock that is used as GDC core clock. Configuration clock for control / status register in the GDC core (CFGCLK). Subsystem controller also generates clocks from reference clock for peripherals. 3.3 Display clock using a fixed point divider. HyperBus interface controller clock using an integral divider. SDRAM controller clock using an integral divider. QSPI controller clock using an integral divider. GDC Core Refer to FM4 Family Peripheral Manual GDC Core part. 3.4 HS-SPI External Memory Interface Refer to FM4 Family Peripheral Manual Communication Part. Notes: − Both Mode0 and Mode4 are supported in the GDC subsystem. Mode1 ,2, and 3 are not supported in the GDC subsystem. − To set Mode4, set 1 to ACES field of the HSSPIn_PCC0, HSSPIn_PCC1, HSSPIn_PCC2, and HSSPIn_PCC3. Mode4 can be set in Command Sequencer Mode only. RTM=1 mode is not supported in the GDC subsystem. − − February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 15 CHAPTER 1: Overview 3. Function Summary P E R I P H E R A L 3.5 M A N U A L SDRAM External Memory Controller Refer to FM4 Family Peripheral Manual. 3.6 HyperBus Interface Refer to FM4 Family Peripheral Manual Communication Part. 16 CONFIDENTIAL FM4_MN709-00014-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector This chapter explains the functions and operations of the reference clock selector 1. Overview 2. Block Diagram 3. Operation 4. Registers February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 17 CHAPTER 2: Reference Clock Selector 1. Overview P E R I P H E R A L 1. M A N U A L Overview This section describes the overview of the reference clock selector module. 1.1 Feature Summary Reference clock selector selects reference clocks for the GDC subsystem. Reference clocks consist of reference clock for GDC clock and reference clock for peripherals. 1.1.1 Reference Clock for GDC Clock Clock source can be selected for GDC clock: GDC PLL output clock Main PLL output clock HCLK GDC clock is divided from reference clock for GDC clock, division ratio 1 and 2 to 255, in the GDC subsystem control module. 1.1.2 Reference Clock for Peripherals Clock source can be selected for peripherals that are clock for display controller, HyperBus Interface, SDRAM controller, and QSPI controller: GDC PLL output clock HCLK − Display clock is divided from Reference Clock for Peripherals, division ratio 2.0 to 255.99609375, in the GDC subsystem control module. − Clock for SDRAM interface controller and QSPI interface controller is divided from Reference Clock for Peripherals, division ration 2 to 255, in the GDC subsystem control module. − Clock for HyperBus interface is divided from Reference Clock for Peripherals, division ration 4 to 32 in the GDC subsystem control module. − 1.1.3 Software Reset Reference Clock Selector generates software reset signal for the GDC subsystem. Note: − 18 CONFIDENTIAL Reference Clock for GDC clock and Reference Clock for Peripherals should stop providing as negating software reset. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 2. Block Diagram P E R I P H E R A L 2. M A N U A L Block Diagram Figure 2-1 Block Diagram of the Reference Clock Selector Reference Clock Selector GDC PLL Main Oscillation circuit K frequency division High-speed CR Oscillation circuit PLL IN PLL Analog PLL OUT FB reg *1 N frequency division reg *2 reg *3 Reference clock for GDC clock CLKPLL Base clock (HCLK) reg *4 Reference clock for peripherals reg *5 reg *6 *1: GPCR1: GPINC (GDC PLL input clock select bit) *2: GSSEN: GCCR (GSS clock output enable bit) *3: GSCR: ACG (Clock gating for Reference clock for GDC clock) *4: GSCR: ASEL (Reference clock for the GDC clock select bit) *5: GCSR: PCG (HCLK Clock gating for Reference clock for Peripherals) *6: GCSR: PSEL (Peripheral clock for the GDC subsystem select bit) February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 19 CHAPTER 2: Reference Clock Selector 3. Operation P E R I P H E R A L 3. M A N U A L Operation This section describes the operation of the Reference Clock Selector module. 3.1 Clock Set up Reference clock set up for the GDC subsystem is illustrated in Figure 3-1. Make sure to operate this flow to set GDC and peripheral clock appropriately. Figure 3-1 Reference Clock Setup Flow Start Reference clocks settings YES Is GSS used in TIMER-mode? Set GCCR.GSSEN=0 NO Read the GCCR Register GCCR.GSSEN=0 ? Set GMCR.TEN=0 NO YES Set GPCR1.GPLLEN=0 Set IPINT_CLR.IPCSC=1 CLKHC Set GPCR1.GPLLEN=1 CLKMO Set GPCR1.GPINC=0 NO Is an interrupt used? YES PLL Clock source? Set GMCR.TEN=1 Set GPCR1.GPLLEN=1 No interrupt Set GPCR1.GPINC=1 Wait interrupt GP_STR.GPRDY=1? Interrupt assert Set GPCR2.GPOWT NO YES IRQ handler NO GPINT_STR.GPCSI=1 ? Set GPCR3.GPLLK YES Set GPCR4.GPLLN Set GPINT_CLR.GPCSC=1 (Error) Check the settings Set GCSR.ASEL and GCSR.PSEL Set GCCR.GSSEN=1 Set GCSR.ACG and GCSR.PCG End of Reference clocks setting 20 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 3. Operation P E R I P H E R A L 3.2 M A N U A L Setting the Multiplication Ratio to generate output clock of GDC PLL Each frequency division clock in the PLL Multiplication Circuit must be set using GPCR3 and GPCR4. The Table provides example of frequency setting. Table 3-1 Example of PLL Multiplication Ratio Setting Input Clock K PLLin N PLLOUT_GDC 4 MHz 1 4 MHz 49 200 MHz 4 MHz 1 4 MHz 59 240 MHz 4 MHz 1 4 MHz 69 280 MHz 4 MHz 1 4 MHz 79 320 MHz 4 MHz 1 4 MHz 89 360 MHz 4 MHz 1 4 MHz 99 400 MHz 5 MHz 1 5 MHz 39 200 MHz 5 MHz 1 5 MHz 49 250 MHz 5 MHz 1 5 MHz 59 300 MHz 5 MHz 1 5 MHz 69 350 MHz 5 MHz 1 5 MHz 79 400 MHz 6 MHz 1 6 MHz 39 240 MHz 6 MHz 1 6 MHz 49 300 MHz 6 MHz 1 6 MHz 59 360 MHz 8 MHz 1 8 MHz 24 200 MHz 8 MHz 1 8 MHz 29 240 MHz 8 MHz 1 8 MHz 39 320 MHz 8 MHz 1 8 MHz 49 400 MHz 10 MHz 1 10 MHz 19 200 MHz 10 MHz 1 10 MHz 24 250 MHz 10 MHz 1 10 MHz 29 300 MHz 10 MHz 1 10 MHz 34 350 MHz 10 MHz 1 10 MHz 39 400 MHz 12 MHz 1 12 MHz 19 240 MHz 12 MHz 1 12 MHz 24 300 MHz 12 MHz 1 12 MHz 29 360 MHz 16 MHz 1 16 MHz 14 240 MHz 16 MHz 2 8 MHz 49 400 MHz 19.2 MHz 2 9.6 MHz 29 288 MHz 19.2 MHz 2 9.6 MHz 39 384 MHz 20 MHz 2 10 MHz 39 400 MHz 48 MHz 3 16 MHz 19 320 MHz 48 MHz 4 12 MHz 29 360 MHz 48 MHz 6 8 MHz 39 320 MHz Notes: − − For PLL characteristics, see the data sheet of the product used. Set the PLLin within the value PLL input clock frequency: fPLLI shown in the data sheet. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 21 CHAPTER 2: Reference Clock Selector 3. Operation P E R I P H E R A L 3.3 M A N U A L Reset Setup Hardware and software setup for the GDC subsystem is illustrated in Figure 3-2 Hardware and Software Reset Setup. Figure 3-2 Hardware and Software Reset Setup Hardware Reset Reference Clocks setting Interrupt setting/ factor force clear? Want to change the Reference Clocks setting? NO NO YES Set GCSR=0x0000 YES APB2 Bus-Reset enable (Set APBC2_PSR.APBC2RST=1) Set GCCR.GSSEN=0 APB2 Bus-Reset disable (Set APBC2_PSR.APBC2RST=0) Set GPCR1.GPLLEN=0 Set GRCR.RSTEN=1 Read the APBC2_PSR Register Set GRCR.RSTEN=0 APBC2_PSR. APBC2RST=0 ? YES NO Read the GRCR Register NO GRCR.RSTEN=0 ? YES Reference Clocks setting End 22 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4. M A N U A L Registers This section describes the registers of the reference clock selector in detail. Registers of the Reference Clock Selector The following registers are available for each instance of the module. Abbreviation Reference GCCR GDC Clock Control Register 4.1 GPCR1 GDC PLL Control Register 1 4.2 GPCR2 GDC PLL Control Register 2 4.3 GPCR3 GDC PLL Control Register 3 4.4 GPCR4 GDC PLL Control Register 4 4.5 GP_STR GDC PLL Status Register 4.6 GPINT_ENR GDC PLL Interrupt Enable Register 4.7 GPINT_CLR GDC PLL Interrupt Clear Register 4.8 GPINT_STR GDC PLL Interrupt Status Register 4.9 GCSR GDC Clock Select Register 4.10 GRCR GDC Reset Control Register 4.11 GMCR GDC Mode Control Register 4.12 February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL Register Name 23 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.1 M A N U A L GCCR The GCCR enables/disables output of the GDC PLL. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. GSSEN Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b000000 is read from these bits. Set 0b000000 to these bits when writing. [bit0] GSSEN: GSS clock output enable/disable setting bit bit Description 0 Disables output of the GDC PLL 1 Enables output of the GDC PLL. Note: − 24 CONFIDENTIAL This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.2 M A N U A L GPCR1 The GPCR1 selects PLL input clock and enables/disables the PLL oscillation. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. GPINC GPLLEN Attribute - R/W R/W Initial value 0b0000000 0b0 0b0 Register functions [bit7:2 Reserved: Reserved bits 0b000000 is read from these bits. Set these bits to 0b000000 when writing. [bit1] GPINC: GDC PLL input clock selection bit bit Description 0 Selects CLKMO (main clock oscillation) 1 Selects CLKHC (high-speed CR clock) Note: − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. [bit0] GPLLEN: GDC PLL enable/disable setting bit bit Description 0 Disables oscillation. 1 Enables oscillation. Note: − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 25 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.3 M A N U A L GPCR2 The GPCR2 sets the PLL clock stabilization wait time. Register configuration bit 7 6 5 4 3 2 1 Field Reserved. Attribute - R/W Initial value 0b00000 0b000 0 GPOWT Register functions [bit7:3] Reserved: Reserved bits 0b00000 is read from these bits. Set these bit to 0b00000 when writing. [bit2:0] GPOWT: PLL clock stabilization wait time set up bits bit[2:0] Description 000 29 cycles 001 210 cycles (Approx. 256 µsec, Fin = 4 MHz) 010 211 cycles (Approx. 512 µsec, Fin = 4 MHz) 011 212 cycles (Approx. 1024 µsec, Fin = 4 MHz) 100 213 cycles (Approx. 2048 µsec, Fin = 4 MHz) 101 214 cycles (Approx. 4096 µsec, Fin = 4 MHz) 15 (Approx. 128 µsec, Fin = 4 MHz) 110 2 cycles 111 216cycles (Approx. 16384 µsec, Fin = 4 MHz) (Approx. 8192 µsec, Fin = 4 MHz) Note: − 26 CONFIDENTIAL This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.4 M A N U A L GPCR3 The GPCR3 sets the PLL frequency division ration. Register configuration bit 7 6 5 4 3 2 Field Reserved Attribute - R/W Initial value 0b000 0b00000 1 0 GPLLK Register functions [bit7:5] Reserved: Reserved bits 0b000 is read from these bits. Set these bits to 0b000 when writing. [bit4:0] GPLLK: PLL input clock frequency division ration setting bits bit[4:0] Description 00000 1/1 00001 1/2 00010 1/3 1/(bit[4:0] + 1) 11111 1/32 Note: − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 27 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.5 M A N U A L GPCR4 The GPCR4 sets the PLL frequency division ratio. Register configuration bit 7 6 5 4 3 Field Reserved. Attribute - R/W Initial value 0b0 0b0000000 2 1 0 GPLLN Register functions [bit7] Reserved: Reserved bit 0b0 is read from this bit. Set this bit to 0b0 when writing. [bit6:0] GPLLN: PLL feedback frequency division ratio setting bits bit[6:0] Description 000000 setting is prohibited 000001 setting is prohibited setting is prohibited 0001011 setting is prohibited 0001100 1/13 0001101 1/14 1/(GPLLN[6:0] + 1) 0011111 1/32 010000 setting is prohibited setting is prohibited 1111111 setting is prohibited Note: − 28 CONFIDENTIAL This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.6 M A N U A L GP_STR The GP_STR indicates status of the PLL. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. GPRDY Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b0000000 is read from these bits. Set 0b000000 to these bits when writing. [bit0] GPRDY: GDC PLL status bit This bit indicates status of GDC PLL. bit Description 0 No PLL oscillation stabilization wait completion has been asserted 1 A PLL oscillation stabilization wait completion has been asserted Note: − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 29 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.7 M A N U A L GPINT_ENR The GPINT_ENR enables/disables interrupts. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. GPCSE Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b0000000 is read from these bits. Set 0b0000000 to these bits when writing. [bit0] GPCSE: PLL oscillation stabilization wait completion interrupt enable bit bit Description 0 Disables PLL oscillation stabilization wait completion interrupts 1 Enables PLL oscillation stabilization wait completion interrupts Note: − 30 CONFIDENTIAL This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.8 M A N U A L GPINT_CLR The GPINT_CLR clears interrupt factor. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. GPCSC Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b0000000 is read from these bits. Set 0b000000 to these bits when writing. [bit0] GPCSC: GDC PLL oscillation stabilization wait completion interrupt clear bit bit Description 0 Not affected 1 Clears GDC PLL oscillation stabilization wait complete interrupt factor. Note: − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 31 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L 4.9 M A N U A L GPINT_STR The GPINT_STR indicates the status of interrupts. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. GPCSI Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b0000000 is read from these bits. Set 0b0000000 to these bits when writing. [bit0] GPCSI: GDC PLL oscillation stabilization wait completion interrupt status bit bit Description 0 No PLL oscillation stabilization wait completion interrupt has been asserted 1 PLL oscillation stabilization wait completion interrupt has been asserted Note: − 32 CONFIDENTIAL This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L M A N U A L 4.10 GCSR The GCSR enables/disables output of GDC clock and peripheral clock. The GCSR also selects clock sources for GDC reference clock and peripheral reference clock. Register configuration bit 15 14 13 12 11 10 9 8 Field Reserved. PCG Reserved. PSEL Attribute - R/W - R/W Initial value 0b000 0b0 0b000 0b0 bit 7 Field 6 5 4 3 2 1 Reserved. 0 Reserved. ACG ASEL Attribute - R/W - R/W Initial value 0b000 0b0 0b00 0b00 Register functions [bit15:13] Reserved: Reserved bits 0b000 is read from these bits. Set 0b000 to these bits when writing. [bit12] PCG: HCLK Clock gating for Reference clock for Peripherals setting bit bit Description 0 Disables output of reference clock for peripherals 1 Enables output of reference clock for peripherals Notes: − − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. As operate PSEL field, write '0' to this field to stop providing Reference Clock of peripherals clock to the GDC subsystem. [bit11:9] Reserved: Reserved bits 0b000 is read from these bits. Set 0b000 to these bits when writing. [bit8] PSEL: Peripheral clock for the GDC subsystem selection bit bit Description 0 Selects output of GDC PLL 1 Selects HCLK Note: − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. [bit7:5] Reserved : Reserved bits 0b000 is read from these bits. Set 0b000 to these bits when writing. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 33 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L M A N U A L [bit4] ACG: Clock gating for Reference clock for GDC clock setting bit bit Description 0 Disables output of reference clock for GDC 1 Enables output of reference clock for GDC Notes: − − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. As operate ASEL field or wait for PLL oscillation stabilization, write 0 to this field to stop providing reference clock of GDC clock. [bit3:2] Reserved: Reserved bits “0b00” is read from these bits. Set “0b00” to these bits when writing. [bit1:0] ASEL: Reference clock for the GDC clock selection bits These bits select Reference clock for GDC clock. bit1:0 Description 00 Selects output clock of GDC PLL 01 Selects HCLK 10 Selects output clock of Main PLL 11 Selects HCLK Note: − 34 CONFIDENTIAL These bits initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L M A N U A L 4.11 GRCR The GRCR sets software reset for the GDC subsystem control. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. RESETN Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b0000000 is read from these bits. Set 0b0000000 to these bits when writing. [bit0] RSTEN: Software reset for the GDC subsystem setting bit bit Description 0 Releases Software reset 1 Enables software reset Notes: − − This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. Reference clock for GDC clock and Reference clock for peripherals should be stopped before releasing, writing 0 to the field of RESETN, Software reset. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 35 CHAPTER 2: Reference Clock Selector 4. Registers P E R I P H E R A L M A N U A L 4.12 GMCR The GMCR enables/disables GDC PLL oscillation in case of Timer mode. Register configuration bit 7 6 5 4 3 2 1 0 Field Reserved. TEN Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit7:1] Reserved: Reserved bits 0b0000000 is read from these bits. Set 0b0000000 to these bits when writing. [bit0] TEN: PLL oscillation in case of Timer mode control bit bit Description 0 Stop oscillation in case of Timer mode 1 Continue PLL status in case of Timer mode Note: − 36 CONFIDENTIAL This bit initialized by CRGRSTOUT_N, not initialized by PRESETn. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control This chapter explains the functions and operations of the GDC Subsystem control 1. Overview 2. Block Diagram 3. Function and Operation 4. Registers February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 37 CHAPTER 3: Subsystem Control 1. Overview P E R I P H E R A L 1. M A N U A L Overview This section describes the overview of the GDC subsystem control. 1.1 Feature Summary 38 CONFIDENTIAL GDC clock divider CONFIG clock divider HyperBus interface clock divider SDRAM interface clock divider QSPI interface clock divider FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 2. Block Diagram P E R I P H E R A L 2. M A N U A L Block Diagram Figure 2-1 Block Diagram of the Subsystem Control Reference Clock for the GDC clock Reference Clock Selector PLL for the GDC Sub system Main Oscillation circuit K frequency division High-speed CR Oscillation circuit PLL IN PLL Analog PLL OUT FB reg N frequency division reg reg CLKPLL Base clock (HCLK) Reference Clock for the peripherals reg DIV 2 to 255 frequency division (default 4) reg reg reg Sub system control GDC clock *1 DIV 2 to 8 frequency division (default 2) DIV 2.0 to 255.996 frequency division (default 65.875) reg *2 DISPLAY clock reg *3 DIV 2 to 255 frequency division (default 4) reg *4 SDRAM interface clock reg *5 DIV 2 to 255 frequency division (default 4) reg *6 DIV 4 to 32 frequency division (default 4) reg CONFIG clock QSPI interface clock reg *7 HyperBus interface clock *8 *1: GDC_ClcokDivider: GDCClockSelect (Division ration of GDC clock generation from the Reference clock for GDC clock) *2: dsp0_ClockDivider: dsp0ClockDivider (Division ratio from the Reference clock for peripherals) *3: dsp0_DomaonControl: dsp0_ClockEnable (Display clock output control) *4: SDRAMC_ClockDivider: SDRAMC_ClockDivider (Division ratio from the Reference clock for peripherals) *5: SDRAMC_DomainControl: SDRAMC_ClockEnable (SDRAM interface clock output control) *6: HSSPIC_ClockDivider: HSSPIC_ClockDivider (Division ratio from the Reference clock for peripherals) *7: HSSPIC_DomainControl: HSSPIC_ClockEnable (Division ratio from the Reference clock for peripherals) *8: RPCC_ClockDivider: RPCC_ClockDivider (Division ratio from the Reference clock for peripherals) February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 39 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3. M A N U A L Function and Operation This section describes function and operation of the GDC subsystem control module. 3.1 Overview This subsection describes configuration of each clock in the GDC subsystem. 3.1.1 Reference Clocks Reference clock for GDC GDC clock and CONFIG clock are generated from this reference clock. The source clock for reference clock can be selected from three clock sources. For more information, refer to Chapter 2. Reference clock for peripherals. Clocks for peripherals are generated from this reference clock. The source clock for reference clock can be selected from two clock sources. For more information, refer to Chapter 2. 3.1.2 GDC Clock GDC clock is used for GDC core and GDC bus operation mainly. 3.1.3 CONFIG Clock CONFIG clock is used for configuration register operation in the GDC core. 3.1.4 Peripheral Clocks Peripheral clocks are generated from the Reference clock for Peripherals. dsp0 clock dsp0 clock is used for operation of display controller in the GDC core. Dot clock Dot clock is output for external TFT panel. This clock is divided by 2 automatically at the display controller in the GDC core. SDRAM interface clock SDRAM interface clock is used for operation of SDRAM controller in the GDC subsystem, and external SDRAM devices. QSPI interface clock QSPI interface clock is used for operation of QSPI controller in the GDC subsystem, and external QSPI devices. HyperBus interface clock The HyperBus interface clock is used for operation of the HyperBus controller in the GDC subsystem, and external HyperBus devices. 40 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3.2 M A N U A L GDC Clock Set up The GDC clock frequency used in the GDC subsystem can be setup using register field GDCClockSelect in the GDC subsystem control module. It specifies the divider used to generate the GDC clock from the reference clock for GDC clock. The reference clock for GDC clock is selected in the Reference Clock Selector module. Configuration of the GDC clock can be modified during operation. How to set up GDC clock. 1. Select the Reference clock for GDC. For more information, refer to Chapter 2. 2. Set Division ratio to the register field of GDCClockSelect in the register of GDC_ClockDivider. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 41 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3.3 M A N U A L CONFIG Clock Set up The CONFIG clock frequency used in the GDC subsystem can be setup using register field ConfigClockSelect in the GDC subsystem control module. It specifies the divider used to generate the CONFIG clock from GDC clock only. The minimum allowed divider setting can select divided clock from 2 to 8. The CONFIG clock is generated form GDC clock automatically. There is not a procedure to generate the CONFIG clock. The CONFIG clock can be changed at any time (even when transfers are in progress), but note that configuration access bandwidth and latency are greatly influenced by this setting. The CONFIG clock is generated automatically as the GDC clock key in the divider. No other register modifications are needed. 3.4 Display Clock Set up There is one display clock management unit available in the GDC subsystem Control module of the GDC subsystem. It contains clock generation utility to generate the display clock from the reference clock for peripherals by using a fixed point divider. In addition the generated display clock can be shifted against the output display data to allow creation of sufficient margin for setup and hold times at the connected external device. The display clock and clock can be changed at any time (even when transfers are in progress). 3.4.1 Display Clock Generation and Reset Control The display clock generation can create the display clock from the input reference clock by application of a fixed point divider. To determine the best possible display clock frequency divide the reference clock frequency by a multiple of 2 of the desired display clock frequency round this value to a fixed point with 8 decimal places and program the result to register field dsp0_ClockDivider. Then set register field dsp0_ClockEnable in the register of dsp0_DomainControl to 1 to start generation of the display clock. The field dsp0_ClockDivider can be updated at any point in time (even when dsp0_ClockEnable is set to 1 and the display clock is output). The display clock generation will then update the generated clocks frequency in such a manner that continuity of the generated display clock is guaranteed (for example, no glitches are produced). In addition, to enabling the dsp0_ClockEnable setting the dsp0_SoftwareReset should be set to 0 to release the reset of the display logic and make it functional. Write dsp0_SoftwareReset to 1 only when the display engine has been completely shut down. Note: − 42 CONFIDENTIAL Use of the generated display clock for display clock output is only allowed if the GDC core DisEngCfg ClockCtrl setting is set to DIV2. Do not set this to DIV1. For more information, refer to the Peripheral Manual GDC (Core) part. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3.4.2 M A N U A L Display Clock Shift To allow creating sufficient margin for setup and hold times at the external device the output display clock can be shifted. The dsp0_Clock Offset setting can shift the display clock up to (not including) 180 degrees in reference clock period steps. To achieve shifts larger or equal to 180 degrees the dsp0_ClockInvert setting can be used in addition to add 180 degrees to the shift achieved with dsp0ClockOffset. It is recommended to verify the achieved margins in setup and hold times by using eg an oscilloscope. Note that the generated display clock periods can jitter from cycle to cycle by the reference clock period due to the way the fixed point clock division works. The dsp0_ClockOffset and dsp0_ClockInvert settings must not be changed when dsp0_ClockEnable is set to 1. Otherwise corruption of displayed content is possible. 3.4.3 How to Set up Display clock 1. Select the reference clock for peripherals. For more information, refer to Chapter 2. 2. Set division ratio to the field of dsp0_ClockDivider in the register of the dsp0_ClockDivider. 3. Set 0b1 to the field of dsp0_clockEnable in the register of dsp0_DomainControl to start provide the display clock to the display controller in the GDC core. 4. Wait for 0b1 of the register field of DspClockDomainReady in the register of ClockDomainStatus to make sure the display clock domain ready. 5. After hardware or software reset, set 0b0 to the field of dsp0_Software Reset in the register of the dsp_DomainControl to activate display controller in the GDC core. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 43 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3.5 M A N U A L HyperBus Interface Clock Set up The HyperBus interface clock frequency used in the GDC subsystem can be setup using register field RPCC_ClockDivider in the GDC subsystem control module. It specifies the divider used to generate the clock from reference clock for peripheral only. After setting the register field RPCC_ClockDiver, to provide the HyperBus interface clock, the register field RPCC_ClockEnable in the RPCC_DomainControl should be set 1. The HyperBus interface clock cannot be changed in operating the HyperBus Interface. To change the frequency the HyperBus interface clock: 1. 2. 3. 4. 3.6 Write 0 to the register field RPCC_ClockEnable in the register of RPCC_DomainControl. Stop providing the reference clock for peripheral. Modify the register field RPCC_ClockDivider in the register of RPCC_ClockDivider. Write 1 to the register field RPCC_ClockEnable in the register of RPCC_DomainControl. SDRAM Interface Clock Setup The SDRAM interface clock frequency used in the GDC subsystem can be setup using register field SDRAMC_ClockDivider in the register of SDRAMC_ClockDivider in the GDC subsystem control module. It specifies the divider used to generate the clock from reference clock for peripherals only. After setting the register field of SDRAMC_ClockDivider, to provide the SDRAM interface clock, the register field SDRAMC_ClockEnable in the SDRAMC_DomainControl should be set 1. After hardware reset or software reset, to activate SDRAM controller, write 0 to register field SDRAMC_SoftwareReset in the SDRAMC_DomainControl. The SDRAM interface clock can be changed in operating SDRAM interface. Notes: − − 3.7 Decimal part of the SDRAMC_ClockDivider field should be “0x00”. To shut down the SDRAM controller, setting 1 to the field of SDRAMC_SoftwareReset can be allowed. To re-activate the SDRAM controller, setting 0 again to the field cannot be allowed. QSPI Interface Clock Setup The QSPI interface clock frequency used in the GDC subsystem can be setup using register field HSSPIC_ClockDivider in the GDC subsystem control module. It specifies the divider used to generate the clock from reference clock for peripheral only. The clock frequency generated by this divider has to be two times of the output clock frequency of external QSPI interface. After setting the register field HSSPIC_ClockDivider, to provide the QSPI interface clock, the register field HSSPIC_ClockEnable in the HSSPIC_DomainControl should be set 1. After hardware reset or software reset, to activate HSSPI controller, write 0 to register field HSSPIC_SoftwareReset in the HSSPIC_DomainControl. The QSPI interface clock can be changed in operating QSPI interface. Notes: − − 44 CONFIDENTIAL Decimal part of the SDRAMC_ClockDivider field should be 0x00. To shut down the QSPI controller, setting 1 to the field of HSSPIC_SoftwareReset can be allowed. To re-activate the SDRAM controller, setting 0 again to the field cannot be allowed. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3.8 M A N U A L Clock Frequency Setup Example Examples of clock set up are described in this section. Note: − 3.8.1 To make sure maximum frequency of each clock, refer to related data sheet. Example1 3.8.1.1 Register Field Setting Register Field Setting Value Remarks GSSEN *1 0b1 Enables output of CLKPLL_GDC GPINC *1 0b0 Selects external main oscillator for PLL_GDC input clock. In this case, the GPLLEN *1 0b0 Enables PLL_GDC GPOWT *1 0b000 Sets PLL_GDC output clock stabilization time to Approx. 128 µsec GPLLK *1 1 Input clock PLL_GDC sets 4 MHz GPLLN *1 99 PLL_GDC generates 400 MHz clock PCG *1 0b0 This field does not need to be set to 1 PSEL *1 0b0 Selects PLL_GDC output for Reference clock for peripherals ACG *1 0b0 This field does not need to be set to 1. ASEL *1 0b00 Selects PLL_GDC output for Reference clock for GDC RESETN *1 0b0 Disables software reset for GDC subsystem. TEN *1 0b0 Stop oscillation as Timer mode. GDCClockSelect *2 0x0300 Sets division ratio 3.0 for generating GDC clock CNFIGClockSelect *2 0b001 Sets division ratio 2 for generation CONFIG clock dsp0_Clock_Divider *2 0x2150 Sets division ratio 33.3125 for generating dsp0 clock SDRAMC_ClockDivider *2 0x0500 Sets division ratio 5.0 for generating SDRAM interface clock RPCC_ClockDivider *2 0b000 Set division ration 4 for generating HyperBus interface clock external main oscillator generates 4 MHz clock for example. *1: Refer to Chapter 2.4 for more information. *2: Refer to Chapter 3.4 for more information. 3.8.1.2 Output Frequency of Each Clock Output Clock Frequency Remarks GDC clock 133 MHz 400 MHz divided by 3.0 equals 133 MHz CONFIG clock 66 MHz 133 MHz divided by 2 equals 66 MHz dsp0_clock 12.0075 MHz 400 MHz divided by 33.3125 equals 12.0075 MHz Dot clock for external TFT 6.00375 MHz Dot clock frequency for external TFT panel is divided by 2 in the GDC Core SDRAM interface clock 80 MHz 400 MHz divided by 5.0 equals 80 MHz HyperBus interface clock 100 MHz 400 MHz divided by 4 equals 80 MHz automatically. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 45 CHAPTER 3: Subsystem Control 3. Function and Operation P E R I P H E R A L 3.8.2 M A N U A L Example2 3.8.2.1 Register Field Setting Register Field Setting Value Remarks GSSEN *1 0b1 Enables output of CLKPLL_GDC GPINC *1 0b0 Selects external main oscillator for PLL_GDC input clock. In this case, the GPLLEN *1 0b0 Enables PLL_GDC GPOWT *1 0b000 Sets PLL_GDC output clock stabilization time to Approx. 128 µsec GPLLK *1 2 Input clock PLL_GDC sets 10 MHz GPLLN *1 31 PLL_GDC generates 320 MHz clock PCG *1 0b0 This field does not need to be set to 1/ PSEL *1 0b0 Selects PLL_GDC output for Reference clock for peripherals ACG *1 0b0 This field does not need to be set to 1. ASEL *1 0b00 Selects PLL_GDC output for Reference clock for GDC RESETN *1 0b0 Disables software reset for GDC subsystem. TEN *1 0b0 Stop oscillation as Timer mode. GDCClockSelect *2 0x0200 Sets division ratio 2.0 for generating GDC clock CNFIGClockSelect *2 0b001 Sets division ratio 2 for generation CONFIG clock dsp0_Clock_Divider *2 0x1A90 Sets division ratio 26.5625 for generating dsp0 clock SDRAMC_ClockDivider *2 0x0400 Sets division ratio 4.0 for generating SDRAM interface clock HSSPIC_ClockDivider *2 0x0200 Set division ration 4 for generating HyperBus interface clock external main oscillator generates 20 MHz clock for example. *1: Refer to Chapter 2.4 for more information. *2: Refer to Chapter 3.4 for more information. 3.8.2.2 Output Frequency of Each Clock Output Clock Frequency Remarks CLKPLL_GDC 320 MHz GDC clock 160 MHz 320 MHz divided by 2.0 equals 160 MHz CONFIG clock 80 MHz 160 MHz divided by 2 equals 80 MHz dsp0_clock 12.0075 MHz 320 MHz divided by 26.5625 equals 12.047 Dot clock for external TFT 6.02352 MHz Dot clock frequency for external TFT panel is divided by 2 in the GDC Core automatically. SDRAM interface clock 80 MHz 320 MHz divided by 4.0 equals 80 MHz QSPI interface clock 160 MHz 320 MHz divided by 2.0 equals 160 MHz. Clock frequency for external QSPI memories is divided by 2 in the QSPI interface controller automatically. 46 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4. M A N U A L Registers This section describes function and operation of the register for software interface of the GDC subsystem control module. Notes: − − The registers in this module can be accessed by word only. Either byte access or half word access causes a bus error response. Registers of the subsystem Control The following registers are available for each instance of the module. Abbreviation Register Name LockUnlock 4.1 LockStatus LockStatus 4.2 TEST (Reserved) TEST (Reserved) 4.3 CnfigClockControl CnfigClockControl 4.4 VRamInterruptEnable VRamInterruptEnable 4.5 TEST (Reserved) TEST (Reserved) 4.6 VraminterruptClear VraminterruptClear 4.7 VramInterruptStatus VramInterruptStatus 4.8 ExtFlashDevSelect ExtFlashDevSelect 4.9 VramRemapDisable VramRemapDisable 4.10 PanicSwitch PanicSwitch 4.11 GDC_ClockDivider GDC_ClockDivider 4.12 WkupTriggerMask WkupTriggerMask 4.13 ClockDomainStatus ClockDomainStatus 4.14 Abbreviation Register Name Reference dsp0_LockUnlock dsp0_LockUnlock 4.15 dsp0_LockStatus dsp0_LockStatus 4.16 dsp0_ClockDivider dsp0_ClockDivider 4.17 dsp0_DomainControl dsp0_DomainControl 4.18 dsp0_ClockShift dsp0_ClockShift 4.19 TEST (Reserved) TEST (Reserved) 4.20 dsp0_PowerEnControl dsp0_PowerEnControl 4.21 dsp0_ClockGateModeControl dsp0_ClockGateModeControl 4.22 dsp0_ClockGateControl dsp0_ClockGateControl 4.23 February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL Reference LockUnlock 47 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L Abbreviation Register Name CONFIDENTIAL Reference SDRAMC_ClockDivider SDRAMC_ClockDivider 4.24 SDRAMC_DomainControl SDRAMC_DomainControl 4.25 HSSPIC_ClockDivider HSSPIC_ClockDivider 4.26 HSSPIC_DomainControl HSSPIC_DomainControl 4.27 RPCC_ClockDivider RPCC_ClockDivider 4.28 RPCC_DomainControl RPCC_DomainControl 4.29 Abbreviation 48 M A N U A L Register Name Reference vram_LockUnlock vram_LockUnlock 4.30 vram_LockStatus vram_LockStatus 4.31 vram_sram_select vram_sram_select 4.32 TEST (Reserved) TEST (Reserved) 4.33 TEST (Reserved) TEST (Reserved) 4.34 TEST (Reserved) TEST (Reserved) 4.35 TEST (Reserved) TEST (Reserved) 4.36 TEST (Reserved) TEST (Reserved) 4.37 TEST (Reserved) TEST (Reserved) 4.38 TEST (Reserved) TEST (Reserved) 4.39 TEST (Reserved) TEST (Reserved) 4.40 vram_aberraddr_s0 vram_aberraddr_s0 4.41 vram_aberraddr_s1 vram_aberraddr_s1 4.42 vram_arbiter_priority vram_arbiter_priority 4.43 FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.1 M A N U A L LockUnlock The LockUnlock writes key codes of this address block. The protection status is changed by writing one of the following key values to this field. Writing illegal key code results a bus error response. This register can be written during operation. Register configuration bit 31 30 29 28 27 Field LockUnlock Attribute W Initial value 0x00 bit 23 22 21 20 Field 19 W Initial value 0x00 15 14 13 12 11 Field LockUnlock Attribute W Initial value 0x00 bit 25 24 18 17 16 10 9 8 2 1 0 LockUnlock Attribute bit 26 7 6 5 Field 4 3 LockUnlock Attribute W Initial value 0x00 Register functions [bit31:0] LockUnlock : Protection key of this address block setting bits The protection status is changed by writing one of the following key values to this field. When lock protection is active, no write but only read access is possible to all registers of this address block. When privilege protection is active, only privileged read and write access is possible. Both protections can be active at the same time. Reading this register results in an error response. bit[31:0] 0x5651F763 Description lock_key: Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. 0x691DB936 unlock_key: Increments the unlock counter. Max allowed value is 15 0xAEE95CDC privilege_key: Enables privilege protection. Disabled after reset. 0xB5E2466E unprivilege_key: Disables privilege protection. 0xFBE8B1E6 freeze_key: Freezes current protection status. Writing keys to this register has no more effect until reset. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 49 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.2 M A N U A L LockStatus The LockStatus indicates protection status of this address block Register configuration bit 31 30 29 28 Field R Initial value 0x00 23 22 21 20 Field 25 24 19 18 17 16 11 10 9 8 Reserved Attribute R Initial value 0x00 bit 26 Reserved Attribute bit 27 15 14 13 12 Field Reserved Freeze Attribute R R Initial value 0b0000000 0b0 Status bit 7 6 5 4 3 Privilege 2 Reserved 1 0 Field Reserved Attribute R R R R Initial value 0b000 0b0 0b000 0b0 Status Lock Status Register functions [bit31:9] Reserved: Reserved bits [bit8] FreezeStatus: Current status of freeze status bit Description 0 Protection status can be changed 1 Cannot be changed [bit7:5] Reserved: Reserved for future use [bit4] PrivilegeStatus: Current status of privilege protection bit Description 0 Current status of privilege protection is inactive. 1 Current status of privilege protection is active. [bit3:1] Reserved: Reserved bits [bit0] LockStatus: Current status of lock protection bit 50 CONFIDENTIAL Description 0 Current status of lock protection is inactive. 1 Current status of lock protection is active. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.3 M A N U A L TEST (Reserved) This register is implemented for internal device test purposes. When writing this register, it should be set to the initial value. Register configuration bit 31 29 28 27 26 Field Reserved Reserved Attribute R/W R/W Initial value 0x2 0x2 bit 23 22 21 20 19 18 Field Reserved Reserved Attribute R/W R/W Initial value 0x4 0x4 bit 15 14 13 12 11 10 Field Reserved Reserved Attribute R/W R/W Initial value 0x1 0x4 bit 7 6 5 4 3 2 Field Reserved Reserved Attribute R/W R/W Initial value 0x1 0x0 February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 30 25 24 17 16 9 8 1 0 51 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.4 M A N U A L CnfigClockControl CnfigClockControl sets CONFIG clock generation. This register can be written during operation. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 20 Field Attribute 0x00 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 4 Field Reserved ConfigClockSelect Attribute - R/W Initial value 0b00000 0b001 Register functions [bit31:8] Reserved: Reserved bits 0x000000 is read from these bits. Set 0x000000 to these bits when writing. [bit7:3] Reserved: Reserved bits 0b00000 is read from these bits. Set 0b00000 to these bits when writing. [bit2:0] ConfigClockSelect: CONFIG Clock division ratio setting bits bit[2:0] 52 CONFIDENTIAL Description 000 Reserved. Do not set this value. 001 Division ratio : 2. 010 Division ratio : 3. 011 Division ratio : 4. 100 Division ratio : 5. 101 Division ratio : 6. 110 Division ratio : 7. 111 Division ratio : 8. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.5 M A N U A L VRamInterruptEnable The VramInterruptEnable enables/disables interrupt of VRAM ECC error. Register cofiguration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 11 10 9 8 3 2 Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field Reserved Attribute - Initial value 0x00 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 7 6 5 Field 4 Reserved 1 0 VramInterr VramInterr uptEnable uptEnable Sec1 Sec0 Attribute - R/W R/W Initial value 0b000000 0b1 0b1 Register functions [bit31:8] Reserved: Reserved bits 0x000000 is read from these bits. Set 0x000000 to these bits when writing. [bit7:2] Reserved: Reserved bits 0b000000 is read from these bits. Set 0b000000 to these bits when writing. [bit1] VramInterruptEnableSec1: Interrupt control of VRAM ECC error for VRAM port1 bit Description 0 Disable interrupt 1 Enable interrupt Note: − This field can be programmed only once after reset. A second attempt at programming this will cause an error response and no change to the enable. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 53 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit0] M A N U A L VramInterruptEnableSec0: Interrupt control of VRAM ECC error for VRAM port0 bit Description 0 Disable interrupt 1 Enable interrupt Note: − 54 CONFIDENTIAL This field can be programmed only once after reset. A second attempt at programming this will cause an error response and no change to the enable. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.6 M A N U A L TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 11 10 9 8 3 2 Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field Reserved Attribute - Initial value 0x00 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 1 0 Field bit 7 6 5 Reserved 4 Reserved Reserved Attribute - W W Initial value 0b000000 0b0 0b0 Register functions [bit31:2] Reserved: Reserved bits Do not read these bits. Set initial value to these bits when writing. [bit1] Reserved: (for internal device test purposes) bit Description 0 (for internal device test purpose) 1 (for internal device test purpose) Note: − This field can be written as 0b0 only. [bit0] Reserved: (for internal device test purposes) bit Description 0 (for internal device test purpose) 1 (for internal device test purpose) Note: − This field can be written as 0b0 only. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 55 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.7 M A N U A L VramInterruptClear The VramInterruptClear clears interrupt of VRAM ECC error. Register configuration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 11 10 9 8 Reserved Attribute - Initial value 0x0 bit 23 22 21 20 Field Reserved Attribute - Initial value 0x0 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x0 bit 7 6 Field 5 4 3 2 Reserved 1 0 VramInterru VramInterrupt ptClearSec1 ClearSec0 Attribute - W W Initial value 0b000000 0b0 0b0 Register function [bit31:2] Reserved: Reserved bits Do not read these bits. Set the initial value to these bits when writing. [bit1] VramInterruptClearSec1: Clear interrupt register bit Description 0 Do not write 0b0 to this field. 1 Clear interrupt field of VramInterruputStatusSec1 in the VramInterrupt status register. Note: − This field can be written as 0b1 only. [bit0] VramInterruptClearSec0: Clear interrupt register bit Description 0 Do not write 0b0 to this field. 1 Clear interrupt field of VramInterruputStatusSec1 in the VramInterrupt status register. Note: − 56 CONFIDENTIAL This field can be written as 0b1 only. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.8 M A N U A L VRamInterrunptStatus VRamInterruptStatus indicates status of VRAM ECC error interrupt. Register configuration bit 31 30 29 28 Field - Initial value 0x0 23 22 21 20 Field Attribute 0x0 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 Reserved Attribute - Initial value 0x0 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 Field 4 3 2 Reserved 1 0 VramInterrupt VramInterrupt StatusSec1 StatusSec0 Attribute - R R Initial value 0b000000 0b0 0b0 Register function [bit31:2] Reserved: Reserved bits The initial value if read from these bits. Do not write to these bits. [bit1] VramInterruptStatusSec1: Indicator of VRAM Interrupt status bit Description 0 No interrupt of VRAM ECC error at VRAM access port1. 1 Caused interrupt of VRAM ECC error at VRAM access port1 [bit0] VramInterruptClearSec0: Indicator of VRAM Interrupt status bit Description 0 No interrupt of VRAM ECC error at VRAM access port1 has been asserted. 1 Interrupt of VRAM ECC error at VRAM access port1 has been asserted. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 57 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L 4.9 M A N U A L ExtFlashDevSelect ExtFlashDevSelect selects either QSPI flash or HyperFlash as external flash memory. register configuration bit 31 30 29 28 Field - Initial value 0x0 23 22 21 20 Field Attribute 0x0 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 Reserved Attribute - Initial value 0x0 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 4 3 2 1 0 Field Reserved ExtFlashDevSelect Attribute - R/W Initial value 0b0000000 0b1 Register functions [bit31:1] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] ExtFlashDevSelect: External memory device selection bit bit 58 CONFIDENTIAL Description 0 Selects HyperFlash as external flash memory. 1 Selects QSPI flash as external flash memory. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.10 VramRemapDisable VramRemapDisable sets either VRAM remap mode or VRAM non-remap mode. Register configuration bit 31 30 29 28 Field - Initial value 0x0 23 22 21 20 Field Attribute 0x0 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 Reserved Attribute - Initial value 0x0 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 4 3 2 1 0 Field Reserved VramRemapDisable Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit31:1] Reserved: Reserved bits The initial value is read from these bits Set the initial value to these bits when writing. [bit0] VramRemapDisable: VRAM address remap or non-remap selection bit bit Description 0 Selects remap mode. 1 Selects non-remap mode. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 59 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.11 PanicSwitch PanicSwitch selects either Panic display mode or normal display mode. Register configuration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 11 10 9 8 3 2 Reserved Attribute - Initial value 0x0 bit 23 22 21 20 Field Reserved Attribute - Initial value 0x0 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x0 bit 7 6 5 4 1 0 Field Reserved PanicSwitch Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit31:1] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] PanicSwitch: Panic display mode or normal display mode selection bit bit Description 0 Disable panic display mode. 1 Enable panic display mode. . Note: − 60 CONFIDENTIAL For more information, Refer to the Peripheral Manual GDC (Core) part. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.12 GDC_ClockDivider GDC_ClockDivider sets GDC clock generation. Register configuration bit 31 30 29 28 Field Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 27 26 25 24 19 18 17 16 10 9 8 2 1 0 GDCClockSelect(integral part) Attribute R/W Initial value 0x04 bit 15 14 13 Field 12 11 GDCClockSelect(decimal part) Attribute R/W Initial value 0x00 bit 7 6 5 Field 4 3 Reserved Attribute - Initial value 0x00 [bit31:24] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit23:8] GDCClockSelect: Controls GDC clock generation. Notes: − − − This field must set at least 2.0. The decimal part of this field can be written 0x00 only. This field can be written during operation. [bit7:0] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 61 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.13 WkupTriggerMask Wkup TrigerMask is a register to mask the CPU wake-up trigger, which is used to transfer from timer-mode to run-mode. For details about Timer-mode, refer to FM4 Family Peripheral Manual. This register can be written during operation. Register configuration bit 31 30 26 25 24 Reserved WTrigMaskRpc WtrigMaskSdram WTrigMaskQspi Attribute - R/W R/W R/W Initial value 0b00000 0b0 0b0 0b0 Field bit 23 29 28 22 27 21 20 19 18 17 Field Reserved Attribute - R/W Initial value 0b00000 0b000 bit 15 14 13 WTrigMaskGe 12 Field 11 10 9 8 2 1 0 WTrigMaskGe Attribute R/W Initial value 0x00 bit 16 7 6 5 Field 4 3 WTrigMaskGe Attribute R/W Initial value 0x00 Register function [bit31:27] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit26] WtrigMaskRpc: Wake up trigger mask for HyperBus interface Wake-up trigger mask setting for CPU- low power consumption mode. This bit corresponds to IENOn of HyperBus interface. bit Description 0 Disable wake up trigger. 1 Enable wake up trigger. [bit25] WtrigMaskSdram: Wake up trigger mask for SDRAM interface Wake-up trigger mask setting for CPU- low power consumption mode. This bit corresponds to MerrInt of SDRAM interface. bit 62 CONFIDENTIAL Description 0 Disable wake up trigger. 1 Enable wake up trigger. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit24] M A N U A L WtrigMaskQspi: Wake up trigger mask for QSPI interface Wake-up trigger mask setting for CPU- low power consumption mode. This bit corresponds to IRQ_FAULT of QSPI interface. bit Description 0 Disable wake up trigger. 1 Enable wake up trigger. [bit23:19] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit18:0] WTrigMaskGe: Wake up trigger mask for GDC Core Wake-up trigger mask setting for CPU- low power consumption mode. Each bit corresponds to irq[18:0] of the GDC core interrupts. bit18:0 Description 0 Disable wake up trigger. 1 Enable wake up trigger. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 63 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.14 ClockDomainStatus ClockDomainstatus indicates status of each clock domain. Make sure these four bits are set to 1 before accessing the bits’ corresponding domains. Accessing domains that are not yet operational causes bus to lock. Register configration bit 31 30 29 28 Field Attribute - Initial value 0x0 bit 23 22 21 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Hsspi Rpc Sdram DspClock Clock Clock Clock Domain Domain Domain Domain Ready Ready Ready Ready 20 Field Reserved Attribute - Initial value 0x0 bit 27 Reserved 15 14 13 12 Field Reserved Attribute - Initial value 0x0 bit 7 Field 6 5 Reserved 4 Attribute - R/W R/W R/W R/W Initial value 0x0 0b0 0b0 0b0 0b0 Register functions [bit31:4] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit3] HsspiClockDomainReady: Clock status of QSPI interface clock domain bit Description 0 This clock domain is not ready 1 This clock domain can be operated [bit2] RpcClockDomainReady: Clock status of HyperBus interface clock domain bit 64 CONFIDENTIAL Description 0 This clock domain is not ready 1 This clock domain can be operated FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit1] M A N U A L SdramClockDomainReady: Clock status of SDRAM interface clock domain bit Description 0 This clock domain is not ready 1 This clock domain can be operated [bit0] DspClockDomainReady: Clock status of Display clock domain bit Description 0 This clock domain is not ready 1 This clock domain can be operated February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 65 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.15 dsp_LockUnlock The dsp_LockUnlock writes key codes of this address block. The protection status is changed by writing one of the following key values to this field. Writing illegal key code results a bus error response. This register can be written during operation. Register configuration bit 31 30 29 28 27 Field dsp_LockUnlock Attribute W Initial value 0x00 bit 23 22 21 Field 20 19 W Initial value 0x00 15 14 13 12 11 Field dsp_LockUnlock Attribute W Initial value 0x00 bit 25 24 18 17 16 10 9 8 2 1 0 dsp_LockUnlock Attribute bit 26 7 6 5 Field 4 3 dsp_LockUnlock Attribute W Initial value 0x00 Register functions [bit31:0] dsp_LockUnlock : Protection key of this address block setting bits The protection status is changed by writing one of the following key values to this field. When lock protection is active, no write but only read access is possible to all registers of this address block. When privilege protection is active, only privileged read and write access is possible. Both protections can be active at the same time. Reading this register results in an error response. bit[31:0] 0x5651F763 CONFIDENTIAL lock_key: Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. 0x691DB936 unlock_key: Increments the unlock counter. Max allowed value is 15 0xAEE95CDC privilege_key: Enables privilege protection. Disabled after reset. 0xB5E2466E unprivilege_key: Disables privilege protection. 0xFBE8B1E6 66 Description freeze_key: Freezes current protection status. Writing keys to this register has no more effect until reset. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.16 dsp_LockStatus dsp_LockStatus indicates protection status of this address block Register configuraion bit 31 30 29 28 Field Reserved Attribute R Initial value 0x00 bit 23 22 21 20 Field 26 25 24 19 18 17 16 11 10 9 8 Reserved Attribute R Initial value 0x00 bit 27 15 14 13 Field 12 Reserved dsp_ Freeze Status Attribute R R Initial value 0b0000000 0b0 bit 7 Field 6 5 Reserved 4 3 dsp_ 2 Reserved 1 0 dsp_ Privilege Lock Status Status Attribute R R R R Initial value 0b000 0b0 0b000 0b0 Register functions [bit31:9] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit8] dsp_FreezeStatus: Current status of freeze status bit Description 0 Protection status can be changed 1 Cannot be changed [bit7:5] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 67 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit4] dsp_PrivilegeStatus: Current status of privilege protection bit Description 0 Current status of privilege protection is inactive. 1 Current status of privilege protection is active. [bit3:1] M A N U A L Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] dsp_LockStatus: Current status of lock protection bit 68 CONFIDENTIAL Description 0 Current status of lock protection is inactive. 1 Current status of lock protection is active. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.17 dsp0_ClockDivider dsp0_ClockDivider sets display Clock divider ratio. This register can be written during operation. Register configuration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 10 9 8 2 1 0 Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field dsp0_ClockDivider (integral part) Attribute R/W Initial value 0x41 bit 15 14 13 Field 12 11 dsp0_ClockDivider (decimal part) Attribute R/W Initial value 0xE0 bit 7 6 5 4 3 Field Reserved Attribute - Initial value 0x00 Register functions [bit31:24] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit23:8] dsp0_ClockDivider: Division ratio from the Reference clock for peripherals. bit15:0 Description 0x0200 Division ratio: 2.0 0x0201 Division ratio: 2.0 + 2-8 0x0202 Division ratio: 2.0 + 2-7 0x0203 Division ratio: 2.0 + 2 + 2 -7 -8 (Continued) 0xFFFF Division ratio: 255 + 2-1+ 2-2+ 2-3+ 2-4+ 2-5+ 2-6+ 2-7+ 2-8 Note − This field must set at least 2.0. [bit7:0] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 69 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.18 dsp0_DomainControl dsp0_DomainControl sets display clock domain control operation. Register configuration bit 31 30 29 28 Field 27 26 25 19 18 17 24 Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 Reserved 16 dsp0_ Software Reset Attribute - R/W Initial value 0b0000000 0b1 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 7 6 5 Field 11 10 9 8 3 2 1 0 4 Reserved dsp0_ Clock Enable Attribute - R/W Initial value 0b0000000 0b0 Register function [bit31:17] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit16] dsp0_SoftwareReset: Display clock domain software reset bit Description 0 Display clock domain operational. 1 Display clock domain in reset state. Note: − Setting 0 to this field can be allowed after either hardware reset or software reset only. [bit15:1] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] dsp0_ClockEnable: Display clock output control bit 70 CONFIDENTIAL Description 0 Disables display clock generation. 1 Enables display clock generation. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.19 dsp0_ClockShift The dsp0_ClockShift is a register for display clock shift. This register can be written during operation. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 Field 20 Attribute R/W 0x00 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 3 2 1 Reserved Attribute - Initial value 0x00 bit 25 dsp0_ClockOffset Initial value bit 26 Reserved Attribute bit 27 7 6 5 Field 4 Reserved 0 dsp0_ Clock Invert Attribute - R/W Initial value 0b0000000 0x1 Register functions [bit31:24] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit23:16] dsp0_ClockOffset: Display clock phase setting bits bit7:0 0x00 to 0xFF Description Sets the offset in reference clock cycles for the display clock output with reference to the data output. This has to be smaller than the integer part of dsp0_ClockDivider. This setting shift the data output to forward part of the display clock output. [bit31:24] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] dsp0_ClockInvert: Display clock polarity setting bit bit 0 1 Description Not invert display clock output. At this time, data output is toggled with reference to rise-edge of display clock. Invert display clock output. At this time, data output is toggled with reference to fall-edge of display clock. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 71 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.20 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field 27 26 25 19 18 17 24 Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 16 Reserved Reserved Attribute - R/W Initial value 0x00 0b0 bit 15 14 13 12 Field 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 7 Field Reserved 6 5 4 Reserved Attribute - R/W Initial value 0b0 0b0000000 [bit31:27] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit16] Reserved: (for internal device test purposes) Note: − This field can be written as 0b0 only. [bit15:7] Reserved: Reserved bit The initial value is read from these bits. Set the initial value to these bits when writing. [bit6:0] Reserved: (for internal device test purpose) Note: − 72 CONFIDENTIAL This field can be written as 0b0000000 only. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.21 dsp0_PowerEnControl The dsp0_PowerEnControl is a register for display Power Enable Signal Control. This register can be written during operation. Register configuration bit 31 30 29 28 Field Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field Attribute 0x00 15 14 13 12 Field 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved Attribute - Initial value 0x00 bit 26 Reserved Initial value bit 27 7 6 5 4 0 Field Reserved Power_ Attribute - R/W Initial value 0b0000000 0b0 Enable Register functions [bit31:1] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing [bit0] Power_Enable: Power control of external TFT panel setting bit bit Description 0 PowerEnable signal is held LOW 1 Assert PowerEnable signal HIGH February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 73 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.22 dsp0_ClockGateModeLock The dsp0_ClockGateModeLock is a register to change the protection to change dsp0_ClockGateControl value. Writing illegal key code or byte and half word access results an error response. This register can be written during operation. Register configuratiion bit 31 30 29 28 27 Field LockUnlock Attribute W Initial value 0x00 bit 23 22 21 20 Field 19 W Initial value 0x00 15 14 13 12 11 Field LockUnlock Attribute W Initial value 0x00 bit 25 24 18 17 16 10 9 8 2 1 0 LockUnlock Attribute bit 26 7 6 5 Field 4 3 LockUnlock Attribute W Initial value 0x00 Register functions [bit31:0] LockUnlock : Protection of this address block setting bits bit[31:0] 0x5651F763 CONFIDENTIAL Reset counter value is 1. 0x691DB936 unlock_key: Increments the unlock counter. Max allowed value is 15 0xAEE95CDC privilege_key: Enables privilege protection. Disabled after reset. 0xB5E2466E unprivilege_key: Disables privilege protection. 0xFBE8B1E6 74 Description lock_key: Decrements the unlock counter. When the counter value is null, lock protection is active. freeze_key: Freezes current protection status. Writing keys to this register has no more effect until reset. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.23 dsp0_ClockGateControl The dsp0_ClockGateControl is a register for display Clock Gate Control. This register can be written during operation. Register configuration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 11 10 9 8 3 2 Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field Reserved Attribute - Initial value 0x00 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 7 6 5 4 1 0 Field Reserved ClockGate_ Attribute - R/W Initial value 0b0000000 0b0 Enable Register functions [bit31:1] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] ClockGate_Enable: Dot clock for external TFT panel control bit bit Description 0 Enables output of Dot clock for external TFT panel. 1 Disables output of Dot clock for external TFT panel. Note: − To use this function, set TCON_CTRL_Bypass register in the GDC core to 0. For more information, refer to Peripheral Manual GDC (Core) part. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 75 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.24 SDRAMC_ClockDivider The SDRAMC_ClockDivider sets division ratio of SDRAM interface. This register can be written during operation. Register configuration bit 31 30 29 28 Field Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 27 26 25 24 19 18 17 16 10 9 8 2 1 0 SDRAMC_ClockDivider (integral part) Attribute R/W Initial value 0x04 bit 15 14 13 Field 12 11 SDRAMC_ClockDivider (decimal part) Attribute R/W Initial value 0x00 bit 7 6 5 Field 4 3 Reserved Attribute - Initial value 0x00 Register function [bit31:24] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit23:8] SDRAMC_ClockDivider: Division ratio from the Reference clock for peripherals. bit15:0 Description 0x0000 Do not set this value to this field. 0x0100 Do not set this value to this field. 0x0200 Division ratio : 2 0x0300 Division ratio : 3. 0x0400 Division ratio : 4. .(Continued) 0xFE00 Division ratio: 254. 0xFF00 Division ratio: 255 Notes: − − This field must set at least 2.0. The decimal part of this field can be written as 0x00 only. [bit7:0] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. 76 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.25 SDRAMC_DomainControl The SDRAMC_DomainControl sets operation of SDRAM interface clock domain. Register configuration bit 31 30 29 28 Field 27 26 19 18 25 24 Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 17 Reserved 16 SDRAMC_ Software Reset Attribute - R/W Initial value 0b0000000 0b1 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 7 6 5 Field 11 10 3 2 4 9 1 Reserved 8 0 SDRAMC_ Clock Enable Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit31:17] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit16] SDRAMC_SoftwareReset: Software for SDRAM interface clock domain bit Description 0 SDRAM interface clock domain operational. 1 SDRAM interface clock domain in reset state. Note: − Setting 0 to this field can be allowed after either hardware reset or software reset only. [bit15:1] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 77 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit0] SDRAMC_ClockEnable: M A N U A L SDRAM interface clock output control bit Description 0 Disables SDRAM interface clock generation. 1 Enables SDRAM interface clock generation. Note: − 78 CONFIDENTIAL This register can be written during operation. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.26 HSSPIC_ClockDivider The HSSPIC_ClockDivider sets division ratio of QSPI interface. This register can be written during operation. Register configuration bit 31 30 29 28 Field Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 27 26 25 24 19 18 17 16 10 9 8 2 1 0 HSSPIC_ClockDivider (integral part) Attribute R/W Initial value 0x04 bit 15 14 13 Field 12 11 HSSPIC_ClockDivider (decimal part) Attribute R/W Initial value 0x00 bit 7 6 5 Field 4 3 Reserved Attribute - Initial value 0x00 Register functions [bit31:24] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit23:8] HSSPIC_ClockDivider: Division ratio from the Reference clock for peripherals. bit15:0 Description 0x0000 Do not set this value to this field. 0x0100 Do not set this value to this field. 0x0200 Division ratio : 2 0x0300 Division ratio : 3. 0x0400 Division ratio : 4. .(Continued) 0xFE00 Division ratio: 254. 0xFF00 Division ratio: 255 Notes: − − This field must set at least 2.0. The decimal part of this field can be written as 0x00 only. [bit7:0] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 79 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.27 HSSPIC_DomainControl The HSSPI_DomainControl sets operation of QSPI interface clock domain. Register configuration bit 31 30 29 28 Field 27 26 19 18 25 24 Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field 17 Reserved 16 HSSPIC_ Software Reset Attribute - R/W Initial value 0b0000000 0b1 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 7 6 5 11 10 3 2 4 Field 9 1 Reserved 8 0 HSSPIC_ Clock Enable Attribute - R/W Initial value 0b0000000 0b0 Register functions [bit31:17] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit16] HSSPIC_SoftwareReset: QSPI interface clock domain software reset bit Description 0 QSPI interface clock domain operational. 1 QSPI interface clock domain in reset state. Note: − Setting 0 to this field can be allowed after either hardware reset or software reset only. [bit15:1] Reserved: Reserved bit The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] HSSPIC_ClockEnable: QSPI interface clock output control bit Description 0 Disables QSPI interface clock generation. 1 Enables QSPI interface clock generation. Note: − 80 CONFIDENTIAL This register can be written during operation. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.28 RPCC_ClockDivider The RPCC_ClockDivider sets division ratio of HyperBus interface. Register configuration bit 31 30 29 28 Field 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 23 22 21 20 Field Reserved Attribute - Initial value 0x00 bit 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 7 6 5 4 Field Reserved RPCC_ClockDivider Attribute - R/W Initial value 0x00 0b000 Register fuction [bit31:3] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit2:0] RPCC_ClockDivider: Division ratio from the Reference clock for peripherals. bit2:0 Description 000 Division ratio: 4 001 Division ratio: 8 010 Division ratio: 12 011 Division ratio: 16 100 Division ratio: 20 101 Division ratio: 24 110 Division ratio: 28 111 Division ratio: 32 Note: − This field cannot be written during operation. For modify contents of this field: 1. Stop providing the Reference clock for Peripherals. 2. Modify this field. 3. Restart providing the Reference clock for Peripherals. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 81 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.29 RPCC_DomainControl The RPCC_DomainControl sets operation of HyperBus interface clock domain. Register configuration bit 31 30 29 28 Field 27 26 25 19 18 17 24 Reserved Attribute - Initial value 0x00 bit 23 22 21 Field 20 16 Reserved Reserved Attribute - R/W Initial value 0x00 0x1 bit 15 14 13 12 Field 11 10 3 2 9 8 Reserved Attribute - Initial value 0x00 bit 7 6 5 Field 4 Reserved 1 0 RPCC_ ClockEnable Attribute - R/W Initial value 0x00 0x0 Register function [bit31:17] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. [bit16] Reserved: (for internal device test purpose) Note: − This field can only be written 0b1 only. [bit15:1] Reserved: Reserved for future use [bit0] RPCC_ClockEnable: HyperBus interface clock output control bit Description 0 Disables HyperBus interface clock generation. 1 Enables HyperBus interface clock generation. Note: − 82 CONFIDENTIAL This register can be written during operation. FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.30 vram_LockUnlock The vram_LockUnlock writes key codes of this address block. The protection status is changed by writing one of the following key values to this field. Writing illegal key code results a bus error response. This register can be written during operation. Register configuration bit 31 30 29 28 27 Field vram_LockUnlock Attribute W Initial value 0x00 bit 23 22 21 Field 20 19 W Initial value 0x00 15 14 13 12 11 Field vram_LockUnlock Attribute W Initial value 0x00 bit 25 24 18 17 16 10 9 8 2 1 0 vram_LockUnlock Attribute bit 26 7 6 5 Field 4 3 vram_LockUnlock Attribute W Initial value 0x00 Register functions [bit31:0] vram_LockUnlock: Protection key of this address block setting bit The protection status is changed by writing one of the following key values to this field. When lock protection is active, no write but only read access is possible to all registers of this address block. When privilege protection is active, only privileged read and write access is possible. Both protections can be active at the same time. Reading this register results in an error response. bit[31:0] 0x5651F763 Description lock_key: Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. 0x691DB936 unlock_key: Increments the unlock counter. Max allowed value is 15 0xAEE95CDC privilege_key: Enables privilege protection. Disabled after reset. 0xB5E2466E unprivilege_key: Disables privilege protection. 0xFBE8B1E6 freeze_key: Freezes current protection status. Writing keys to this register has no more effect until reset. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 83 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.31 vram_LockStatus The vram_LockStatus indicates protection status of this address block. Register configuration bit 31 30 29 28 Field R Initial value 0x00 23 22 21 20 Field 25 24 19 18 17 16 11 10 9 8 Reserved Attribute R Initial value 0x00 bit 26 Reserved Attribute bit 27 15 14 13 Field 12 Reserved vram_ Freeze Status Attribute R R Initial value 0b0000000 0b0 bit 7 Field 6 5 Reserved 4 3 vram_ 2 Reserved 1 0 vram_ Privilege Lock Status Status Attribute R R R R Initial value 0b000 0b0 0b000 0b0 Register functions [bit31:9] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. [bit8] vram_FreezeStatus: Current status of freeze status bit Description 0 Protection status can be changed 1 Cannot be changed [bit7:5] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. 84 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit4] M A N U A L vram_PrivilegeStatus: Current status of privilege protection bit Description 0 Current status of privilege protection is inactive. 1 Current status of privilege protection is active. [bit3:1] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. [bit0] vram_LockStatus: Current status of lock protection bit Description 0 Current status of lock protection is inactive. 1 Current status of lock protection is active. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 85 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.32 vram_sram_select The vram_sram_select sets the size of the ECC protected memory region selection. This register can be written before VRAM access. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 20 Field 25 24 19 18 17 16 11 10 9 8 Reserved. Attribute - Initial value 0x00 bit 26 Reserved. Attribute bit 27 15 14 13 12 Field Reserved. vram_sram_select Attribute - R/W Initial value 0x0 0x0 bit 7 6 5 Field 4 3 2 1 0 vram_sram_select Attribute R/W Initial value 0x00 Register functions [bit3:12] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. [bit11:0] vram_sram_select: Selects the size of the ECC protected region For detail, refer to Table 4-1, Table 4-2, Table 4-3, and Table 4-4. 86 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L Table 4-1 ECC Protected Region (1/4) sr am _se le c t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EC C - pr o t e c t e d u se r spac e EC C - u n pr o t e c t e d u se r spac e st ar t o ffse t end o ffse t c apac it y [KB] st ar t o ffse t end o ffse t c apac it y [KB] st ar t o ffse t end o ffse t c apac it y [KB] 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x00000 0x007F8 0x00FF8 0x017F8 0x01FF8 0x027F8 0x02FF8 0x037F8 0x03FF8 0x047F8 0x04FF8 0x057F8 0x05FF8 0x067F8 0x06FF8 0x077F8 0x07FF8 0x087F8 0x08FF8 0x097F8 0x09FF8 0x0A7F8 0x0AFF8 0x0B7F8 0x0BFF8 0x0C7F8 0x0CFF8 0x0D7F8 0x0DFF8 0x0E7F8 0x0EFF8 0x0F7F8 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 0x00800 0x01000 0x01800 0x02000 0x02800 0x03000 0x03800 0x04000 0x04800 0x05000 0x05800 0x06000 0x06800 0x07000 0x07800 0x08000 0x08800 0x09000 0x09800 0x0A000 0x0A800 0x0B000 0x0B800 0x0C000 0x0C800 0x0D000 0x0D800 0x0E000 0x0E800 0x0F000 0x0F800 0x00FF8 0x01FF8 0x02FF8 0x03FF8 0x04FF8 0x05FF8 0x06FF8 0x07FF8 0x08FF8 0x09FF8 0x0AFF8 0x0BFF8 0x0CFF8 0x0DFF8 0x0EFF8 0x0FFF8 0x10FF8 0x11FF8 0x12FF8 0x13FF8 0x14FF8 0x15FF8 0x16FF8 0x17FF8 0x18FF8 0x19FF8 0x1AFF8 0x1BFF8 0x1CFF8 0x1DFF8 0x1EFF8 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 0x00000 0x01000 0x02000 0x03000 0x04000 0x05000 0x06000 0x07000 0x08000 0x09000 0x0A000 0x0B000 0x0C000 0x0D000 0x0E000 0x0F000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1A000 0x1B000 0x1C000 0x1D000 0x1E000 0x1F000 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 512 508 504 500 496 492 488 484 480 476 472 468 464 460 456 452 448 444 440 436 432 428 424 420 416 412 408 404 400 396 392 388 February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL Re agio n r e se r ve d fo r EC C 87 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L Table 4-2 ECC Protected Region (2/4) sr am _se le c t 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 88 CONFIDENTIAL EC C - pr o t e c t e d u se r spac e st ar t o ffse t end o ffse t 0x00000 0xFFFFFFFFF8 0x00000 0x007F8 0x00000 0x00FF8 0x00000 0x017F8 0x00000 0x01FF8 0x00000 0x027F8 0x00000 0x02FF8 0x00000 0x037F8 0x00000 0x03FF8 0x00000 0x047F8 0x00000 0x04FF8 0x00000 0x057F8 0x00000 0x05FF8 0x00000 0x067F8 0x00000 0x06FF8 0x00000 0x077F8 0x00000 0x07FF8 0x00000 0x087F8 0x00000 0x08FF8 0x00000 0x097F8 0x00000 0x09FF8 0x00000 0x0A7F8 0x00000 0x0AFF8 0x00000 0x0B7F8 0x00000 0x0BFF8 0x00000 0x0C7F8 0x00000 0x0CFF8 0x00000 0x0D7F8 0x00000 0x0DFF8 0x00000 0x0E7F8 0x00000 0x0EFF8 0x00000 0x0F7F8 Re agio n r e se r ve d fo r EC C c apac it y [KB] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 st ar t o ffse t end o ffse t 0x00000 0xFFFFFFFFF8 0x00800 0x00FF8 0x01000 0x01FF8 0x01800 0x02FF8 0x02000 0x03FF8 0x02800 0x04FF8 0x03000 0x05FF8 0x03800 0x06FF8 0x04000 0x07FF8 0x04800 0x08FF8 0x05000 0x09FF8 0x05800 0x0AFF8 0x06000 0x0BFF8 0x06800 0x0CFF8 0x07000 0x0DFF8 0x07800 0x0EFF8 0x08000 0x0FFF8 0x08800 0x10FF8 0x09000 0x11FF8 0x09800 0x12FF8 0x0A000 0x13FF8 0x0A800 0x14FF8 0x0B000 0x15FF8 0x0B800 0x16FF8 0x0C000 0x17FF8 0x0C800 0x18FF8 0x0D000 0x19FF8 0x0D800 0x1AFF8 0x0E000 0x1BFF8 0x0E800 0x1CFF8 0x0F000 0x1DFF8 0x0F800 0x1EFF8 EC C - u n pr o t e c t e d u se r spac e c apac it y [KB] st ar t o ffse t end o ffse t c apac it y [KB] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 0x00000 0x01000 0x02000 0x03000 0x04000 0x05000 0x06000 0x07000 0x08000 0x09000 0x0A000 0x0B000 0x0C000 0x0D000 0x0E000 0x0F000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1A000 0x1B000 0x1C000 0x1D000 0x1E000 0x1F000 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 512 508 504 500 496 492 488 484 480 476 472 468 464 460 456 452 448 444 440 436 432 428 424 420 416 412 408 404 400 396 392 388 FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L Table 4-3 ECC Protected Region (3/4) sr am _se le c t 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 EC C - pr o t e c t e d u se r spac e st ar t o ffse t end o ffse t 0x00000 0xFFFFFFFFF8 0x00000 0x007F8 0x00000 0x00FF8 0x00000 0x017F8 0x00000 0x01FF8 0x00000 0x027F8 0x00000 0x02FF8 0x00000 0x037F8 0x00000 0x03FF8 0x00000 0x047F8 0x00000 0x04FF8 0x00000 0x057F8 0x00000 0x05FF8 0x00000 0x067F8 0x00000 0x06FF8 0x00000 0x077F8 0x00000 0x07FF8 0x00000 0x087F8 0x00000 0x08FF8 0x00000 0x097F8 0x00000 0x09FF8 0x00000 0x0A7F8 0x00000 0x0AFF8 0x00000 0x0B7F8 0x00000 0x0BFF8 0x00000 0x0C7F8 0x00000 0x0CFF8 0x00000 0x0D7F8 0x00000 0x0DFF8 0x00000 0x0E7F8 0x00000 0x0EFF8 0x00000 0x0F7F8 February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL Re agio n r e se r ve d fo r EC C c apac it y [KB] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 st ar t o ffse t end o ffse t 0x00000 0xFFFFFFFFF8 0x00800 0x00FF8 0x01000 0x01FF8 0x01800 0x02FF8 0x02000 0x03FF8 0x02800 0x04FF8 0x03000 0x05FF8 0x03800 0x06FF8 0x04000 0x07FF8 0x04800 0x08FF8 0x05000 0x09FF8 0x05800 0x0AFF8 0x06000 0x0BFF8 0x06800 0x0CFF8 0x07000 0x0DFF8 0x07800 0x0EFF8 0x08000 0x0FFF8 0x08800 0x10FF8 0x09000 0x11FF8 0x09800 0x12FF8 0x0A000 0x13FF8 0x0A800 0x14FF8 0x0B000 0x15FF8 0x0B800 0x16FF8 0x0C000 0x17FF8 0x0C800 0x18FF8 0x0D000 0x19FF8 0x0D800 0x1AFF8 0x0E000 0x1BFF8 0x0E800 0x1CFF8 0x0F000 0x1DFF8 0x0F800 0x1EFF8 EC C - u n pr o t e c t e d u se r spac e c apac it y [KB] st ar t o ffse t end o ffse t c apac it y [KB] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 0x00000 0x01000 0x02000 0x03000 0x04000 0x05000 0x06000 0x07000 0x08000 0x09000 0x0A000 0x0B000 0x0C000 0x0D000 0x0E000 0x0F000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1A000 0x1B000 0x1C000 0x1D000 0x1E000 0x1F000 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 512 508 504 500 496 492 488 484 480 476 472 468 464 460 456 452 448 444 440 436 432 428 424 420 416 412 408 404 400 396 392 388 89 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L Table 4-4 ECC Protected Region (4/4) sr am _se le c t 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 90 CONFIDENTIAL EC C - pr o t e c t e d u se r spac e st ar t o ffse t end o ffse t 0x00000 0xFFFFFFFFF8 0x00000 0x007F8 0x00000 0x00FF8 0x00000 0x017F8 0x00000 0x01FF8 0x00000 0x027F8 0x00000 0x02FF8 0x00000 0x037F8 0x00000 0x03FF8 0x00000 0x047F8 0x00000 0x04FF8 0x00000 0x057F8 0x00000 0x05FF8 0x00000 0x067F8 0x00000 0x06FF8 0x00000 0x077F8 0x00000 0x07FF8 0x00000 0x087F8 0x00000 0x08FF8 0x00000 0x097F8 0x00000 0x09FF8 0x00000 0x0A7F8 0x00000 0x0AFF8 0x00000 0x0B7F8 0x00000 0x0BFF8 0x00000 0x0C7F8 0x00000 0x0CFF8 0x00000 0x0D7F8 0x00000 0x0DFF8 0x00000 0x0E7F8 0x00000 0x0EFF8 0x00000 0x0F7F8 0x00000 0x0FFF8 Re agio n r e se r ve d fo r EC C c apac it y [KB] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 st ar t o ffse t end o ffse t 0x00000 0xFFFFFFFFF8 0x00800 0x00FF8 0x01000 0x01FF8 0x01800 0x02FF8 0x02000 0x03FF8 0x02800 0x04FF8 0x03000 0x05FF8 0x03800 0x06FF8 0x04000 0x07FF8 0x04800 0x08FF8 0x05000 0x09FF8 0x05800 0x0AFF8 0x06000 0x0BFF8 0x06800 0x0CFF8 0x07000 0x0DFF8 0x07800 0x0EFF8 0x08000 0x0FFF8 0x08800 0x10FF8 0x09000 0x11FF8 0x09800 0x12FF8 0x0A000 0x13FF8 0x0A800 0x14FF8 0x0B000 0x15FF8 0x0B800 0x16FF8 0x0C000 0x17FF8 0x0C800 0x18FF8 0x0D000 0x19FF8 0x0D800 0x1AFF8 0x0E000 0x1BFF8 0x0E800 0x1CFF8 0x0F000 0x1DFF8 0x0F800 0x1EFF8 0x10000 0x1FFF8 EC C - u n pr o t e c t e d u se r spac e c apac it y [KB] st ar t o ffse t end o ffse t c apac it y [KB] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 0x00000 0x01000 0x02000 0x03000 0x04000 0x05000 0x06000 0x07000 0x08000 0x09000 0x0A000 0x0B000 0x0C000 0x0D000 0x0E000 0x0F000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000 0x17000 0x18000 0x19000 0x1A000 0x1B000 0x1C000 0x1D000 0x1E000 0x1F000 - 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF 0x7FFFF - 512 508 504 500 496 492 488 484 480 476 472 468 464 460 456 452 448 444 440 436 432 428 424 420 416 412 408 404 400 396 392 388 384 FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.33 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 20 Field Attribute 0x00 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 Field 4 Reserved Attribute Initial value 0x00 Register functions [bit31:0] Reserved: (for internal device test purposes) These bits allow can be written as 0x00000000 only. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 91 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.34 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 20 Field Attribute 0x00 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 Field 4 Reserved Attribute Initial value 0x00 Register function [bit31:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000000 only. 92 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.35 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field 26 19 18 - Initial value 0x00 23 22 Field 21 20 Reserved Reserved Attribute - R/W Initial value 0x0 0x0 bit 15 14 13 12 Field 11 24 17 16 10 9 8 1 0 Reservedi Attribute R/W Initial value 0x00 bit 25 Reserved. Attribute bit 27 7 6 5 4 3 Field Reserved Attribute R/W Initial value 0x00 Register function [bit31:20] Reserved: Reserved bits The initial value is read from these bits. Set the initial value to these bits when writing. [bit19:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000 only. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 93 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.36 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field 26 19 18 - Initial value 0x00 23 22 Field 21 20 Reserved Reserved Attribute - R/W Initial value 0x0 0x0 bit 15 14 13 12 Field 11 24 17 16 10 9 8 1 0 Reserved Attribute R/W Initial value 0x00 bit 25 Reserved. Attribute bit 27 7 6 5 4 3 Field Reserved Attribute R/W Initial value 0x00 Register functions [bit31:20] Reserved: Reserved bit The initial value is read from these bits. Set the initial value to these bits when writing. [bit19:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000 only. 94 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.37 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 20 Field Attribute 0x00 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 Field 4 Reserved Attribute Initial value 0x00 Register function [bit31:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000000 only. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 95 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.38 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field - Initial value 0x00 23 22 21 20 Field Attribute 0x00 15 14 13 12 Field 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute - Initial value 0x00 bit 25 Reserved Initial value bit 26 Reserved Attribute bit 27 7 6 5 Field 4 Reserved Attribute Initial value 0x00 Register functions [bit31:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000000 only. 96 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.39 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field 26 19 18 - Initial value 0x00 23 22 Field 21 20 Reserved Reserved Attribute - R/W Initial value 0x0 0x0 bit 15 14 13 12 Field 11 24 17 16 10 9 8 1 0 Reserved Attribute R/W Initial value 0x00 bit 25 Reserved. Attribute bit 27 7 6 5 4 3 Field Reserved Attribute R/W Initial value 0x00 Register functions [bit31:20] Reserved: Reserved bits 0x000 is read from these bits. Set 0x000 to these bits when writing. [bit19:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000 only. February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 97 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.40 TEST (Reserved) This register is implemented for internal device test purposes. Register configuration bit 31 30 29 28 Field 26 19 18 - Initial value 0x00 23 22 Field 21 20 Reserved Reserved Attribute - R/W Initial value 0x0 0x0 bit 15 14 13 12 Field 11 24 17 16 10 9 8 1 0 Reserved Attribute R/W Initial value 0x00 bit 25 Reserved. Attribute bit 27 7 6 5 4 3 Field Reserved Attribute R/W Initial value 0x00 Register functions [bit31:20] Reserved: Reserved bits 0x000 is read from these bits. Set 0x000 to these bits when writing. [bit19:0] Reserved: (for internal device test purposes) These bits can be written as 0x00000 only. 98 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.41 vram_sberraddr_s0 The vram_sberraddr_s0 indicates GDC bus address of the read access at S0 interface which had a single-bit ECC error. Register configuration bit 31 30 29 28 27 Field vram_sberraddr_s0 Attribute R Initial value 0x00 bit 23 22 21 Field 20 19 Attribute R 0x00 15 14 13 Field 12 11 24 18 17 16 10 9 8 2 1 0 vram_sberraddr_s0 Attribute R Initial value 0x00 bit 25 vram_sberraddr_s0 Initial value bit 26 7 Field 6 5 4 3 vram_sberraddr_s0 Attribute R Initial value 0x00 Register function [bit31:0] vram_sberraddr_s0: Indicates address which had an ECC single bit error February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 99 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.42 vram_sberraddr_s1 The vram_sberraddr_s1 indicates GDC bus address of the read access at S1 interface which had a single-bit ECC error. Register configuration bit 31 30 29 28 27 Field vram_sberraddr_s1 Attribute R Initial value 0x00 bit 23 22 21 Field 20 19 Attribute R 0x00 15 14 13 Field 12 11 24 18 17 16 10 9 8 2 1 0 vram_sberraddr_s1 Attribute R Initial value 0x00 bit 25 vram_sberraddr_s1 Initial value bit 26 7 Field 6 5 4 3 vram_sberraddr_s1 Attribute R Initial value 0x00 Register function [bit31:0] 100 CONFIDENTIAL vram_sberraddr_s1: Indicates address which had an ECC single bit error FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L M A N U A L 4.43 vram_arbiter_priority The vram_arviter_priority assigns fixed arbitration priorities to each GDC bus slave interface. An interface with a higher priority will always win over an interface with a lower one. Interfaces with equal priorities will be round-robin arbitrated. This register can be written during operation. Register configuration bit 31 30 29 28 Field Attribute - Initial value 0x00 bit 23 22 21 20 Field - Initial value 0x00 15 14 13 12 Field Reserved Attribute - Initial value 0x00 bit 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved Attribute bit 27 Reserved 7 6 5 4 Field vram_priority_s2_read vram_priority_s1_read vram_priority_s0_read Attribute R/W R/W R/W vram_priority_s0_write R/W Initial value 0b00 0b00 0b00 0b00 Register function [bit31:8] Reserved: Reserved for future use The initial value is read from these bits. Set the initial value to these bits when writing. [bit7:6] vram_priority_s2_read: (for internal device test purpose) These bits allow writing 0b00 only. [bit5:4] vram_priority_s1_read bit1:0 Description 00 Highest priority 01 Second-highest priority 10 Third-highest priority 11 Lowest priority February 2, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 101 CHAPTER 3: Subsystem Control 4. Registers P E R I P H E R A L [bit3:2] vram_priority_s0_read bit1:0 Description 00 Highest priority 01 Second-highest priority 10 Third-highest priority 11 Lowest priority [bit1:0] vram_priority_s0_write bit1:0 102 CONFIDENTIAL M A N U A L Description 00 Highest priority 01 Second-highest priority 10 Third-highest priority 11 Lowest priority FM4_MN709-00019-1v0-E, February 2, 2015 CHAPTER 4: Software Interface This chapter explains Software Interface of the GDC Subsystem. 1. Map Tables February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 103 CHAPTER 4: Software Interface 1. Map Tables P E R I P H E R A L 1. M A N U A L Map Tables 1.1 Interrupt Map The given GDC Core ID is the bit number of the corresponding event as used in the Common Control configuration of the GDC Core module. 104 CONFIDENTIAL FM4_MN709-00014-1v0-E, February 2, 2015 CHAPTER 4: Software Interface 1. Map Tables P E R I P H E R A L M A N U A L Table 1-1 Interrupt Map Interrupt Type IRQ GDC Sub System GDC FM4Interrupt Core ID ID(IRQMON) (Reserved) (19) 92(bit8) This IRQ is controlled by the GDC Core. 20 Interrupt Name Interrupt Events IRQ Name irq[0] GDCCORE_CommandSequencer 21 22 23 24 IRQ irq[1] GDCCORE_BlitEngine This IRQ is controlled by the GDC Core. 0 93(bit8) 1 2 IRQ irq[2] (Reserved) - - 94(bit8) IRQ irq[3] GDCCORE_ContentStream0 This IRQ is controlled by the GDC Core. 3 95(bit8) 4 5 27 28 13 IRQ irq[4] GDC_SaftyStream0 This IRQ is controlled by the GDC Core. 6 96(bit8) 7 8 25 26 12 IRQ irq[5] GDC_DisplayStream0 This IRQ is controlled by the GDC Core. 9 97(bit8) 10 11 IRQ irq[6] GDC_Signature0 This IRQ is controlled by the GDC Core. 16 98(bit8) 17 18 IRQ irq[7] GDC_Display0_Sync0 IRQ irq[8] GDC_Display0_Sync1 IRQ irq[9] (Reserved) IRQ irq[10] IRQ irq[11] IRQ 14 99(bit8) 15 100(bit8) - - 101(bit8) (Reserved) - - 102(bit8) (Reserved) - - 103(bit8) irq[12] (Reserved) - - 104(bit8) IRQ irq[13] (Reserved) - - 105(bit8) IRQ irq[14] (Reserved) - - 106(bit8) IRQ irq[15] (Reserved) - - 107(bit8) IRQ irq[16] (Reserved) - - 108(bit8) IRQ irq[17] (Reserved) - 109(bit8) IRQ irq[18] VramEccError_or_GDCBusError VRAM_ECC_Disp or GDC_Bus_Error - 110(bit8) IRQ qspi_irq_rx FIP006.IRQ_RX HS_SPI_Tx_FIFO 120(bit8) IRQ qspi_irq_tx FIP006.IRQ_TX HS_SPI_Rx_FIFO 121(bit8) IRQ qspi_irq_fault FIP006.IRQ_FAULT HS_SPI 122(bit8) IRQ sdram_merrint BMEMCSE.MerrInt Sdramc_MerrInt 49(bit1) IRQ rpc_int RPC2.IENOn RPC2 Interrupt 123(bit8) February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL This IRQ is controlled by the GDC Core. Fault 105 CHAPTER 4: Software Interface 1. Map Tables P E R I P H E R A L 106 CONFIDENTIAL M A N U A L FM4_MN709-00014-1v0-E, February 2, 2015 Appendixes This chapter shows the register map, list of notes, limitations and product type list. A. Register Map February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 107 A. Register Map This chapter shows the register map. 1. Register Map 1.1. FLASH_IF 1.2. Unique ID 1.3. ECC Capture Address 1.4. Clock/Reset 1.5. HW WDT 1.6. SW WDT 1.7. Dual_Timer 1.8. MFT 1.9. PPG 1.10. Base Timer 1.11. IO Selector for Base Timer 1.12. QPRC 1.13. QPRC NF 1.14. A/DC 1.15. CR Trim 1.16. EXTI 1.17. INT-Req. READ 1.18. D/AC 1.19. HDMI-CEC 1.20. GPIO 1.21. LVD 1.22. DS_Mode 1.23. USB Clock 1.24. CAN_Prescaler 1.25. MFS 1.26. CRC 1.27. Watch Counter 1.28. RTC 1.29. Low-speed CR Prescaler 1.30. Peripheral Clock Gating 1.31. I2S Prescaler 1.32. GDC_Prescalar 1.33. EXT-Bus I/F 1.34. USB 1.35. DMAC 1.36. DSTC 1.37. CAN 1.38. Ethernet-MAC 1.39. Ethernet-Control 1.40. I2S 108 CONFIDENTIAL FM4_MN709-00019-1v0-E, February 2, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.41. SD-Card 1.42. CAN FD 1.43. Programmable-CRC 1.44. WorkFlash_IF 1.45. Hi-Speed Quad SPI controller 1.46. HyperBus Interface 1.47. GDC Sub system controller 1.48. GDC Sub system SDRAM controller CODE: 9BFREGMAP_FM4-J01.0 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 109 A. Register Map 1. Register Map P E R I P H E R A L 1. M A N U A L Register Map Register map is shown on the table every module/function. [How to read the each table] Module/function name and its base address Clock/Reset Base_Address: 0x4001_0000 Base_Address Register + Address +3 0x000 +2 - 0x004 +1 - - +0 SCM_CTL[B,H,W] - - 00000-0SCM_STR[B,H,W] - 00000-0- STB_CTL[B,H,W] 0x008 00000000 00000000 -------- ---0--00 0x00C - - RST_STR[B,H,W] -------0 00000-01 Initial value after reset -: Reserved area *: Test register area 1: Initial value is 1 0: Initial value is 0 X: Initial value is undefined -: Reserved bit Register name Access unit (B: byte, H: half word, W: word) Rightmost register address (For word-length access, the +0 column of the register is the LSB of the data.) Notes: − − − − − − − 110 CONFIDENTIAL The register table is represented in the little-endian. When performing a data access, the addresses should be as below according to the access size. Word access: Address should be multiples of 4 (least significant 2 bits should be 0x00) Half word access: Address should be multiples of 2 (least significant bit should be 0x0) Byte access: Do not access the test register area. Do not access the area that is not written in the register table. FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.1 M A N U A L FLASH_IF 1.1.1 TYPE1-M4, TYPE2-M4 products FLASH_IF Base_Address : 0x4000_0000 Register Base_Address + Address +3 +2 0x000 FASZR[B,H,W] 0x004 FRWTR[B,H,W] 0x008 FSTR[B,H,W] 0x00C * 0x010 FSYNDN[B,H,W] 0x014 FBFCR[B,H,W] 0x018 - 0x01C - - 0x020 FISR[B,H,W] 0x028 FICLR[B,H,W] - - - - 0x100 0x104 - 0x1FC +0 - - - - - - FICR[B,H,W] 0x024 0x02C - 0x0FC +1 CRTRMM[B,H,W] Note: − For details of Flash I/F registers, see FLASH Programming Manual of the product used. February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 111 A. Register Map 1. Register Map P E R I P H E R A L 1.1.2 M A N U A L TYPE3-M4 product FLASH_IF Base_Address : 0x4000_0000 Register Base_Address + Address +3 +2 0x000 FASZR[B,H,W] 0x004 FRWTR[B,H,W] 0x008 FSTR[B,H,W] 0x00C * 0x010 FSYNDN[B,H,W] 0x014 FBFCR[B,H,W] 0x018 - 0x01C - - 0x020 FICR[B,H,W] 0x024 FISR[B,H,W] 0x028 0x02C - - - - FGPDM1[B,H,W] 0x114 FGPDM2[B,H,W] 0x118 FGPDM3[B,H,W] 0x11C - - - - - - - - +1 +0 - - Register +3 +2 0x400 DFASZR[B,H,W] 0x404 DFRWTR[B,H,W] 0x408 0x40C - 0x4FC - FGPDM4[B,H,W] - Base_Address + Address - CRTRMM[B,H,W] 0x110 0x120 - 0x1FC - DFCTRLR[W] 0x100 0x104 - 0x10C +0 FICLR[B,H,W] - 0x030 0x034 - 0x0FC +1 DFSTR[B,H,W] - - Note: − 112 CONFIDENTIAL For details of Flash I/F registers, see "FLASH PROGRAMMING MANUAL" of the product used. FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.1.3 M A N U A L TYPE4-M4 product FLASH_IF Base_Address : 0x4000_0000 Register Base_Address + Address +3 +2 0x000 FASZR[B,H,W] 0x004 FRWTR[B,H,W] 0x008 FSTR[B,H,W] 0x00C * 0x010 FSYNDN[B,H,W] 0x014 FBFCR[B,H,W] 0x018 - 0x01C - - 0x020 FICR[B,H,W] 0x024 FISR[B,H,W] 0x028 +0 - - - - - - FICLR[B,H,W] 0x02C - 0x0FC - - 0x100 CRTRMM[B,H,W] 0x104 - 0x10C - 0x110 0x114 +1 FGPDM1[B,H,W] FGPDM2[B,H,W] 0x118 FGPDM3[B,H,W] 0x11C FGPDM4[B,H,W] 0x120 - 0x1FC - Note: − For details of Flash I/F registers, see FLASH Programming Manual of the product used. February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 113 A. Register Map 1. Register Map P E R I P H E R A L 1.2 M A N U A L Unique ID Unique ID Base_Address : 0x4000_0200 Register Base_Address + Address +3 +0 XXXXXXXX XXXXXXXX XXXXXXXX XXXX---UIDR1[W] 0x004 1.3 +1 UIDR0[W] 0x000 0x008 - 0xDFC +2 -------- -------- ---XXXXX XXXXXXXX - - - - +1 +0 ECC Capture Address ECC Capture Address Base_Address : 0x4000_0300 Register Base_Address + Address +3 FERRAD[W] 0x000 0x004 - 0xFFC 114 CONFIDENTIAL +2 -------- -XXXXXXX XXXXXXXX XXXXXXXX - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.4 M A N U A L Clock/Reset Clock/Reset Base_Address : 0x4001_0000 Register Base_Address + Address 0x000 0x004 +3 - - +1 - - - 00000-0SCM_STR[W] - 00000-0- 00000000 00000000 -------- ---0-000 RST_STR[W] 0x00C - - 0x010 - - - 0x014 - - - 0x018 - - - 0x01C - - - -------0 0000--01 0x020 - - - 0x024 – 0x027 - - - 0x028 - - - 0x02C – 0x02F - - - 0x030 - - - 0x034 - - - 0x038 - - - 0x03C - - - 0x040 - - 0x044 - - 0x048 - - 0x04C - - February 10, 2015, FM4_MN709-00019-1v0-E +0 SCM_CTL[W] STB_CTL[W] 0x008 CONFIDENTIAL +2 BSC_PSR[W] -----000 APBC0_PSR[W] ------00 APBC1_PSR[W] 1--0--00 APBC2_PSR[W] 1--0--00 SWC_PSR[W] ------00 TTC_PSR[W] ------00 CSW_TMR[W] 00000000 PSW_TMR[W] ---0-000 PLL_CTL1[W] 00000000 PLL_CTL2[W] --000000 CSV_CTL[W] -111--00 ------11 - CSV_STR[W] ------00 FCSWH_CTL[W] 11111111 11111111 FCSWL_CTL[W] 00000000 00000000 115 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address 116 CONFIDENTIAL M A N U A L + Address +3 +2 0x050 - - 0x054 - - - 0x058 - - - 0x05C - 0x05F - - - +1 +0 FCSWD_CTL[W] 00000000 00000000 0x060 - - - 0x064 - - - 0x068 - - - 0x06C – 0xFFC - - - DBWDT_CTL[W] 0-0----* INT_ENR[W] --0--000 INT_STR[W] --0–000 INT_CLR[W] --0--000 - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.5 M A N U A L HW WDT HW WDT Base_Address : 0x4001_1000 Register Base_Address + Address +3 +2 0x000 WDG_VLR[W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0x008 - - - 0x00C - - - 0x010 - - - - - 0x014 0x018 – 0xBFC WDG_CTL[W] ------11 WDG_ICL[W] XXXXXXXX WDG_RIS[W] -------0 * - - WDG_LCK[W] 0xC00 0xC04 – 0xFFC +0 00000000 00000000 11111111 11111111 0x004 1.6 +1 WDG_LDR[W] 00000000 00000000 00000000 00000001 - - - - +1 +0 SW WDT SW WDT Base_Address : 0x4001_2000 Register Base_Address + Address +3 WdogLoad[W] 0x000 11111111 11111111 11111111 11111111 WdogValue[W] 0x004 0x008 11111111 11111111 11111111 11111111 - - - - - - - - 0x01C – 0xBFC - - - February 10, 2015, FM4_MN709-00019-1v0-E -------0 WdogSPMC[W] -------0 - 00000000 00000000 00000000 00000000 - - 0xF00 - 0xF04 0xFE0 - 0xFFC WdogRIS[W] WdogLock[W] 0xC00 0xF08 - 0xFDF ---00000 * 0x018 0xC04 - 0xDFC WdogControl[W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0x014 CONFIDENTIAL WdogIntClr[W] 0x00C 0x010 +2 - - - - * - * 117 A. Register Map 1. Register Map P E R I P H E R A L 1.7 M A N U A L Dual_Timer Dual_Timer Base_Address : 0x4001_5000 Register Base_Address + Address +3 Timer1Value[W] 11111111 11111111 11111111 11111111 Timer1Control[W] 0x008 -------- -------- -------- 00100000 Timer1IntClr[W] 0x00C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Timer1RIS[W] 0x010 -------- -------- -------- -------0 Timer1MIS[W] 0x014 -------- -------- -------- -------0 Timer1BGLoad[W] 0x018 00000000 00000000 00000000 00000000 Timer2Load[W] 0x020 00000000 00000000 00000000 00000000 Timer2Value[W] 0x024 11111111 11111111 11111111 11111111 Timer2Control[W] 0x028 -------- -------- -------- 00100000 Timer2IntClr[W] 0x02C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Timer2RIS[W] 0x030 -------- -------- -------- -------0 Timer2MIS[W] 0x034 -------- -------- -------- -------0 Timer2BGLoad[W] 0x038 CONFIDENTIAL +0 00000000 00000000 00000000 00000000 0x004 118 +1 Timer1Load[W] 0x000 0x040 - 0xFFC +2 00000000 00000000 00000000 00000000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.8 MFT 1.8.1 TYPE1-M4, TYPE2-M4 products MFT unit0 Base_Address : 0x4002_0000 MFT unit1 Base_Address : 0x4002_1000 MFT unit2 Base_Address : 0x4002_2000 Register Base_Address + Address +3 +0 - - - - - - - - - - - - OCSD10[B,H,W] OCSB10[B,H,W] OCSA10[B,H,W] 00000000 00000000 00000000 OCSD32[B,H,W] OCSB32[B,H,W] OCSA32[B,H,W] 00000000 00000000 00000000 OCSD54[B,H,W] OCSB54[B,H,W] OCSA54[B,H,W] 00000000 00000000 00000000 00000000 OCCP1[H,W] 0x104 00000000 00000000 OCCP2[H,W] 0x108 00000000 00000000 OCCP3[H,W] 0x10C 00000000 00000000 OCCP4[H,W] 0x110 00000000 00000000 OCCP5[H,W] 0x114 00000000 00000000 0x118 - 0x11C - 00000000 0x124 - - 0x128 - - 0x130 0x13C 0x140 0x144 0x148 0x14C February 10, 2015, FM4_MN709-00019-1v0-E --000000 - OCSE0[B,H,W] 00000000 00000000 00000000 00000000 00000000 00000000 - OCSE2[B,H,W] - 00000000 00000000 OCSE3[B,H,W] 0x134 0x138 OCSC[B,H,W] OCSE1[B,H,W] 0x12C CONFIDENTIAL +1 OCCP0[H,W] 0x100 0x120 +2 00000000 00000000 00000000 00000000 - OCSE4[B,H,W] - 00000000 00000000 OCSE5[B,H,W] 00000000 00000000 00000000 00000000 TCCP0[H,W] 11111111 11111111 TCDT0[H,W] 00000000 00000000 - - - - TCSC0[H,W] TCSA0[B,H,W] 00000000 00000000 00000000 01000000 TCCP1[H,W] 11111111 11111111 - 119 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 TCDT1[H,W] 0x150 00000000 00000000 0x154 - - TCSC1[H,W] TCSA1[B,H,W] 00000000 01000000 11111111 11111111 TCDT2[H,W] 0x15C +0 00000000 00000000 TCCP2[H,W] 0x158 +1 00000000 00000000 - - - - TCSC2[H,W] 0x160 TCSA2[B,H,W] 00000000 00000000 00000000 01000000 TCAL[W] 00000000 00000000 11111111 11111111 *1 0x164 - - - - *2 OCFS32[B,H,W] OCFS10[B,H,W] *1 MFT unit0 *2 MFT unit1,unit2 0x168 - 0x16C - 0x170 - 00000000 00000000 00000000 ICFS32[B,H,W] ICFS10[B,H,W] 00000000 00000000 ACFS54[B,H,W] ACFS32[B,H,W] ACFS10[B,H,W] 00000000 00000000 00000000 - - - - - - - - ICSB10[B,H,W] ICSA10[B,H,W] - ICCP0[H,W] 0x174 00000000 00000000 ICCP1[H,W] 0x178 00000000 00000000 ICCP2[H,W] 0x17C 00000000 00000000 ICCP3[H,W] 0x180 0x184 OCFS54[B,H,W] 00000000 00000000 - - 0x188 0x18C 0x190 0x194 0x198 0x19C 120 CONFIDENTIAL WFTF10[H,W] 00000000 00000000 ------00 00000000 ICSB32[B,H,W] ICSA32[B,H,W] ------00 00000000 - - WFTB10[H,W] WFTA10[H,W] 00000000 00000000 00000000 00000000 WFTF32[H,W] 00000000 00000000 - - WFTB32[H,W] WFTA32[H,W] 00000000 00000000 00000000 00000000 WFTF54[H,W] 00000000 00000000 - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 0x1A0 WFTA54[H,W] 00000000 00000000 - 0x1A8 - - 0x1AC - - 0x1B0 - - 0x1B4 - ACMP0[H,W] 00000000 00000000 ACMP1[H,W] 00000000 00000000 ACMP2[H,W] 0x1C0 00000000 00000000 ACMP3[H,W] 0x1C4 00000000 00000000 ACMP4[H,W] 0x1C8 00000000 00000000 ACMP5[H,W] 0x1CC 0x1D0 00000000 00000000 - WFSA10[B,H,W] --000000 000000 WFSA32[B,H,W] --000000 000000 WFSA54[B,H,W] --000000 000000 WFIR[H,W] 00000000 00000000 NZCL[H,W] 00000000 00000000 - - - - - - - - - - - ACSA[B,H,W] - 0x1D4 - - 0x1D8 - - 0x1DC - - 0x1E0 - - 0x1E4 - - 0x1E8 - - 0x1EC-0xFFC - - February 10, 2015, FM4_MN709-00019-1v0-E +0 WFTB54[H,W] - 0x1BC +1 00000000 00000000 0x1A4 0x1B8 CONFIDENTIAL +2 00000000 00000000 ACSD0[B,H,W] ACSC0[B,H,W] 00000000 00000000 ACSD1[B,H,W] ACSC1[B,H,W] 00000000 00000000 ACSD2[B,H,W] ACSC2[B,H,W] 00000000 00000000 ACSD3[B,H,W] ACSC3[B,H,W] 00000000 00000000 ACSD4[B,H,W] ACSC4[B,H,W] 00000000 00000000 ACSD5[B,H,W] ACSC5[B,H,W] 00000000 00000000 - - 121 A. Register Map 1. Register Map P E R I P H E R A L 1.8.2 TYPE3-M4, TYPE4-M4 products MFT unit0 Base_Address : 0x4002_0000 MFT unit1 Base_Address : 0x4002_1000 MFT unit2 Base_Address : 0x4002_2000 Register Base_Address + Address +3 00000000 00000000 OCCP1[H,W] 0x104 00000000 00000000 OCCP2[H,W] 0x108 00000000 00000000 OCCP3[H,W] 0x10C 00000000 00000000 OCCP4[H,W] 0x110 00000000 00000000 OCCP5[H,W] 0x114 00000000 00000000 0x118 0x11C 0x120 - - - - - - - OCSA32[B,H,W] OCSD32[B,H,W] OCSB32[B,H,W] 00000000 00000000 OCSD54[B,H,W] OCSB54[B,H,W] OCSA54[B,H,W] 00000000 00000000 OCSC[B,H,W] --000000 - OCSE0[B,H,W] 00000000 00000000 OCSE1[B,H,W] 00000000 00000000 00000000 00000000 - OCSE2[B,H,W] - 00000000 00000000 OCSE3[B,H,W] 0x134 0x14C - --000000 00000000 - 0x148 - 00000000 - 0x144 - OCSA10[B,H,W] 0x128 0x140 - 00000000 - 0x13C - OCSB10[B,H,W] - 0x138 +0 OCSD10[B,H,W] 0x124 0x130 +1 --000000 00000000 --000000 00000000 0x12C CONFIDENTIAL +2 OCCP0[H,W] 0x100 122 M A N U A L 00000000 00000000 00000000 00000000 - OCSE4[B,H,W] - 00000000 00000000 OCSE5[B,H,W] 00000000 00000000 00000000 00000000 TCCP0[H,W] 11111111 11111111 TCDT0[H,W] 00000000 00000000 - - - - TCSC0[H,W] TCSA0[B,H,W] 00000000 00000000 00000000 01000000 TCCP1[H,W] 11111111 11111111 - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 TCDT1[H,W] 0x150 00000000 00000000 0x154 - - TCSC1[H,W] TCSA1[B,H,W] 00000000 01000000 11111111 11111111 TCDT2[H,W] 0x15C +0 00000000 00000000 TCCP2[H,W] 0x158 +1 00000000 00000000 - - - - TCSC2[H,W] 0x160 TCSA2[B,H,W] 00000000 00000000 00000000 01000000 TCAL[W] 00000000 00000000 11111111 11111111 *1 0x164 - - - - *2 OCFS32[B,H,W] OCFS10[B,H,W] *1 MFT unit0 *2 MFT unit1,unit2 0x168 - 0x16C - 0x170 - 00000000 00000000 00000000 ICFS32[B,H,W] ICFS10[B,H,W] 00000000 00000000 ACFS54[B,H,W] ACFS32[B,H,W] ACFS10[B,H,W] 00000000 00000000 00000000 - - - - - - - - ICSB10[B,H,W] ICSA10[B,H,W] - ICCP0[H,W] 0x174 00000000 00000000 ICCP1[H,W] 0x178 00000000 00000000 ICCP2[H,W] 0x17C 00000000 00000000 ICCP3[H,W] 0x180 0x184 OCFS54[B,H,W] 00000000 00000000 - - 0x188 0x18C 0x190 0x194 0x198 0x19C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL WFTF10[H,W] 00000000 00000000 ------00 00000000 ICSB32[B,H,W] ICSA32[B,H,W] ------00 00000000 - - WFTB10[H,W] WFTA10[H,W] 00000000 00000000 00000000 00000000 WFTF32[H,W] 00000000 00000000 - - WFTB32[H,W] WFTA32[H,W] 00000000 00000000 00000000 00000000 WFTF54[H,W] 00000000 00000000 - - 123 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 0x1A0 0x1A8 - - 0x1AC - - 0x1B0 - - 0x1B4 - ACMP0[H,W] 00000000 00000000 ACMP1[H,W] 00000000 00000000 ACMP2[H,W] 00000000 00000000 ACMP3[H,W] 0x1C4 00000000 00000000 ACMP4[H,W] 0x1C8 00000000 00000000 ACMP5[H,W] 0x1CC 0x1D0 CONFIDENTIAL WFTA54[H,W] 00000000 00000000 - 0x1C0 00000000 00000000 - 0x1D4 - 0x1D8 - 0x1DC - 0x1E0 - 0x1E4 - 0x1E8 - +0 WFTB54[H,W] - 0x1BC +1 00000000 00000000 0x1A4 0x1B8 124 +2 WFSA10[B,H,W] --000000 000000 WFSA32[B,H,W] --000000 000000 WFSA54[B,H,W] --000000 000000 WFIR[H,W] 00000000 00000000 NZCL[H,W] 00000000 00000000 - - - - - - - - - - - ACSA[B,H,W] - 00000000 00000000 ACMC0[B,H,W] ACSD0[B,H,W] ACSC0[B,H,W] 00--0000 00000000 00000000 ACMC1[B,H,W] ACSD1[B,H,W] ACSC1[B,H,W] 00--0000 00000000 00000000 ACMC2[B,H,W] ACSD2[B,H,W] ACSC2[B,H,W] 00--0000 00000000 00000000 ACMC3[B,H,W] ACSD3[B,H,W] ACSC3[B,H,W] 00--0000 00000000 00000000 ACMC4[B,H,W] ACSD4[B,H,W] ACSC4[B,H,W] 00--0000 00000000 00000000 ACMC5[B,H,W] ACSD5[B,H,W] ACSC5[B,H,W] 00--0000 00000000 0x1EC - - - 0x1F0-0xFFC - - - 00000000 TCSD[B,H,W] ------00 - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.9 M A N U A L PPG PPG Base_Address : 0x4002_4000 Register Base_Address + Address +2 0x000 - - 0x004 - - 0x008 - - 0x00C - - +1 +0 TTCR0 [B,H,W] - 11110000 - * COMP0 [B,H,W] - 00000000 COMP2 [B,H,W] - 00000000 COMP4 [B,H,W] 0x010 - - 0x014 - - - 0x018 - 0x01C - - - 0x020 - - 0x024 - - 0x028 - - 0x02C - - 0x030 - - 0x034 - - - 0x038 - 0x03C - - - 0x040 - - 0x044 - - 0x048 - - 0x04C - - 0x050 - - 0x054 - - - 0x058 - 0x0FC - - - 0x100 - - 0x104 - - 0x108 - 0x13C - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 - 00000000 COMP6 [B,H,W] 00000000 - TTCR1 [B,H,W] - 11110000 - * COMP1 [B,H,W] - 00000000 COMP3 [B,H,W] - 00000000 COMP5 [B,H,W] - 00000000 COMP7 [B,H,W] 00000000 - TTCR2 [B,H,W] - 11110000 - * COMP8 [B,H,W] - 00000000 COMP10 [B,H,W] - 00000000 COMP12 [B,H,W] - 00000000 COMP14 [B,H,W] 00000000 TRG0 [B,H,W] 00000000 00000000 REVC0 [B,H,W] 00000000 00000000 - - 125 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 0x140 - - 0x144 - - 0x148 - 0x1FC - - 0x200 - 0x208 - - 0x20C - - 0x210 - - - - 0x218 - - 0x21C - 0x23C - - 0x240 - - 0x244 - - - - 0x24C - - 0x250 - - +1 +0 TRG1 [B,H,W] -------- 00000000 REVC1 [B,H,W] -------- 00000000 - - PPGC0 [B,H,W] PPGC1 [B,H,W] 00000000 00000000 PPGC2 [B,H,W] PPGC3 [B,H,W] 00000000 00000000 PRLH0 [B,H,W] PRLL0 [B,H,W] XXXXXXXX XXXXXXXX PRLH1 [B,H,W] PRLL1 [B,H,W] XXXXXXXX XXXXXXXX PRLH2 [B,H,W] PRLL2 [B,H,W] XXXXXXXX XXXXXXXX PRLH3 [B,H,W] PRLL3 [B,H,W] XXXXXXXX - XXXXXXXX GATEC0 [B,H,W] --00---00 - - PPGC4 [B,H,W] PPGC5 [B,H,W] 00000000 00000000 PPGC6 [B,H,W] PPGC7 [B,H,W] 00000000 00000000 PRLH4 [B,H,W] PRLL4 [B.H.W] XXXXXXXX XXXXXXXX PRLH5 [B,H,W] PRLL5 [B,H,W] XXXXXXXX XXXXXXXX PRLH6 [B,H,W] PRLL6 [B,H,W] XXXXXXXX XXXXXXXX PRLH7 [B,H,W] PRLL7 [B,H,W] XXXXXXXX XXXXXXXX 0x254 - - 0x258 - - - 0x25C - 0x27C - - - - 0x280 - - PPGC8 [B,H,W] PPGC9 [B,H,W] 0x284 - - 0x288 - - 0x28C - - 0x290 CONFIDENTIAL - - 0x248 126 - 0x204 0x214 M A N U A L - - GATEC4 [B,H,W] ------00 00000000 00000000 PPGC10 [B,H,W] PPGC11 [B,H,W] 00000000 00000000 PRLH8 [B,H,W] PRLL8 [B,H,W] XXXXXXXX XXXXXXXX PRLH9 [B,H,W] PRLL9 [B,H,W] XXXXXXXX XXXXXXXX PRLH10 [B,H,W] PRLL10 [B,H,W] XXXXXXXX XXXXXXXX PRLH11 [B,H,W] PRLL11 [B,H,W] XXXXXXXX XXXXXXXX 0x294 - - 0x298 - - - 0x29C - 0x2BC - - - GATEC8 [B,H,W] --00--00 - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 0x2C0 - - 0x2C4 - - 0x2C8 - - 0x2CC 0x2D0 - - 0x2D4 - - 0x2D8 - - 0x2DC - 0x2FC - - 0x300 - - 0x304 - - 0x308 - - 0x30C - - 0x310 - - 0x314 - - +0 PPGC12 [B,H,W] PPGC13 [B,H,W] 00000000 00000000 PPGC14 [B,H,W] PPGC15 [B,H,W] 00000000 00000000 PRLH12 [B,H,W] PRLL12 [B,H,W] XXXXXXXX XXXXXXXX PRLH13 [B,H,W] PRLL13 [B,H,W] XXXXXXXX XXXXXXXX PRLH14 [B,H,W] PRLL14 [B,H,W] XXXXXXXX XXXXXXXX PRLH15 [B,H,W] PRLL15 [B,H,W] XXXXXXXX XXXXXXXX - GATEC12 [B,H,W] ------00 - - PPGC16 [B,H,W] PPGC17 [B,H,W] 00000000 00000000 PPGC18 [B,H,W] PPGC19 [B,H,W] 00000000 00000000 PRLH16 [B,H,W] PRLL16 [B,H,W] XXXXXXXX XXXXXXXX PRLH17 [B,H,W] PRLL17 [B,H,W] XXXXXXXX XXXXXXXX PRLH18 [B,H,W] PRLL18 [B,H,W] XXXXXXXX XXXXXXXX PRLH19 [B,H,W] PRLL19 [B,H,W] XXXXXXXX XXXXXXXX GATEC16 [B,H,W] 0x318 - - - 0x31C - 0x33C - - - - 0x340 - - PPGC20 [B,H,W] PPGC21 [B,H,W] 0x344 0x348 - - --00---00 00000000 00000000 PPGC22 [B,H,W] PPGC23 [B,H,W] 00000000 00000000 PRLH20 [B,H,W] PRLL20 [B.H.W] XXXXXXXX XXXXXXXX PRLH21 [B,H,W] PRLL21 [B,H,W] XXXXXXXX XXXXXXXX PRLH22 [B,H,W] PRLL22 [B,H,W] XXXXXXXX XXXXXXXX PRLH23 [B,H,W] PRLL23 [B,H,W] XXXXXXXX XXXXXXXX 0x34C - - 0x350 - - 0x354 - - 0x358 - - - 0x35C - 0x37C - - - - 0x380 - - - - 0x384 - 0xFFC - - - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - +1 GATEC20 [B,H,W] ------00 127 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.10 Base Timer Base Timer ch.0 Base Address : 0x4002_5000 Base Timer ch.1 Base Address : 0x4002_5040 Base Timer ch.2 Base Address : 0x4002_5080 Base Timer ch.3 Base Address : 0x4002_50C0 Base Timer ch.4 Base Address : 0x4002_5200 Base Timer ch.5 Base Address : 0x4002_5240 Base Timer ch.6 Base Address : 0x4002_5280 Base Timer ch.7 Base Address : 0x4002_52C0 Base Timer ch.8 Base Address : 0x4002_5400 Base Timer ch.9 Base Address : 0x4002_5440 Base Timer ch.10 Base Address : 0x4002_5480 Base Timer ch.11 Base Address : 0x4002_54C0 Base Timer ch.12 Base Address : 0x4002_5600 Base Timer ch.13 Base Address : 0x4002_5640 Base Timer ch.14 Base Address : 0x4002_5680 Base Timer ch.15 Base Address : 0x4002_56C0 Register Base_Address 128 CONFIDENTIAL + Address +3 +2 0x000 - - 0x004 - - 0x008 - - 0x00C - - 0x010 - - 0x014 - 0x03C - - +1 +0 PCSR/PRLL [H,W] XXXXXXXX XXXXXXXX PDUT/PRLH/DTBF [H,W] XXXXXXXX XXXXXXXX TMR [H,W] 00000000 00000000 TMCR [B,H,W] -0000000 00000000 TMCR2 [B,H,W] STC [B,H,W] 0------0 0000-000 - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.11 IO Selector for Base Timer IO Selector for ch.0-ch.3 (Base Timer) Base Address : 0x4002_5100 Register Base_Address + Address +3 +2 0x000 - - 0x004 - 0x0FC - - +1 +0 BTSEL0123 [B,H,W] - 00000000 - - IO Selector for ch.4-ch.7(Base Timer) Base Address : 0x4002_5300 Register Base_Address + Address +3 +2 0x000 - - 0x004 - 0x0FC - - IO Selector for ch.8-ch.11(Base Timer) +0 BTSEL4567 [B,H,W] - 00000000 - - Base Address : 0x4002_5500 Register Base_Address + Address +3 +2 0x000 - - 0x004 - 0x0FC - - IO Selector for ch.12-ch.15(Base Timer) +1 +0 BTSEL89AB [B,H,W] - 00000000 - - Base Address : 0x4002_5700 Register Base_Address + Address +3 +2 0x000 - - 0x004 - 0x0FC - - Software-based Simulation Startup(Base Timer) +1 +0 BTSELCDEF [B,H,W] - 00000000 - - Base Address : 0x4002_5F00 Register Base_Address + Address +3 +2 +1 +0 0x000 - 0x0FB - - - - 0x0FC - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +1 BTSSSR [B,H,W] XXXXXXXX XXXXXXXX 129 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.12 QPRC 1.12.1 TYPE1-M4, TYPE2-M4 products QPRC ch.0 Base Address : 0x4002_6000 QPRC ch.1 Base Address : 0x4002_6040 QPRC ch.2 Base Address : 0x4002_6080 QPRC ch.3 Base Address : 0x4002_60C0 Register Base_Address + Address +3 +2 0x0000 - - 0x0004 - - 0x0008 - - 0x000C - - 0x0010 - - 0x0014 - - 0x0018 - - 0x001C - - - - 0x0020 0x003B 0x003C 130 CONFIDENTIAL +1 +0 QPCR [H,W] 00000000 00000000 QRCR [H,W] 00000000 00000000 QPCCR [H,W] 00000000 00000000 QPRCR [H,W] 00000000 00000000 QMPR [H,W] 11111111 11111111 QICRH [B,H,W] QICRL [B,H,W] --000000 00000000 QCRH [B,H,W] QCRL [B,H,W] 00000000 00000000 QECR [B,H,W] -------- -----000 - - QPCRR[B,H,W] QRCRR[B,H,W] 00000000 00000000 00000000 00000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.12.2 M A N U A L TYPE3-M4, TYPE4-M4 products QPRC ch.0 Base Address : 0x4002_6000 QPRC ch.1 Base Address : 0x4002_6040 QPRC ch.2 Base Address : 0x4002_6080 QPRC ch.3 Base Address : 0x4002_60C0 Register Base_Address + Address +3 +2 0x0000 - - 0x0004 - - 0x0008 - - 0x000C - - 0x0010 - - 0x0014 - 0x0018 - - 0x001C - - - - 0x0020 0x003B 0x003C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - +1 +0 QPCR [H,W] 00000000 00000000 QRCR [H,W] 00000000 00000000 QPCCR [H,W] 00000000 00000000 QPRCR [H,W] 00000000 00000000 QMPR [H,W] 11111111 11111111 QICRH [B,H,W] QICRL [B,H,W] --000000 00000000 QCRH [B,H,W] QCRL [B,H,W] 00000000 00000000 QECR [B,H,W] -------- ----0000 - - QPCRR[B,H,W] QRCRR[B,H,W] 00000000 00000000 00000000 00000000 131 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.13 QPRC NF QPRC ch.0 NF Base Address : 0x4002_6100 QPRC ch.1 NF Base Address : 0x4002_6110 QPRC ch.2 NF Base Address : 0x4002_6120 QPRC ch.3 NF Base Address : 0x4002_6130 Register Base_Address 132 CONFIDENTIAL + Address +3 +2 +1 0x0000 - - - 0x0004 - - - 0x0008 - - - 0x000C - - - +0 NFCTLA[B,H,W] --00-000 NFCTLB[B,H,W] --00-000 NFCTLZ[B,H,W] --00-000 - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.14 A/DC 12bit A/DC unit0 Base_Address : 0x4002_7000 12bit A/DC unit1 Base_Address : 0x4002_7100 12bit A/DC unit2 Base_Address : 0x4002_7200 Register Base_Address + Address +3 +2 0x000 - - 0x004 - - 0x008 - - - - 0x018 - - - CMPD[B,H,W] - 0x030 - - 0x034 - - 0x038 - - - 00000000 SCIS0[B,H,W] 00000000 00000000 PCCR[B,H,W] PFNS[B,H,W] 10000000 --XX--00 PCIS[B,H,W] 00000000 CMPCR[B,H,W] 00000000 ADSS2[B,H,W] 00000000 00000000 ADSS1[B,H,W] ADSS0[B,H,W] 00000000 00000000 ADST0[B,H,W] ADST1[B,H,W] 00010000 00010000 ADCT[B,H,W] - 00000111 SCTSL[B,H,W] PRTSL[B,H,W] ----0000 ----0000 ADCEN[B,H,W] 11111111 ------00 * - - - - - 0x050 CONFIDENTIAL 00000000 - 0x040 February 10, 2015, FM4_MN709-00019-1v0-E SCIS2[B,H,W] SCIS1[B,H,W] ADSS3[B,H,W] - 0x040 - 0x0FC ----0000 - - 0x04C SFNS[B,H,W] 1000-000 - 00000000 00------ 0x02C 0x048 SCCR[B,H,W] XXXXXXXX XXXX---- ---X-XXX ---XXXXX 0x024 0x044 * PCFD[B,H,W] 0x01C 0x03C 00---000 - SCIS3[B,H,W] - - 0x028 000-0000 XXXXXXXX XXXX---- ---X--XX ---XXXXX 0x014 0x020 +0 ADSR[B,H,W] SCFD[B,H,W] 0x00C 0x010 +1 ADCR[B,H,W] - - WCMRCOT[B,H,W] - 00000000 WCMRCIF[B,H,W] - 00000000 WCMPSR[B,H,W] WCMPCR[B,H,W] 00000000 00100000 WCMPDH[B,H,W] WCMPDL[B,H,W] 00000000 00000000 00000000 00000000 - - - 133 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.15 CR Trim CR Trim Base_Address : 0x4002_E000 Register Base_Address + Address 0x000 +3 +2 - +1 - 0x004 - - 0x008 - - +0 MCR_PSR[B,H,W] - -----001 MCR_FTRM[B,H,W] ------01 11101111 - MCR_TTRM[B,H,W] ---10000 MCR_RLR[W] 0x00C 00000000 00000000 00000000 00000001 0x010 - 0x0FC - - - - +1 +0 1.16 EXTI EXTI Base_Address : 0x4003_0000 Register Base_Address + Address +3 ENIR[B,H,W] 0x000 00000000 00000000 00000000 00000000 EIRR[B,H,W] 0x004 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EICL[B,H,W] 0x008 11111111 11111111 11111111 11111111 ELVR[B,H,W] 0x00C 00000000 00000000 00000000 00000000 ELVR1[B,H,W] 0x010 134 CONFIDENTIAL +2 00000000 00000000 00000000 00000000 NMIRR[B,H,W] 0x014 - - - 0x018 - - - 0x01C - - - - 0x020 - 0x0FC - - - - -------0 NMICL[B,H,W] -------1 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.17 INT-Req. READ 1.17.1 TYPE1-M4, TYPE2-M4 products INT-Req. READ Base_Address : 0x4003_1000 Register Base_Address + Address +3 +2 0x000 +0 00000000 00000000 00000000 00000000 0x004 – 0x00C ODDPKS[B] 0x010 - - - 0x014 - - - - 0x018 - * - * 0x01C – 0x10C - - - - -------- 00000000 -------- 00000000 IRQ004SEL[B,H,W] 0x114 -------- 00000000 -------- 00000000 IRQ005SEL[B,H,W] 0x118 -------- 00000000 -------- 00000000 IRQ006SEL[B,H,W] 0x11C -------- 00000000 -------- 00000000 IRQ007SEL[B,H,W] 0x120 -------- 00000000 -------- 00000000 IRQ008SEL[B,H,W] 0x124 -------- 00000000 -------- 00000000 IRQ009SEL[B,H,W] 0x128 -------- 00000000 -------- 00000000 IRQ010SEL[B,H,W] 0x12C 0x130 – 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 February 10, 2015, FM4_MN709-00019-1v0-E ---00000 IRQ003SEL[B,H,W] 0x110 CONFIDENTIAL +1 DRQSEL[B,H,W] -------- 00000000 -------- 00000000 - - - - EXC02MON[B,H,W] -------- -------- -------- ------00 IRQ000MON[B,H,W] -------- -------- -------- -------0 IRQ001MON[B,H,W] -------- -------- -------- -------0 IRQ002MON[B,H,W] -------- -------- -------- -------0 IRQ003MON[B,H,W] -------- -------- -------- 00000000 IRQ004MON[B,H,W] -------- -------- -------- 00000000 IRQ005MON[B,H,W] -------- -------- -------- 00000000 135 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 136 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ006MON[B,H,W] -------- -------- -------- 00000000 IRQ007MON[B,H,W] -------- -------- -------- 00000000 IRQ008MON[B,H,W] -------- -------- -------- 00000000 IRQ009MON[B,H,W] -------- -------- -------- 00000000 IRQ010MON[B,H,W] -------- -------- -------- 00000000 IRQ011MON[B,H,W] -------- -------- -------- -------0 IRQ012MON[B,H,W] -------- -------- -------- -------0 IRQ013MON[B,H,W] -------- -------- -------- -------0 IRQ014MON[B,H,W] -------- -------- -------- -------0 IRQ015MON[B,H,W] -------- -------- -------- -------0 IRQ016MON[B,H,W] -------- -------- -------- -------0 IRQ017MON[B,H,W] -------- -------- -------- -------0 IRQ018MON[B,H,W] -------- -------- -------- -------0 IRQ019MON[B,H,W] -------- -------- -------- --000000 IRQ020MON[B,H,W] -------- -------- -------- --000000 IRQ021MON[B,H,W] -------- -------- -------- ----0000 IRQ022MON[B,H,W] -------- -------- -------- ----0000 IRQ023MON[B,H,W] -------- -------- -------- ----0000 IRQ024MON[B,H,W] -------- -------- -------- -----000 IRQ025MON[B,H,W] -------- -------- -------- -----000 IRQ026MON[B,H,W] -------- -------- -------- ----0000 IRQ027MON[B,H,W] -------- -------- -------- --000000 IRQ028MON[B,H,W] -------- -------- -------- -----000 IRQ029MON[B,H,W] -------- -------- -------- -----000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x27C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ030MON[B,H,W] -------- -------- -------- ----0000 IRQ031MON[B,H,W] -------- -------- -------- --000000 IRQ032MON[B,H,W] -------- -------- -------- -----000 IRQ033MON[B,H,W] -------- -------- -------- -----000 IRQ034MON[B,H,W] -------- -------- -------- ---00000 IRQ035MON[B,H,W] -------- -------- -------- --000000 IRQ036MON[B,H,W] -------- -------- -------- -----000 IRQ037MON[B,H,W] -------- -------- -------- -----000 IRQ038MON[B,H,W] -------- -------- -------- -----000 IRQ039MON[B,H,W] -------- -------- -------- ------00 IRQ040MON[B,H,W] -------- -------- -------- ------00 IRQ041MON[B,H,W] -------- -------- -------- ------00 IRQ042MON[B,H,W] -------- -------- -------- ------00 IRQ043MON[B,H,W] -------- -------- -------- ------00 IRQ044MON[B,H,W] -------- -------- -------- ------00 IRQ045MON[B,H,W] -------- -------- -------- ------00 IRQ046MON[B,H,W] -------- -------- -------- ------00 IRQ047MON[B,H,W] -------- -------- -------- ------00 IRQ048MON[B,H,W] -------- -------- -------- -------0 IRQ049MON[B,H,W] -------- -------- -------- -------0 IRQ050MON[B,H,W] -------- -------- -------- -------0 IRQ051MON[B,H,W] -------- -------- -------- -------0 IRQ052MON[B,H,W] -------- -------- -------- -------0 IRQ053MON[B,H,W] -------- -------- -------- -------0 137 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 138 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ054MON[B,H,W] -------- -------- -------- -------0 IRQ055MON[B,H,W] -------- -------- -------- -------0 IRQ056MON[B,H,W] -------- -------- -------- -------0 IRQ057MON[B,H,W] -------- -------- -------- -------0 IRQ058MON[B,H,W] -------- -------- -------- -------0 IRQ059MON[B,H,W] -------- -------- -------- ----0000 IRQ060MON[B,H,W] -------- -------- -------- -------0 IRQ061MON[B,H,W] -------- -------- -------- ------00 IRQ062MON[B,H,W] -------- -------- -------- -------0 IRQ063MON[B,H,W] -------- -------- -------- ------00 IRQ064MON[B,H,W] -------- -------- -------- -------0 IRQ065MON[B,H,W] -------- -------- -------- ------00 IRQ066MON[B,H,W] -------- -------- -------- -------0 IRQ067MON[B,H,W] -------- -------- -------- ------00 IRQ068MON[B,H,W] -------- -------- -------- -------0 IRQ069MON[B,H,W] -------- -------- -------- ------00 IRQ070MON[B,H,W] -------- -------- -------- -------0 IRQ071MON[B,H,W] -------- -------- -------- ------00 IRQ072MON[B,H,W] -------- -------- -------- -------0 IRQ073MON[B,H,W] -------- -------- -------- ------00 IRQ074MON[B,H,W] -------- -------- -------- -------0 IRQ075MON[B,H,W] -------- -------- -------- ------00 IRQ076MON[B,H,W] -------- -------- -------- ---00000 IRQ077MON[B,H,W] -------- -------- -------- ---00000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x33C 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ078MON[B,H,W] -------- -------- -------- ---00000 IRQ079MON[B,H,W] -------- -------- -------- --000000 IRQ080MON[B,H,W] -------- -------- -------- -------0 IRQ081MON[B,H,W] -------- -------- -------- -------0 IRQ082MON[B,H,W] -------- -------- -------- -----000 IRQ083MON[B,H,W] -------- -------- -------- -------0 IRQ084MON[B,H,W] -------- -------- -------- -------0 IRQ085MON[B,H,W] -------- -------- -------- -------0 IRQ086MON[B,H,W] -------- -------- -------- -------0 IRQ087MON[B,H,W] -------- -------- -------- -------0 IRQ088MON[B,H,W] -------- -------- -------- -------0 IRQ089MON[B,H,W] -------- -------- -------- -------0 IRQ090MON[B,H,W] -------- -------- -------- -------0 IRQ091MON[B,H,W] -------- -------- -------- ------00 IRQ092MON[B,H,W] -------- -------- -------- ----0000 IRQ093MON[B,H,W] -------- -------- -------- ----0000 IRQ094MON[B,H,W] -------- -------- -------- ----0000 IRQ095MON[B,H,W] -------- -------- -------- ----0000 IRQ096MON[B,H,W] -------- -------- -------- --000000 IRQ097MON[B,H,W] -------- -------- -------- --000000 IRQ098MON[B,H,W] -------- -------- -------- ------00 IRQ099MON[B,H,W] -------- -------- -------- ------00 IRQ100MON[B,H,W] -------- -------- -------- ------00 IRQ101MON[B,H,W] -------- -------- -------- ------00 139 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 IRQ103MON[B,H,W] IRQ104MON[B,H,W] -------- -------- -------- ------00 IRQ105MON[B,H,W] 0x3A8 -------- -------- -------- -------0 IRQ106MON[B,H,W] 0x3AC -------- -------- -------- ------00 IRQ107MON[B,H,W] 0x3B0 -------- -------- -------- -------0 IRQ108MON[B,H,W] 0x3B4 -------- -------- -------- ------00 IRQ109MON[B,H,W] 0x3B8 -------- -------- -------- -------0 IRQ110MON[B,H,W] 0x3BC -------- -------- -------- ------00 IRQ111MON[B,H,W] 0x3C0 -------- -------- -------- ---00000 - - - -------- -------- -------- ---00000 IRQ114MON[B,H,W] 0x3CC -------- -------- -------- --000000 - - - - IRQ118MON[B,H,W] 0x3DC -------- -------- -------- ------00 IRQ119MON[B,H,W] 0x3E0 -------- -------- -------- -------0 IRQ120MON[B,H,W] 0x3E4 -------- -------- -------- -------0 IRQ121MON[B,H,W] 0x3E8 -------- -------- -------- ------00 IRQ122MON[B,H,W] 0x3EC -------- -------- -------- -------0 IRQ123MON[B,H,W] 0x3F0 -------- -------- -------- ------00 IRQ124MON[B,H,W] 0x3F4 -------- -------- -------- -------0 IRQ125MON[B,H,W] 0x3F8 -------- -------- -------- ------00 IRQ126MON[B,H,W] 0x3FC -------- -------- -------- -------0 IRQ127MON[B,H,W] 0x400 CONFIDENTIAL IRQ113MON[B,H,W] 0x3C8 140 +0 -------- -------- -------- -------0 0x3A4 0x404 – 0xFFC +1 -------- -------- -------- ------00 0x3A0 0x3D0 – 0x3D8 +2 IRQ102MON[B,H,W] 0x39C 0x3C4 M A N U A L -------- -------- -------- ------00 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.17.2 M A N U A L TYPE3-M4 product INT-Req. READ Base_Address : 0x4003_1000 Register Base_Address + Address +3 +2 0x000 - - - ODDPKS[B] ---00000 ODDPKS1[B] 0x014 - - - 0x018 - * - * 0x01C – 0x10C - - - - -------- 00000000 -------- 00000000 IRQ004SEL[B,H,W] 0x114 -------- 00000000 -------- 00000000 IRQ005SEL[B,H,W] 0x118 -------- 00000000 -------- 00000000 IRQ006SEL[B,H,W] 0x11C -------- 00000000 -------- 00000000 IRQ007SEL[B,H,W] 0x120 -------- 00000000 -------- 00000000 IRQ008SEL[B,H,W] 0x124 -------- 00000000 -------- 00000000 IRQ009SEL[B,H,W] 0x128 -------- 00000000 -------- 00000000 IRQ010SEL[B,H,W] 0x12C 0x130 – 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C February 10, 2015, FM4_MN709-00019-1v0-E --00000 IRQ003SEL[B,H,W] 0x110 CONFIDENTIAL +0 00000000 00000000 00000000 00000000 0x004 – 0x00C 0x010 +1 DRQSEL[B,H,W] -------- 00000000 -------- 00000000 - - - - EXC02MON[B,H,W] -------- -------- -------- ------00 IRQ000MON[B,H,W] -------- -------- -------- -------0 IRQ001MON[B,H,W] -------- -------- -------- -------0 IRQ002MON[B,H,W] -------- -------- -------- -------0 IRQ003MON[B,H,W] -------- -------- -------- 00000000 IRQ004MON[B,H,W] -------- -------- -------- 00000000 IRQ005MON[B,H,W] -------- -------- -------- 00000000 IRQ006MON[B,H,W] -------- -------- -------- 00000000 141 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C 142 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ007MON[B,H,W] -------- -------- -------- 00000000 IRQ008MON[B,H,W] -------- -------- -------- 00000000 IRQ009MON[B,H,W] -------- -------- -------- 00000000 IRQ010MON[B,H,W] -------- -------- -------- 00000000 IRQ011MON[B,H,W] -------- -------- -------- -------0 IRQ012MON[B,H,W] -------- -------- -------- -------0 IRQ013MON[B,H,W] -------- -------- -------- -------0 IRQ014MON[B,H,W] -------- -------- -------- -------0 IRQ015MON[B,H,W] -------- -------- -------- -------0 IRQ016MON[B,H,W] -------- -------- -------- -------0 IRQ017MON[B,H,W] -------- -------- -------- -------0 IRQ018MON[B,H,W] -------- -------- -------- -------0 IRQ019MON[B,H,W] -------- -------- -------- --000000 IRQ020MON[B,H,W] -------- -------- -------- --000000 IRQ021MON[B,H,W] -------- -------- -------- ----0000 IRQ022MON[B,H,W] -------- -------- -------- ----0000 IRQ023MON[B,H,W] -------- -------- -------- ----0000 IRQ024MON[B,H,W] -------- -------- -------- -----000 IRQ025MON[B,H,W] -------- -------- -------- -----000 IRQ026MON[B,H,W] -------- -------- -------- ----0000 IRQ027MON[B,H,W] -------- -------- -------- --000000 IRQ028MON[B,H,W] -------- -------- -------- -----000 IRQ029MON[B,H,W] -------- -------- -------- -----000 IRQ030MON[B,H,W] -------- -------- -------- ----0000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ031MON[B,H,W] -------- -------- -------- --000000 IRQ032MON[B,H,W] -------- -------- -------- -----000 IRQ033MON[B,H,W] -------- -------- -------- -----000 IRQ034MON[B,H,W] -------- -------- -------- ---00000 IRQ035MON[B,H,W] -------- -------- -------- --000000 IRQ036MON[B,H,W] -------- -------- -------- -----000 IRQ037MON[B,H,W] -------- -------- -------- -----000 IRQ038MON[B,H,W] -------- -------- -------- -----000 IRQ039MON[B,H,W] -------- -------- -------- ------00 IRQ040MON[B,H,W] -------- -------- -------- ------00 IRQ041MON[B,H,W] -------- -------- -------- ------00 IRQ042MON[B,H,W] -------- -------- -------- ------00 IRQ043MON[B,H,W] -------- -------- -------- ------00 IRQ044MON[B,H,W] -------- -------- -------- ------00 IRQ045MON[B,H,W] -------- -------- -------- ------00 IRQ046MON[B,H,W] -------- -------- -------- ------00 IRQ047MON[B,H,W] -------- -------- -------- ------00 IRQ048MON[B,H,W] -------- -------- -------- -------0 IRQ049MON[B,H,W] -------- -------- -------- -------0 IRQ050MON[B,H,W] -------- -------- -------- -------0 IRQ051MON[B,H,W] -------- -------- -------- -------0 IRQ052MON[B,H,W] -------- -------- -------- -------0 IRQ053MON[B,H,W] -------- -------- -------- -------0 IRQ054MON[B,H,W] -------- -------- -------- -------0 143 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 144 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ055MON[B,H,W] -------- -------- -------- -------0 IRQ056MON[B,H,W] -------- -------- -------- -------0 IRQ057MON[B,H,W] -------- -------- -------- -------0 IRQ058MON[B,H,W] -------- -------- -------- -------0 IRQ059MON[B,H,W] -------- -------- -------- ---00000 IRQ060MON[B,H,W] -------- -------- -------- -------0 IRQ061MON[B,H,W] -------- -------- -------- ------00 IRQ062MON[B,H,W] -------- -------- -------- -------0 IRQ063MON[B,H,W] -------- -------- -------- ------00 IRQ064MON[B,H,W] -------- -------- -------- -------0 IRQ065MON[B,H,W] -------- -------- -------- ------00 IRQ066MON[B,H,W] -------- -------- -------- -------0 IRQ067MON[B,H,W] -------- -------- -------- ------00 IRQ068MON[B,H,W] -------- -------- -------- -------0 IRQ069MON[B,H,W] -------- -------- -------- ------00 IRQ070MON[B,H,W] -------- -------- -------- -------0 IRQ071MON[B,H,W] -------- -------- -------- ------00 IRQ072MON[B,H,W] -------- -------- -------- -------0 IRQ073MON[B,H,W] -------- -------- -------- ------00 IRQ074MON[B,H,W] -------- -------- -------- -------0 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x330 0x334 0x338 0x33C 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ075MON[B,H,W] -------- -------- -------- ------00 IRQ076MON[B,H,W] -------- -------- -------- ---00000 IRQ077MON[B,H,W] -------- -------- -------- ---00000 IRQ078MON[B,H,W] -------- -------- -------- ---00000 IRQ079MON[B,H,W] -------- -------- -------- --000000 IRQ080MON[B,H,W] -------- -------- -------- -------0 IRQ081MON[B,H,W] -------- -------- -------- ---00000 IRQ082MON[B,H,W] -------- -------- -------- -----000 IRQ083MON[B,H,W] -------- -------- -------- -------0 IRQ084MON[B,H,W] -------- -------- -------- -------0 IRQ085MON[B,H,W] -------- -------- -------- -------0 IRQ086MON[B,H,W] -------- -------- -------- -------0 IRQ087MON[B,H,W] -------- -------- -------- -------0 IRQ088MON[B,H,W] -------- -------- -------- -------0 IRQ089MON[B,H,W] -------- -------- -------- -------0 IRQ090MON[B,H,W] -------- -------- -------- -------0 IRQ091MON[B,H,W] -------- -------- -------- ------00 IRQ092MON[B,H,W] -------- -------- -------- ----0000 IRQ093MON[B,H,W] -------- -------- -------- ----0000 IRQ094MON[B,H,W] -------- -------- -------- ----0000 145 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC 0x3C0 0x3C4 0x3C8 0x3CC 146 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ095MON[B,H,W] -------- -------- -------- ----0000 IRQ096MON[B,H,W] -------- -------- -------- --000000 IRQ097MON[B,H,W] -------- -------- -------- --000000 IRQ098MON[B,H,W] -------- -------- -------- ------00 IRQ099MON[B,H,W] -------- -------- -------- ------00 IRQ100MON[B,H,W] -------- -------- -------- ------00 IRQ101MON[B,H,W] -------- -------- -------- ------00 IRQ102MON[B,H,W] -------- -------- -------- ------00 IRQ103MON[B,H,W] -------- -------- -------- -------0 IRQ104MON[B,H,W] -------- -------- -------- ------00 IRQ105MON[B,H,W] -------- -------- -------- -------0 IRQ106MON[B,H,W] -------- -------- -------- ------00 IRQ107MON[B,H,W] -------- -------- -------- -------0 IRQ108MON[B,H,W] -------- -------- -------- ------00 IRQ109MON[B,H,W] -------- -------- -------- -------0 IRQ110MON[B,H,W] -------- -------- -------- ------00 IRQ111MON[B,H,W] -------- -------- -------- ---00000 IRQ112MON[B,H,W] -------- -------- -------- --000000 IRQ113MON[B,H,W] -------- -------- -------- --000000 IRQ114MON[B,H,W] -------- -------- -------- -0000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 -------- -------- -------- -----000 IRQ116MON[B,H,W] 0x3D4 -------- -------- -------- -------IRQ117MON[B,H,W] 0x3D8 -------- -------- -------- ------00 IRQ118MON[B,H,W] 0x3DC -------- -------- -------- ------00 IRQ119MON[B,H,W] 0x3E0 -------- -------- -------- -------0 IRQ120MON[B,H,W] 0x3E4 -------- -------- -------- -------0 IRQ121MON[B,H,W] 0x3E8 -------- -------- -------- ------00 IRQ122MON[B,H,W] 0x3EC -------- -------- -------- -------0 IRQ123MON[B,H,W] 0x3F0 -------- -------- -------- ------00 IRQ124MON[B,H,W] 0x3F4 -------- -------- -------- -------0 IRQ125MON[B,H,W] 0x3F8 -------- -------- -------- ------00 IRQ126MON[B,H,W] 0x3FC -------- -------- -------- -------0 IRQ127MON[B,H,W] 0x400 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 IRQ115MON[B,H,W] 0x3D0 0x404 – 0xFFC +1 -------- -------- -------- ------00 - - - - 147 A. Register Map 1. Register Map P E R I P H E R A L 1.17.3 TYPE4-M4 product INT-Req. READ Base_Address : 0x4003_1000 Register Base_Address + Address +3 +2 - - - ODDPKS[B] ---00000 ODDPKS1[B] 0x014 - - - 0x018 - * - * 0x01C – 0x10C - - - - 00000000 00000000 -------- 00000000 IRQ004SEL[B,H,W] 0x114 00000000 00000000 -------- 00000000 IRQ005SEL[B,H,W] 0x118 00000000 00000000 -------- 00000000 IRQ006SEL[B,H,W] 0x11C 00000000 00000000 -------- 00000000 IRQ007SEL[B,H,W] 0x120 00000000 00000000 -------- 00000000 IRQ008SEL[B,H,W] 0x124 00000000 00000000 -------- 00000000 IRQ009SEL[B,H,W] 0x128 00000000 00000000 -------- 00000000 IRQ010SEL[B,H,W] 0x12C 0x130 – 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C --00000 IRQ003SEL[B,H,W] 0x110 CONFIDENTIAL +0 00000000 00000000 00000000 00000000 0x004 – 0x00C 0x010 +1 DRQSEL[B,H,W] 0x000 148 M A N U A L 00000000 00000000 -------- 00000000 - - - - EXC02MON[B,H,W] -------- -------- -------- ------00 IRQ000MON[B,H,W] -------- -------- -------- -------0 IRQ001MON[B,H,W] -------- -------- -------- -------0 IRQ002MON[B,H,W] -------- -------- -------- -------0 IRQ003MON[B,H,W] -------- -------- -------- 00000000 IRQ004MON[B,H,W] -------- -------- -------- 00000000 IRQ005MON[B,H,W] -------- -------- -------- 00000000 IRQ006MON[B,H,W] -------- -------- -------- 00000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ007MON[B,H,W] -------- -------- -------- 00000000 IRQ008MON[B,H,W] -------- -------- -------- 00000000 IRQ009MON[B,H,W] -------- -------- -------- 00000000 IRQ010MON[B,H,W] -------- -------- -------- 00000000 IRQ011MON[B,H,W] -------- -------- -------- -------0 IRQ012MON[B,H,W] -------- -------- -------- -------0 IRQ013MON[B,H,W] -------- -------- -------- -------0 IRQ014MON[B,H,W] -------- -------- -------- -------0 IRQ015MON[B,H,W] -------- -------- -------- -------0 IRQ016MON[B,H,W] -------- -------- -------- -------0 IRQ017MON[B,H,W] -------- -------- -------- -------0 IRQ018MON[B,H,W] -------- -------- -------- -------0 IRQ019MON[B,H,W] -------- -------- -------- --000000 IRQ020MON[B,H,W] -------- -------- -------- --000000 IRQ021MON[B,H,W] -------- -------- -------- ----0000 IRQ022MON[B,H,W] -------- -------- -------- ----0000 IRQ023MON[B,H,W] -------- -------- -------- ----0000 IRQ024MON[B,H,W] -------- -------- -------- -----000 IRQ025MON[B,H,W] -------- -------- -------- -----000 IRQ026MON[B,H,W] -------- -------- -------- ----0000 IRQ027MON[B,H,W] -------- -------- -------- --000000 IRQ028MON[B,H,W] -------- -------- -------- -----000 IRQ029MON[B,H,W] -------- -------- -------- -----000 IRQ030MON[B,H,W] -------- -------- -------- ----0000 149 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 150 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ031MON[B,H,W] -------- -------- -------- --000000 IRQ032MON[B,H,W] -------- -------- -------- -----000 IRQ033MON[B,H,W] -------- -------- -------- -----000 IRQ034MON[B,H,W] -------- -------- -------- ---00000 IRQ035MON[B,H,W] -------- -------- -------- --000000 IRQ036MON[B,H,W] -------- -------- -------- -----000 IRQ037MON[B,H,W] -------- -------- -------- -----000 IRQ038MON[B,H,W] -------- -------- -------- -----000 IRQ039MON[B,H,W] -------- -------- -------- ------00 IRQ040MON[B,H,W] -------- -------- -------- ------00 IRQ041MON[B,H,W] -------- -------- -------- ------00 IRQ042MON[B,H,W] -------- -------- -------- ------00 IRQ043MON[B,H,W] -------- -------- -------- ------00 IRQ044MON[B,H,W] -------- -------- -------- ------00 IRQ045MON[B,H,W] -------- -------- -------- ------00 IRQ046MON[B,H,W] -------- -------- -------- ------00 IRQ047MON[B,H,W] -------- -------- -------- ------00 IRQ048MON[B,H,W] -------- -------- -------- -------0 IRQ049MON[B,H,W] -------- -------- -------- ------00 IRQ050MON[B,H,W] -------- -------- -------- -------0 IRQ051MON[B,H,W] -------- -------- -------- -------0 IRQ052MON[B,H,W] -------- -------- -------- -------0 IRQ053MON[B,H,W] -------- -------- -------- -------0 IRQ054MON[B,H,W] -------- -------- -------- -------0 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ055MON[B,H,W] -------- -------- -------- -------0 IRQ056MON[B,H,W] -------- -------- -------- -------0 IRQ057MON[B,H,W] -------- -------- -------- -------0 IRQ058MON[B,H,W] -------- -------- -------- -------0 IRQ059MON[B,H,W] -------- -------- -------- --000000 IRQ060MON[B,H,W] -------- -------- -------- -------0 IRQ061MON[B,H,W] -------- -------- -------- ------00 IRQ062MON[B,H,W] -------- -------- -------- -------0 IRQ063MON[B,H,W] -------- -------- -------- ------00 IRQ064MON[B,H,W] -------- -------- -------- -------0 IRQ065MON[B,H,W] -------- -------- -------- ------00 IRQ066MON[B,H,W] -------- -------- -------- -------0 IRQ067MON[B,H,W] -------- -------- -------- ------00 IRQ068MON[B,H,W] -------- -------- -------- -------0 IRQ069MON[B,H,W] -------- -------- -------- ------00 IRQ070MON[B,H,W] -------- -------- -------- -------0 IRQ071MON[B,H,W] -------- -------- -------- ------00 IRQ072MON[B,H,W] -------- -------- -------- -------0 IRQ073MON[B,H,W] -------- -------- -------- ------00 IRQ074MON[B,H,W] -------- -------- -------- -------0 151 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x330 0x334 0x338 0x33C 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C 152 CONFIDENTIAL M A N U A L +3 +2 +1 +0 IRQ075MON[B,H,W] -------- -------- -------- ------00 IRQ076MON[B,H,W] -------- -------- -------- ---00000 IRQ077MON[B,H,W] -------- -------- -------- ---00000 IRQ078MON[B,H,W] -------- -------- -------- ---00000 IRQ079MON[B,H,W] -------- -------- -------- --000000 IRQ080MON[B,H,W] -------- -------- -------- -------0 IRQ081MON[B,H,W] -------- -------- -------- ---00000 IRQ082MON[B,H,W] -------- -------- -------- -----000 IRQ083MON[B,H,W] -------- -------- -------- -------0 IRQ084MON[B,H,W] -------- -------- -------- -------0 IRQ085MON[B,H,W] -------- -------- -------- -------0 IRQ086MON[B,H,W] -------- -------- -------- -------0 IRQ087MON[B,H,W] -------- -------- -------- -------0 IRQ088MON[B,H,W] -------- -------- -------- -------0 IRQ089MON[B,H,W] -------- -------- -------- -------0 IRQ090MON[B,H,W] -------- -------- -------- -------0 IRQ091MON[B,H,W] -------- -------- -------- ------00 IRQ092MON[B,H,W] -------- -------- -------0 ----0000 IRQ093MON[B,H,W] -------- -------- -------0 ----0000 IRQ094MON[B,H,W] -------- -------- -------0 ----0000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC 0x3C0 0x3C4 0x3C8 0x3CC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 IRQ095MON[B,H,W] -------- -------- -------0 ----0000 IRQ096MON[B,H,W] -------- -------- -------0 --000000 IRQ097MON[B,H,W] -------- -------- -------0 --000000 IRQ098MON[B,H,W] -------- -------- -------0 ------00 IRQ099MON[B,H,W] -------- -------- -------0 ------00 IRQ100MON[B,H,W] -------- -------- -------0 ------00 IRQ101MON[B,H,W] -------- -------- -------0 ------00 IRQ102MON[B,H,W] -------- -------- -------0 ------00 IRQ103MON[B,H,W] -------- -------- -------0 -------0 IRQ104MON[B,H,W] -------- -------- -------0 ------00 IRQ105MON[B,H,W] -------- -------- -------0 -------0 IRQ106MON[B,H,W] -------- -------- -------0 ------00 IRQ107MON[B,H,W] -------- -------- -------0 -------0 IRQ108MON[B,H,W] -------- -------- -------0 ------00 IRQ109MON[B,H,W] -------- -------- -------0 -------0 IRQ110MON[B,H,W] -------- -------- -------0 ------00 IRQ111MON[B,H,W] -------- -------- -------- ---00000 IRQ112MON[B,H,W] -------- -------- ------00 00000000 IRQ113MON[B,H,W] -------- -------- -------- --000000 IRQ114MON[B,H,W] -------- -------- -------- -0000000 153 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 IRQ116MON[B,H,W] -------- -------- -------- -------IRQ117MON[B,H,W] 0x3D8 -------- -------- -------- -----000 IRQ118MON[B,H,W] 0x3DC -------- -------- -------- ------00 IRQ119MON[B,H,W] 0x3E0 -------- -------- -------- -------0 IRQ120MON[B,H,W] 0x3E4 -------- -------- -------0 -------0 IRQ121MON[B,H,W] 0x3E8 -------- -------- -------0 ------00 IRQ122MON[B,H,W] 0x3EC -------- -------- -------0 -------0 IRQ123MON[B,H,W] 0x3F0 -------- -------- -------0 ------00 IRQ124MON[B,H,W] 0x3F4 -------- -------- -------- -------0 IRQ125MON[B,H,W] 0x3F8 -------- -------- -------- ------00 IRQ126MON[B,H,W] 0x3FC -------- -------- -------- -------0 IRQ127MON[B,H,W] 0x400 CONFIDENTIAL +0 -------- -------- -------- -----000 0x3D4 154 +1 IRQ115MON[B,H,W] 0x3D0 0x404 – 0xFFC M A N U A L -------- -------- -------- ------00 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.18 D/AC 12bit D/AC unit0 Base_Address : 0x4003_3000 12bit D/AC unit1 Base_Address : 0x4003_3008 Register Base_Address + Address +3 +2 +1 0x000 - - - 0x004 - - 0x010 – 0xFFC - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 DACR[B,H,W] --00--00 DADR[H,W] ----XXXX XXXXXXXX - - 155 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.19 HDMI-CEC HDMI-CEC/Remote Control Receiver ch.0 Base_Address : 0x4003_4000 HDMI-CEC/Remote Control Receiver ch.1 Base_Address : 0x4003_4100 Register Base_Address + Address +3 +2 +1 0x000 - - - 0x004 --0000-0 TXDATA[B,H,W] - 00000000 TXSTS[B,H,W] - - - 0x00C - - - 0x010 – 0x03C - - - - 0x040 - - RCCR[B,H,W] RCST[B,H,W] - - 0x048 - - 0x04C - - 0x050 - - 0x054 - - 0x058 CONFIDENTIAL - TXCTRL[B,H,W] 0x008 0x044 156 - +0 - - 0x060 - - 0x064 - - 0x068 – 0x0FC - - SFREE[B,H,W] ----0000 0---0000 00000000 RCSHW[B,H,W] RCDAHW[B,H,W] 00000000 00000000 RCDBHW[B,H,W] - 00000000 RCADR1[B,H,W] RCADR2[B,H,W] ---00000 ---00000 RCDTHH[B,H,W] RCDTHL[B,H,W] 00000000 00000000 RCDTLH[B,H,W] RCDTLL[B,H,W] 00000000 00000000 RCCKD[B,H,W] - 0x05C --00---0 ---00000 00000000 RCRC[B,H,W] RCRHW[B,H,W] ---0---0 00000000 RCLE[B,H,W] 00000-00 - RCLELW[B,H,W] RCLESW[B,H,W] 00000000 00000000 - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.20 GPIO 1.20.1 TYPE1-M4, TYPE2-M4 products GPIO Base_Address : 0x4006_F000 Register Base_Address + Address +3 PFR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PFR2[B,H,W] 0x008 ---- ---- ---- ---- 0000 0000 0000 0000 PFR3[B,H,W] 0x00C ---- ---- ---- ---- 0000 0000 0000 0000 PFR4[B,H,W] 0x010 ---- ---- ---- ---- 0000 0000 0000 0000 PFR5[B,H,W] 0x014 ---- ---- ---- ---- 0000 0000 0000 0000 PFR6[B,H,W] 0x018 ---- ---- ---- ---- 0000 0000 0000 0000 PFR7[B,H,W] 0x01C ---- ---- ---- ---- 0000 0000 0000 0000 PFR8[B,H,W] 0x020 ---- ---- ---- ---- 0000 0000 0000 0000 PFR9[B,H,W] 0x024 ---- ---- ---- ---- 0000 0000 0000 0000 PFRA[B,H,W] 0x028 ---- ---- ---- ---- 0000 0000 0000 0000 PFRB[B,H,W] 0x02C ---- ---- ---- ---- 0000 0000 0000 0000 PFRC[B,H,W] 0x030 ---- ---- ---- ---- 0000 0000 0000 0000 PFRD[B,H,W] 0x034 ---- ---- ---- ---- 0000 0000 0000 0000 PFRE[B,H,W] 0x038 ---- ---- ---- ---- 0000 0000 0000 0000 PFRF[B,H,W] 0x03C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0001 1111 0x004 February 10, 2015, FM4_MN709-00019-1v0-E +1 PFR0[B,H,W] 0x000 0x040 - 0x0FC +2 ---- ---- ---- ---- 0000 0000 0000 0000 - - - - 157 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 PCR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PCR2[B,H,W] 0x108 ---- ---- ---- ---- 0000 0000 0000 0000 PCR3[B,H,W] 0x10C ---- ---- ---- ---- 0000 0000 0000 0000 PCR4[B,H,W] 0x110 ---- ---- ---- ---- 0000 0000 0000 0000 PCR5[B,H,W] 0x114 ---- ---- ---- ---- 0000 0000 0000 0000 PCR6[B,H,W] 0x118 ---- ---- ---- ---- 0000 0000 0000 0000 PCR7[B,H,W] 0x11C ---- ---- ---- ---- 0000 0000 0000 0000 0x120 PCR9[B,H,W] 0x124 ---- ---- ---- ---- 0000 0000 0000 0000 PCRA[B,H,W] 0x128 ---- ---- ---- ---- 0000 0000 0000 0000 PCRB[B,H,W] 0x12C ---- ---- ---- ---- 0000 0000 0000 0000 PCRC[B,H,W] 0x130 ---- ---- ---- ---- 0000 0000 0000 0000 PCRD[B,H,W] 0x134 ---- ---- ---- ---- 0000 0000 0000 0000 PCRE[B,H,W] 0x138 ---- ---- ---- ---- 0000 0000 0000 0000 PCRF[B,H,W] 0x13C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0001 1111 0x104 158 +1 PCR0[B,H,W] 0x100 0x140 - 0x1FC M A N U A L ---- ---- ---- ---- 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 DDR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 DDR2[B,H,W] 0x208 ---- ---- ---- ---- 0000 0000 0000 0000 DDR3[B,H,W] 0x20C ---- ---- ---- ---- 0000 0000 0000 0000 DDR4[B,H,W] 0x210 ---- ---- ---- ---- 0000 0000 0000 0000 DDR5[B,H,W] 0x214 ---- ---- ---- ---- 0000 0000 0000 0000 DDR6[B,H,W] 0x218 ---- ---- ---- ---- 0000 0000 0000 0000 DDR7[B,H,W] 0x21C ---- ---- ---- ---- 0000 0000 0000 0000 DDR8[B,H,W] 0x220 ---- ---- ---- ---- 0000 0000 0000 0000 DDR9[B,H,W] 0x224 ---- ---- ---- ---- 0000 0000 0000 0000 DDRA[B,H,W] 0x228 ---- ---- ---- ---- 0000 0000 0000 0000 DDRB[B,H,W] 0x22C ---- ---- ---- ---- 0000 0000 0000 0000 DDRC[B,H,W] 0x230 ---- ---- ---- ---- 0000 0000 0000 0000 DDRD[B,H,W] 0x234 ---- ---- ---- ---- 0000 0000 0000 0000 DDRE[B,H,W] 0x238 ---- ---- ---- ---- 0000 0000 0000 0000 DDRF[B,H,W] 0x23C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x204 February 10, 2015, FM4_MN709-00019-1v0-E +1 DDR0[B,H,W] 0x200 0x240 - 0x2FC +2 ---- ---- ---- ---- 0000 0000 0000 0000 - - - - 159 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +0 PDIR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDIR2[B,H,W] 0x308 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR3[B,H,W] 0x30C ---- ---- ---- ---- 0000 0000 0000 0000 PDIR4[B,H,W] 0x310 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR5[B,H,W] 0x314 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR6[B,H,W] 0x318 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR7[B,H,W] 0x31C ---- ---- ---- ---- 0000 0000 0000 0000 PDIR8[B,H,W] 0x320 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR9[B,H,W] 0x324 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRA[B,H,W] 0x328 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRB[B,H,W] 0x32C ---- ---- ---- ---- 0000 0000 0000 0000 PDIRC[B,H,W] 0x330 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRD[B,H,W] 0x334 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRE[B,H,W] 0x338 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRF[B,H,W] 0x33C CONFIDENTIAL +1 ---- ---- ---- ---- 0000 0000 0000 0000 0x304 160 +2 PDIR0[B,H,W] 0x300 0x340 - 0x3FC M A N U A L ---- ---- ---- ---- 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 PDOR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDOR2[B,H,W] 0x408 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR3[B,H,W] 0x40C ---- ---- ---- ---- 0000 0000 0000 0000 PDOR4[B,H,W] 0x410 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR5[B,H,W] 0x414 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR6[B,H,W] 0x418 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR7[B,H,W] 0x41C ---- ---- ---- ---- 0000 0000 0000 0000 PDOR8[B,H,W] 0x420 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR9[B,H,W] 0x424 ---- ---- ---- ---- 0000 0000 0000 0000 PDORA[B,H,W] 0x428 ---- ---- ---- ---- 0000 0000 0000 0000 PDORB[B,H,W] 0x42C ---- ---- ---- ---- 0000 0000 0000 0000 PDORC[B,H,W] 0x430 ---- ---- ---- ---- 0000 0000 0000 0000 PDORD[B,H,W] 0x434 ---- ---- ---- ---- 0000 0000 0000 0000 PDORE[B,H,W] 0x438 ---- ---- ---- ---- 0000 0000 0000 0000 PDORF[B,H,W] 0x43C ---- ---- ---- ---- 0000 0000 0000 0000 - CONFIDENTIAL - - 1111 1111 1111 1111 1111 1111 1111 1111 - - - - SPSR[B,H,W] 0x580 February 10, 2015, FM4_MN709-00019-1v0-E ADE[B,H,W] 0x500 0x584 - 0x5FC +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x404 0x504 - 0x57C +1 PDOR0[B,H,W] 0x400 0x440 - 0x4FC +2 ---- ---- ---- ---- ---- ---- --00 01-- - - - 161 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +0 EPFR01[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR02[B,H,W] 0x608 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR03[B,H,W] 0x60C 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR04[B,H,W] 0x610 --00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W] 0x614 --00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W] 0x618 0000 0000 0000 0000 0000 0000 0000 0000 EPFR07[B,H,W] 0x61C 0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W] 0x620 0000 0000 0000 0000 0000 0000 0000 0000 EPFR09[B,H,W] 0x624 0000 0000 0000 0000 0000 0000 0000 0000 EPFR10[B,H,W] 0x628 0000 0000 0000 0000 0000 0000 0000 0000 EPFR11[B,H,W] 0x62C ---- --00 0000 0000 0000 0000 0000 0000 EPFR12[B,H,W] 0x630 --00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W] 0x634 --00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W] 0x638 --00 0000 0000 00-- ---- ---- --00 0000 EPFR15[B,H,W] 0x63C 0000 0000 0000 0000 0000 0000 0000 0000 EPFR16[B,H,W] 0x640 --00 0000 0000 0000 0000 0000 0000 0000 EPFR17[B,H,W] 0x644 ---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W] 0x648 --00 0000 0000 0000 00-- --00 0000 ---EPFR19[B,H,W] 0x64C ---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W] 0x650 CONFIDENTIAL +1 ---- --00 ---- --11 --0- --0- 0000 --00 0x604 162 +2 EPFR00[B,H,W] 0x600 0x654 – 0x6FC M A N U A L ---- ---0 0000 0000 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 PZR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR2[B,H,W] 0x708 ---- ---- ---- ---- 0000 0000 0000 0000 PZR3[B,H,W] 0x70C ---- ---- ---- ---- 0000 0000 0000 0000 PZR4[B,H,W] 0x710 ---- ---- ---- ---- 0000 0000 0000 0000 PZR5[B,H,W] 0x714 ---- ---- ---- ---- 0000 0000 0000 0000 PZR6[B,H,W] 0x718 ---- ---- ---- ---- 0000 0000 0000 0000 PZR7[B,H,W] 0x71C ---- ---- ---- ---- 0000 0000 0000 0000 PZR8[B,H,W] 0x720 ---- ---- ---- ---- 0000 0000 0000 0000 PZR9[B,H,W] 0x724 ---- ---- ---- ---- 0000 0000 0000 0000 PZRA[B,H,W] 0x728 ---- ---- ---- ---- 0000 0000 0000 0000 PZRB[B,H,W] 0x72C ---- ---- ---- ---- 0000 0000 0000 0000 PZRC[B,H,W] 0x730 ---- ---- ---- ---- 0000 0000 0000 0000 PZRD[B,H,W] 0x734 ---- ---- ---- ---- 0000 0000 0000 0000 PZRE[B,H,W] 0x738 ---- ---- ---- ---- 0000 0000 0000 0000 PZRF[B,H,W] 0x73C ---- ---- ---- ---- 0000 0000 0000 0000 - - 0xF00 – 0xF04 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - - - - - - * - - - - 0xFE0 0xFE4 - 0xFFC +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x704 0xF08 – 0xFDC +1 PZR0[B,H,W] 0x700 0x740 - 0xEFC +2 * 163 A. Register Map 1. Register Map P E R I P H E R A L 1.20.2 TYPE3-M4 product GPIO Base_Address : 0x4006_F000 Register Base_Address + Address +3 +0 PFR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PFR2[B,H,W] 0x008 ---- ---- ---- ---- 0000 0000 0000 0000 PFR3[B,H,W] 0x00C ---- ---- ---- ---- 0000 0000 0000 0000 PFR4[B,H,W] 0x010 ---- ---- ---- ---- 0000 0000 0000 0000 PFR5[B,H,W] 0x014 ---- ---- ---- ---- 0000 0000 0000 0000 PFR6[B,H,W] 0x018 ---- ---- ---- ---- 0000 0000 0000 0000 PFR7[B,H,W] 0x01C ---- ---- ---- ---- 0000 0000 0000 0000 PFR8[B,H,W] 0x020 ---- ---- ---- ---- 0000 0000 0000 0000 PFR9[B,H,W] 0x024 ---- ---- ---- ---- 0000 0000 0000 0000 PFRA[B,H,W] 0x028 ---- ---- ---- ---- 0000 0000 0000 0000 PFRB[B,H,W] 0x02C ---- ---- ---- ---- 0000 0000 0000 0000 PFRC[B,H,W] 0x030 ---- ---- ---- ---- 0000 0000 0000 0000 PFRD[B,H,W] 0x034 ---- ---- ---- ---- 0000 0000 0000 0000 PFRE[B,H,W] 0x038 ---- ---- ---- ---- 0000 0000 0000 0000 PFRF[B,H,W] 0x03C CONFIDENTIAL +1 ---- ---- ---- ---- 0000 0000 0001 1111 0x004 0x040 - 0x0FC +2 PFR0[B,H,W] 0x000 164 M A N U A L ---- ---- ---- ---- 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 ---- ---- ---- ---- 0000 0000 0001 1111 PCR1[B,H,W] 0x104 ---- ---- ---- ---- 0000 0000 0000 0000 PCR2[B,H,W] 0x108 ---- ---- ---- ---- 0000 0000 0000 0000 PCR3[B,H,W] 0x10C ---- ---- ---- ---- 0000 0000 0000 0000 PCR4[B,H,W] 0x110 ---- ---- ---- ---- 0000 0000 0000 0000 PCR5[B,H,W] 0x114 ---- ---- ---- ---- 0000 0000 0000 0000 PCR6[B,H,W] 0x118 ---- ---- ---- ---- 0000 0000 0000 0000 PCR7[B,H,W] 0x11C ---- ---- ---- ---- 0000 0000 0000 0000 0x120 PCR9[B,H,W] 0x124 ---- ---- ---- ---- 0000 0000 0000 0000 PCRA[B,H,W] 0x128 ---- ---- ---- ---- 0000 0000 0000 0000 PCRB[B,H,W] 0x12C ---- ---- ---- ---- 0000 0000 0000 0000 PCRC[B,H,W] 0x130 ---- ---- ---- ---- 0000 0000 0000 0000 PCRD[B,H,W] 0x134 ---- ---- ---- ---- 0000 0000 0000 0000 PCRE[B,H,W] 0x138 ---- ---- ---- ---- 0000 0000 0000 0000 PCRF[B,H,W] 0x13C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 PCR0[B,H,W] 0x100 0x140 - 0x1FC +1 ---- ---- ---- ---- 0000 0000 0000 0000 - - - - 165 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +0 DDR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 DDR2[B,H,W] 0x208 ---- ---- ---- ---- 0000 0000 0000 0000 DDR3[B,H,W] 0x20C ---- ---- ---- ---- 0000 0000 0000 0000 DDR4[B,H,W] 0x210 ---- ---- ---- ---- 0000 0000 0000 0000 DDR5[B,H,W] 0x214 ---- ---- ---- ---- 0000 0000 0000 0000 DDR6[B,H,W] 0x218 ---- ---- ---- ---- 0000 0000 0000 0000 DDR7[B,H,W] 0x21C ---- ---- ---- ---- 0000 0000 0000 0000 DDR8[B,H,W] 0x220 ---- ---- ---- ---- 0000 0000 0000 0000 DDR9[B,H,W] 0x224 ---- ---- ---- ---- 0000 0000 0000 0000 DDRA[B,H,W] 0x228 ---- ---- ---- ---- 0000 0000 0000 0000 DDRB[B,H,W] 0x22C ---- ---- ---- ---- 0000 0000 0000 0000 DDRC[B,H,W] 0x230 ---- ---- ---- ---- 0000 0000 0000 0000 DDRD[B,H,W] 0x234 ---- ---- ---- ---- 0000 0000 0000 0000 DDRE[B,H,W] 0x238 ---- ---- ---- ---- 0000 0000 0000 0000 DDRF[B,H,W] 0x23C CONFIDENTIAL +1 ---- ---- ---- ---- 0000 0000 0000 0000 0x204 166 +2 DDR0[B,H,W] 0x200 0x240 - 0x2FC M A N U A L ---- ---- ---- ---- 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 PDIR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDIR2[B,H,W] 0x308 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR3[B,H,W] 0x30C ---- ---- ---- ---- 0000 0000 0000 0000 PDIR4[B,H,W] 0x310 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR5[B,H,W] 0x314 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR6[B,H,W] 0x318 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR7[B,H,W] 0x31C ---- ---- ---- ---- 0000 0000 0000 0000 PDIR8[B,H,W] 0x320 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR9[B,H,W] 0x324 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRA[B,H,W] 0x328 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRB[B,H,W] 0x32C ---- ---- ---- ---- 0000 0000 0000 0000 PDIRC[B,H,W] 0x330 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRD[B,H,W] 0x334 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRE[B,H,W] 0x338 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRF[B,H,W] 0x33C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x304 February 10, 2015, FM4_MN709-00019-1v0-E +1 PDIR0[B,H,W] 0x300 0x340 - 0x3FC +2 ---- ---- ---- ---- 0000 0000 0000 0000 - - - - 167 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 PDOR1[B,H,W] PDOR2[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDOR3[B,H,W] 0x40C ---- ---- ---- ---- 0000 0000 0000 0000 PDOR4[B,H,W] 0x410 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR5[B,H,W] 0x414 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR6[B,H,W] 0x418 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR7[B,H,W] 0x41C ---- ---- ---- ---- 0000 0000 0000 0000 PDOR8[B,H,W] 0x420 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR9[B,H,W] 0x424 ---- ---- ---- ---- 0000 0000 0000 0000 PDORA[B,H,W] 0x428 ---- ---- ---- ---- 0000 0000 0000 0000 PDORB[B,H,W] 0x42C ---- ---- ---- ---- 0000 0000 0000 0000 PDORC[B,H,W] 0x430 ---- ---- ---- ---- 0000 0000 0000 0000 PDORD[B,H,W] 0x434 ---- ---- ---- ---- 0000 0000 0000 0000 PDORE[B,H,W] 0x438 ---- ---- ---- ---- 0000 0000 0000 0000 PDORF[B,H,W] 0x43C ---- ---- ---- ---- 0000 0000 0000 0000 - - - 1111 1111 1111 1111 1111 1111 1111 1111 - - - - SPSR[B,H,W] 0x580 CONFIDENTIAL ADE[B,H,W] 0x500 168 +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x408 0x584 - 0x5FC +1 ---- ---- ---- ---- 0000 0000 0000 0000 0x404 0x504 - 0x57C +2 PDOR0[B,H,W] 0x400 0x440 - 0x4FC M A N U A L ---- ---- ---- ---- ---- ---- --00 01-- - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620 0x624 0x628 0x62C 0x630 0x634 0x638 0x63C 0x640 0x644 0x648 0x64C 0x650 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 EPFR00[B,H,W] ---- 0000 ---- --11 --0- --0- 0000 –00 EPFR01[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR02[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR03[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR04[B,H,W] --00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W] --00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR07[B,H,W] 0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR09[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR10[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR11[B,H,W] ---- --00 0000 0000 0000 0000 0000 0000 EPFR12[B,H,W] --00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W] --00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W] --00 0000 0000 00-- ---- ---- --00 0000 EPFR15[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR16[B,H,W] --00 0000 0000 0000 0000 0000 0000 0000 EPFR17[B,H,W] ---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W] --00 0000 0000 0000 00-- --00 0000 0000 EPFR19[B,H,W] ---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W] ---- ---0 0000 0000 0000 0000 0000 0000 169 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +0 EPFR22[B,H,W] ---- ---- ---- ---- ---- ---- ---- ---EPFR23[B,H,W] 0x65C ---- ---- ---- ---- 0000 0000 0000 0000 EPFR24[B,H,W] 0x660 ---- ---- ---- ---- ---- 0000 0000 0000 EPFR25[B,H,W] 0x664 ---- ---- ---- ---- ---- ---- ---- 0000 EPFR26[B,H,W] 0x668 CONFIDENTIAL +1 ---- ---- ---- ---- ---- ---- ---- ---- 0x658 170 +2 EPFR21[B,H,W] 0x654 0x66C – 0x6FC M A N U A L ---- ---- ---- --00 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x700 0x704 0x708 0x70C 0x710 0x714 0x718 0x71C 0x720 0x724 0x728 0x72C 0x730 0x734 0x738 0x73C 0x740 0x744 0x748 0x74C 0x750 0x754 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 PZR0[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR2[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR3[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR4[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR5[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR6[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR7[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR8[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR9[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRA[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRB[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRC[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRD[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRE[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRF[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR0[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR2[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR3[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR4[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR5[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 171 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 PDSR7[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDSR8[B,H,W] 0x760 ---- ---- ---- ---- 0000 0000 0000 0000 PDSR9[B,H,W] 0x764 ---- ---- ---- ---- 0000 0000 0000 0000 PDSRA[B,H,W] 0x768 ---- ---- ---- ---- 0000 0000 0000 0000 PDSRB[B,H,W] 0x76C ---- ---- ---- ---- 0000 0000 0000 0000 PDSRC[B,H,W] 0x770 ---- ---- ---- ---- 0000 0000 0000 0000 PDSRD[B,H,W] 0x774 ---- ---- ---- ---- 0000 0000 0000 0000 PDSRE[B,H,W] 0x778 ---- ---- ---- ---- 0000 0000 0000 0000 PDSRF[B,H,W] 0x77C ---- ---- ---- ---- 0000 0000 0000 0000 - - 0xF00 – 0xF04 172 CONFIDENTIAL - - - - - - * - - - - 0xFE0 0xFE4 - 0xFFC +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x75C 0xF08 – 0xFDC +1 PDSR6[B,H,W] 0x758 0x780 - 0xEFC M A N U A L * FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.20.3 M A N U A L TYPE4-M4 product GPIO Base_Address : 0x4006_F000 Register Base_Address + Address +3 PFR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PFR2[B,H,W] 0x008 ---- ---- ---- ---- 0000 0000 0000 0000 PFR3[B,H,W] 0x00C ---- ---- ---- ---- 0000 0000 0000 0000 PFR4[B,H,W] 0x010 ---- ---- ---- ---- 0000 0000 0000 0000 PFR5[B,H,W] 0x014 ---- ---- ---- ---- 0000 0000 0000 0000 PFR6[B,H,W] 0x018 ---- ---- ---- ---- 0000 0000 0000 0000 PFR7[B,H,W] 0x01C ---- ---- ---- ---- 0000 0000 0000 0000 PFR8[B,H,W] 0x020 ---- ---- ---- ---- 0000 0000 0000 0000 PFR9[B,H,W] 0x024 ---- ---- ---- ---- 0000 0000 0000 0000 PFRA[B,H,W] 0x028 ---- ---- ---- ---- 0000 0000 0000 0000 PFRB[B,H,W] 0x02C ---- ---- ---- ---- 0000 0000 0000 0000 PFRC[B,H,W] 0x030 ---- ---- ---- ---- 0000 0000 0000 0000 PFRD[B,H,W] 0x034 ---- ---- ---- ---- 0000 0000 0000 0000 PFRE[B,H,W] 0x038 ---- ---- ---- ---- 0000 0000 0000 0000 PFRF[B,H,W] 0x03C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0001 1111 0x004 February 10, 2015, FM4_MN709-00019-1v0-E +1 PFR0[B,H,W] 0x000 0x040 - 0x0FC +2 ---- ---- ---- ---- 0000 0000 0000 0000 - - - - 173 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 PCR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PCR2[B,H,W] 0x108 ---- ---- ---- ---- 0000 0000 0000 0000 PCR3[B,H,W] 0x10C ---- ---- ---- ---- 0000 0000 0000 0000 PCR4[B,H,W] 0x110 ---- ---- ---- ---- 0000 0000 0000 0000 PCR5[B,H,W] 0x114 ---- ---- ---- ---- 0000 0000 0000 0000 PCR6[B,H,W] 0x118 ---- ---- ---- ---- 0000 0000 0000 0000 PCR7[B,H,W] 0x11C ---- ---- ---- ---- 0000 0000 0000 0000 0x120 PCR9[B,H,W] 0x124 ---- ---- ---- ---- 0000 0000 0000 0000 PCRA[B,H,W] 0x128 ---- ---- ---- ---- 0000 0000 0000 0000 PCRB[B,H,W] 0x12C ---- ---- ---- ---- 0000 0000 0000 0000 PCRC[B,H,W] 0x130 ---- ---- ---- ---- 0000 0000 0000 0000 PCRD[B,H,W] 0x134 ---- ---- ---- ---- 0000 0000 0000 0000 PCRE[B,H,W] 0x138 ---- ---- ---- ---- 0000 0000 0000 0000 PCRF[B,H,W] 0x13C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0001 1111 0x104 174 +1 PCR0[B,H,W] 0x100 0x140 - 0x1FC M A N U A L ---- ---- ---- ---- 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 DDR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 DDR2[B,H,W] 0x208 ---- ---- ---- ---- 0000 0000 0000 0000 DDR3[B,H,W] 0x20C ---- ---- ---- ---- 0000 0000 0000 0000 DDR4[B,H,W] 0x210 ---- ---- ---- ---- 0000 0000 0000 0000 DDR5[B,H,W] 0x214 ---- ---- ---- ---- 0000 0000 0000 0000 DDR6[B,H,W] 0x218 ---- ---- ---- ---- 0000 0000 0000 0000 DDR7[B,H,W] 0x21C ---- ---- ---- ---- 0000 0000 0000 0000 DDR8[B,H,W] 0x220 ---- ---- ---- ---- 0000 0000 0000 0000 DDR9[B,H,W] 0x224 ---- ---- ---- ---- 0000 0000 0000 0000 DDRA[B,H,W] 0x228 ---- ---- ---- ---- 0000 0000 0000 0000 DDRB[B,H,W] 0x22C ---- ---- ---- ---- 0000 0000 0000 0000 DDRC[B,H,W] 0x230 ---- ---- ---- ---- 0000 0000 0000 0000 DDRD[B,H,W] 0x234 ---- ---- ---- ---- 0000 0000 0000 0000 DDRE[B,H,W] 0x238 ---- ---- ---- ---- 0000 0000 0000 0000 DDRF[B,H,W] 0x23C CONFIDENTIAL +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x204 February 10, 2015, FM4_MN709-00019-1v0-E +1 DDR0[B,H,W] 0x200 0x240 - 0x2FC +2 ---- ---- ---- ---- 0000 0000 0000 0000 - - - - 175 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +0 PDIR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDIR2[B,H,W] 0x308 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR3[B,H,W] 0x30C ---- ---- ---- ---- 0000 0000 0000 0000 PDIR4[B,H,W] 0x310 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR5[B,H,W] 0x314 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR6[B,H,W] 0x318 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR7[B,H,W] 0x31C ---- ---- ---- ---- 0000 0000 0000 0000 PDIR8[B,H,W] 0x320 ---- ---- ---- ---- 0000 0000 0000 0000 PDIR9[B,H,W] 0x324 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRA[B,H,W] 0x328 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRB[B,H,W] 0x32C ---- ---- ---- ---- 0000 0000 0000 0000 PDIRC[B,H,W] 0x330 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRD[B,H,W] 0x334 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRE[B,H,W] 0x338 ---- ---- ---- ---- 0000 0000 0000 0000 PDIRF[B,H,W] 0x33C CONFIDENTIAL +1 ---- ---- ---- ---- 0000 0000 0000 0000 0x304 176 +2 PDIR0[B,H,W] 0x300 0x340 - 0x3FC M A N U A L ---- ---- ---- ---- 0000 0000 0000 0000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 PDOR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PDOR2[B,H,W] 0x408 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR3[B,H,W] 0x40C ---- ---- ---- ---- 0000 0000 0000 0000 PDOR4[B,H,W] 0x410 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR5[B,H,W] 0x414 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR6[B,H,W] 0x418 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR7[B,H,W] 0x41C ---- ---- ---- ---- 0000 0000 0000 0000 PDOR8[B,H,W] 0x420 ---- ---- ---- ---- 0000 0000 0000 0000 PDOR9[B,H,W] 0x424 ---- ---- ---- ---- 0000 0000 0000 0000 PDORA[B,H,W] 0x428 ---- ---- ---- ---- 0000 0000 0000 0000 PDORB[B,H,W] 0x42C ---- ---- ---- ---- 0000 0000 0000 0000 PDORC[B,H,W] 0x430 ---- ---- ---- ---- 0000 0000 0000 0000 PDORD[B,H,W] 0x434 ---- ---- ---- ---- 0000 0000 0000 0000 PDORE[B,H,W] 0x438 ---- ---- ---- ---- 0000 0000 0000 0000 PDORF[B,H,W] 0x43C ---- ---- ---- ---- 0000 0000 0000 0000 - CONFIDENTIAL - - 1111 1111 1111 1111 1111 1111 1111 1111 - - - - SPSR[B,H,W] 0x580 February 10, 2015, FM4_MN709-00019-1v0-E ADE[B,H,W] 0x500 0x584 - 0x5FC +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x404 0x504 - 0x57C +1 PDOR0[B,H,W] 0x400 0x440 - 0x4FC +2 ---- ---- ---- ---- ---- ---- --00 01-- - - - 177 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x600 0x604 0x608 0x60C 0x610 0x614 0x618 0x61C 0x620 0x624 0x628 0x62C 0x630 0x634 0x638 0x63C 0x640 0x644 0x648 0x64C 0x650 178 CONFIDENTIAL M A N U A L +3 +2 +1 +0 EPFR00[B,H,W] ---- 0000 ---- --11 --0- --0- 0000 –00 EPFR01[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR02[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR03[B,H,W] 0000 0000 0000 0000 ---0 0000 0000 0000 EPFR04[B,H,W] --00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W] --00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR07[B,H,W] 0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR09[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR10[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR11[B,H,W] ---- --00 0000 0000 0000 0000 0000 0000 EPFR12[B,H,W] --00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W] --00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W] --00 0000 0000 00-- ---- ---- --00 0000 EPFR15[B,H,W] 0000 0000 0000 0000 0000 0000 0000 0000 EPFR16[B,H,W] --00 0000 0000 0000 0000 0000 0000 0000 EPFR17[B,H,W] ---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W] --00 0000 0000 0000 00-- --00 0000 0000 EPFR19[B,H,W] ---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W] ---- ---0 0000 0000 0000 0000 0000 0000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 EPFR22[B,H,W] ---- ---- ---- ---- ---- ---- ---- ---EPFR23[B,H,W] 0x65C ---- ---- ---- ---- 0000 0000 0000 0000 EPFR24[B,H,W] 0x660 ---- 0000 0000 0000 ---- 0000 0000 0000 EPFR25[B,H,W] 0x664 ---- ---- ---- ---- ---- ---- ---- 0000 EPFR26[B,H,W] 0x668 ---- ---- ---- --00 0000 0000 0000 0000 EPFR27[B,H,W] 0x66C 0000 0000 0000 0000 0000 0000 0000 0000 EPFR28[B,H,W] 0x670 0000 0000 0000 0000 0000 0000 0000 0000 EPFR29[B,H,W] 0x674 0000 0000 0000 00-- 0000 0000 0000 0000 EPFR30[B,H,W] 0x67C 0x704 0x708 0x70C 0x710 0x714 0x718 0x71C 0x720 0x724 0x728 0x72C 0x730 0x734 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 ---- ---- ---- ---- ---- ---- ---- ---- 0x658 0x700 +1 EPFR21[B,H,W] 0x654 0x680 – 0x6FC +2 ---- --00 0000 0000 ---- 0000 0000 0000 - - - - PZR0[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR1[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR2[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR3[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR4[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR5[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR6[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR7[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR8[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZR9[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRA[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRB[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRC[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 PZRD[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 179 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 PZRF[B,H,W] ---- ---- ---- ---- 0000 0000 0000 0000 - - - - - - 0xF00 – 0xF04 180 CONFIDENTIAL - - - - - - * 0xFE0 0xFE4 - 0xFFC +0 ---- ---- ---- ---- 0000 0000 0000 0000 0x73C 0xF08 – 0xFDC +1 PZRE[B,H,W] 0x738 0x740 - 0xEFC M A N U A L * FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.21 LVD LVD Base_Address : 0x4003_5000 Register Base_Address + Address +3 0x000 +2 - 0x004 - - 0x008 +1 - - - +0 LVD_CTL[B,H,W] 000111-LVD_STR[B,H,W] - - 0------LVD_CLR[B,H,W] - 1------- LVD_RLR[W] 0x00C 00000000 00000000 00000000 00000001 LVD_STR2 [B,H,W] 0x010 - - - 0x014 - 0x0FC - - - - 0------ 1.22 DS_Mode DS_Mode Base_Address : 0x4003_5100 Register Base_Address + Address +3 +2 +1 +0 0x000 - - - * 0x004 - - - 0x008 - 0x6FC - - - 0x700 - - - 0x704 - - - 0x708 - - 0x70C - - 0x710 - - 0x714 - 0x718 - 0x7FC 0x800 0x804 0x808 ------01 PMD_CTL[B,H,W] -------0 WRFSR[B,H,W] ------00 WIFSR[B,H,W] ------00 00000000 WIER[B,H,W] ------00 00000-00 - WILVR[B,H,W] ---00000 DSRAMR[B,H,W] ------00 - - - - BUR04[B,H,W] BUR03[B,H,W] BUR02[B,H,W] BUR01[B,H,W] 00000000 00000000 00000000 00000000 BUR08[B,H,W] BUR07[B,H,W] BUR06[B,H,W] BUR05[B,H,W] 00000000 00000000 00000000 00000000 BUR012[B,H,W] BUR11[B,H,W] BUR10[B,H,W] BUR09[B,H,W] 0x80C 0x810 - 0xEFC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - RCK_CTL[B,H,W] 00000000 00000000 00000000 00000000 BUR16[B,H,W] BUR15[B,H,W] BUR14[B,H,W] BUR13[B,H,W] 00000000 00000000 00000000 00000000 - - - 181 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.23 USB Clock USB Clock Base_Address : 0x4003_6000 Register Base_Address + Address 0x000 0x004 - - - +1 - - - - - 0x00C - - - 0x010 - - - 0x014 - - - 0x018 - - - 0x01C - - - 0x024 CONFIDENTIAL - +2 0x008 0x020 182 +3 - - - 0x028 - - - 0x02C - - - 0x030 - - - 0x034 - - - 0x038 - 0x0FC - - - +0 UCCR[B,H,W] -0000000 UPCR1[B,H,W] ------00 UPCR2[B,H,W] -----000 UPCR3[B,H,W] ---00000 UPCR4[B,H,W] -0111011 UP_STR[B,H,W] -------0 UPINT_ENR[B,H,W] -------0 UPINT_CLR[B,H,W] -------0 UPINT_STR[B,H,W] -------0 UPCR5[B,H,W] ----0100 UPCR6[B,H,W] ----0010 UPCR7[B,H,W] -------0 USBEN0[B,H,W] -------0 USBEN1[B,H,W] -------0 - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.24 CAN_Prescaler CAN_Prescaler Base_Address : 0x4003_7000 Register Base_Address + Address +3 +2 +1 +0 CANPRE[B,H,W] 0x000 - - - 0x004 - 0xFFC - - - - +1 +0 ----1011 1.25 MFS MFS ch.0 Base_Address : 0x4003_8000 MFS ch.1 Base_Address : 0x4003_8100 MFS ch.2 Base_Address : 0x4003_8200 MFS ch.3 Base_Address : 0x4003_8300 MFS ch.4 Base_Address : 0x4003_8400 MFS ch.5 Base_Address : 0x4003_8500 MFS ch.6 Base_Address : 0x4003_8600 MFS ch.7 Base_Address : 0x4003_8700 MFS ch.8 Base_Address : 0x4003_8800 MFS ch.9 Base_Address : 0x4003_8900 MFS ch.10Base_Address : 0x4003_8A00 MFS ch.11 Base_Address : 0x4003_8B00 MFS ch.12Base_Address : 0x4003_8C00 MFS ch.13Base_Address : 0x4003_8D00 MFS ch.14Base_Address : 0x4003_8E00 MFS ch.15Base_Address : 0x4003_8F00 Register Base_Address + Address +3 +2 SCR / 0x000 - - IBCR[B,H,W] SMR[B,H,W] 000-00-0 0--00000 0x004 0x008 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - - - - SSR[B,H,W] 0-000011 ESCR / IBSR[B,H,W] 00000000 RDR/TDR[H,W] 00000000 00000000 183 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +3 0x00C - - 0x010 - - 0x014 - - 0x018 0x01C 0x020 0x024 0x028 184 CONFIDENTIAL M A N U A L - - - - - - 0x02C - - 0x030 - - 0x034 - - 0x038 - - 0x03C - - 0x040 - - 0x0144 - 0x1FC - - +3 +3 BGR1[B,H,W] BGR0[B,H,W] 00000000 00000000 ISMK[B,H,W] ISBA[B,H,W] -------- -------- FCR1[B,H,W] FCR0[B,H,W] ---00100 -0000000 FBYTE2[B,H,W] FBYTE1[B,H,W] 00000000 00000000 SCSTR1/ SCSTR0/ EIBCR[B,H,W] NFCR[B,H,W] 00000000 00000000 SCSTR3[B,H,W] SCSTR2[B,H,W] 00000000 00000000 SACSR1[B,H,W] SACSR0[B,H,W] 00000000 00000000 STMR1[B,H,W] STMR0[B,H,W] 00000000 00000000 STMCR1[B,H,W] STMCR0[B,H,W] 00000000 00000000 SCSCR1[B,H,W] SCSCR0[B,H,W] 00000000 00100000 SCSFR1[B,H,W] SCSFR0[B,H,W] 10000000 10000000 - SCSFR2[B,H,W] 10000000 TBYTE1[B,H,W] TBYTE0[B,H,W] 00000000 00000000 TBYTE3[B,H,W] TBYTE2[B,H,W] 00000000 00000000 - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.26 CRC CRC Base_Address : 0x4003_9000 Base_Address + Address 0x000 Register +3 - +2 +1 - +0 CRCCR[B,H,W] - -0000000 CRCINIT[B,H,W] 0x004 11111111 11111111 11111111 11111111 CRCIN[B,H,W] 0x008 00000000 00000000 00000000 00000000 CRCR[B,H,W] 0x00C 11111111 11111111 11111111 11111111 1.27 Watch Counter Watch Counter Base_Address : 0x4003_A000 Base_Address +3 +2 +1 +0 0x000 - WCCR[B,H,W] WCRL[B,H,W] WCRD[B,H,W] 00--0000 --000000 --000000 0x004 - 0x00C - - - - 0x010 - - 0x014 - - - 0x018 - 0xFFC - - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL Register + Address CLK_SEL[B,H,W] -----000 -------0 CLK_EN[B,H,W] ------00 - 185 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.28 RTC 1.28.1 TYPE1-M4, TYPE2-M4, TYPE3-M4 products RTC Base_Address : 0x4003_B000 Register Base_Address + Address 0x100 - +1 - - - - 0x108 - - - 0x10C - - - 0x110 - - - 0x114 - - - 0x118 - - - 0x11C - - - 0x120 - - - 0x124 - - - 0x128 - - - 0x12C - - - - - - 0x134 - - - 0x138 - - - 0x13C - - - 0x140 - - - 0x144 - - - 0x148 - - - 0x14C - - - 0x150 0x154 CONFIDENTIAL - +2 0x104 0x130 186 +3 - - - +0 WTCR10[B,H,W] 00000000 WTCR11[B,H,W] ---00000 WTCR12[B,H,W] 00000000 WTCR13[B,H,W] 00000000 WTCR20[B,H,W] --000000 WTCR21[B,H,W] -----000 * WTSR[B,H,W] -0000000 WTMIR[B,H,W] -0000000 WTHR[B,H,W] --000000 WTDR[B,H,W] --000000 WTDW[B,H,W] -----000 WTMOR[B,H,W] ---00000 WTYR[B,H,W] 00000000 ALMIR[B,H,W] -0000000 ALHR[B,H,W] --000000 ALDR[B,H,W] --000000 ALMOR[B,H,W] ---00000 ALYR[B,H,W] 00000000 WTTR0[B,H,W] 00000000 WTTR1[B,H,W] 00000000 WTTR2[B,H,W] ------00 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 +1 0x158 - - - 0x15C - - 0x160 - - - 0x164 - - - 0x168 - - - 0x16C - - - 0x170 - - - 0x174 - - - 0x178 - - - 0x17C - - - 0x180 - - - 0x184 - - - 0x188 - - - 0x18C - - - 0x190 - - - 0x194 - - - 0x198 - - - 0x19C - - - 0x1A0 - - - 0x1A4 - - - 0x1A8 - - - 0x1AC - - - 0x0B0 - - - 0x1B4-1FF - - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - +0 WTCAL0[B,H,W] 00000000 WTCAL1[B,H,W] ------00 WTCALEN[B,H,W] -------0 WTDIV[B,H,W] ----0000 WTDIVEN[B,H,W] ------00 WTCALPRD[B,H,W] --010011 WTCOSEL[B,H,W] -------0 VB_CLKDIV[B,H,W] 00000111 WTOSCCNT[B,H,W] ------01 CCS[B,H,W] 00001000 CCB[B,H,W] 00010000 * BOOST[B,H,W] ------11 EWKUP[B,H,W] -------0 VDET[B,H,W] 00-----* HIBRST[B,H,W] -------0 VBPFR[B,H,W] --011100 VBPCR[B,H,W] ----0000 VBDDR[B,H,W] ----XXXX VBDIR[B,H,W] ----0000 VBDOR[B,H,W] ----1111 VBPZR[B,H,W] ------11 - 187 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 188 CONFIDENTIAL +3 +2 +1 +0 BREG03[B,H,W] BREG02[B,H,W] BREG01[B,H,W] BREG00[B,H,W] 00000000 00000000 00000000 00000000 BREG07[B,H,W] BREG06[B,H,W] BREG05[B,H,W] BREG04[B,H,W] 00000000 00000000 00000000 00000000 BREG0B[B,H,W] BREG0A[B,H,W] BREG09[B,H,W] BREG08[B,H,W] 00000000 00000000 00000000 00000000 BREG0F[B,H,W] BREG0E[B,H,W] BREG0D[B,H,W] BREG0C[B,H,W] 00000000 00000000 00000000 00000000 BREG13[B,H,W] BREG12[B,H,W] BREG11[B,H,W] BREG10[B,H,W] 00000000 00000000 00000000 00000000 BREG17[B,H,W] BREG16[B,H,W] BREG15[B,H,W] BREG14[B,H,W] 00000000 00000000 00000000 00000000 BREG1B[B,H,W] BREG1A[B,H,W] BREG19[B,H,W] BREG18[B,H,W] 00000000 00000000 00000000 00000000 BREG1F[B,H,W] BREG1E[B,H,W] BREG1D[B,H,W] BREG1C[B,H,W] 00000000 00000000 00000000 00000000 BREG23[B,H,W] BREG22[B,H,W] BREG21[B,H,W] BREG20[B,H,W] 00000000 00000000 00000000 00000000 BREG27[B,H,W] BREG26[B,H,W] BREG25[B,H,W] BREG24[B,H,W] 00000000 00000000 00000000 00000000 BREG2B[B,H,W] BREG2A[B,H,W] BREG29[B,H,W] BREG28[B,H,W] 00000000 00000000 00000000 00000000 BREG2F[B,H,W] BREG2E[B,H,W] BREG2D[B,H,W] BREG2C[B,H,W] 00000000 00000000 00000000 00000000 BREG33[B,H,W] BREG32[B,H,W] BREG31[B,H,W] BREG30[B,H,W] 00000000 00000000 00000000 00000000 BREG37[B,H,W] BREG36[B,H,W] BREG35[B,H,W] BREG34[B,H,W] 00000000 00000000 00000000 00000000 BREG3B[B,H,W] BREG3A[B,H,W] BREG39[B,H,W] BREG38[B,H,W] 00000000 00000000 00000000 00000000 BREG3F[B,H,W] BREG3E[B,H,W] BREG3D[B,H,W] BREG3C[B,H,W] 00000000 00000000 00000000 00000000 BREG43[B,H,W] BREG42[B,H,W] BREG41[B,H,W] BREG40[B,H,W] 00000000 00000000 00000000 00000000 BREG47[B,H,W] BREG46[B,H,W] BREG45[B,H,W] BREG44[B,H,W] 00000000 00000000 00000000 00000000 BREG4B[B,H,W] BREG4A[B,H,W] BREG49[B,H,W] BREG48[B,H,W] 00000000 00000000 00000000 00000000 BREG4F[B,H,W] BREG4E[B,H,W] BREG4D[B,H,W] BREG4C[B,H,W] 00000000 00000000 00000000 00000000 BREG53[B,H,W] BREG52[B,H,W] BREG51[B,H,W] BREG50[B,H,W] 00000000 00000000 00000000 00000000 BREG57[B,H,W] BREG56[B,H,W] BREG55[B,H,W] BREG54[B,H,W] 00000000 00000000 00000000 00000000 BREG5B[B,H,W] BREG5A[B,H,W] BREG59[B,H,W] BREG58[B,H,W] 00000000 00000000 00000000 00000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C +3 +2 +1 +0 BREG5F[B,H,W] BREG5E[B,H,W] BREG5D[B,H,W] BREG5C[B,H,W] 00000000 00000000 00000000 00000000 BREG63[B,H,W] BREG62[B,H,W] BREG61[B,H,W] BREG60[B,H,W] 00000000 00000000 00000000 00000000 BREG67[B,H,W] BREG66[B,H,W] BREG65[B,H,W] BREG64[B,H,W] 00000000 00000000 00000000 00000000 BREG6B[B,H,W] BREG6A[B,H,W] BREG69[B,H,W] BREG68[B,H,W] 00000000 00000000 00000000 00000000 BREG6F[B,H,W] BREG6E[B,H,W] BREG6D[B,H,W] BREG6C[B,H,W] 00000000 00000000 00000000 00000000 BREG73[B,H,W] BREG72[B,H,W] BREG71[B,H,W] BREG70[B,H,W] 00000000 00000000 00000000 00000000 BREG77[B,H,W] BREG76[B,H,W] BREG75[B,H,W] BREG74[B,H,W] 00000000 00000000 00000000 00000000 BREG7B[B,H,W] BREG7A[B,H,W] BREG79[B,H,W] BREG78[B,H,W] 00000000 00000000 00000000 00000000 BREG7F[B,H,W] BREG7E[B,H,W] BREG7D[B,H,W] BREG7C[B,H,W] 00000000 00000000 00000000 00000000 - - - - 0x280-0xFFC 1.28.2 TYPE4-M4 product RTC Base_Address : 0x4003_B000 Register Base_Address + Address +2 +1 0x100 - - - 0x104 - - - 0x108 - - - 0x10C - - - 0x110 - - - 0x114 - - - 0x118 - - - 0x11C - - - 0x120 - - - 0x124 - - - 0x128 - - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +0 WTCR10[B,H,W] 00000000 WTCR11[B,H,W] ---00000 WTCR12[B,H,W] 00000000 WTCR13[B,H,W] 00000000 WTCR20[B,H,W] --000000 WTCR21[B,H,W] -----000 * WTSR[B,H,W] -0000000 WTMIR[B,H,W] -0000000 WTHR[B,H,W] --000000 WTDR[B,H,W] --000000 189 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 +1 0x12C - - - 0x130 - - - - - 0x138 - - - 0x13C - - - 0x140 - - - - - - 0x148 - - - 0x14C - - - 0x150 - - - 0x154 - - - 0x158 - - - 0x15C 0x160 CONFIDENTIAL - 0x134 0x144 190 M A N U A L - - - 0x164 - - - 0x168 - - - 0x16C - - - 0x170 - - - 0x174 - - - 0x178 - - - 0x17C - - - 0x180 - - - 0x184 - - - 0x188 - - - +0 WTDW[B,H,W] -----000 WTMOR[B,H,W] ---00000 WTYR[B,H,W] 00000000 ALMIR[B,H,W] -0000000 ALHR[B,H,W] --000000 ALDR[B,H,W] --000000 ALMOR[B,H,W] ---00000 ALYR[B,H,W] 00000000 WTTR0[B,H,W] 00000000 WTTR1[B,H,W] 00000000 WTTR2[B,H,W] ------00 WTCAL0[B,H,W] 00000000 WTCAL1[B,H,W] ------00 WTCALEN[B,H,W] -------0 WTDIV[B,H,W] ----0000 WTDIVEN[B,H,W] ------00 WTCALPRD[B,H,W] --010011 WTCOSEL[B,H,W] -------0 VB_DIVCLK[B,H,W] 00000111 WTOSCCNT[B,H,W] ------01 CCS[B,H,W] 11001110 CCB[B,H,W] 11001110 * BOOST[B,H,W] ------11 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 +1 0x18C - - - 0x190 - - - 0x194 - - - 0x198 - - - 0x19C - - EWKUP[B,H,W] -------0 VDET[B,H,W] 00-----* HIBRST[B,H,W] -------0 VBPFR[B,H,W] --011100 VBPCR[B,H,W] 0x1A0 - - - 0x1A4 - - - 0x1A8 - - - 0x1AC - - - 0x1B0 - - - 0x1B4-1FF - - - - BREG03[B,H,W] BREG02[B,H,W] BREG01[B,H,W] BREG00[B,H,W] 00000000 00000000 00000000 00000000 BREG07[B,H,W] BREG06[B,H,W] BREG05[B,H,W] BREG04[B,H,W] 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 ----0000 VBDDR[B,H,W] ----0000 VBDIR[B,H,W] ----XXXX VBDOR[B,H,W] ----1111 VBPZR[B,H,W] ------11 00000000 00000000 00000000 00000000 BREG0B[B,H,W] BREG0A[B,H,W] BREG09[B,H,W] BREG08[B,H,W] 00000000 00000000 00000000 00000000 BREG0F[B,H,W] BREG0E[B,H,W] BREG0D[B,H,W] BREG0C[B,H,W] 00000000 00000000 00000000 00000000 BREG13[B,H,W] BREG12[B,H,W] BREG11[B,H,W] BREG10[B,H,W] 00000000 00000000 00000000 00000000 BREG17[B,H,W] BREG16[B,H,W] BREG15[B,H,W] BREG14[B,H,W] 00000000 00000000 00000000 00000000 BREG1B[B,H,W] BREG1A[B,H,W] BREG19[B,H,W] BREG18[B,H,W] 00000000 00000000 00000000 00000000 BREG1F[B,H,W] BREG1E[B,H,W] BREG1D[B,H,W] BREG1C[B,H,W] 00000000 00000000 00000000 00000000 BREG23[B,H,W] BREG22[B,H,W] BREG21[B,H,W] BREG20[B,H,W] 00000000 00000000 00000000 00000000 BREG27[B,H,W] BREG26[B,H,W] BREG25[B,H,W] BREG24[B,H,W] 00000000 00000000 00000000 00000000 BREG2B[B,H,W] BREG2A[B,H,W] BREG29[B,H,W] BREG28[B,H,W] 00000000 00000000 00000000 00000000 BREG2F[B,H,W] BREG2E[B,H,W] BREG2D[B,H,W] BREG2C[B,H,W] 00000000 00000000 00000000 00000000 BREG33[B,H,W] BREG32[B,H,W] BREG31[B,H,W] BREG30[B,H,W] 00000000 00000000 00000000 00000000 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - +0 191 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C 0x280-0xFFC 192 CONFIDENTIAL +3 +2 +1 +0 BREG37[B,H,W] BREG36[B,H,W] BREG35[B,H,W] BREG34[B,H,W] 00000000 00000000 00000000 00000000 BREG3B[B,H,W] BREG3A[B,H,W] BREG39[B,H,W] BREG38[B,H,W] 00000000 00000000 00000000 00000000 BREG3F[B,H,W] BREG3E[B,H,W] BREG3D[B,H,W] BREG3C[B,H,W] 00000000 00000000 00000000 00000000 BREG43[B,H,W] BREG42[B,H,W] BREG41[B,H,W] BREG40[B,H,W] 00000000 00000000 00000000 00000000 BREG47[B,H,W] BREG46[B,H,W] BREG45[B,H,W] BREG44[B,H,W] 00000000 00000000 00000000 00000000 BREG4B[B,H,W] BREG4A[B,H,W] BREG49[B,H,W] BREG48[B,H,W] 00000000 00000000 00000000 00000000 BREG4F[B,H,W] BREG4E[B,H,W] BREG4D[B,H,W] BREG4C[B,H,W] 00000000 00000000 00000000 00000000 BREG53[B,H,W] BREG52[B,H,W] BREG51[B,H,W] BREG50[B,H,W] 00000000 00000000 00000000 00000000 BREG57[B,H,W] BREG56[B,H,W] BREG55[B,H,W] BREG54[B,H,W] 00000000 00000000 00000000 00000000 BREG5B[B,H,W] BREG5A[B,H,W] BREG59[B,H,W] BREG58[B,H,W] 00000000 00000000 00000000 00000000 BREG5F[B,H,W] BREG5E[B,H,W] BREG5D[B,H,W] BREG5C[B,H,W] 00000000 00000000 00000000 00000000 BREG63[B,H,W] BREG62[B,H,W] BREG61[B,H,W] BREG60[B,H,W] 00000000 00000000 00000000 00000000 BREG67[B,H,W] BREG66[B,H,W] BREG65[B,H,W] BREG64[B,H,W] 00000000 00000000 00000000 00000000 BREG6B[B,H,W] BREG6A[B,H,W] BREG69[B,H,W] BREG68[B,H,W] 00000000 00000000 00000000 00000000 BREG6F[B,H,W] BREG6E[B,H,W] BREG6D[B,H,W] BREG6C[B,H,W] 00000000 00000000 00000000 00000000 BREG73[B,H,W] BREG72[B,H,W] BREG71[B,H,W] BREG70[B,H,W] 00000000 00000000 00000000 00000000 BREG77[B,H,W] BREG76[B,H,W] BREG75[B,H,W] BREG74[B,H,W] 00000000 00000000 00000000 00000000 BREG7B[B,H,W] BREG7A[B,H,W] BREG79[B,H,W] BREG78[B,H,W] 00000000 00000000 00000000 00000000 BREG7F[B,H,W] BREG7E[B,H,W] BREG7D[B,H,W] BREG7C[B,H,W] 00000000 00000000 00000000 00000000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.29 Low-speed CR Prescaler Low-speed CR Prescaler Base_Address : 0x4003_C000 Base_Address + Address +2 +1 0x000 - - - 0x004 – 0x0FC - - - February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL Register +3 +0 LCR_PRSLD[B,H,W], --000000 - 193 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.30 Peripheral Clock Gating 1.30.1 TYPE1-M1, TYPE2-M4 products Peripheral Clock Gating Base_Address : 0x4003_C100 Register Base_Address + Address +3 +2 ---1-1-1 ----1111 11111111 11111111 MRST0[B,H,W] 0x004 -----0-0 ----0000 00000000 00000000 - - - - CKEN1[B,H,W] 0x010 -------- ----1111 ----1111 ----1111 MRST1[B,H,W] 0x014 0x018 – 0x01F +0 CKEN0[B,H,W] 0x000 0x008 – 0x00F +1 -------- ----0000 ----0000 ----0000 - - - - CKEN2[B,H,W] -------- -------- -------0 --**--00 0x020 Products with CAN : *="1" Products without CAN : *="0" MRST2[B,H,W] 0x024 0x028 – 0x67C 1.30.2 -------- -------- -------0 --00--00 - - - - TYPE3-M4, TYPE4-M4 products Peripheral Clock Gating Base_Address : 0x4003_C100 Register Base_Address + Address +3 +0 ---1-1-1 ----1111 11111111 11111111 MRST0[B,H,W] 0x004 -----0-0 ----0000 00000000 00000000 - - - - CKEN1[B,H,W] 0x010 -------- ----1111 ----1111 ----1111 MRST1[B,H,W] 0x014 0x018 – 0x01F +1 CKEN0[B,H,W] 0x000 0x008 – 0x00F +2 -------- ----0000 ----0000 ----0000 - - - - CKEN2[B,H,W] ---0--11 ---1--00 -------0 -***--00 0x020 Products with : *="1" Products without CAN : *="0" MRST2[B,H,W] 0x024 0x028 – 0x67C 194 CONFIDENTIAL ---0--00 ---0--00 -------0 -000--00 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.31 I2S Prescaler 1.31.1 TYPE1-M4, TYPE2-M4, TYPE3-M4 products I2S_Prescaler Base_Address : 0x4003_D000 Register Base_Address + Address +3 IPCR1[B,H,W] -------- -------- -------- -------0 IPCR2[B,H,W] 0x008 -------- -------- -------- -----000 IPCR3[B,H,W] 0x00C -------- -------- -------- ---00001 IPCR4[B,H,W] 0x010 -------- -------- -------- -0011111 IP_STR[B,H,W] 0x014 -------- -------- -------- -------0 IPINT_ENR[B,H,W] 0x018 -------- -------- -------- -------0 IPINT_CLR[B,H,W] 0x01C -------- -------- -------- -------0 IPINT_STR[B,H,W] 0x020 -------- -------- -------- -------0 IPCR5[B,H,W] 0x024 CONFIDENTIAL +0 -------- -------- -------- ------00 0x004 February 10, 2015, FM4_MN709-00019-1v0-E +1 ICCR[B,H,W] 0x000 0x028 – 0xFFC +2 -------- -------- -------- -0011000 - - - - 195 A. Register Map 1. Register Map P E R I P H E R A L 1.31.2 TYPE4-M4 product I2S_Prescaler Base_Address : 0x4003_D000 Register Base_Address + Address +3 -------- -------- -------- -------0 IPCR2[B,H,W] -------- -------- -------- -----000 IPCR3[B,H,W] 0x00C -------- -------- -------- ---00001 IPCR4[B,H,W] 0x010 -------- -------- -------- -0011111 IP_STR[B,H,W] 0x014 -------- -------- -------- -------0 IPINT_ENR[B,H,W] 0x018 -------- -------- -------- -------0 IPINT_CLR[B,H,W] 0x01C -------- -------- -------- -------0 IPINT_STR[B,H,W] 0x020 -------- -------- -------- -------0 IPCR5[B,H,W] 0x024 -------- -------- -------- -0011000 - - - - ICCR_1[B,H,W] 0x030 -------- -------- -------- -----000 IPCR5_1[B,H,W] 0x034 CONFIDENTIAL +0 IPCR1[B,H,W] 0x008 0x038 – 0xFFC +1 -------- -------- -------- ------00 0x004 0x028 – 0x02C +2 ICCR[B,H,W] 0x000 196 M A N U A L -------- -------- -------- -0000000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.32 GDC_Prescaler GDC_Prescaler Base_Address : 0x4003_D100 Register Base_Address + Address +3 +2 0x000 GPCR1[B,H,W] -------- -------- -------- ------00 GPCR2[B,H,W] 0x008 -------- -------- -------- -----000 GPCR3 [B,H,W] 0x00C -------- -------- -------- ---00000 GPCR4 [B,H,W] 0x010 -------- -------- -------- -0000000 GP_STR[B,H,W] 0x014 -------- -------- -------- -------0 GPINT_ENR[B,H,W] 0x018 -------- -------- -------- -------0 GPINT_CLR[B,H,W] 0x01C -------- -------- -------- -------0 GPINT_STR[B,H,W] 0x020 -------- -------- -------- -------0 - - - - GCSR[B,H,W] 0x028 -------- -------- ---0---0 ---0--00 GRCR[B,H,W] 0x02C -------- -------- -------- -------0 GMCR[B,H,W] 0x030 0x034- 0xFFC +0 -------- -------- -------- -------0 0x004 0x024 +1 GCCR[B,H,W] -------- -------- -------- -------0 - - - - Note: − For the register details of GDC, refer to the "CHAPTER:GDC". February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 197 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.33 EXT-Bus I/F 1.33.1 TYPE1-M4 product EXT-Bus I/F Base_Address : 0x4003_F000 Register Base_Address + Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 198 CONFIDENTIAL +3 +2 +1 +0 MODE0[W] -------- -------- --000-00 00000000 MODE1[W] -------- -------- --000-00 00000000 MODE2[W] -------- -------- --000-00 00000000 MODE3[W] -------- -------- --000-00 00000000 MODE4[W] -------- -------- --000-00 00000001 MODE5[W] -------- -------- --000-00 00000000 MODE6[W] -------- -------- --000-00 00000000 MODE7[W] -------- -------- --000-00 00000000 TIM0[W] 00000101 01011111 11110000 00001111 TIM1[W] 00000101 01011111 11110000 00001111 TIM2[W] 00000101 01011111 11110000 00001111 TIM3[W] 00000101 01011111 11110000 00001111 TIM4[W] 00000101 01011111 11110000 00001111 TIM5[W] 00000101 01011111 11110000 00001111 TIM6[W] 00000101 01011111 11110000 00001111 TIM7[W] 00000101 01011111 11110000 00001111 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 AREA1[W] -------- -0001111 -------- 00010000 AREA2[W] 0x0048 -------- -0001111 -------- 00100000 AREA3[W] 0x004C -------- -0001111 -------- 00110000 AREA4[W] 0x0050 -------- -0001111 -------- 01000000 AREA5[W] 0x0054 -------- -0001111 -------- 01010000 AREA6[W] 0x0058 -------- -0001111 -------- 01100000 AREA7[W] 0x005C -------- -0001111 -------- 01110000 ATIM0[W] 0x0060 -------- -------- ----0100 01011111 ATIM1[W] 0x0064 -------- -------- ----0100 01011111 ATIM2[W] 0x0068 -------- -------- ----0100 01011111 ATIM3[W] 0x006C -------- -------- ----0100 01011111 ATIM4[W] 0x0070 -------- -------- ----0100 01011111 ATIM5[W] 0x0074 -------- -------- ----0100 01011111 ATIM6[W] 0x0078 -------- -------- ----0100 01011111 ATIM7[W] 0x007C -------- -------- ----0100 01011111 - -------0 00000000 0000000000110011 PWRDWN[W] -------- -------- 00000000 00000000 SDTIM[W] 0x010C ------00 01000010 00010001 0100--01 SDCMD[W] 0x0110 CONFIDENTIAL - REFTIM[W] 0x0108 February 10, 2015, FM4_MN709-00019-1v0-E - -------- -------0 00010011 --00-000 0x0104 0x01FC SDMODE[W] 0x0100 0x0114 - +0 -------- -0001111 -------- 00000000 0x0044 0x00FC +1 AREA0[W] 0x0040 0x0080 - +2 0------- ---00000 00000000 00000000 - - - - 199 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 0x02FC - 0x0FFC 200 CONFIDENTIAL - EST WEAD 00000000 00000000 000000000 00000000 ESCLR[W] -------- -------- -------- -------1 AMODE[W] 0x0310 0x0F18 – - -------- -------- -------- -------0 0x030C 0x0F14 - -------- -------- -------- ---01111 0x0308 0x0F00 – +0 DCLKR[W] 0x0304 0x0EFC +1 -------- -------- -------- ----0000 0x0300 0x031C - +2 MEMCERR[W] 0x0200 0x0204 – M A N U A L -------- -------- -------- -------1 - - - - * * * * - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.33.2 M A N U A L TYPE3-M4, TYPE4-M4 products EXT-Bus I/F Base_Address : 0x4003_F000 Register Base_Address + Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 MODE0[W] -------- -------- --000-00 00000000 MODE1[W] -------- -------- --000-00 00000000 MODE2[W] -------- -------- --000-00 00000000 MODE3[W] -------- -------- --000-00 00000000 MODE4[W] -------- -------- --000-00 00000001 MODE5[W] -------- -------- --000-00 00000000 MODE6[W] -------- -------- --000-00 00000000 MODE7[W] -------- -------- --000-00 00000000 TIM0[W] 00000101 01011111 11110000 00001111 TIM1[W] 00000101 01011111 11110000 00001111 TIM2[W] 00000101 01011111 11110000 00001111 TIM3[W] 00000101 01011111 11110000 00001111 TIM4[W] 00000101 01011111 11110000 00001111 TIM5[W] 00000101 01011111 11110000 00001111 TIM6[W] 00000101 01011111 11110000 00001111 TIM7[W] 00000101 01011111 11110000 00001111 201 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 AREA1[W] AREA2[W] -------- -0001111 -------- 00100000 AREA3[W] 0x004C -------- -0001111 -------- 00110000 AREA4[W] 0x0050 -------- -0001111 -------- 01000000 AREA5[W] 0x0054 -------- -0001111 -------- 01010000 AREA6[W] 0x0058 -------- -0001111 -------- 01100000 AREA7[W] 0x005C -------- -0001111 -------- 01110000 ATIM0[W] 0x0060 -------- -------- ----0100 01011111 ATIM1[W] 0x0064 -------- -------- ----0100 01011111 ATIM2[W] 0x0068 -------- -------- ----0100 01011111 ATIM3[W] 0x006C -------- -------- ----0100 01011111 ATIM4[W] 0x0070 -------- -------- ----0100 01011111 ATIM5[W] 0x0074 -------- -------- ----0100 01011111 ATIM6[W] 0x0078 -------- -------- ----0100 01011111 ATIM7[W] 0x007C -------- -------- ----0100 01011111 - - REFTIM[W] -------0 00000000 0000000000110011 PWRDWN[W] 0x0108 -------- -------- 00000000 00000000 SDTIM[W] 0x010C 0-----00 01000010 00010001 0100--01 SDCMD[W] 0x0110 CONFIDENTIAL - -------- -------0 00010011 --00-000 0x0104 202 SDMODE[W] 0x0100 0x01FC +0 -------- -0001111 -------- 00010000 0x0048 0x0114 - +1 -------- -0001111 -------- 00000000 0x0044 0x00FC +2 AREA0[W] 0x0040 0x0080 - M A N U A L 0------- ---00000 00000000 00000000 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 0x02FC - EST WEAD 00000000 00000000 000000000 00000000 ESCLR[W] -------- -------- -------- -------1 AMODE[W] 0x0310 0x0F18 – 0x0FFC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - -------- -------- -------- -------0 0x030C 0x0F14 - -------- -------- -------- ---01111 0x0308 0x0F00 – DCLKR[W] 0x0304 0x0EFC +0 -------- -------- -------- ----0000 0x0300 0x031C - +1 MEMCERR[W] 0x0200 0x0204 – +2 -------- -------- -------- -------1 - - - - * * * * - - - - 203 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.34 USB USB ch.0 Base_Address : 0x4004_0000 USB ch.1 Base_Address : 0x4005_0000 Register Base_Address + Address +3 +2 0x2100 - - 0x2104 - - 0x2108 - - 0x210C - - 0x2110 0x2114 204 CONFIDENTIAL - - +1 +0 HCNT1[B,H,W] HCNT0[B,H,W] -----001 00000000 HERR[B,H,W] HIRQ[B,H,W] 00000011 0-000000 HFCOMP[B,H,W] HSTATE[B,H,W] 00000000 --010010 HRTIMER(1/0)[B,H,W] 00000000 00000000 HADR[B,H,W] HRTIMER(2)[B,H,W] -0000000 ------00 HEOF(1/0)[B,H,W] - 0x2118 - - 0x211C - - 0x2120 - - 0x2124 - - 0x2128 - - 0x212C - - 0x2130 - - 0x2134 - - 0x2138 - - 0x213C - - 0x2140 - - 0x2144 - - 0x2148 - - 0x214C - - --000000 00000000 HFRAME(1/0)[B,H,W] -----000 00000000 HTOKEN[B,H,W] - 00000000 UDCC[B,H,W] -------- 10100-00 EP0C[H,W] ------0- -1000000 EP1C[H,W] 01100001 00000000 EP2C[H,W] 0110000- -1000000 EP3C[H,W] 0110000- -1000000 EP4C[H,W] 0110000- -1000000 EP5C[H,W] 0110000- -1000000 TMSP[H,W] -----000 00000000 UDCIE[B,H,W] UDCS[B,H,W] --000000 --000000 EP0IS[H,W] 10---1-- -------EP0OS[H,W] 100--00- -XXXXXXX EP1S[H,W] 100-000X XXXXXXXX FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 0x2150 - - 0x2154 - - 0x2158 - - 0x215C - - 0x2160 - 0x2164 - - 0x2168 - - 0x216C - - 0x2170 - - 0x2174 - - - - 0x2178 0x217C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL - +1 +0 EP2S[H,W] 100-000- -XXXXXXX EP3S[H,W] 100-000- -XXXXXXX EP4S[H,W] 100-000- -XXXXXXX EP5S[H,W] 100-000- -XXXXXXX EP0DTH[B,H,W] EP0DTL[B,H,W] XXXXXXXX XXXXXXXX EP1DTH[B,H,W] EP1DTL[B,H,W] XXXXXXXX XXXXXXXX EP2DTH[B,H,W] EP2DTL[B,H,W] XXXXXXXX XXXXXXXX EP3DTH[B,H,W] EP3DTL[B,H,W] XXXXXXXX XXXXXXXX EP4DTH[B,H,W] EP4DTL[B,H,W] XXXXXXXX XXXXXXXX EP5DTH[B,H,W] EP5DTL[B,H,W] XXXXXXXX XXXXXXXX - - 205 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.35 DMAC DMAC Base_Address : 0x4006_0000 Base_Address + Address 0x0000 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 206 CONFIDENTIAL Register +3 +2 +1 +0 DMACR[B,H,W] 00-00000 -------- -------- -------DMACA0[B,H,W] 00000000 0---0000 00000000 00000000 DMACB0[B,H,W] --000000 00000000 00000000 -------0 DMACSA0[B,H,W] 00000000 00000000 00000000 00000000 DMACDA0[B,H,W] 00000000 00000000 00000000 00000000 DMACA1[B,H,W] 00000000 0---0000 00000000 00000000 DMACB1[B,H,W] --000000 00000000 00000000 -------0 DMACSA1[B,H,W] 00000000 00000000 00000000 00000000 DMACDA1[B,H,W] 00000000 00000000 00000000 00000000 DMACA2[B,H,W] 00000000 0---0000 00000000 00000000 DMACB2[B,H,W] --000000 00000000 00000000 -------0 DMACSA2[B,H,W] 00000000 00000000 00000000 00000000 DMACDA2[B,H,W] 00000000 00000000 00000000 00000000 DMACA3[B,H,W] 00000000 0---0000 00000000 00000000 DMACB3[B,H,W] --000000 00000000 00000000 -------0 DMACSA3[B,H,W] 00000000 00000000 00000000 00000000 DMACDA3[B,H,W] 00000000 00000000 00000000 00000000 DMACA4[B,H,W] 00000000 0---0000 00000000 00000000 DMACB4[B,H,W] --000000 00000000 00000000 -------0 DMACSA4[B,H,W] 00000000 00000000 00000000 00000000 DMACDA4[B,H,W] 00000000 00000000 00000000 00000000 DMACA5[B,H,W] 00000000 0---0000 00000000 00000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 DMACSA5[B,H,W] 00000000 00000000 00000000 00000000 DMACDA5[B,H,W] 0x006C 00000000 00000000 00000000 00000000 DMACA6[B,H,W] 0x0070 00000000 0---0000 00000000 00000000 DMACB6[B,H,W] 0x0074 --000000 00000000 00000000 -------0 DMACSA6[B,H,W] 0x0078 00000000 00000000 00000000 00000000 DMACDA6[B,H,W] 0x007C 00000000 00000000 00000000 00000000 DMACA7[B,H,W] 0x0080 00000000 0---0000 00000000 00000000 DMACB7[B,H,W] 0x0084 --000000 00000000 00000000 -------0 DMACSA7[B,H,W] 0x0088 00000000 00000000 00000000 00000000 DMACDA7[B,H,W] 0x008C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 --000000 00000000 00000000 -------0 0x0068 0x00FC +1 DMACB5[B,H,W] 0x0064 0x0090 - +2 00000000 00000000 00000000 00000000 - - - - 207 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.36 DSTC DSTC Base_Address : 0x4006_1000 Base_Address + Address Register +3 +2 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 208 CONFIDENTIAL +1 +0 DESTP[B,H,W] 00000000 00000000 00000000 00000000 HWDESP[B,H,W] 00XXXXXX XXXXXX00 00000000 00000000 SWTR[H] CFG[B] CMD[B] 00000000 00000000 01000000 00000001 MONERS[B,H,W] 00XXXXXX XXXXXX00 XXXXXXXX XXX00000 DREQENB[31:0] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[63:32] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[95:64] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[127:96] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[159:128] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[191:160] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[223:192] [B,H,W] 00000000 00000000 00000000 00000000 DREQENB[255:224] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[31:0] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[63:32] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[95:64] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[127:96] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[159:128] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[191:160] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[223:192] [B,H,W] 00000000 00000000 00000000 00000000 HWINT[255:224] [B,H,W] 00000000 00000000 00000000 00000000 HWINTCLR[31:0] [B,H,W] 00000000 00000000 00000000 00000000 HWINTCLR[63:32] [B,H,W] 00000000 00000000 00000000 00000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Base_Address + Address Register +3 HWINTCLR[127:96] [B,H,W] 00000000 00000000 00000000 00000000 HWINTCLR[159:128] [B,H,W] 0x060 00000000 00000000 00000000 00000000 HWINTCLR[191:160] [B,H,W] 0x064 00000000 00000000 00000000 00000000 HWINTCLR[223:192] [B,H,W] 0x068 00000000 00000000 00000000 00000000 HWINTCLR[255:224] [B,H,W] 0x06C 00000000 00000000 00000000 00000000 DQMSK[31:0] [B,H,W] 0x070 00000000 00000000 00000000 00000000 DQMSK[63:32] [B,H,W] 0x074 00000000 00000000 00000000 00000000 DQMSK[95:64] [B,H,W] 0x078 00000000 00000000 00000000 00000000 DQMSK[127:96] [B,H,W] 0x07C 00000000 00000000 00000000 00000000 DQMSK[159:128] [B,H,W] 0x080 00000000 00000000 00000000 00000000 DQMSK[191:160] [B,H,W] 0x084 00000000 00000000 00000000 00000000 DQMSK[223:192] [B,H,W] 0x088 00000000 00000000 00000000 00000000 DQMSK[255:224] [B,H,W] 0x08C 00000000 00000000 00000000 00000000 DQMSKCLR[31:0] [B,H,W] 0x090 00000000 00000000 00000000 00000000 DQMSKCLR[63:32] [B,H,W] 0x094 00000000 00000000 00000000 00000000 DQMSKCLR[95:64] [B,H,W] 0x098 00000000 00000000 00000000 00000000 DQMSKCLR[127:96] [B,H,W] 0x09C 00000000 00000000 00000000 00000000 DQMSKCLR[159:128] [B,H,W] 0x0A0 00000000 00000000 00000000 00000000 DQMSKCLR[191:160] [B,H,W] 0x0A4 00000000 00000000 00000000 00000000 DQMSKCLR[223:192] [B,H,W] 0x0A8 00000000 00000000 00000000 00000000 DQMSKCLR[255:224] [B,H,W] 0x0AC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 00000000 00000000 00000000 00000000 0x005C 0x0FFC +1 HWINTCLR[95:64] [B,H,W] 0x0058 0x00B0 - +2 00000000 00000000 00000000 00000000 - - - - 209 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.37 CAN CAN ch.0 Base_Address : 0x4006_2000 CAN ch.1 Base_Address : 0x4006_3000 Register Base_Address + Address +3 0x0000 0x0004 0x0008 0x000C 0x0014 0x0018 0x0024 0x0028 0x002F 0x0034 0x0038 0x003C 0x0044 0x0048 0x0054 0x005C 210 CONFIDENTIAL ERRCNT[B,H,W] 00000000 00000000 TESTR[B,H,W] INTR[B,H,W] -------- X00000-- 00000000 00000000 - BRPER[B,H,W] - -------- ----0000 IF1CMSK[B,H,W] IF1CREQ[B,H,W] -------- 00000000 0------- 00000001 IF1MSK2[B,H,W] IF1MSK1[B,H,W] 11-11111 11111111 11111111 11111111 IF1ARB2[B,H,W] IF1ARB1[B,H,W] 00000000 00000000 00000000 00000000 IF1MCTR[B,H,W] - 00000000 0---0000 IF1DTA2[B,H,W] IF1DTA1[B,H,W] 00000000 00000000 00000000 00000000 IF1DTB2[B,H,W] IF1DTB1[B,H,W] 00000000 00000000 00000000 00000000 - - - IF1DTA1[B,H,W] IF1DTA2[B,H,W] 00000000 00000000 00000000 00000000 IF1DTB1[B,H,W] IF1DTB2[B,H,W] 00000000 00000000 00000000 00000000 - - - IF2CMSK[B,H,W] IF2CREQ[B,H,W] -------- 00000000 0------- 00000001 IF2MSK2[B,H,W] IF2MSK1[B,H,W] 11-11111 11111111 11111111 11111111 IF2ARB2[B,H,W] IF2ARB1[B,H,W] 00000000 00000000 00000000 00000000 - 0x0050 0x0058 - BTR[B,H,W] -0100011 00000001 - 0x0040 0x004C CTRLR[B,H,W] -------- 000-0001 - 0x0030 +0 STATR[B,H,W] - 0x0020 +1 -------- 00000000 - 0x0010 0x001C +2 IF2MCTR[B,H,W] - 00000000 0---0000 IF2DTA2[B,H,W] IF2DTA1[B,H,W] 00000000 00000000 00000000 00000000 IF2DTB2[B,H,W] IF2DTB1[B,H,W] 00000000 00000000 00000000 00000000 - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 0x0060 0x0064 0x0068 0x007C 0x008F 0x0094 0x009F 0x00A4 0x00AF 0x0FFC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL IF2DTB1[B,H,W] IF2DTB2[B,H,W] 00000000 00000000 00000000 00000000 - - - - TREQR2[B,H,W] TREQR1[B,H,W] 00000000 00000000 00000000 00000000 - - - NEWDT2[B,H,W] NEWDT1[B,H,W] 00000000 00000000 00000000 00000000 - - - INTPND2[B,H,W] INTPND1[B,H,W] 00000000 00000000 00000000 00000000 - 0x00B0 0x00B4 - IF2DTA2[B,H,W] 00000000 00000000 - 0x00A0 +0 IF2DTA1[B,H,W] - 0x0090 +1 00000000 00000000 - 0x0080 0x0084 - +2 - - - MSGVAL2[B,H,W] MSGVAL1[B,H,W] 00000000 00000000 00000000 00000000 - - - 211 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.38 Ethernet-MAC Ethernet-MAC Base_Address : 0x4006_4000 Register Base_Address + Address 0x0000 – 0x1FFC +3 +2 +1 +0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Note: − For the register details of Ethernet-MAC block, refer to the Ethernet part. 1.39 Ethernet-Control Ethernet-Control Base_Address : 0x4006_6000 Register Base_Address + Address +3 +2 +1 +0 0x000 - 0xFFC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Note: − 212 CONFIDENTIAL For the register details of Ethernet-Control block, refer to the Ethernet part. FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.40 I2S I2S ch.0 Base_Address : 0x4006_C000 I2S ch.1 Base_Address : 0x4006_C800 Register Base_Address + Address +3 +2 +1 +0 RXFDAT[B,H,W] 0x000 00000000 00000000 00000000 00000000 TXFDAT[B,H,W] 0x004 00000000 00000000 00000000 00000000 CNTREG[B,H,W] 0x008 00000000 00000000 00000000 00000000 MCR0REG[B,H,W] 0x00C -0000000 00000000 -0000000 00000000 MCR1REG[B,H,W] 0x010 00000000 00000000 00000000 00000000 MCR2REG[B,H,W] 0x014 00000000 00000000 00000000 00000000 OPRREG[B,H,W] 0x018 -------0 -------0 -------- -------0 SRST[B,H,W] 0x01C -------- -------- -------- -------0 INTCNT[B,H,W] 0x020 -1111111 --111111 ----0000 --000000 STATUS[B,H,W] 0x024 00000000 ----0000 00000000 00000000 DMAACT[B,H,W] 0x028 -------0 -------0 -------0 -------0 TSTREG[B,H,W] 0x02C -------- -------- -------- -------0 0x030 - 0xFFC - - - - 1.41 SD-Card SD-Card Base_Address : 0x4006_E000 Base_Address Register + Address +3 +2 +1 +0 0x000 – 0xFFC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Note: − For the register details of SD-Card block, refer to the Chapter: SD Card Interface. February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 213 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.42 CAN FD CAN FD Base_Address : 0x4007_0000 Register Base_Address + Address +3 ENDN[B,H,W] 10000111 01100101 01000011 00100001 - -------- -------- --000000 X000---RWD[B,H,W] -------- -------- 00000000 00000000 CCCR[B,H,W] 0x018 -------- -------- -0000000 00000001 BTP[B,H,W] 0x01C ------00 00000000 --001010 00110011 TSCC[B,H,W] 0x020 -------- ----0000 -------- ------00 TSCV[B,H,W] 0x024 -------- -------- 00000000 00000000 TOCC[B,H,W] 0x028 11111111 11111111 -------- -----000 TOCV[B,H,W] 0x02C -------- -------- 11111111 11111111 - - - - ECR[B,H,W] 0x040 -------- 00000000 00000000 00000000 PSR[B,H,W] 0x044 -------- -------- --000111 00000111 - - - - IR[B,H,W] 0x050 00000000 00000000 00000000 00000000 IE[B,H,W] 0x054 00000000 00000000 00000000 00000000 ILS[B,H,W] 0x058 00000000 00000000 00000000 00000000 ILE[B,H,W] 0x05C CONFIDENTIAL - TEST[B,H,W] 0x014 214 - ---00000 0--00000 ----1010 -011--11 0x010 0x060 - 0x07C FBTP[B,H,W] 0x00C 0x048 - 0x04C +0 00110000 00010011 00000101 0000110 0x004 0x030 - 0x03C +1 CREL[B,H,W] 0x000 0x008 +2 -------- -------- -------- ------00 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 SIDFC[B,H,W] -------- 00000000 00000000 000000-XIDFC[B,H,W] 0x088 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x0D4 0x0D8 0x0DC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +0 -------- -------- -------- --000000 0x084 0x090 +1 GFC[B,H,W] 0x080 0x08C +2 -------- -0000000 00000000 000000-- - - - XIDAM[B,H,W] ---11111 11111111 11111111 11111111 HPMS[B,H,W] -------- -------- 00000000 00000000 NDAT1[B,H,W] 00000000 00000000 00000000 00000000 NDAT2[B,H,W] 00000000 00000000 00000000 00000000 RXF0C[B,H,W] 00000000 -0000000 00000000 000000-RXF0S[B,H,W] ------00 --000000 --000000 -0000000 RXF0A[B,H,W] -------- -------- -------- --000000 RXBC[B,H,W] -------- -------- 00000000 000000-RXF1C[B,H,W] 00000000 -0000000 00000000 000000-RXF1S[B,H,W] 00----00 --000000 --000000 -0000000 RXF1A[B,H,W] -------- -------- -------- --000000 RXESC[B,H,W] -------- -------- -----000 -000-000 TXBC[B,H,W] -0000000 --000000 00000000 000000-TXFQS[B,H,W] -------- --000000 ---00000 –000000 TXESC[B,H,W] -------- -------- -------- -----000 TXBRP[B,H,W] 00000000 00000000 00000000 00000000 TXBAR[B,H,W] 00000000 00000000 00000000 00000000 TXBCR[B,H,W] 00000000 00000000 00000000 00000000 TXBTO[B,H,W] 00000000 00000000 00000000 00000000 TXBCF[B,H,W] 00000000 00000000 00000000 00000000 215 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 TXBCIE[B,H,W] 00000000 00000000 00000000 00000000 - - - --000000 --000000 00000000 000000-TXEFS[B,H,W] 0x0F4 ------00 ---00000 ---00000 --000000 TXEFA[B,H,W] 0x0F8 -------- -------- -------- ---00000 - 0x200 0x204 - - - FDSEAR[B,H,W] FDESR[B,H,W] FDECR[B,H,W] 00000000 00000000 ------00 ----0000 FDDEAR[B,H,W] FDESCR[B,H,W] 00000000 00000000 ------00 - FDFECR[B,H,W] 0x208 0------- -----000 00000000 00000000 - 0x210 - - - TSMDR[B,H,W] TSCNTR[B,H,W] -------- -------0 -------- -------0 TSDIVR[B,H,W] 0x214 -------- -------- 00000000 00000000 0x218 0x21C - 0xFFC TXEFC[B,H,W] 0x0F0 0x20C +0 00000000 00000000 00000000 00000000 0x0E4 0x0FC - 0x1FC +1 TXBTIE[B,H,W] 0x0E0 0x0E8 - 0x0EC M A N U A L TSCPCLR[B,H,W] TSCDTR[B,H,W] 00000000 00000000 00000000 00000000 - - +3 +2 - - +1 +0 CAN FD Message RAM Message RAM Base_Address + Address Rx Buffer and FIFO Element [W] 0x8000 0xBFFC Tx Buffer Element [W] Tx Event FIFO Element [W] Standard Message ID Filter Element [W] Extended Message ID Filter Element [W] Note: − 216 CONFIDENTIAL For the register details of CAN FD Message RAM block, refer to the Chapter: CAN FD Controller". FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.43 Programmable-CRC Programmable-CRC Base_Address : 0x4008_0000 Register Base_Address + Address +3 +1 +0 CRCn_PORY[B,H,W] 0x000 00000100 11000001 00011101 10110111 CRCn_SEED[B,H,W] 0x004 11111111 11111111 11111111 11111111 CRCn_FXOR[B,H,W] 0x008 11111111 11111111 11111111 11111111 CRCn_CFG[B,H,W] 0x00C 00000000 11100000 00000000 00000000 CRCn_WR[B,H,W] 0x010 00000000 00000000 00000000 00000000 CRCn_RD[B,H,W] 0x014 0x018 - 0xFFC +2 00000000 00000000 00000000 00000000 - - - - +1 +0 - - 1.44 WorkFlash_IF WorkFlash_IF Base_Address : 0x200E_0000 Base_Address + Address Register +3 +2 0x000 WFASZR[B,H,W] 0x004 WFRWTR[B,H,W] 0x008 0x00C - 0xFFF WFSTR[B,H,W] - - Note: − For the register details of Workflash IF block, refer to the FLASH Programming Manual of the product used. February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL 217 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.45 Hi-Speed Quad SPI controller 1.45.1 TYPE1-M4, TYPE2-M4, TYPE3-M4 products Hi-Speed Quad SPI controller Base_Address : 0xD000_0000 Register Base_Address + Address +3 +2 0x000 HSSPIn_PCC0[B,H,W] -------- -1111111 00000000 00000000 HSSPIn_PCC1[B,H,W] 0x008 -------- -1111111 00000000 00000000 HSSPIn_PCC2[B,H,W] 0x00C -------- -1111111 00000000 00000000 HSSPIn_PCC3[B,H,W] 0x010 -------- -1111111 00000000 00000000 HSSPIn_TXF[B,H,W] 0x014 -------- -------- -------- -0000000 HSSPIn_TXE[B,H,W] 0x018 -------- -------- -------- -0000000 HSSPIn_TXC[B,H,W] 0x01C -------- -------- -------- -0000000 HSSPIn_RXF[B,H,W] 0x020 -------- -------- -------- -0000000 HSSPIn_RXE[B,H,W] 0x024 -------- -------- -------- -0000000 HSSPIn_RXC[B,H,W] 0x028 -------- -------- -------- -0000000 HSSPIn_FAULTF[B,H,W] 0x02C -------- -------- -------- ---00000 HSSPIn_FAULTC[B,H,W] 0x030 0x038 -------- -------- -------- ---00000 - HSSPIn_DMDMAEN HSSPIn_DMCFG [B,H,W] [B,H,W] ------00 -----001 HSSPIn_DMPSEL HSSPIn_DMSTOP HSSPIn_DMSTART [B,H,W] [B,H,W] [B,H,W] [B,H,W] ----0000 ------00 -------0 -------0 HSSPIn_DMBCS[B,H,W] HSSPIn_DMBCC[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_DMSTATUS[B,H,W] 0x040 -------- ---00000 ---00000 ------00 0x044 - - - - 0x048 - - - - 0x04C CONFIDENTIAL - HSSPIn_DMTRP 0x03C 218 +0 -------- -------- -------- --000-00 0x004 0x034 +1 HSSPIn_MCTRL[B,H,W] HSSPIn_FIFOCFG[B,H,W] --------_--------_---00000_01110111 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +2 +1 +0 HSSPIn_TXFIFO0[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO1[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO2[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO3[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO4[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO5[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO6[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO7[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO8[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO9[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO10[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO11[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO12[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO13[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO14[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO15[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO0[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO1[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO2[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO3[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO4[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO5[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO6[B,H,W] 00000000 00000000 00000000 00000000 219 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address +3 +2 HSSPIn_RXFIFO8[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO9[B,H,W] 0x0B4 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO10[B,H,W] 0x0B8 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO11[B,H,W] 0x0BC 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO12[B,H,W] 0x0C0 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO13[B,H,W] 0x0C4 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO14[B,H,W] 0x0C8 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO15[B,H,W] 0x0CC 00000000 00000000 00000000 00000000 HSSPIn_CSCFG[B,H,W] 0x0D0 -------- ----0000 ----0000 --000000 HSSPIn_CSITIME[B,H,W] 0x0D4 -------- -------- 11111111 11111111 HSSPIn_CSAEXT[B,H,W] 0x0D8 0x0E4 0x0E8 0x0EC 0x0F0 0x0F4 0x0F8 00000000 00000000 000----- -------HSSPIn_RDCSDC1[B,H,W] HSSPIn_RDCSDC0[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_RDCSDC3[B,H,W] HSSPIn_RDCSDC2[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_RDCSDC5[B,H,W] HSSPIn_RDCSDC4[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_RDCSDC7[B,H,W] HSSPIn_RDCSDC6[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC1[B,H,W] HSSPIn_WRCSDC0[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC3[B,H,W] HSSPIn_WRCSDC2[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC5[B,H,W] HSSPIn_WRCSDC4[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC7[B,H,W] HSSPIn_WRCSDC6[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_MID[B,H,W] 0x0FC 220 CONFIDENTIAL +0 00000000 00000000 00000000 00000000 0x0B0 0x0E0 +1 HSSPIn_RXFIFO7[B,H,W] 0x0AC 0x0DC M A N U A L 00000000 00000000 00000110 00110000 0x100 - 0x3FC - - - 0x400 - - - 0x404 - - - 0x408 - 0xFFC - - - QDCLKR[B,H,W] ----1111 DBCNT[B,H,W] ------00 - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L 1.45.2 M A N U A L TYPE4-M4 product Hi-Speed Quad SPI controller Base_Address : 0xD0A0_4000 Register Base_Address + Address +3 +2 0x000 +0 -------- -------- -------- --000-00 HSSPIn_PCC0[B,H,W] 0x004 -------- -1111111 00000000 00000000 HSSPIn_PCC1[B,H,W] 0x008 -------- -1111111 00000000 00000000 HSSPIn_PCC2[B,H,W] 0x00C -------- -1111111 00000000 00000000 HSSPIn_PCC3[B,H,W] 0x010 -------- -1111111 00000000 00000000 HSSPIn_TXF[B,H,W] 0x014 -------- -------- -------- -0000000 HSSPIn_TXE[B,H,W] 0x018 -------- -------- -------- -0000000 HSSPIn_TXC[B,H,W] 0x01C -------- -------- -------- -0000000 HSSPIn_RXF[B,H,W] 0x020 -------- -------- -------- -0000000 HSSPIn_RXE[B,H,W] 0x024 -------- -------- -------- -0000000 HSSPIn_RXC[B,H,W] 0x028 -------- -------- -------- -0000000 HSSPIn_FAULTF[B,H,W] 0x02C -------- -------- -------- ---00000 HSSPIn_FAULTC[B,H,W] 0x030 -------- -------- -------- ---00000 0x034 - - HSSPIn_DMDMAEN HSSPIn_DMCFG [B,H,W] [B,H,W] ------00 -----001 HSSPIn_DMTRP HSSPIn_DMPSEL HSSPIn_DMSTOP HSSPIn_DMSTART [B,H,W] [B,H,W] [B,H,W] [B,H,W] ----0000 ------00 -------0 -------0 0x038 0x03C HSSPIn_DMBCS[B,H,W] HSSPIn_DMBCC[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_DMSTATUS[B,H,W] 0x040 -------- ---00000 ---00000 ------00 0x044 - - - - 0x048 - - - - 0x04C February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +1 HSSPIn_MCTRL[B,H,W] HSSPIn_FIFOCFG[B,H,W] --------_--------_---00000_01110111 221 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 222 CONFIDENTIAL M A N U A L +3 +2 +1 +0 HSSPIn_TXFIFO0[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO1[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO2[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO3[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO4[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO5[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO6[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO7[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO8[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO9[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO10[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO11[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO12[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO13[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO14[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_TXFIFO15[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO0[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO1[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO2[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO3[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO4[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO5[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO6[B,H,W] 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO7[B,H,W] 00000000 00000000 00000000 00000000 FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +3 +2 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO9[B,H,W] 0x0B4 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO10[B,H,W] 0x0B8 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO11[B,H,W] 0x0BC 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO12[B,H,W] 0x0C0 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO13[B,H,W] 0x0C4 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO14[B,H,W] 0x0C8 00000000 00000000 00000000 00000000 HSSPIn_RXFIFO15[B,H,W] 0x0CC 00000000 00000000 00000000 00000000 HSSPIn_CSCFG[B,H,W] 0x0D0 -------- ----0000 ----0000 --000000 HSSPIn_CSITIME[B,H,W] 0x0D4 -------- -------- 11111111 11111111 HSSPIn_CSAEXT[B,H,W] 0x0D8 0x0E0 0x0E4 0x0E8 0x0EC 0x0F0 0x0F4 0x0F8 00000000 00000000 000----- -------HSSPIn_RDCSDC1[B,H,W] CONFIDENTIAL HSSPIn_RDCSDC0[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_RDCSDC3[B,H,W] HSSPIn_RDCSDC2[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_RDCSDC5[B,H,W] HSSPIn_RDCSDC4[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_RDCSDC7[B,H,W] HSSPIn_RDCSDC6[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC1[B,H,W] HSSPIn_WRCSDC0[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC3[B,H,W] HSSPIn_WRCSDC2[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC5[B,H,W] HSSPIn_WRCSDC4[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_WRCSDC7[B,H,W] HSSPIn_WRCSDC6[B,H,W] 00000000 ----0000 00000000 ----0000 HSSPIn_MID[B,H,W] 0x0FC 00000000 00000000 00000110 00110000 0x100 - 0x3FC - - - 0x400 - - - 0x404 - - - 0x408 - 0xFFC - - - February 10, 2015, FM4_MN709-00019-1v0-E +0 HSSPIn_RXFIFO8[B,H,W] 0x0B0 0x0DC +1 QDCLKR[B,H,W] ----1111 DBCNT[B,H,W] ------00 - 223 A. Register Map 1. Register Map P E R I P H E R A L 1.46 M A N U A L HyperBus Interface HyperBus Interface Base_Address : 0xD0A0_5000 Register Base_Address + Address +3 +2 0x000 IEN[B,H,W] 0------- -------- -------- -------0 ISR[B,H,W] 0x008 -------- -------- -------- -------0 - - MBR1[B,H,W] 00000000 00000000 00000000 00000000 MCR0[B,H,W] 0x018 -------- ------00 -------- --00--11 MCR1[B,H,W] 0x01C -------- ------00 -------- --00--11 MTR0[B,H,W] 0x020 00000000 00000000 00000000 ----0000 MTR1[B,H,W] 0x024 00000000 00000000 00000000 ----0000 GPOR[B,H,W] 0x028 -------- -------- -------- ------00 WPR[B,H,W] 0x02C -------- -------- -------- -------0 TEST[B,H,W] 0x030 CONFIDENTIAL - 00000000 00000000 00000000 00000000 0x014 224 MBR0[B,H,W] 0x010 0x034- 0xFFC +0 -----000 -------0 ----0000 -------0 0x004 0x024 +1 CSR[B,H,W] -------- -------- -------- -------0 - - - - FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.47 GDC Sub system controller GDC Sub system controller Base_Address : 0xD0A0_0000 Register Base_Address + Address 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 +2 +1 00000000 00000000 00000000 00000000 LockStatus[W] -------- -------- -------0 ---0---0 *[W] CnfigClockControl[W] -------- -------- -------- -----001 VRamInterruptEnable[W] -------- -------- -------- ------11 *[W] VRamInterruptClear[W] -------- -------- -------- ------00 VRamInterruptStatus[W] -------- -------- -------- ------00 ExtFlashDevSelect[W] -------- -------- -------- -------1 VRamRemapDisable[W] -------- -------- -------- -------0 PanicSwitch[W] -------- -------- -------- -------1 GDC_ClockDivider[W] -------- -----100 00000000 -------WkupTriggerMask[W] -----000 -----000 00000000 00000000 ClockDomainStatus[W] -------- -------- -------- ----0000 - 0x03C - 0x044 0x048 0x04C 0x050 February 10, 2015, FM4_MN709-00019-1v0-E +0 LockUnlock[W] 0x038 0x040 CONFIDENTIAL +3 dsp_LoxkUnlock[W] 00000000 00000000 00000000 00000000 dsp_LockStatus[W] -------- -------- -------0 ---0---0 dsp0_ClockDivider[W] -------- 01000001 11100000 -------dsp0_DomainControl[W] -------- -------1 -------- -------0 dsp0_ClockShift[W] -------- -------- -------- -------1 225 A. Register Map 1. Register Map P E R I P H E R A L Register Base_Address + Address 0x054 0x058 0x05C 0x060 +2 +1 dsp0_PowerEnControl[W] -------- -------- -------- -------0 dsp0_ClockGateModeLock[W] 00000000 00000000 00000000 00000000 dsp0_ClockGateControl[W] -------- -------- -------- -------0 0x068 - 0x06C - 0x070 - 0x074 - 0x080 0x084 0x088 0x08C SDRAMC_ClcokDivider[W] -------- 00000100 00000000 -------SDRAMC_DomainControl[W] -------- -------1 -------- -------0 HSSPIC_ClockDivider[W] -------- 00000100 00000000 -------HSSPIC_DomainControl[W] -------- -------1 -------- -------0 RPCC_ClcokDivider[W] -------- -------- -------- -----000 RPCC_DomainControl[W] -------- -------1 -------- -------0 0x090 - 0x094 - 0x098 - 0x09C - 0x100 0x104 0x108 0x10C +0 *[W] - 0x07C CONFIDENTIAL +3 0x064 0x078 226 M A N U A L vram_LockUnlock[W] 00000000 00000000 00000000 00000000 vram_LockStatus[W] -------- -------- -------0 ---0---0 vram_sram_select[W] -------- -------- ----0000 00000000 *[W] FM4_MN709-00004-3v0-E, January 9, 2015 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L Register Base_Address + Address +2 +1 0x110 *[W] 0x114 *[W] 0x118 *[W] 0x11C *[W] 0x120 *[W] 0x124 *[W] 0x128 *[W] 0x12C - 0x130 - 0x134 - 0x138 - 0x13C 0x140 0x144 0x148 0x14C-0xFFC February 10, 2015, FM4_MN709-00019-1v0-E CONFIDENTIAL +3 +0 vram_sberraddr_s0[W] 00000000 00000000 0000000 00000000 vram_sberraddr_s1[W] 00000000 00000000 0000000 00000000 vram_arbiter_priority[W] -------- -------- -------- 00000000 - 227 A. Register Map 1. Register Map P E R I P H E R A L M A N U A L 1.48 GDC Sub system SDRAM controller GDC Sub system SDRAM controller Base_Address : 0xD0A3_0000 Register Base_Address + Address 0x000-0x0FF 0x100 0x104 0x108 0x10C 0x110 0x114-0xFFC 228 CONFIDENTIAL +3 +2 +1 +0 SDMODE[W] -------- -------0 00010011 --00-000 REFTIM[W] -------0 00000000 0000000000110011 PWRDWN[W] -------- -------- 00000000 00000000 SDTIM[W] 0-----00 01000010 00010001 0100--01 SDCMD[W] 0------- ---00000 00000000 00000000 - FM4_MN709-00004-3v0-E, January 9, 2015 P E R I P H E R A L M A N U A L Major Changes Page Section Changes Revision 1.0 - - January 15, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL Initial release 229 P E R I P H E R A L 230 CONFIDENTIAL M A N U A L FM4_MN709-00014-1v0-E, January 15, 2015 P E R I P H E R A L M A N U A L MN709-00014-1v0-E Spansion・Controller Manual 32-BIT MICROCONTROLLER FM4 Family PERIPHERAL MANUAL GDC part February 2015 Rev. 1.0 Published : Spansion Inc. Edited : Communications Dept. February 2, 2015, FM4_MN709-00014-1v0-E CONFIDENTIAL 231 P E R I P H E R A L M A N U A L Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. ® ® ® TM Copyright © 2015 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse , TM TM TM ORNAND , Easy DesignSim , Traveo and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 232 CONFIDENTIAL FM4_MN709-00014-1v0-E, February 2, 2015