POSEICO SPA Via Pillea 42-44, 16153 Genova - ITALY Tel. + 39 010 8599400 - Fax + 39 010 8682006 Sales Office: Tel. + 39 010 8599400 - Fax + 39 010 8681180 POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation PHASE CONTROL THYRISTOR AT906 Repetitive voltage up to Mean on-state current Surge current 800 V 6240 A 95 kA FINAL SPECIFICATION giu 08 - ISSUE : 03 Symbol Characteristic Conditions Tj [°C] Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 800 V V RSM Non-repetitive peak reverse voltage 125 900 V V DRM Repetitive peak off-state voltage 125 800 V I RRM Repetitive peak reverse current V=VRRM 125 300 mA I DRM Repetitive peak off-state current V=VDRM 125 300 mA CONDUCTING I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, dou ble side cooled 6240 A I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, dou ble side cooled 4685 A I TSM Surge on-state current sine wave, 10 ms 95 kA I² t I² t VR ≤ 0.5 VRRM V T On-state voltage On-state current = V T(TO) T r 125 45125 x1E3 9000 A A²s 25 1,26 V Threshold voltage 125 0,85 V On-state slope resistance 125 0,045 mohm SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 4000 A, gate 10V 5ohm 125 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 1000 V/µs td Gate controlled delay time, typical VD=100V, gate source 10V, 10 ohm , tr=.5 µs 25 tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM Q rr µs 500 125 µs Reverse recovery charge di/dt=-20 A/µs, I= 4000 A I rr Peak reverse recovery current VR= 50 V µC I H Holding current, typical VD=5V, gate open circuit 25 500 mA I L Latching current, typical VD=12V, tp=30µs 25 3000 mA A GATE V GT Gate trigger voltage VD=12V 25 3,5 V I GT Gate trigger current VD=12V 25 400 mA V GD Non-trigger gate voltage, min. VD=VDRM 125 0,4 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) 10 V P GM Peak gate power dissipation 150 W P G Average gate power dissipation 3 W R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled 7,0 °C/kW R th(c-h) Thermal impedance Case to heatsink, double side cooled 1,0 °C/kW T F j Operating junction temperature Mounting force Mass Pulse width 100 µs MOUNTING -30 / 125 80 / 100 3000 ORDERING INFORMATION : AT906 S 08 standard specification VDRM&VRRM/100 °C kN g AT906 PHASE CONTROL THYRISTOR FINAL SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation giu 08 - ISSUE : 03 SURGE CHARACTERISTIC Tj = 125 °C 20000 100 18000 90 16000 80 14000 70 12000 60 ITSM [kA] On-state Current [A] ON-STATE CHARACTERISTIC Tj = 125 °C 10000 8000 50 40 6000 30 4000 20 2000 10 0 0 0,6 1,1 1,6 2,1 1 On-state Voltage [V] 10 n°cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 8,0 7,0 Zth j-h [°C/kW] 6,0 5,0 4,0 3,0 2,0 1,0 0,0 0,001 0,01 0,1 1 t[s] 10 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO SpA reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100