POSEICO AT847LT

ANSALDO
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori
PHASE CONTROL THYRISTOR
AT847LT
Repetitive voltage up to
Mean on-state current
Surge current
2500 V
3265 A
39.2 kA
FINAL SPECIFICATION
apr 97 - ISSUE : 01
Symbol
Characteristic
Tj
[°C]
Conditions
Value
Unit
BLOCKING
V
RRM
Repetitive peak reverse voltage
125
2500
V
V
V
RSM
Non-repetitive peak reverse voltage
125
2600
V
DRM
Repetitive peak off-state voltage
125
2500
V
I
RRM
Repetitive peak reverse current
V=VRRM
125
200
mA
I
DRM
Repetitive peak off-state current
V=VDRM
125
200
mA
I
T (AV)
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
3265
A
I
T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
I
TSM
Surge on-state current
sine wave, 10 ms
I² t
I² t
without reverse voltage
V
T
On-state voltage
On-state current =
V
T(TO)
Threshold voltage
125
0.85
V
T
On-state slope resistance
125
0.175
mohm
CONDUCTING
r
125
2100 A
25
2665
A
39.2
kA
7683 x1E3
A²s
1.22
V
SWITCHING
di/dt
Critical rate of rise of on-state current, min.
From 75% VDRM up to 3280 A, gate 10V 5ohm
125
800
A/µs
dv/dt
Critical rate of rise of off-state voltage, min.
Linear ramp up to 70% of VDRM
125
1000
V/µs
td
Gate controlled delay time, typical
VD=100V, gate source 10V, 10 ohm , tr=.5 µs
25
2
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/µs linear up to 75% VDRM
Q rr
Reverse recovery charge
di/dt=-20 A/µs, I= 2150 A
I rr
Peak reverse recovery current
VR= 50 V
I
H
Holding current, typical
VD=5V, gate open circuit
25
500
mA
I
L
Latching current, typical
VD=12V, tp=30µs
25
1000
mA
400
125
µs
µs
µC
A
GATE
V
GT
Gate trigger voltage
VD=12V
25
3.5
V
I
GT
Gate trigger current
VD=12V
25
400
mA
VD=VDRM
125
V
GD
Non-trigger gate voltage, min.
0.25
V
V
FGM
Peak gate voltage (forward)
30
V
I
FGM
Peak gate current
10
A
V
RGM
Peak gate voltage (reverse)
10
V
P
GM
Peak gate power dissipation
150
W
P
G
Average gate power dissipation
10
W
R
th(j-h)
Thermal impedance, DC
Junction to heatsink, double side cooled
9.5
°C/kW
R
th(c-h)
Thermal impedance
Case to heatsink, double side cooled
2
°C/kW
T
F
j
Operating junction temperature
Mounting force
Mass
-30 / 125
40.0 / 50.0
1150
°C
kN
g
Pulse width 100 µs
MOUNTING
ORDERING INFORMATION : AT847LT S 25
standard specification
VDRM&VRRM/100
ANSALDO
AT847LT PHASE CONTROL THYRISTOR
FINAL SPECIFICATION
apr 97 - ISSUE : 01
DISSIPATION CHARACTERISTICS
SQUARE WAVE
Th [°C]
130
120
110
100
90
80
30°
60°
70
90°
120°
60
180°
DC
50
0
1000
2000
3000
4000
5000
IF(AV) [A]
PF(AV) [W]
8000
DC
7000
120°
6000
180°
90°
60°
5000
30°
4000
3000
2000
1000
0
0
1000
2000
3000
IF(AV) [A]
4000
5000
ANSALDO
AT847LT PHASE CONTROL THYRISTOR
FINAL SPECIFICATION
apr 97 - ISSUE : 01
ON-STATE CHARACTERISTIC
Tj = 125 °C
SURGE CHARACTERISTIC
Tj = 125 °C
10000
40
9000
35
30
7000
6000
ITSM [kA]
On-state Current [A]
8000
5000
4000
25
20
15
3000
10
2000
5
1000
0
0
0.6
1.1
1.6
2.1
2.6
1
On-state Voltage [V]
10
n° cycles
TRANSIENT THERMAL IMPEDANCE
DOUBLE SIDE COOLED
10.0
9.0
8.0
Zth j-h [°C/kW]
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.001
0.01
0.1
1
t[s]
10
100
Cathode terminal type DIN 46244 - A 4.8 - 0.8
Gate terminal type AMP 60598 - 1
Distributed by
All the characteristics given in this data sheet are guaranteed only with uniform
clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03
mm and roughness < 2 µm.
In the interest of product improvement ANSALDO reserves the right to change
any data given in this data sheet at any time without previous notice.
If not stated otherwise the maximum value of ratings (simbols over shaded
background) and characteristics is reported.
100