IDT ICS83905AG

ICS83905
LOW SKEW, 1:6 CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL
ICS
Fanout Buffer and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from IDT.
The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased from 6
to 12 by utilizing the ability of the outputs to drive two series
terminated lines.
• Six LVCMOS / LVTTL outputs
• Outputs able to drive 12 series terminated lines
• Crystal oscillator interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
• RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (VDD = VDDO = 2.5V)
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the
ICS83905 ideal for high performance, single ended applications that also require a limited output voltage.
Phase noise:
Offset
Noise Power
100Hz ............. -129.7 dBc/Hz
1kHz ............. -144.4 dBc/Hz
10kHz ............. -147.3 dBc/Hz
100kHz ............. -157.3 dBc/Hz
• 5V tolerant enable inputs
PIN ASSIGNMENTS
• Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
nc
ENABLE 1
XTAL_IN
XTAL_OUT
ENABLE 2
• Synchronous output enables
20 19 18 17 16
XTAL_OUT
ENABLE 2
GND
BCLK0
VDDo
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
BCLK5
• 0°C to 70°C ambient operating temperature
GND
2
14
VDDO
BCLK0
3
13
BCLK4
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
VDDO
4
12
GND
BCLK1
5
11
GND
16
15
14
13
12
11
10
9
7
8
9 10
XTAL_IN
ENABLE 1
BCLK5
VDDO
BCLK4
GND
BCLK3
VDD
BCLK3
6
VDD
15
BCLK2
K Package
Top View
1
GND
20-Lead VFQFN
4mm x 4mm x 0.9mm
body package
GND
GND
ICS83905
BLOCK DIAGRAM
BCLK0
BCLK1
XTAL_IN
BCLK2
XTAL_OUT
ICS83905
BCLK3
16-Lead SOIC
3.9mm x 9.9mm x 1.38mm body
package
M Pacakge
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body
package
G Pacakge
Top View
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
BCLK4
ENABLE 1
SYNCHRONIZE
BCLK5
ENABLE 2
1
SYNCHRONIZE
ICS83905AM REV. B JULY 9, 2007
ICS83905
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
XTAL_OUT
Output
XTAL_IN
Input
Cr ystal oscillator interface. XTAL_IN is the input.
Cr ystal oscillator interface. XTAL_OUT is the output.
ENABLE 1, ENABLE 2
BCLK0, BCLK1, BCLK2,
BCLK3, BCLK4, BCLK5
GND
Input
Clock enable. LVCMOS / LVTTL interface levels. See Table 3.
Output
Clock outputs. LVCMOS / LVTTL interface levels.
Power
Power supply ground.
VDD
Power
Core supply pin.
VDDO
Power
Output supply pin.
n/c
Unused
No connect.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
Minimum
Typical
4
Output Impedance
Units
pF
VDDO = 3.465V
19
pF
VDDO = 2.625V
18
pF
16
pF
VDDO = 2V
ROUT
Maximum
VDDO = 3.3V ± 5%
7
Ω
VDDO = 2.5V ± 5%
7
Ω
VDDO = 1.8V ± 0.2V
10
Ω
TABLE 3. CLOCK ENABLE FUNCTION TABLE
Control Inputs
Outputs
ENABLE 1
ENABLE 2
BCLK0:BCLK4
BCLK5
0
0
LOW
LOW
0
1
LOW
Toggling
1
0
Toggling
LOW
1
1
Toggling
Toggling
BCLK5
BCLK0:4
ENABLE2
ENABLE1
FIGURE 1. ENABLE TIMING DIAGRAM
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VDD + 0.5 V
Maximum Ratings may cause permanent damage to the
Outputs, VO
-0.5V to VDDO + 0.5V
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
Package Thermal Impedance, θJA
16 Lead SOIC package
78.8°C/W (0 mps)
16 Lead TSSOP package
89°C/W (0 lfpm)
20 Lead VFQFN package
60.4°C/W (0 mps)
Storage Temperature, TSTG
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
ENABLE 1:2 = 00
10
mA
IDDO
Output Supply Current
ENABLE 1:2 = 00
5
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
ENABLE 1:2 = 00
8
mA
IDDO
Output Supply Current
ENABLE 1:2 = 00
4
mA
Maximum
Units
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VDD
Core Supply Voltage
1.6
1.8
2.0
V
VDDO
Output Supply Voltage
1.6
1.8
2.0
V
IDD
Power Supply Current
ENABLE 1:2 = 00
5
mA
IDDO
Output Supply Current
ENABLE 1:2 = 00
3
mA
Maximum
Units
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
ENABLE 1:2 = 00
10
mA
IDDO
Output Supply Current
ENABLE 1:2 = 00
4
mA
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1.6
1.8
VDDO
Output Supply Voltage
2.0
V
IDD
Power Supply Current
ENABLE 1:2 = 00
10
mA
IDDO
Output Supply Current
ENABLE 1:2 = 00
3
mA
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
1.6
1.8
VDDO
Output Supply Voltage
2.0
V
IDD
Power Supply Current
ENABLE 1:2 = 00
8
mA
IDDO
Output Supply Current
ENABLE 1:2 = 00
3
mA
Maximum
Units
VDD + 0.3
V
TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol
VIH
VIL
Parameter
Input High Voltage
Input Low Voltage
VOH
ENABLE 1,
ENABLE 2
ENABLE 1,
ENABLE 2
Output High Voltage
Test Conditions
Minimum
VDD = 3.3V ± 5%
2
Typical
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 1.8V ± 0.2V
0.65*VDD
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0.8
V
VDD = 2.5V ± 5%
-0.3
0.7
V
VDD = 1.8V ± 0.2V
-0.3
0.35*VDD
V
VDDO = 3.3V ± 5%; NOTE 1
2.6
V
VDDO = 2.5V ± 5%; IOH = -1mA
2
V
VDDO = 2.5V ± 5%; NOTE 1
1.8
V
VDDO = 1.8V ± 0.2V; NOTE 1
VDDO - 0.3
V
VDDO = 3.3V ± 5%; NOTE 1
VOL
Output Low Voltage
0.5
V
VDDO = 2.5V ± 5%; IOL = 1mA
0.4
V
VDDO = 2.5V ± 5%; NOTE 1
0.45
V
VDDO = 1.8V ± 0.2V; NOTE 1
0.35
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Maximum
Units
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Mode of Oscillation
Fundamental
Frequency
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Typical
10
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40
MHz
Using External Clock
Source; NOTE 1
DC
100
MHz
48
52
%
80
ps
fMAX
Output Frequency
o dc
Output Duty Cycle
tsk(o)
Output Skew; NOTE 2, 4
tjit(Ø)
RMS Phase Jitter (Random)
tR/tF
Output Rise/Fall Time
tEN
Output Enable Time;
NOTE 3
ENABLE 2
4
cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4
cycles
4
cycles
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
0.13
200
ENABLE 1
ps
800
ps
4
cycles
All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40
MHz
Using External Clock
Source; NOTE 1
DC
100
MHz
47
53
%
80
ps
fMAX
Output Frequency
o dc
Output Duty Cycle
tsk(o)
Output Skew; NOTE 2, 5
tjit(Ø)
RMS Phase Jitter (Random); NOTE 3
tR/tF
Output Rise/Fall Time
tEN
Output Enable Time;
NOTE 4
ENABLE 2
4
cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
4
cycles
4
cycles
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
ENABLE 1
0.26
200
ps
800
ps
4
cycles
All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Please refer to phase noise plot.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40
MHz
Using External Clock
Source; NOTE 1
DC
100
MHz
47
53
%
80
ps
fMAX
Output Frequency
o dc
Output Duty Cycle
tsk(o)
Output Skew; NOTE 2, 4
tjit(Ø)
RMS Phase Jitter (Random)
tR/tF
Output Rise/Fall Time
tEN
Output Enable Time;
NOTE 3
tDIS
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
0.27
200
ps
900
ps
ENABLE 1
4
cycles
ENABLE 2
4
cycles
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4
cycles
4
cycles
All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40
MHz
Using External Clock
Source; NOTE 1
DC
100
MHz
48
52
%
80
ps
fMAX
Output Frequency
o dc
Output Duty Cycle
tsk(o)
Output Skew; NOTE 2, 4
tjit(Ø)
RMS Phase Jitter (Random)
tR/tF
Output Rise/Fall Time
tEN
Output Enable Time;
NOTE 3
tDIS
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
0.14
200
ps
800
ps
ENABLE 1
4
cycles
ENABLE 2
4
cycles
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4
cycles
4
cycles
All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6E. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40
MHz
Using External Clock
Source; NOTE 1
DC
100
MHz
48
52
%
80
ps
fMAX
Output Frequency
o dc
Output Duty Cycle
tsk(o)
Output Skew; NOTE 2, 4
tjit(Ø)
RMS Phase Jitter (Random)
tR/tF
Output Rise/Fall Time
tEN
Output Enable Time;
NOTE 3
ENABLE 2
4
cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4
cycles
4
cycles
25MHz @ (Integration
Range: 100Hz-1MHz)
0.18
20% to 80%
200
ENABLE 1
ps
900
ps
4
cycles
All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6F. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40
MHz
Using External Clock
Source; NOTE 1
DC
100
MHz
47
53
%
80
ps
fMAX
Output Frequency
o dc
Output Duty Cycle
tsk(o)
Output Skew; NOTE 2, 4
tjit(Ø)
RMS Phase Jitter (Random)
tR/tF
Output Rise/Fall Time
25MHz @ (Integration
Range: 100Hz-1MHz)
20% to 80%
0.19
200
ps
900
ps
ENABLE 1
4
cycles
tEN
Output Enable Time;
NOTE 3
ENABLE 2
4
cycles
tDIS
Output Disable Time; ENABLE 1
NOTE 3
ENABLE 2
4
cycles
4
cycles
All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TYPICAL PHASE NOISE AT 25MHZ (2.5V CORE/ 2.5V OUTPUT)
0
-10
25MHz
-20
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.26ps (typical)
-30
-40
NOISE POWER dBc
Hz
-50
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 25MHZ (3.3V CORE/ 3.3V OUTPUT)
0
-10
25MHz
-20
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.13ps (typical)
-30
-40
NOISE POWER dBc
Hz
-50
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PARAMETER MEASUREMENT INFORMATION
1.25V±5%
1.65V±5%
SCOPE
VDD,
VDDO
SCOPE
VDD,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
0.9V±0.1V
1.25V±5%
SCOPE
VDD,
VDDO
SCOPE
VDD
VDDO
Qx
LVCMOS
Qx
GND
LVCMOS
GND
-0.9V ± 0.1V
-1.25V±5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V±0.025%
2.4±0.9V
0.9V±0.1V
0.9V±0.1V
SCOPE
VDD
VDDO
VDDO
Qx
Qx
GND
GND
LVCMOS
LVCMOS
-0.9V±0.1V
-0.9V±0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
SCOPE
VDD
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
V
DD
V
DDO
Qx
2
BCLKx
2
t PW
t
V
PERIOD
DDO
Qy
2
tsk(o)
odc =
t PW
x 100%
t PERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
Clock
Outputs
80%
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
layouts. Slightly increasing the C1 and C2 values will slightly reduce
the frequency. Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can be
used, but is not required. For new designs, it is recommended
that R1 not be used.
Figure 2 shows an example of ICS83905 crystal interface with a
parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
C2 = 15pF to start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board
XTAL_IN
C1
15p
X1
18pF Parallel Cry stal
0
XTAL_OUT
C2
15p
R1 (optional)
FIGURE 2. CRYSTAL OSCILLATOR INTERFACE
LVCMOS TO XTAL INTERFACE
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
VDD
VCC
VDD
VCC
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
11
TO
XTAL INPUT INTERFACE
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. There should be
no trace attached.
THERMAL RELEASE PATH
solder as shown in Figure 4. For further information, please refer
to the Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package, Amkor
Technology.
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
EXPOSED PAD
SOLDER M ASK
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
THERM AL VIA
(GROUND PAD)
FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LAYOUT GUIDELINE
accurate, but minor adjustments might be required. For the
LVCMOS output drivers, two termination examples are shown in
the schematic. For additional termination, examples are shown
in the LVCMOS Termination Application Note.
Figure 5 shows an example of ICS83905 application schematic.
In this example, the device is operated at VDD = 3.3V and VDDO =
3.3V. The decoupling capacitors should be located as close as
possible to the power pins. The input is driven by an 18pF load
resonant quartz crystal. The tuning capacitors (C1, C2) are fairly
VDDO = 3.3V
VDD = 3.3V
R2
31
Zo = 50 Ohm
CL = 18 pf
C2
15pf
C1
15pF
LVCMOS
U1
ENABLE 2
VDDO
1
2
3
4
5
6
7
8
XTAL_OUT
ENABLE 2
GND
BCLK0
VDDO
BCLK1
GND
BCLK2
XTAL_IN
ENABLE 1
BCLK5
VDDO
BCLK4
GND
BCLK3
VDD
16
15
14
13
12
11
10
9
ENABLE 1
VDD
R3
100
Zo = 50 Ohm
R4
100
ICS83905
LVCMOS
VDD
C3
10uF
VDDO
C4
.1uF
C5
.1uF
Optional Termination
C6
.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE
FOR
16 LEAD SOIC
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
TABLE 7B. θJAVS. AIR FLOW TABLE
FOR
0
1
2
78.8°C/W
71.1°C/W
66.2°C/W
16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7C. θJAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
3
60.4°C/W
52.8°C/W
46.0°C/W
TRANSISTOR COUNT
The transistor count for ICS83905 is: 339
Pin compatible to MPC905
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS83905AM REV. B JULY 9, 2007
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PACKAGE OUTLINE - M SUFFIX FOR 16 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL
FOR
16 LEAD SOIC
Millimeters
MINIMUM
N
SYMBOL
MAXIMUM
16
FOR TSSOP
Millimeters
Minimum
N
Maximum
16
A
1.35
1.75
A
--
1.20
A1
0.10
0.25
A1
0.05
0.15
B
0.33
0.51
A2
0.80
1.05
C
0.19
0.25
b
0.19
0.30
D
9.80
10.00
c
0.09
0.20
E
3.80
4.00
D
4.90
5.10
e
1.27 BASIC
E
6.40 BASIC
H
5.80
6.20
E1
h
0.25
0.50
e
L
0.40
1.27
L
0.45
0.75
α
0°
8°
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-012
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
15
4.30
4.50
0.65 BASIC
ICS83905AM REV. B JULY 9, 2007
ICS83905
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
TABLE 8C. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
20
N
A
0.80
A1
0
1.0
0.05
0.25 Reference
A3
b
MAXIMUM
0.18
0.30
e
0.50 BASIC
ND
5
NE
5
D
4.0
D2
0.75
2.80
4.0
E
E2
0.75
2.80
L
0.35
0.75
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS83905AM
83905AM
16 Lead SOIC
tube
0°C to 70°C
ICS83905AMT
83905AM
16 Lead SOIC
2500 tape & reel
0°C to 70°C
ICS83905AMLF
83905AML
16 Lead "Lead-Free" SOIC
tube
0°C to 70°C
ICS83905AMLFT
83905AML
16 Lead "Lead-Free" SOIC
2500 tape & reel
0°C to 70°C
ICS83905AG
83905AG
16 Lead TSSOP
tube
0°C to 70°C
ICS83905AGT
83905AG
16 Lead TSSOP
2500 tape & reel
0°C to 70°C
ICS83905AGLF
83905AGL
16 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
ICS83905AGLFT
83905AGL
16 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
ICS83905AK
83905A
20 Lead VFQFN
tube
0°C to 70°C
ICS83905AKT
83905A
20 Lead VFQFN
2500 tape & reel
0°C to 70°C
ICS83905AKLF
3905AL
20 Lead "Lead-Free" VFQFN
tube
0°C to 70°C
ICS83905AKLFT
3905AL
20 Lead "Lead-Free" VFQFN
2500 tape & reel
0°C to 70°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
A
B
6A - 6F
B
T9
B
B
T7C
B
T9
Page
2
1
5-7
8
14
11
12
3
11
13
11
12
17
Description of Change
Date
Added Enable Timing Diagram.
Features Section - added RMS Phase Jitter bullet.
AC Characteristics Tables - added RMS Phase Jitter spec.
Added Phase Noise Plot.
Ordering Information Table - add TSSOP, non-LF par t number.
Added Cr ystal Input Interface in Application Section.
Added schematic layout.
Absolute Maximum Ratings - correct 20 lead VFQFN Package Thermal
Impedance.
Added Recommendations for Unused Input and Output Pins.
Corrected Theta JA Air Flow Table for 20 lead VFQFN.
Added LVCMOS to XTAL Interface section.
Added Thermal Release Path section.
AC Characteristics Table - added lead-free marking for 20 VFQFN package.
IDT ™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
18
3/28/05
4/8/05
4/25/05
5/16/05
10/2/06
7/9/07
ICS83905AM REV. B JULY 9, 2007
ICS83905
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
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