ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/ LVCMOS-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8308I is a low-skew, 1-to-8 Fanout Buffer and a member of the HiPerClockS™ family of High Perfor mance Clock Solutions from IDT. The ICS8308I has two selectable clock inputs. The CLK, nCLK pair can accept most differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated transmission lines. • Eight LVCMOS/LVTTL outputs, (7Ω typical output impedance) • Selectable LVCMOS_CLK or differential CLK, nCLK inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum Output Frequency: 350MHz • Output Skew: (3.3V± 5%): 100ps (maximum) • Part to Part Skew: (3.3V± 5%): 1ns (maximum) • Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V The ICS8308I is characterized for 3.3V core/3.3V output, 3.3V core/2.5V output or 2.5V core/2.5V output operation. Guaranteed output and part-part skew characteristics make the 8308I ideal for those clock distribution applications requiring well defined performance and repeatability. • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM CLK_EN Pullup PIN ASSIGNMENT Q0 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q1 VDDO D Q LVCMOS_CLK Pullup CLK Pullup nCLK Pulldown LE 1 Q0 0 Q1 CLK_SEL Pullup Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDDO Q2 GND Q3 VDDO Q4 GND Q5 VDDO Q6 GND Q7 Q4 ICS8308I Q5 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm body package G Package Top View Q6 Q7 OE Pullup IDT ™ / ICS™ LVCMOS FANOUT BUFFER 1 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 11, 13, 15, 17, 19, 21, 23 2, 10, 14, 18, 22 Name Q0, Q1, Q7, Q6, Q5, Q4,Q3, Q2 GND Type Description Output Clock outputs. LVCMOS / LVTTL interface levels. Power 3 CLK_SEL Input Pullup 4 LVCMOS_CLK Input Pullup Power supply ground. Clock select input. Selects LVCMOS clock input when HIGH. Selects CLK, nCLK inputs when LOW. See Table 3A. LVCMOS / LVTTL interface levels. Clock input. LVCMOS / LVTTL interface levels. Pullup Non-inver ting differential clock input. 5 CLK Input 6 nCLK Input 7 CLK_EN Input Pullup 8 OE Input Pullup 9 VDD Power Clock enable. LVCMOS / LVTTL interface levels. Output enable. LVCMOS / LVTTL interface levels. See Table 3B. Core supply pin. 12, 16, 20, 24 VDDO Power Output supply pins. Pulldown Inver ting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN 4 pF 12 pF RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance CPD Test Conditions 5 TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input Typical Maximum 7 12 Units Ω TABLE 3B. OE SELECT FUNCTION TABLE Control Input Clock Input CLK_SEL Minimum OE Output Operation 0 CLK, nCLK is selected 0 Outputs Q0:Q7 are in Hi-Z (disabled) 1 LVCMOS_CLK is selected 1 Outputs Q0:Q7 are active (enabled) TABLE 3C. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK_SEL LVCMOS_CLK CLK nCLK Q0:Q7 0 — 0 1 LOW Input to Output Mode Polarity Differential to Single Ended Non Inver ting 0 — 1 0 HIGH Differential to Single Ended Non Inver ting 0 — 0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inver ting 0 — 1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inver ting 0 — Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inver ting 0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inver ting 1 0 — — LOW Single Ended to Single Ended Non Inver ting 1 1 — — HIGH Single Ended to Single Ended Non Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". IDT ™ / ICS™ LVCMOS FANOUT BUFFER 2 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85° Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 46 mA IDDO Output Supply Current 11 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter VDD Minimum Typical Maximum Units Core Supply Voltage Test Conditions 3.135 3. 3 3.465 V 2.375 2. 5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 46 mA IDDO Output Supply Current 10 mA Maximum Units TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD, VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter Test Conditions Minimum Typical VDD Core Supply Voltage 2.375 2. 5 2.625 V VDDO Output Supply Voltage 2.375 2. 5 2.625 V IDD Power Supply Current 43 mA IDDO Output Supply Current 10 mA IDT ™ / ICS™ LVCMOS FANOUT BUFFER 3 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85° Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Test Conditions Minimum LVCMOS LVCMOS_CLK Maximum Units 2 Typical VDD + 0.3 V -0.3 1.3 V 0.8 0.8 300 µA CLK_EN, OE IIN Input Current VIN = VDD or VIN = GND V OH Output High Voltage; NOTE 1 IOH = -24mA VOL Output Low Voltage; NOTE 1 2.4 V IOL = 24mA 0.55 IOL = 12mA 0.30 V 1.3 V VDD - 0.85 V Maximum Units VDD + 0.3 V VPP Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. V TABLE 4E. DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIN Input Current VIN = VDD or VIN = GND V OH Output High Voltage; NOTE 1 IOH = -15mA VOL Output Low Voltage; NOTE 1 IOL = 15mA LVCMOS Minimum Typical 2 LVCMOS_CLK -0.3 CLK_EN, OE VPP 4 V V 300 µA 1.8 Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; CLK, nCLK GND + 0.5 VCMR NOTE 2, 3 NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 1.3 0.8 V 0.6 V 1.3 V VDD - 0.85 V ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER TABLE 4F. DC CHARACTERISTICS, VDD, VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIN Input Current VIN = VDD or VIN = GND V OH Output High Voltage; NOTE 1 IOH = -15mA VOL Output Low Voltage; NOTE 1 IOL = 15mA LVCMOS Minimum Typical 2 LVCMOS_CLK -0.3 CLK_EN, OE Maximum Units VDD + 0.3 V 1.3 V 0.7 V 300 µA 1.8 V VPP Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; CLK, nCLK GND + 0.5 VCMR NOTE 2, 3 NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. 0.6 V 1.3 V VDD - 0.85 V Maximum 350 Units MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85° Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical ƒ≤ 350MHz 2 4 ns ƒ≤ 350MHz 2 4 ns t sk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 100 ps t sk(pp) Par t-to-Par t Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 1 ns tR / tF Output Rise/Fall Time ns 0.8V to 2V 0.2 1 ƒ≤ 150MHz, Ref = CLK, nCLK 45 55 % 5 ns Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK Setup Time; tS CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. ns odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 tPLZ, tPHZ IDT ™ / ICS™ LVCMOS FANOUT BUFFER 5 ns ns ns ns ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum ƒ≤ 350MHz ƒ≤ 350MHz Typical Maximum 350 Units MHz 2 4 ns 2 4 ns t sk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 100 ps t sk(pp) Par t-to-Par t Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 1 ns tR / tF Output Rise/Fall Time odc Output Duty Cycle 0.6V to 1.8V 0.2 1.0 ns ƒ≤ 150MHz, Ref = CLK, nCLK 45 55 % tPZL, tPZH Output Enable Time; NOTE 5 5 ns Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK Setup Time; tS CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. ns tPLZ, tPHZ IDT ™ / ICS™ LVCMOS FANOUT BUFFER 6 ns ns ns ns ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum ƒ≤ 350MHz ƒ≤ 350MHz Typical Maximum 350 Units MHz 1.5 4.2 ns 1. 7 4.4 ns t sk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 160 ps t sk(pp) Par t-to-Par t Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 2 ns tR / tF Output Rise/Fall Time odc Output Duty Cycle 0.6V to 1.8V 0.2 1.0 ns ƒ≤ 150MHz, Ref = CLK, nCLK 40 60 % tPZL, tPZH Output Enable Time; NOTE 5 5 ns Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK Setup Time; tS CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. ns tPLZ, tPHZ IDT ™ / ICS™ LVCMOS FANOUT BUFFER 7 ns ns ns ns ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDO SCOPE VDD Qx VDDO Qx LVCMOS GND LVCMOS GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% VDD SCOPE VDD, VDDO nCLK V Qx Cross Points PP V CMR CLK LVCMOS GND GND -1.25V±5% DIFFERENTIAL INPUT LEVEL 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT PART 1 Qx V DDO Qx 2 PART 2 Qy V DDO Qy 2 tsk(o) OUTPUT SKEW IDT ™ / ICS™ LVCMOS FANOUT BUFFER V DDO 2 V DDO 2 tsk(pp) PART-TO-PART SKEW 8 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER 2V 2V VDD = VDDO = 3.3V Clock Outputs 0.8V 0.8V tR LVCMOS_ CLK tF VDDO 2 nCLK CLK 1.8V 1.8V VDD = VDDO = 2.5V or tR 0.6V VDDO 2 Q0:Q7 tF ➤ Clock Outputs VDD = 3.3V, VDDO = 2.5V 0.6V tPD ➤ PROPAGATION DELAY OUTPUT RISE/FALL TIME V DDO 2 Q0:Q7 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVCMOS FANOUT BUFFER 9 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 10 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE IDT ™ / ICS™ LVCMOS FANOUT BUFFER BY 11 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER SCHEMATIC EXAMPLE capacitors should be physically located near the power pin. Figure 3 shows a schematic example of the ICS8308I. In this example, the LVCMOS_CLK input is selected. The decoupling VDD Zo = 50 Ohm R1 R9 1K R10 1K R12 1K 43 VDD VDD U1 3.3V LVCMOS/LVTTL VDD Ro ~ 7 Ohm R11 1 2 3 4 5 6 7 8 9 10 11 12 Zo = 50 Ohm 43 3.3V_LVCMOS VDD=3.3V (U1,9) VDD (U1,12) C1 0.1u C2 0.1u (U1,16) (U1,20) C3 0.1u Q0 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q1 VDDO VDDO Q2 GND Q3 VDDO Q4 GND Q5 VDDO Q6 GND Q7 24 23 22 21 20 19 18 17 16 15 14 13 (U1,24) C4 0.1u Zo = 50 Ohm R8 C5 0.1u 43 ICS8308I 3.3V LVCMOS/LVTTL FIGURE 3. ICS8308I LVPECL BUFFER SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70°C/W 63°C/W 60°C/W TRANSISTOR COUNT The transistor count for ICS8308I is: 1040 IDT ™ / ICS™ LVCMOS FANOUT BUFFER 12 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 IDT ™ / ICS™ LVCMOS FANOUT BUFFER 13 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8308AGI ICS8308AGI 24 Lead TSSOP tube -40°C to 85°C ICS8308AGIT ICS8308AGI 24 Lead TSSOP tape & reel -40°C to 85°C ICS8308AGILF ICS8308AGILF 24 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS8308AGILFT ICS8308AGILF 24 Lead "Lead-Free" TSSOP tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 14 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER REVISION HISTORY SHEET Rev Table A B T4B T4E T 5B B T8 B T8 B B T3B Page Description of Change Date 11 1 3 4 6 8 14 1 10 14 1 Added Schematic Layout Features section - added mix supply voltage bullet. Added Mix Power Supply Table. Added Mix DC Characteristics Table. Added Mix AC Characteristics Table. Added Mix Output Load AC Test Circuit Diagram. Ordering Information Table - added "Lead-Free" par t number. Corrected Block Diagram, added CLK_SEL. Added "Recommendations for Unused Input and Output Pins". Ordering Information Table - added Lead-Free note. Pin Assignment - corrected package information from 300-MIL to 173-MIL. 2 Added OE Select Function Table. IDT ™ / ICS™ LVCMOS FANOUT BUFFER 4/16/04 10/20/04 1/12/05 7/25/05 8/4/06 10/16/07 15 ICS8308AGI REV. B OCTOBER 16, 2007 ICS8308I LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA