IDT ICS87001-01

PRELIMINARY
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
General Description
Features
The ICS87001-01 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5,
÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider
HiPerClockS™
and a member of theHiPerClockS™ family of High
Performance Clock Solutions from IDT. The
ICS87001-01 has selectable clock inputs that
accept single ended input levels. Output enable pin controls
whether the output is in the active or high impedance state.
•
•
•
•
•
One LVCMOS / LVTTL output, 15Ω output impedance
•
•
0°C to 70°C ambient operating temperature
ICS
The ICS87001-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001-01 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
CLK_SEL Pulldown
Pulldown
0
CLK1
Pulldown
1
N2:N0 Pulldown
OE
Maximum output frequency: 250MHz
Part-to-part skew: TBD
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
OE
VDD
CLK0
CLK_SEL
CLK1
N2
N1
N0
N Output Divider
N2:N0
CLK0
Selectable LVCMOS / LVTTL clock inputs
000
001
010
011
100
101
110
111
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
÷16
Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
nc
Q
nc
GND
nc
nc
GND
ICS87001-01
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
Top View
3
Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
1
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 1. Pin Descriptions
Number
Name
Type
Description
1
OE
Input
2
VDD
Power
3, 5
CLK0, CLK1
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
4
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
6, 7, 8
N2, N1, N0
Input
Pulldown
N divider pins. LVCMOS/LVTTL interface levels. See Table 3.
9, 12
GND
Power
10, 11, 13, 15
nc
Unused
No connect.
14
Q
Output
Single-ended clock output. 15Ω output impedance.
LVCMOS/LVTTL interface levels.
16
VDDO
Power
Output supply pin.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Pullup
Power supply pin.
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation Capacitance
10
pF
ROUT
Output Impedance
15
Ω
Function Tables
Table 3. Programmable Output Divider Function Table
Inputs
N2
N1
N0
N Divider Value
Output Frequency (MHz)
0
0
0
÷1 (default)
250
0
0
1
÷2
125
0
1
0
÷3
83.333
0
1
1
÷4
62.5
1
0
0
÷5
50
1
0
1
÷6
41.667
1
1
0
÷8
31.25
1
1
1
÷16
15.625
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
2
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO+ 0.5V
Package Thermal Impedance, θJA
100.3°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%,TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Positive Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
40
mA
IDDO
Output Supply Current
1
mA
Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO =2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Positive Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
40
mA
IDDO
Output Supply Current
1
mA
Table 4C. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO =1.8V ± 0.15V, TA = 0°C to 70°C
Symbol
Parameter
VDD
Minimum
Typical
Maximum
Units
Positive Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
1.65
1.8
1.95
V
IDD
Power Supply Current
40
mA
IDDO
Output Supply Current
1
mA
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Test Conditions
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 4D. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Positive Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
39
mA
IDDO
Output Supply Current
1
mA
Table 4E. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO =1.8V ± 0.15V, TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Positive Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
1.65
1.8
1.95
V
IDD
Power Supply Current
39
mA
IDDO
Output Supply Current
1
mA
Table 4F. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
VOH
VOL
Input
Low Current
Test Conditions
Minimum
VDD = 3.465V
Typical
Maximum
Units
2
VDD + 0.3
V
VDD = 2.625V
1.7
VDD + 0.3
V
VDD = 3.465V
-0.3
0.8
V
VDD = 2.625V
-0.3
0.7
V
CLK0, CLK1,
N[2:0], CLK_SEL
VDD = VIN = 3.465V or 2.625V
150
µA
OE
VDD = VIN = 3.465V or 2.625V
5
µA
CLK0, CLK1,
N[2:0], CLK_SEL
VDD = 3.465V or 2.625V, VIN = 0V
-5
µA
OE
VDD = 3.465V or 2.625V, VIN = 0V
-150
µA
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 1.8V ± 0.15V
1.5
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOZL
Output Hi-Z Current Low
IOZH
Output Hi-Z Current High
VDDO = 3.3V ± 5%
0.5
V
VDDO = 2.5V ± 5%
0.5
V
VDDO = 1.8V ± 0.15V
0.4
V
-5
µA
5
µA
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
4
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tPD
Propagation Delay,
Low to High; NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
4.3
ns
ps
20% to 80%
700
ps
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay,
Low to High; NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
4.6
ns
ps
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
20% to 80%
800
ps
50
%
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tPD
Propagation Delay,
Low to High; NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
5
ns
ps
20% to 80%
1
ns
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production..
Table 5D. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay,
Low to High; NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
4.7
ns
ps
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
20% to 80%
900
ps
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
6
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 5E. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
tPD
Propagation Delay,
Low to High; NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time; NOTE 4
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 4
5
ns
tDIS
Output Disable Time; NOTE 4
5
ns
5
ns
ps
20% to 80%
1.1
ns
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
7
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
SCOPE
VDD,
SCOPE
VDD
VDDO
LVCMOS
Qx
VDDO
Qx
GND
LVCMOS
GND
-1.65V±5%
-1.25V±5%
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.4V±5%
1.25V±5%
0.9V±0.075V
SCOPE
VDD
VDDO
SCOPE
VDD,
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V±5%
-0.9V±0.075V
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
1.6V±5%
0.9V±0.075V
Part 1
V
SCOPE
VDD
VDDO
DDO
Qx
Qx
2
Part 2
V
GND
DDO
LVCMOS
Qy
2
tsk(pp)
-0.9V±0.075V
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Part-to-Part Skew
8
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Parameter Measurement Information, continued
VDD
2
CLK0, CLK1
80%
Q
VDDO
2
Q
t
80%
20%
20%
tR
tF
PD
Output Rise/Fall Time
Propagation Delay
V
DDO
2
Q
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Reliability Information
Table 6. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
100.3°C/W
96.0°C/W
93.9°C/W
Transistor Count
The transistor count for ICS87001-01: 2781
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Ordering Information
Table 8. Ordering Information
Part/Order Number
87001BG-01
87001BG-01T
87001BG-01LF
87001BG-01LFT
Marking
87001B01
87001B01
7001B01L
7001B01L
Package
16 Lead TSSOP
16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
[email protected]
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA