APW7566/A The Synchronous Buck Converter with 300mA LDO Features General Description • Wide Input Operating Range: 4.5V~5.5V The APW7566 is P-channel low dropout linear regulator • Synchronous Buck Regulators for SoC: and synchronous buck converter which needs input voltage from 4.5 to 5.5V. -Fixed 1.05V (For APW7566) -Fixed 1.2V (For APW7566A) Synchronous buck converter is integrated high side and low side power MOSFET. It is equipped with an auto- - 1.2A peak Output Current for Core Power - 2MHz Switching Frequency • matic PSM/PWM mode operation. At light load, the IC operates in the PSM mode to reduce the switching losses. Low-Dropout Linear Regulators for System Power: At heavy load, the IC works in PWM mode. Low dropout linear regulator delivers current up to 300mA - Fixed 3.3V, 300mA Output Current with high PSRR • Thermal-Overload Protection • Power-OK Indicator after LDO Ready • TDFN2x2-8 Package • Lead Free Green Devices Available (RoHS to set output voltage, and it also can work with low ESR ceramic capacitors. Typical dropout voltage is only 240mV at 300mA loading. The APW7566 is equipped with Power-on-reset, shut- Compliant) down control, soft start, over-temperature and currentlimit into a single package to protect the device against Applications wrong logic control and over-temperature and current over-loads. • • IP-Cam The APW7566 available TDFN2x2-8 provides a very compact system solution external components and PCB area. • Security Car Recorder Simplified Application Circuit VPWM VIN L VDD LX Cout Cin EN POK POK PGND PWM_FB VLDO VLDO AGND CLDO ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 1 www.anpec.com.tw APW7566/A Ordering and Marking Information P a ckage C o de Q B :T Q F N 2 x 2 - 8 O p e r a tin g A m b ie n t T e m p e ra tu r e R a n g e A P W 7 5 6 6 /A L e a d F re e C o d e H a n d lin g C o d e T e m p e ra tu r e R a n g e P a ckage C o de P ro d u c t C o d e I : - 4 0 to 8 5 ° C O u t p u t V o lta g e C o d e: B la n k :1 .0 5 V A :1 .2 V H a n d lin g C o d e TR : Tape & Reel A s s e m b ly M a te r ia l G :H a lo g e n a n d L e e d F re e D e v ic e APW 7566 Q B: W 566 XXXXX X X X X X- -D a te C o d e APW 7566AQ B: W 66A XXXXX X X X X X- -D a te C o d e Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration PGND LX 1 8 AGND 2 7 PWM_FB EN 3 6 VDD POK 4 5 VLDO TDFN2x2-8 (TOP View) Absolute Maximum Ratings (Note 1) Symbol Parameter VDD,VLDO to GND Voltage LX to GND Voltage All other pins Power Dissipation TJ TSTG TSDR Rating Unit -0.3 ~ 7 V >20ns -1 ~ (VVDD)+0.3 V <20ns -3 ~ (VVDD )+3 V -0.3 ~7 V Internally Limited Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature (10 Seconds) W -40 ~ 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 2 www.anpec.com.tw APW7566/A Thermal Characteristics Symbol Parameter Typical Value Junction-to-Ambient Resistance in free air (Note 2) θJA TDFN 2x2-8 165 o 20 o Junction-to-Case Resistance in free air (Note 3) θJC Unit TDFN 2x2-8 C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside. Recommended Operating Conditions (Note 4) Symbol P arame ter VVD D V DD Sup ply Voltage I OUT P eak Con ve rte r O utput Cur rent I LDO V LDO Output Cu rrent L Indu ctor COUT V OUT Ou tpu t Capacitor C LDO V LDO Output Ca pacitor TA Amb ient Temp erature TJ Junction Tempera tu re Range Unit 4 .5 ~ 5 .5 V 0 ~ 1 .2 A 0 ~ 0 .3 A 0 .4 7~2 .2 µH 4 .7~22 µF 1 ~22 µF - 40 ~ 85 o -40 ~ 1 25 o C C Note 4: Refer to the typical application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=5V. Typical values are at TA=25oC. AP W7566 S ym bol Parameter Te st Conditions Unit Min Typ M ax - 250 300 μA - - 5 μA PO R Threshol d 2 .3 2.6 2.85 V PO R Hystere sis - 0.1 - V SUPPLY CURRENT IVDD Qui esce nt Curre nt ISD Shu tdo wn Quiescent VPWM_ FB=0.6V POWER-ON-RES ET (PWM/LDO) OUTPUT VOLTAGE (PWM) Outpu t Voltage Accur acy APW75 66 APW75 66A Line Reg ulation IOUT =1mA, VVDD =4.5V to 5.5V Loa d Re gulation IPWM=30 0mA to 800mA , VVDD = 5V Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 3 1.03 1.0 5 1.07 V 1.17 6 1.2 1.224 V - - 0.7 %/V 0.5 % www.anpec.com.tw APW7566/A Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=5V. Typical values are at TA=25oC. APW75 66 Pa ram eter S ym bol Test Conditions Unit Min Typ Max 3.218 3 .3 3.382 V OUTPUT VOLTAGE (LDO) Output Vo ltag e Accuracy V DROP PS RR IL DO =1mA~0.3 A, o T A=-40 ~85 C Line Regu lation IL DO =1mA, VVDD=4.5V to 5 .5V - - 0 .2 %/V Load Regu lation IL DO =1mA to 300mA, VVDD=4.5V - - 0 .9 % Dr opout Volta ge IL DO =300 mA - 24 0 33 0 mV Power Sup ply Reje ction Ratio IL DO =50mA, C LDO =2.2µF - 50 - dB - 1 - KΩ f=1kHz Di scha rge Resistance POWER MOS FE TS(PWM) R P-FET Hi gh Side P- MOS RD S(ON) IL X=200 mA - 0.35 0 .4 Ω R N-FET Low S ide N-MOS R DS(ON) IL X=200 mA - 0.35 0 .4 Ω De ad Time (Note 5 ) TD 10 ns POWER-OK AND DELAY POK Thresho ld(POK goes high) Risi ng - 90% V LDO - V POK Dela y Time The time from V LDO =90% *V LDO to POK goes high - 16 - ms - 10 0 - µs - 50 0 - Ω POK Debo unce Time POK P ull Low Resista nce VPOK=0.1V ENABLE AND SHUTDO WN Enab le Vo ltag e Thre sh old VEN Risi ng 1 - - V Shutdown Voltage Threshold VEN Falling - - 0 .4 V 1.5 1 .6 - A PROTECTIONS(PWM) Ma ximu m Inductor Current-Limit Soft-Start Time - 0 .7 - ms 1.7 2 2 .3 MHz Un der Voltage Protection - 40 50 % Ma ximu m Duty Cycle - 95 - % 330 45 0 75 0 mA F SW Switchi ng Fr equen cy UV P VPWM_ FB =0 .6V PROTECTIONS(LDO) Cu rrent Limit Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 4 www.anpec.com.tw APW7566/A Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=5V. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7566 Min Typ Max Unit PROTECTIONS(PWM, LDO) T OTP Over-Temperature Protection T J Rising - 150 - °C Over-Temperature Protection Hysteresis T J Falling - 30 - °C Note 5: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 5 www.anpec.com.tw APW7566/A Typical Operating Characteristics VPWM Voltage VS Input Volatge 5 1.08 4 1.07 VPWM Voltage (V) Current (uA) Shutdown Current VS Input Voltage 3 2 1 0 1.06 1.05 1.04 2 2.5 3 3.5 4 4.5 5 5.5 1.03 6 2 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Input Voltage (V) Efficiency VS Input Voltage No Switch Current VS Input Voltage 100 6 500 90 400 70 Current (uA) Efficiency (%) 80 60 50 40 300 200 30 20 100 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 2 2.5 3 3.5 4 4.5 5 5.5 6 Input Voltage (V) Output Loading (A) LDO Voltage VS Input Voltage 3.33 LDO Voltage (V) 3.32 3.31 3.3 3.29 3.28 3.27 2 2.5 3 3.5 4 4.5 5 5.5 6 Input Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 6 www.anpec.com.tw APW7566/A Operating Waveforms Normal Operation – Loading=0.8A Power on VIN – Loading=0.8A CH2 CH2 CH1 CH1 CH3 CH3 CH4 CH4 VIN=12V,Freq=400KHz,ILEDx=120mA,16S4P CH1:VLDO-2V/div CH2:VPWM-1V/div CH3:VIN-5V/div CH4:IL-500mA/div Time:1us/div CH1:VLDO-50V/div CH2:VPWM-500mV/div CH3:VIN-5V/div CH4:IL-1A/div Time:2ms/div Power on VIN – Loading=0.8A Power on VIN - POK CH2 CH2 CH1 CH1 CH3 CH3 CH4 CH4 CH1:VLDO-2V/div CH2:VPOK-2V/div CH3:VVIN-5V/div CH4:IL-200mA/div Time:5ms/div CH1:VPOK-2V/div CH2:VLDO-2V/div CH3:VIN-5V/div CH4:IL-1A/div Time:5ms/div Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 7 www.anpec.com.tw APW7566/A Operating Waveforms Load Transient 0.3A to 0.8A to 0.3A LDO Load Transient - 0A to 0.3A to 0A CH1 CH1 CH2 CH2 VIN=12V,Freq=400KHz,ILEDx=120mA 16S4P,DC Mode CH1:VLDO-100mV/div CH2:ILDO-200mA/div Time:2ms/div CH1:VPWM-20mV/div CH2:IL-500mA/div Time:50us/div OTP – Loading=0.8A CH2 CH3 CH4 CH1 CH1:VPOK-5V/div CH2:VPWM-1V/div CH3:VLDO-5V/Div CH4:IL-1A/div Time:500ms/div Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 8 www.anpec.com.tw APW7566/A Pin Description PIN NO. Name 1 LX 2 AGND 3 EN 4 POK 5 VLDO 6 VDD 7 PWM_FB 8 PGND Function Po wer S witchin g Output. The LX is the ju nctio n o f the high -sid e and low-side po we r MO SFET to supply power to the output LC filter. Conne ct th is pi n with larg e cop per area to neg ative termin als of th e input and outpu t capacitors. En able Control In put. Forcing th is pin above 1.0V enab les the device, or fo rcing thi s pin belo w 0.4V to shut it down. In shu tdo wn , all functions a re disable d. This p in is floating as the d evice will be e nabli ng. Po wer G ood function. Its monitor VL DO o utput voltage . Regul ator Output Pin. Po wer Inpu t. Conne ct a cer amic bypass cap acitor from VDD to GND. VDD is suppl y VL DO ou tp ut po we r. Ou tp ut Feedb ack In put. Th e APW7 566 senses the feedba ck vo ltag e via PWM_FB and regu lates the vol tag e at 1.05V/1.2V. Conne ct th is pi n with larg e cop per area to neg ative termin als of th e input and outpu t capacitors. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 9 www.anpec.com.tw APW7566/A Block Diagram VLDO AVDD POK POK Circuit EA Slop Compensation Oscillator S ICOMP VDD PWM_FB 0.6V EN EA UVLO VDD Shutdown IRCMP PGND Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 LX Control Logic R Q S Q 10 AGND www.anpec.com.tw APW7566/A Typical Application Circuit VPWM VIN 6 AVDD LX 1 L1 2.2uH C1 22uF/6.3V 3 PGND EN 8 C2 22uF/6.3V APW7566/A 4 POK POK PWM_FB 7 VLDO 5 AGND VLDO 2 C4 4.7uF/6.3V *Recommend: The C1 capacitor must be close to the IC side less than 3mm. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 11 www.anpec.com.tw APW7566/A Function Description Power-On-Reset (POR) Power Sequence The APW7566 monitors the input voltage to prevent wrong logic control. The POR function initiates a soft-start pro- The APW7566 provides difference power Sequences to choose for different applications. Figure 1 show the tim- cess after input voltage exceeds its rising POR threshold during power on. The POR function also shuts off the ing diagram of different version of the APW7566. output when the input voltage falls below its falling threshold. VDD Internal Soft-Start EN An internal soft-start function controls rising rate of the output voltage to limit the surge current at start-up. Vout Current-Limit protection The buck converter monitors the output current, flows through the high-side and low-side power MOSFETs, and LDO POK limits the current peak at current-limit level to prevent the IC from damaging during overload, short-circuit 2ms 10ms 0.7ms conditions. Figure 1. Power Sequence Thermal Shutdown A thermal shutdown circuit limits the junction tempera- Under Voltage Protection ture of APW7566. When the junction temperature exceeds +150oC, a thermal sensor turns off the output PMOS, al- The APW7566 had UVP function. In the process of operation, if a short-circuit occurs, the output voltage will lowing the device to cool down. The regulator regulates the output against through initiation of a new soft-start drop quickly. When load current is bigger than current limit threshold value, the output voltage will fall out of the cycle after the junction temperature cools by 150oC. The thermal shutdown is designed with a 30oC hysteresis to required regulation range. If a load step is strong enough to pull the output voltage lower than the under voltage lower the average junction temperature during continuous thermal overload conditions, extending lifetime of threshold (40% of normal output voltage), APW7566 shuts down the output gradually and latches off both high and the device. low side MOSFETs. Power OK Indicator POK is actively held low in shutdown and soft-start status. In the soft-start process, the POK is an open-drain, after Converter is ready, the POK is released. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 12 www.anpec.com.tw APW7566/A Application Information Input Capacitor Selection Output Capacitor The buck converters in APW7566 have a pulsating input current; a low ESR input capacitor is required. This re- The buck converter in APW7566 allows the use of tiny ceramic capacitors. The higher capacitor value provides the good load transients response. Ceramic capacitors sults in the best input voltage filtering, minimizing the interference with other circuits caused by high input volt- with low ESR values have the lowest output voltage ripple and are recommended. If required, tantalum capacitors age spikes. Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load may be used as well. The output ripple is the sum of the voltages across the ESR and the ideal output capacitor. transients. For good input voltage filtering, usually a 22µF input capacitor is sufficient. It can be increased without any limit for better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR VOUT ) 1 VIN (ESR + ) ⋅L 8 ⋅ FSW ⋅ C OUT VOUT ⋅ (1 − ΔV OUT ≅ value, and they are less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input capacitor as close as possible to the VDD to GND pin of the device for better performance. FSW When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These Inductor Selection dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. For high efficiencies, the inductor should have a low DC resistance to minimize conduction losses. Especially at The LDO regulator in APW7566 needs a proper output capacitor to maintain circuit stability and improve transient high-switching frequencies, the core material has a response over temperature and current. In order to in- higher impact on efficiency. W hen using small chip inductors, the efficiency is reduced mainly due to higher sure the circuit stability, the proper output capacitor value should be larger than 4.7µF. With X5R and X7R dielectrics, inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value 4.7µF is sufficient at all operating temperatures. Large output capacitor value can reduce noise and improve load- determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and transient response and PSRR. the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The recommended inductor value can be calculated as below: L≥ VOUT ) VIN ⋅ ∆IL VOUT (1 − FSW IL(MAX)=IOUT(MAX)+1/2x∆IL To avoid the saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 13 www.anpec.com.tw APW7566/A Application Information Layout Consideration The layout is an important step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitor should be placed close to the VDD and GND. Connecting the capacitor and VDD to GND with short and wide trace without any via holes for good input voltage filtering. The distance between VDD to GND to capacitor less than 2mm respectively is recommended. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. 3. The output capacitor should be place closed to LX and GND. 4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 14 www.anpec.com.tw APW7566/A Package Information TDFN2x2-8 A b E D D2 A1 E2 A3 L Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.30 0.007 0.012 0.083 TDFN2x2-8 MILLIMETERS A3 b INCHES 0.20 REF 0.18 0.008 REF D 1.90 2.10 0.075 D2 1.00 1.60 0.039 0.063 E 1.90 2.10 0.075 0.083 E2 0.60 1.00 0.024 0.039 0.45 0.012 e L 0.50 BSC 0.30 0.020 BSC 0.018 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 15 www.anpec.com.tw APW7566/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 2.35 MIN 2.35 MIN 1.00±0.20 4.0±0.10 4.0±0.10 1.5 0.6+0.00 MIN. -0.4 (mm) Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 16 www.anpec.com.tw APW7566/A Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 17 www.anpec.com.tw APW7566/A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 18 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7566/A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2016 19 www.anpec.com.tw