APW7104A 1.5MHz, 1A Synchronous Buck Regulator Features General Description • 1A Output Current • Wide 2.7V~6.0V Input Voltage APW7104A is a 1.5MHz high efficiency monolithic synchronous buck regulator. Design with current mode • Fixed 1.5MHz Switching Frequency • Low Dropout Operating at 100% Duty Cycle • Integrate Synchronous Rectifier • 0.6V Reference Voltage • Current-Mode Operation with Internal operation, extending battery life in portable electrical devices. The internally fixed 1.5MHz operating frequency Compensation - Stable with Ceramic Output Capacitors allows the using of small surface mount inductors and capacitors. The synchronous switches included inside - Fast Line Transient Response scheme, the APW7104A is stable with ceramic output capacitor. Input voltage from 2.7V to 6.0V makes the APW7104A ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout • Short-Circuit Protection increase the efficiency and eliminate the need of an external Schottky diode. • Over-Temperature Protection with Hysteresis The APW7104A is available in SOT-23-5 packages. • Available in SOT-23-5 Packages • Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Applications • HD STB • BT Mouse RUN 1 • PND Instrument GND 2 • Portable Instrument SW 3 APW7104A C1 4.7µF (MLCC) L1 2.2µH 4 VIN 1 VOUT SW 3 APW7104A RUN FB GND 2 C2 10µF (MLCC) R1 5 4 VIN SOT-23-5 (Top View) Simplified Application Circuit VIN 5 FB C3 (option) R2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 1 www.anpec.com.tw APW7104A Ordering and Marking Information Package Code B : SOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7104A Assembly Material Handling Code Temperature Range Package Code APW7104A B : X - Date Code W4AX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter VIN Input Bias Supply Voltage (VIN to GND) VSW SW to GND Voltage > 20ns pulse width < 20ns pulse width RUN, FB to GND Voltage PD Power Dissipation TSDR Unit -0.3 ~ 7 V -0.3 ~ VIN+0.3 V -3 ~ VIN+3 V -0.3 ~ VIN+0.3 V Internally Limited Maximum Junction Temperature TSTG Rating Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) Unit o SOT-23-5 C/W 250 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol VIN Parameter Unit 2.7 ~ 6 V VOUT Converter Output Voltage 0.6 ~ VIN V IOUT Converter Output Current 0~1 A L1 Converter Output Inductor 1.0 ~ 10 µH CIN Converter Input Capacitor 4.7 ~100 µF Converter Output Capacitor 4.7 ~100 µF TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o COUT Input Bias Supply Voltage (VIN to GND) Range C C Note 3: Refer to the typical application circuit Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 2 www.anpec.com.tw APW7104A Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25 oC. Symbol Parameter APW7104A Test Conditions Unit Min. Typ. Max. 2.7 - 6 V - - 0.5 µA UVLO Threshold 2.1 2.35 2.6 V UVLO Hysteresis - 0.1 - V 0.588 0.6 0.612 V -2.5 - +2.5 % -50 - 50 nA SUPPLY VOLTAGE AND CURRENT VIN Input Voltage Range ISD Shutdown Input Current RUN = GND POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS REFERENCE VOLTAGE VREF IFB Reference Voltage VIN=2.7V~6V, TA = -40~85 oC Output Voltage Accuracy 0A < IOUT < 1A FB Input Current INTERNAL POWER MOSFETS FSW Switching Frequency VFB = 0.6V 1.2 1.5 1.8 MHz Foldback Frequency VFB = 0.1V - 210 - kHz Foldback Threshold Voltage on FB VFB Falling - 0.2 - V - 50 - mV Foldback Hysteresis RP-FET High Side N-FET Switch ON Resistance ISW =200mA - 0.28 - Ω RN-FET Low Side P-FET Switch ON Resistance ISW =200mA - 0.25 - Ω Minimum On-Time - - 100 ns Maximum Duty Cycle - - 100 % 1.4 1.6 - A PROTECTION IP-FET, 2.7V≦VIN≦6V ILIM Maximum Inductor Current-Limit TOTP Over-Temperature Protection TJ Rising - 150 - Over-Temperature Protection Hysteresis TJ Falling - 30 - Soft-Start Duration (Note 4) - 0.7 - ms RUN Input High Threshold VIN = 2.7V~6V - - 1 V RUN Input Low Threshold VIN = 2.7V~6V 0.4 - - V RUN Leakage Current VRUN = 5V, VIN = 5V -1 - 1 µA °C START-UP AND SHUTDOWN TSS Note 4: Guarantee by design, not production test. Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 3 www.anpec.com.tw APW7104A Typical Operating Characteristics (Refer to the application circuit in the section “Typical Application Circuits”, VIN=3.6V, VOUT=1.8V, TA=25oC unless otherwise specified ) Efficiency vs. Load Current Efficiency vs. Load Current 100 100 90 90 80 80 70 Efficiency (%) Efficiency (%) 70 60 VIN=5V VIN=3.3V 50 40 60 50 VIN=3.3V 40 30 30 VOUT = 1.8V L = 2.2µH COUT = 10µF 20 10 VOUT = 1.2V L = 2.2µH COUT = 10µF 20 10 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Load Current, IOUT(A) 1 Load Current, IOUT(A) Supply Voltage v.s. Quiescent Current Supply Voltage vs. ON Resistance 40 0.35 35 RP-FET 0.30 30 ON Resistance(Ω) Quiescent Current, IDD(µA) VIN=5V 25 20 15 10 5 0.25 0.20 RN-FET 0.15 0.10 0.05 0 2 2.5 3 3.5 4 4.5 5 5.5 0.00 6 Supply Voltage, V IN(V) 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VIN(V) Supply Voltage v.s. Reference Voltage 0.65 Reference Voltage, VREF(V) 0.64 0.63 0.62 0.61 0.6 0.59 0.58 0.57 0.56 0.55 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 4 www.anpec.com.tw APW7104A Operating Waveforms (Refer to the application circuit in the section “Typical Application Circuits”, VIN=3.6V, VOUT=1.8V, TA=25oC unless otherwise specified) Soft Start Load Transient Response 1A 1 VRUN 300mA 1 VOUT ,1V/Div, DC 2 IOUT, 0.5A/Div, DC VOUT ,100mV/Div, AC 2 3 IIN, 200mA/Div L=2.2µH, VIN=5V, VOUT=1.8V, COUT=10µF L=2.2µH, VIN=5V, COUT=10µF Time: 100µs/Div Time: 100µs/Div Normal Operation 2.5V 1.5V VIN, 0.5V/Div 1 VSW ,2V/Div, DC 2 VOUT ,20mV/Div, AC VOUT,200mV/Div,AC IL, 500mV/Div, DC 3 L=2.2µH, VINI=5V, VOUT=1.2V, COUT=10µF = 100mA OUT Time: 500ns/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 5 www.anpec.com.tw APW7104A Pin Description PIN FUNCTION NO. NAME 1 RUN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts it down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not leave RUN pin floating. 2 GND Power and Signal Ground. 3 SW Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFETs switches. 4 VIN Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7µF or greater ceramic capacitor. 5 FB Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at 0.6V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter. Block Diagram Current Sense Amplifier RUN VIN Shutdown Control Logic Control SW OverTemperature Protection Gate Driver Current -Limit Slope Compensation GND ∑ Oscillator ICMP Error Amplifier FB COMP EAMP SoftStart Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 6 VREF 0.6V www.anpec.com.tw APW7104A Typical Application Circuit IIN VIN L1 2.2µH 4 SW VIN VOUT 3 2.7~6V C1 4.7µF (MLCC) APW7104A 1 RUN FB R1 5 C3 (option) GND 2 0.6V~VIN C2 0~1A 10µF (MLCC) R2 R1 ≤ 1MΩ is recommended R2 ≤ 200kΩ is recommended C1 closed to IC. Less than 2mm is recommended. Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 7 www.anpec.com.tw APW7104A Function Description Main Control Loop internally by adding a compensating ramp to the inductor The APW7104A is a constant frequency, synchronous rec- current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak cur- tifier and current-mode switching regulator. In normal operation, the internal P-channel power MOSFET is rent for duty cycles > 40%. However, the APW7104A uses a special scheme that counteracts this compensating turned on each cycle. The peak inductor current at which ICMP turn off the P-FET is controlled by the voltage on the ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. COMP node, which is the output of the error amplifier (EAMP). An external resistive divider connected between Dropout Operation VOUT and ground allows the EAMP to receive an output feedback voltage VFB at FB pin. When the load current As the input supply voltage decreases to a value ap- increases, it causes a slightly decrease in VFB relative to the 0.6V reference, which in turn causes the COMP volt- proaching the output voltage, the duty cycle increases toward the maximum on time. Further, reduction of the age to increase until the average inductor current matches the new load current. supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The Under-Voltage Lockout input voltage minus the voltage drop will determine the output voltage across the P-FET and the inductor. An under-voltage lockout function prevents the device from operating if the input voltage on VIN is lower than approxi- Dropout Operation (Cont.) An important detail to remember is that on resistance of mately 1.8V. The device automatically enters the shutdown mode if the voltage on VIN drops below approxi- P-FET switch will increase at low input supply voltage. Therefore, the user should calculate the power dissipa- mately 1.8V. This under-voltage lockout function is implemented in order to prevent the malfunctioning of the tion when the APW7104A is used at 100% duty cycle with low input voltage. converter. Soft-Start Over-Temperature Protection (OTP) The APW7104A has a built-in soft-start to control the output voltage rise during start-up. During soft-start, an in- The over-temperature circuit limits the junction temperature of the APW7104A. When the junction temperature ternal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the ref- exceeds 150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sen- erence voltage (0.6V typical) until the ramp voltage reaches the reference voltage. Then, the voltage on FB sor allows the converters to start a soft-start process and regulate the output voltage again after the junction tem- regulated at reference voltage. perature cools by 30oC. The OTP is designed with a 30oC hysteresis to lower the average Junction Temperature Enable/Shutdown (TJ) during continuous thermal overload conditions, increasing the lifetime of the device. Driving RUN to the ground places the APW7104A in shutdown mode. When in shutdown, the internal power Short-Circuit Protection MOSFETs turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5µA maximum. When the output is shortened to the ground, the frequency of the oscillator is reduced to about 210kHz, 1/7 of the Slope Compensation and Inductor Peak Current The APW7104A is a peak current mode PWM step down nominal frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby pre- converter. To prevent sub-harmonic oscillations, the APW7104A sense the peak current and add slope com- venting runaway. The oscillator’s frequency will progressively increase to 1.5MHz when VFB or VOUT rises above pensation to stable the converter. It is accomplished Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 0V. 8 www.anpec.com.tw APW7104A Application Information Input Capacitor Selection shown in “Typical Application Circuits”. A suggestion of Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the maximum value of R2 is 200kΩ to keep the minimum current that provides enough noise rejection ability through best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. the resistor divider. The output voltage can be calculated as below: R1 R1 VOUT = VREF ⋅ 1 + = 0.6 ⋅ 1 + R2 R2 Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For good input voltage filtering, usually a 4.7µF input capacitor is sufficient. It can be increased without any limit for VOUT better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and R1≤1MΩ they are less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input FB R2 ≤ 200kΩ APW7104A capacitor as close as possible to the input and GND pin of the device for better performance. GND Inductor Selection Output Capacitor Selection For high efficiencies, the inductor should have a low DC The current-mode control scheme of the APW7104A allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a pacitor value provides the good load transients response. higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value de- tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the ideal output capacitor. lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient ∆VOUT response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The rec- V VOUT ⋅ 1 − OUT VIN ≅ FSW ⋅ L 1 ⋅ ESR + ⋅ 8 F SW ⋅ COUT When choosing the input and output ceramic capacitors, ommended inductor value can be calculated as below: choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char- V VOUT 1 − OUT V IN L≥ FSW ⋅ ∆IL acteristics of all the ceramics for a given value and size. VIN IL(MAX) = IOUT(MAX) + 1/2 x ∆IL IIN IP-FET To avoid the saturation of the inductor, the inductor should IL be rated at least for the maximum output current of the converter plus the inductor ripple current. CIN Output Voltage Setting P-FET VOUT SW N-FET In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- IOUT ESR COUT nected to the output, allowing remote voltage sensing as Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 9 www.anpec.com.tw APW7104A Application Information (Cont.) Output Capacitor Selection (Cont.) The maximum power dissipation on the device can be shown as follow figure: IL 0.8 Maximum Power Disspation (W) ILIM IPEAK ∆IL IOUT IP-FET 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Thermal Consideration Layout Consideration In most applications, the APW7104A does not dissipate much heat due to its high efficiency. But, in applications For all switching power supplies, the layout is an impor- where the APW7104A is running at high ambient temperature with low supply voltage and high duty cycles, the tant step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully heat dissipated may exceed the maximum junction tem- done, the regulator might show noise problems and duty cycle jitter. perature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with off and the SW node will become high impedance. To avoid the APW7104A from exceeding the maximum short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to deter- to capacitor less than 2mm respectively is recommended. mine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissi- 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed pated by the part is approximated: as close as possible to the SW pin to minimize the noise coupling into other circuits. PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D)) The temperature rise is given by: 3. The output capacitor should be place closed to converter VOUT and GND. TR = (PD)(θJA) 4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed Where PD is the power dissipated by the regulator, D is duty cycle of main switch away from the inductor. The feedback pin and feedback network should be shielded with a ground plane D = VOUT/VIN The θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes TJ, is given by: ground shifts and noise is recommended. TJ = TA + TR Where TA is the ambient temperature. Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 10 www.anpec.com.tw APW7104A Layout Consideration (cont.) Via to GND R2 FB VRUN R1 L1 Via to VOUT VOUT SW COUT CIN VIN GND APW7104A Layout Suggestion Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 11 www.anpec.com.tw APW7104A Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 INCHES MILLIMETERS MIN. MAX. MIN. A MAX. 1.45 0.057 A1 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 e 0.95 BSC e1 0.071 0.037 BSC 1.90 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 12 www.anpec.com.tw APW7104A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSOT-23-5A A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 Application SOT-23-5 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity TSOT-23-5A Tape & Reel 3000 SOT-23-5 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 13 www.anpec.com.tw APW7104A Taping Direction Information SOT-23-5 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 14 www.anpec.com.tw APW7104A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 15 www.anpec.com.tw APW7104A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 16 www.anpec.com.tw