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AMD RS690 ASIC Family Register
Reference Guide
Technical Reference Manual
Rev. 3.00o
P/N: 43372_rs690_rrg_3.00o
© 2007 Advanced Micro Devices, Inc.
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, ATI, Mobility, PowerPlay, CrossFire, Radeon, and combinations thereof, are trademarks of Advanced Micro Devices, Inc.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect
to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except as set forth in AMD's Standard
Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the
implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications
intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or
environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
© 2007 Advanced Micro Devices, Inc. All rights reserved.
Table of Contents
Chapter 1: Introduction
1.1 About this Manual ................................................................................................................................................1-1
1.2 Nomenclature and Conventions .............................................................................................................................1-1
1.2.1
Numeric Representations .........................................................................................................................1-1
1.2.2
Register Description ................................................................................................................................1-2
Chapter 2: Registers Description
2.1 Northbridge Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 PCI Express Registers ........................................................................................................................................2-58
2.3 Graphics Controller Configuration Registers ...................................................................................................... 2-110
2.4 Bus Interface Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-127
2.5 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129
2.6 System Clock Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130
2.7 APC Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-143
2.8 Side-Port Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-153
2.9 System GART Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-266
2.10 Display Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-267
2.11 DAC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-296
2.12 VGA Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-297
2.13 VGA Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-300
2.14 VGA CRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-303
2.15 VGA Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-312
2.16 VGA Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-316
2.17 TV Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-322
2.18 LVTMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-348
2.19 Miscellaneous Detailed Register Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-350
Appendix A: Cross-Referenced Index
A.1 Quick Cross-Referenced Index ......................................................................................................................... A-1
A.2 Index Registers Sorted by Name ....................................................................................................................... A-2
A.3 All Registers Sorted By Name .......................................................................................................................... A-3
A.4 All Registers Sorted By Address ..................................................................................................................... A-29
Appendix B: Revision History
B.1 Rev 3.00o (December 2007) ............................................................................................................................. B-1
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
TOC-1
Table of Contents
AMD RS690 ASIC Family Register Reference Manual
TOC-2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Chapter 1
Introduction
1.1
About this Manual
This document is intended for BIOS engineers designing BIOSes for systems based on AMD’s RS690 family of chipsets.
It describes the register reference information needed to ensure the proper functioning of the RS690 ASIC. Use this
document in conjunction with the related AMD RS690 ASIC Family Register Programming Requirements Guide, and
AMD RS690 ASIC Family BIOS Developer’s Guide.
This document covers register reference information for the following RS690 ASIC variants. Unless specified otherwise,
reference to the RS690 ASIC in this document applies to all of these variants, even when these variants are not
specifically mentioned.
•
Desktop:
•
•
•
Mobile:
•
•
•
•
•
•
RS690
RS690C
RS690M
RS690MC
RS690T
Chapter 1 outlines the notations and conventions used throughout this manual.
Chapter 2 provides detailed descriptions of the registers.
Appendix A provides several cross-referenced lists of the registers (sorted by register name and address).
Changes and additions from the previous release of this document are highlighted in red. Refer to Appendix B: Revision
History at the end of this manual for a detailed revision history. The names of all of the index registers and data registers
in this document (used for indirect access) are highlighted in purple. Refer to section A.2: Index Registers Sorted By Name
for a complete list of all of the index and data registers.
1.2
Nomenclature and Conventions
1.2.1 Numeric Representations
•
Hexadecimal numbers are appended with “h” whenever there is a risk of ambiguity. Other numbers are assumed to be
in decimal.
•
Registers (or fields) of identical function are sometimes indicated by a single expression in which the part of the
signal name that differs is enclosed in [ ] brackets. For example, the eight Host Data registers — HOST_DATA0
through to HOST_DATA7 — are represented by the single expression HOST_DATA[7:0].
•
Series of numbers appearing in similar addresses are sometimes enclosed in [ ] brackets. For example,
PCIE_HDR_LOGO exists for PCI-E device 2 to 8, and the registers’ addresses are expressed collectively as
pcieConfig [2:8]\:0x11C.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
1-1
Nomenclature and Conventions
1.2.2 Register Description
All registers in this document are described with the format of the sample table below. All offsets are in hexadecimal
notation, while programmed bits are in either binomial or hexadecimal notation.
Table 1-1 Register Description Table Notation—Example
DST_HEIGHT_WIDTH_8 - W - 32 bits - [MMReg:0x158C]
Field Name
DST_WIDTH
Bits
Default
Description
23:16
0x0
Destination Width Note: This is an initiator register. Y is
incremented at end of blit. Write 15: 0 to E2_DST_X, Write
31: 16 to E2_DST_WIDTH, then signal blit_start.
E2_DST_Y = E2_DEST_Y (+/-) E2_DST_HEIGHT as function of direction after blit is complete
31:24
0x0
Destination Height Write 15: 0 to E2_DST_Y, Write 31: 16
to E2_DST_HEIGHT
(mirror bits 7:0 of DST_WIDTH:DST_WIDTH)
DST_HEIGHT
(mirror bits 7:0 of DST_HEIGHT:DST_HEIGHT)
[W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to 256 (ZERO extent)
Register Information
Example
Register name
DST_HEIGHT_WIDTH_8
Read / Write capability
R = Readable
W = Writable
RW = Readable and Writable
W
Register size
32 bits
Register address(es)*
MMReg:0x158C
Field name
DST_WIDTH
Field position/size
23:16
Field default value
0x0
Field description
Destination....complete
Field mirror information
(mirror bits 7:0 of DST_WIDTH:DST_WIDTH)
Brief register description
[W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination
width: range 0 to 256 (ZERO extent)
* Note:
There maybe more than one address; the convention used is as follows:
[aperName:offset] - single mapping, to one aperture/decode and one offset
[aperName1, aperName2, …, aperNameN:offset] - multiple mappings to different apertures/decodes
but same offset
[aperName:startOffset-endOffset] - mapped to an offset range in the same aperture/decode
Warning: Do not attempt to modify the values of registers or bit fields that are marked as "Reserved." Doing so may
cause the system to behave in unexpected ways.
AMD RS690 ASIC Family Register Reference Manual
1-2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Chapter 2
Registers Description
2.1
Northbridge Configuration Space Registers
NB_VENDOR_ID - R - 16 bits - nbconfig:0x0
Field Name
VENDOR_ID
Field Name
Bits
Default
15:0
0x1002
Description
Vendor ID.
This 16-bit field identifies the manufacturer of the device:
Advnced Micro Devices, Inc.
NB_DEVICE_ID - R - 16 bits - nbconfig:0x2
Bits
15:0
DEVICE_ID
Default
0x7910
Description
Device Identifier
This 16-bit field is assigned by the device manufacturer and
identifies the type of device. The current northbridge device
ID assignment is 0x7910. The host bridge alternate device
ID is 0x7911 which is selected by the e-fuse configuration
bit.
NB_COMMAND - RW - 16 bits - nbconfig:0x4
Field Name
IO_ACCESS_EN (R)
Bits
0
Default
0x0
MEM_ACCESS_EN
1
0x0
BUS_MASTER_EN (R)
2
0x1
SPECIAL_CYCLE_EN (R)
3
0x0
MEM_WRITE_INVALIDATE_EN (R)
4
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
I/O Access Enable
This bit is always 0 because the RS690 does not respond to
I/O cycles on the PCI Bus.
0=Disable
1=Enable
Memory Access Enable
Controls whether PCI memory accesses to system memory
are accepted.
0=Disable
1=Enable
Bus Master Enable
This bit is always set, indicating that the RS690 is allowed
to act as a bus master on the PCI Bus.
0=Disable
1=Enable
Special Cycle
This bit is always 0 because the RS690 ignores PCI special
cycles.
0=Disable
1=Enable
Memory Write and Invalidate Enable
This bit is always 0 because the RS690 does not generate
memory write and invalidate commands.
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
2-1
PAL_SNOOP_EN (R)
5
0x0
PARITY_ERROR_EN (R)
6
0x0
Reserved0 (R)
7
0x0
SERR_EN
8
0x0
FAST_B2B_EN
9
0x0
15:10
0x0
Reserved (R)
VGA Palette Snoop Enable
This bit is always 0 indicating that the RS690 does not
snoop the VGA palette address range.
0=Disable
1=Enable
Parity Error Response
This bit is always 0 because the RS690 does not report
data parity errors.
0=Disable
1=Enable
This bit is reserved in PCI 2.3. It is hardwired to 0.
0=Disable
1=Enable
System Error Enable
Controls the assertion of SERR#.
0=Disable
1=Enable
Fast Back-to-Back to Different Devices Enable
This bit is always 0, because the RS690 does not allow the
generation of fast back-to-back transactions to different
agents.
0=Disable
1=Enable
NB_STATUS - RW - 16 bits - nbconfig:0x6
Bits
4
Default
0x1
PCI_66_EN (R)
5
0x1
Reserved (R)
FAST_BACK_CAPABLE (R)
6
7
0x0
0x0
10:9
0x1
SIGNAL_TARGET_ABORT (R)
11
0x0
RECEIVED_TARGET_ABORT
12
0x0
RECEIVED_MASTER_ABORT
13
0x0
CAP_LIST (R)
Field Name
DEVSEL_TIMING (R)
AMD RS690 ASIC Family Register Reference Manual
2-2
Description
Capabilities List
This bit is set to indicate that this device's configuration
space supports a capabilities list.
66-MHz Capable
Indicates that the RS690 supports 66 MHz PCI operation
Fast Back-to-Back Capable
This bit is always 0 indicating that the RS690, as a target, is
not capable of accepting fast back-to-back transactions
when the transactions are not to the same agent.
DEVSEL# Timing
This bit field defines the timing of DEVSEL# on the RS690.
The device only supports medium DEVSEL# timing.
Signaled Target Abort
This bit is always 0 because the RS690 does not terminate
transactions with target aborts.
0=No Abort
1=Target Abort asserted
Received Target Abort
This bit is set by whenever a CPU to PCI transaction
(except for a special cycle) is terminated due to a
target-abort. This bit is cleared by writing a 1.
0=Inactive
1=Active
Received Master Abort
This bit is set whenever a CPU to PCI transaction (except
for a special cycle) is terminated due to a master-abort. This
bit is cleared by writing a 1.
0=Inactive
1=Active
© 2007 Advanced Micro Devices, Inc.
Proprietary
SIGNALED_SYSTEM_ERROR
14
0x0
PARITY_ERROR_DETECTED (R)
15
0x0
General NB status Flags
Signaled System Error
This bit is set whenever the RS690 generates a System
Error and asserts the SERR# line (currently only GART
Error). This bit is cleared by writing a 1.
0=No Error
1=SERR asserted
Detected Parity Error
This bit is always 0 because the RS690 does not support
data parity checking.
NB_REVISION_ID - R - 8 bits - nbconfig:0x8
Field Name
MINOR_REV_ID
MAJOR_REV_ID
Revision Identification
Bits
3:0
7:4
Default
0x0
0x0
Description
Identifies the stepping number of the device.
Identifies the revision number of the device.
NB_REGPROG_INF - R - 8 bits - nbconfig:0x9
Field Name
REG_LEVEL_PROG_INF
Bits
Default
7:0
0x0
Description
Indicates a Host bridge.
Program Interface.
NB_SUB_CLASS - R - 8 bits - nbconfig:0xA
Field Name
SUB_CLASS_INF
Bits
Default
7
0x0
Description
Indicates a Host bridge.
Sub-Class Code.
NB_BASE_CODE - R - 8 bits - nbconfig:0xB
Field Name
BASE_CLASS_CODE
Bits
Default
7:0
0x6
Description
Indicates a Bridge device.
Class Code.
NB_CACHE_LINE - R - 8 bits - nbconfig:0xC
Field Name
CACHE_LINE_SIZE
Cache Line Size.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-3
NB_LATENCY - RW - 8 bits - nbconfig:0xD
Field Name
LATENCY_TIMER
Bits
Default
Description
7:0
0x0
This bit field defines the minimum amount of time (in PCI
clock cycles) that the bus master can retain ownership of
the bus. This is mandatory for masters that are capable of
performing a burst consisting of more than two data phases.
Latency Timer.
NB_HEADER - R - 8 bits - nbconfig:0xE
Field Name
HEADER_TYPE
DEVICE_TYPE
Bits
6:0
Default
0x0
7
0x0
Header Type
Description
Bits [6:5] are 0, indicating that Type 00 Configuration Space
Header format is supported.
Bit [7] is always 0, indicating that the RS690's northbridge
block is a single function device.
0=Single-Function Device
1=Multi-Function Device
NB_BIST - R - 8 bits - nbconfig:0xF
Field Name
BIST_COMP
Bits
Default
3:0
0x0
BIST_STRT
6
0x0
BIST_CAP
7
0x0
Description
Built-in-self-test.
NB_BAR2_PM2 - RW - 32 bits - nbconfig:0x18
Bits
0
Default
0x1
RESERVED (R)
PM2_BASE_LOW (R)
1
4:2
0x0
0x0
PM2_BASE
31:5
0x0
MEM_IO (R)
Field Name
Descriptor for Power management PM2 Control Block.
AMD RS690 ASIC Family Register Reference Manual
2-4
Description
I/O Space:
This bit is hardwired to 1 to indicate that this base address
register maps into x86 I/O space.
0=Memory
1=I/O
This field specifies that there are 8 DWORD registers
allocated to this space.
PM2_BLK Base:
This bit field forms the upper part of BAR2. This field is
loaded by BIOS software and specifies the base of
PM2_BLK.
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_BAR3_PCIEXP_MMCFG - RW - 32 bits - nbconfig:0x1C
Field Name
Bits
0
Description
Memory:
This bit is hardwired to 0 to indicate that this base address
register maps into memory space
0=Memory
1=I/O
TYPE (R)
2:1
0x2
Type:
This bit field is hardwired to 2'b10 to indicate that this base
register is 64 bits wide and mapping can be performed
anywhere in the 64-bit address space
PREFETCH_EN (R)
3
0x0
Prefetchable:
This bit is hardwired to 1 to indicate that this range is
prefetchable.
MEM_BASE_LOW (R)
20:4
0x0
Base Address Low:
This bit field is hardwired to return zeros to indicate that xx
Kbytes are allocated to PCI Express Configuration
Registers.
MEM_BASE_HIGH
31:21
0x0
Base Address High:
This bit field forms the upper part of BAR3. This field is
loaded by BIOS software.
Descriptor for memory mapped PCI Express Configuration registers.
MEM_IO (R)
Default
0x0
NB_BAR3_UPPER_PCIEXP_MMCFG - RW - 32 bits - nbconfig:0x20
Field Name
MEM_BASE_UPPER
Bits
Default
31:0
0x0
Description
Upper 32-bit of BAR3 base address.
Descriptor for upper part of memory mapped PCI Express Configuration registers.
NB_ADAPTER_ID - R - 32 bits - nbconfig:0x2C
Field Name
SUBSYSTEM_VENDOR_ID
Bits
15:0
Default
0x0
31:16
0x0
Description
(mirror of
NB_ADAPTER_ID_W:SUBSYSTEM_VENDOR
_ID)
SUBSYSTEM_ID
(mirror of
NB_ADAPTER_ID_W:SUBSYSTEM_ID)
Subsystem Vendor ID and Subsystem ID register
NB_CAPABILITIES_PTR - R - 32 bits - nbconfig:0x34
CAP_PTR
Field Name
Bits
7:0
Default
0xc4
Description
This field contains a byte offset into a device's configuration
space containing the first item in the capabilities list. If no
next item exists, then it is set to null.
Capabilities Pointer
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-5
NB_PCI_CTRL - RW - 32 bits - nbconfig:0x4C
Field Name
FUNCTION_1_ENABLE
Bits
0
Default
0x0
APIC_ENABLE
1
0x1
AlwaysUnLk
2
0x1
Cf8Dis
3
0x0
PMEDis
4
0x0
SErrDis
5
0x0
BMMsgEn
6
0x0
DisLockP2P
7
0x0
PMArbDisSel
10:8
0x0
11
0x0
14:12
15
0x2
0x0
WakeC2En
16
0x0
BAR2_PM2Enable
17
0x0
P4IntEnable
18
0x0
SLPEnable
20
0x0
CsrStatus
CfgRdTime
P2PDynamicClkOff
AMD RS690 ASIC Family Register Reference Manual
2-6
Description
Enables access to Bus0Dev0Fun1.
0=Disable
1=Enable
Not used.
0=Disable
1=Enable
If set, always issues UnLk request for CPU lock transaction.
If not set, only issues UnLk when RdLk is successful.
0=Disable
1=Enable
Disables IO 0xCF8 cycle to the nbcfg block.
0=Enable
1=Disable
Disables PME message generation.
0=Enable
1=Disable
Disables SErr message generation.
0=Enable
1=Disable
Enables BM_Set message generation.
0=Disable
1=Enable
If set, P2P could sneak into the MemRdLk sequence. If not
set, blocks PwP during CPU lock transactions
0=Enable
1=Disable
Setting bit [0] disables BIF request when PMArbDis is set.
Setting bit [1] disables rx0(graphics pcie) DMA request
when PMArbDis is set.
Setting bit [2] disables rx1(SB and general purpose pcie)
DMA request when PMArbDis is set.
1 means CSR is detected. Write 1 to clear this bit. Writing 0
has no effect.
0=Inactive
1=Active
3-bit setting for RBBM read data bus data latch latency
If set to 1, the dynamic clock has to be turned off in order to
support P2P traffic.
0=Enable
1=Disable
1 means enable Wake_from_C2 message. 0 means
disable.
0=Enable
1=Disable
Enables read/write access to the NB_BAR2_PM2 register.
Clearing this bit could hide BAR2.
0=Disable
1=Enable
Enables NB to accept A4 interrupt request from SB.
0=Disable
1=Enable
Enables SLP logic in NB.
0=Enable
1=Disable
© 2007 Advanced Micro Devices, Inc.
Proprietary
SLP_Pad_Enable
21
0x0
BAR1_Enable
22
0x0
MMIOEnable
23
0x0
IsocArbMode
24
0x0
IsocHiPr
25
0x0
HPDis
26
0x0
PCI Control Register.
Enables SLP# pad output.
0=Enable
1=Disable
Enables read/write access to NB_BAR1_RCRB register.
Clearing this bit could hide BAR1.
0=Enable
1=Disable
Enables MMIO decoding.
0=Enable
1=Disable
If set, checks IOCIsocArbiter setting for arbitration. If not
set, checks IsocHiPr for priority.
0=Enable
1=Disable
If set, ISOC has high priority. If not set, the regular channel
has high priority.
0=Enable
1=Disable
If set, disables HP message generation
0=Enable
1=Disable
NB_ADAPTER_ID_W - RW - 32 bits - nbconfig:0x50
Field Name
Bits
Default
SUBSYSTEM_VENDOR_ID
15:0
0x1002
SUBSYSTEM_ID
31:16
0x7910
Description
Subsystem Vendor ID and Subsystem ID write register.
NB_MISC_INDEX - RW - 32 bits - nbconfig:0x60
Field Name
NB_MISC_IND_ADDR
NB_MISC_IND_WR_EN
Bits
Default
6:0
0x0
Northbridge Misc. index register address.
Description
7
0x0
Northbridge Misc. index register write enable.
00=Disable writes to NB_MISC_DATA
01=Enable writes to NB_MISC_DATA
Northbridge Misc. index register address and write enable.
NB_MISC_DATA - RW - 32 bits - nbconfig:0x64
Field Name
NBMISCDATA
Bits
Default
31:0
0x0
Description
Northbridge Misc. index register data.
Northbridge Misc. index register data.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-7
NB_CNTL - RW - 32 bits - NBMISCIND:0x0
Bits
Default
HIDE_NB_AGP_CAP
Field Name
0
0x0
Hides AGP Capabilities in the Host Bridge (NBCFG).
0=Visible (Enable)
1=Hide (Disable)
HIDE_P2P_AGP_CAP
1
0x1
Hides AGP Capabilities in the P2P Bridge (APCCFG).
0=Visible (Enable)
1=Hide (Disable)
HIDE_NB_GART_BAR
2
0x0
Hides NB GART BAR registers and enables MC Indexed
GART registers. When this bit is set to 1, the NB GART
BAR register will read back 00. However, writing to the
register is not disabled.
00=Visible (Enable)
01=Hide (Disable)
HIDE_MMCFG_BAR
3
0x0
Enables PCI Express MMCFG BAR register.
0=Visible (Enable)
1=Hide (Disable)
AGPMODE30
4
0x0
Enables NB/APC AGP3.0 REGISTER MODE
0=Disable
1=Enable AGP3.0 REGISTER MODE
AGP30ENHANCED
5
0x0
Enables NB/APC CFG ENHANCED AGP3.0 MODE (full
appendix).
0=Disable
1=Enable ENHANCED AGP3.0 MODE
NB_SB_CFG_EN
6
0x0
If set, enables CFG access to Dev8, which is the SB P2P
Bridge.
0=Disable
1=Enable
HWINIT_WR_LOCK
7
0x0
If set, it locks HWINIT register values.
0=Disable
1=Enable
HIDE_AGP_CAP
8
0x0
Hides Int Graphics Controller AGP Capabilities.
0=Disable
1=Enable
STRAP_MSI_ENABLE
10
0x1
Enables Int Graphics Controller MSI Capabilities Pointer
0=Disable
1=Enable
TESTMODE_ENABLE (R)
13
0x0
From the Test Controller.
14
0x0
From the Test Controller.
31:16
0x0
ROM Based Diagnostic POST CODE.
COM_PORT_MODE (R)
ROM_CTRL_POST
Description
Northbridge Control.
NB_SPARE1 - RW - 32 bits - NBMISCIND:0x2
Bits
Default
NB_SPARE1_RW
Field Name
15:0
0x0
Spare read/write control bits.
Description
NB_SPARE1_RO (R)
31:16
0x0
Spare read only status bits.
Spare register.
AMD RS690 ASIC Family Register Reference Manual
2-8
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_STRAPS_READBACK_MUX - RW - 32 bits - NBMISCIND:0x3
Field Name
SELECT
Bits
Default
Description
7:0
0x0
This register selects which 32-bits of Power-on STRAPS to
be readback in NB_STRAPS_READBACK_DATA.
Strap Readback Mux Select register.
NB_STRAPS_READBACK_DATA - R - 32 bits - NBMISCIND:0x4
Field Name
READ
Bits
Default
31:0
0x0
Description
Values of STRAPS as selected by the mux selector,
NB_STRAPS_READBACK_MUX.
Strap Readback register.
PCIE_LINK_CFG - RW - 32 bits - NBMISCIND:0x8
Field Name
SW_RESET_DURATION_GFX
ATOMIC_SW_RESET_GFX
RST_cor_reset_GFX
HOLD_TRAIN0_GFX
Bits
1:0
2
3
4
Default
0x0
0x0
0x0
0x1
5
0x1
6
7
11:8
0x0
0x0
0x0
RESERVED_GFX
RST_sty_reset_GFX
CALIB_RESET_GFX
12
13
14
0x0
0x0
0x0
GLOBAL_RESET_GFX
15
0x0
17:16
18
19
20
0x0
0x0
0x0
0x0
HOLD_TRAIN1_GPPSB
21
0x1
HOLD_TRAIN2_GPPSB
22
0x1
HOLD_TRAIN3_GPPSB
23
0x1
HOLD_TRAIN1_GFX
RST_reg_reset_GFX
RST_phy_reset_GFX
MULTIPORT_CONFIG_GFX
SW_RESET_DURATION_GPPSB
ATOMIC_SW_RESET_GPPSB
RST_cor_reset_GPPSB
HOLD_TRAIN0_GPPSB
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Hold Port A from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
Hold Port B from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
Multiport Configuration of External Graphics Link
0=Port A only
1=Port A and Port B
Reserved - do not use
Software Reset of pcie calibration logic
0=Disable
1=Enable
Software Reset of pcie core logic
0=Disable
1=Enable
Hold Port A from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
Hold Port A from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
Hold Port A from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
Hold Port A from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
AMD RS690 ASIC Family Register Reference Manual
2-9
HOLD_TRAIN4_GPPSB
24
0x1
HOLD_TRAIN5_GPPSB
25
0x1
HOLD_TRAIN6_GPPSB
26
0x1
RST_reg_reset_GPPSB
RST_phy_reset_GPPSB
RST_sty_reset_GPPSB
CALIB_RESET_GPPSB
27
28
29
30
0x0
0x0
0x0
0x0
GLOBAL_RESET_GPPSB
31
0x0
PCIE Link Configuration Register
Hold Port A from Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
0=Allow Link Training
1=Hold (Prevent) Link Training
Software Reset of PCIE calibration logic
0=Disable
1=Enable
Software Reset of PCIE core logic
0=Disable
1=Enable
IOC_DMA_ARBITER - RW - 32 bits - NBMISCIND:0x9
Field Name
DMA_ARBITER
Bits
Default
31:0
0x0
Description
Arbitration algorithm implementation.
IOC DMA arbiter.
IOC_PCIE_CSR_Count - RW - 32 bits - NBMISCIND:0xA
Field Name
Bits
Default
Description
CsrDelayCount
23:0
0x0
CSR frequency counter.
CsrLimitCount
31:24
0x0
CSR limit counter.
IOC CSR counter.
IOC_PCIE_CNTL - RW - 32 bits - NBMISCIND:0xB
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
C3STPCLKDectecEn
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
IOC_SB_SetPowEn
IOC_SetDMAInValidEn
IOC_SB_SetPMETurnOffEn
Bits
0
1
2
3
4
7
8
9
10
11
12
13
16
17
18
19
20
21
22
23
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
LockOrderingByPassDisable
24
0x0
AMD RS690 ASIC Family Register Reference Manual
2-10
Description
Dma RO value. Only valid if FixAttrEn is set.
Dma snoop value. Only valid if FixAttrEn is set.
Fix dma request snoop attribute.
Disables peer-to-peer transaction target at SB.
Disables bus-master trigger event from SB.
Enables mst read order rule.
Blocks non-snoop dma request if PMArbDis is set.
Blocks snoop dma request if PMArbDis is set.
Mst RO value. Only valid if next bit is set
Fixes Mst RO attribute.
Enables non-snoop for mst request.
Detects an external device plugged.
Enables external device csr function.
Enables CSR.
Interrupt ABCD(0) or EFGH(1) mode.
Enables set_slot_power message to SB.
Enables Set_Slot_Power_limit/Scale message to SB.
Enables DMA InValid Request handling.
Enables PME_Turn_Off/PME_To_Ack between NB and
SB.
Disables ordering rule by pass for lock transactions.
© 2007 Advanced Micro Devices, Inc.
Proprietary
DMAInvalidMode
26
0x0
CfgDat_Enable_NS_Ordering
CrsIDRdEn
27
28
0x0
0x0
IOC PCIE control counter
Controls DMA InValid request handling mode:
mode0=Return UA for non_posted request
mode1=Drop all requests
Returns 0x0001 for DeviceID and VendorID crs response.
0=Enable
1=Disable
IOC_P2P_CNTL - RW - 32 bits - NBMISCIND:0xC
Field Name
Dev2BridgeDis
Dev3BridgeDis
Dev4BridgeDis
Dev5BridgeDis
Dev6BridgeDis
Dev7BridgeDis
GfxMetaCtl
SBMetaCtl
MsgMetaCtl
DLDownResetEn
NonDev0ToSBEn
GSMEnable
BMREQPinEnable
IOC p2p bridge control
Bits
2
3
4
5
6
7
8
9
10
11
12
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x0
0x1
13
14
0x0
0x0
Description
Setting to 1 could hide Bus0Dev2Fun0 p2p bridge
Setting to 1 could hide Bus0Dev3Fun0 p2p bridge
Setting to 1 could hide Bus0Dev4Fun0 p2p bridge
Settting to 1 could hide Bus0Dev5Fun0 p2p bridge
Setting to 1 could hide Bus0Dev6Fun0 p2p bridge
Setting to 1 could hide Bus0Dev7Fun0 p2p bridge
Enables double flop for metastability
Enables double flop for metastability
Enables double flop for metastability
Enables DLDown Reset all ioc shadowed pcie registers
Enabling this bit will put All Type0NonDev0 external cfg
request to SB
Enables AMD generalized stutter mode
Enables BMREQ Pin
PCIE_NBCFG_REG0 - RW - 32 bits - NBMISCIND:0x32
Field Name
STRAP_BIF_SYMALIGN_DIS_ELIDLE_G
FX
spare_1
STRAP_BIF_SYMALIGN_MODE_GFX
spare_3
STRAP_BIF_ELAST_WATERMARK_GF
X
STRAP_BIF_FORCE_COMPLIANCE_GF
X
STRAP_BIF_BYPASS_SCRAMBLER_GF
X
B_P90RX_INCAL_FEN
spare_10
B_PRX_EN_FEN_GPP
STRAP_BIF_SKIP_INTERVAL_GFX
STRAP_BIF_SKIP_INTERVAL_GPPSB
STRAP_BIF_EXIT_LATENCY_GFX
STRAP_BIF_EXIT_LATENCY_GPPSB
STRAP_BIF_REVERSE_LC_LANES_GP
PSB
PCIE_NBCFG register 0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
Default
0x1
1
2
3
5:4
0x0
0x1
0x0
0x0
7:6
0x0
8
0x0
9
10
11
14:12
17:15
21:18
25:22
31:26
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-11
PCIE_NBCFG_REG3 - RW - 32 bits - NBMISCIND:0x33
Field Name
STRAP_BIF_REVERSE_LC_LANES_GF
X
STRAP_BIF_REVERSE_LANES_GFX
STRAP_BIF_REVERSE_LANES_GPPSB
STRAP_BIF_REVERSE_ALL_GFX
STRAP_BIF_FTS_yTSx_COUNT_GFX
STRAP_BIF_FTS_yTSx_COUNT_GPP
STRAP_BIF_SHORT_yTSx_COUNT_GF
X
STRAP_BIF_SHORT_yTSx_COUNT_GP
P
STRAP_BIF_MED_yTSx_COUNT_GFX
STRAP_BIF_MED_yTSx_COUNT_GPP
STRAP_BIF_LONG_yTSx_COUNT_GFX
STRAP_BIF_LONG_yTSx_COUNT_GPP
STRAP_BIF_BYPASS_RCVR_DET_GFX
STRAP_BIF_BYPASS_RCVR_DET_GPP
STRAP_BIF_COMPLIANCE_DIS_GFX
STRAP_BIF_COMPLIANCE_DIS_GPP
STRAP_BIF_AER_EN_GFX
PCIE_NBCFG register 3
Bits
1:0
Default
0x0
3:2
9:4
10
12:11
14:13
16:15
0x0
0x0
0x0
0x0
0x0
0x0
18:17
0x0
20:19
22:21
24:23
26:25
27
28
29
30
31
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
PCIE_NBCFG_REG4 - RW - 32 bits - NBMISCIND:0x34
Field Name
STRAP_BIF_AER_EN_GPP
STRAP_BIF_PHY_RCVRDET_3NF_GFX
B_P90PLL_RESET_GFX
B_P90PLL_CLKR_GFX
B_P90RX_INCAL_EN_GFX
B_PRX_ARESET
iPCIE_DISP_FIFO_Clock_DISABLE_GFX
B_P90PLL_IBIAS_RD_GFX
B_P90RX_INCAL_FORCE_GFX
B_P90RX_CRFR_GFX
B_P90RX_CRPHSIZE_GFX
B_P90RX_CRFR_ON_GFX
spare_20
spare_21
B_P90RX_CLKG_EN_GFX
B_PTX_PWRS_ENB_GFX
B_PTX_DEEMPH_EN_GFX
STRAP_BIF_ERR_REPORTING_DIS_GF
X
STRAP_BIF_ERR_REPORTING_DIS_G
PPSB
B_P90TX_CLKG_EN_GFX
B_P90PLL_IBIAS_SEL_GFX
B_PRX_DET_BLOCK_GFX
B_PRX_DET_BLOCK_GPPSB
spare_31
PCIE_NBCFG register 4
Bits
0
1
2
4:3
5
6
7
9:8
10
16:11
18:17
19
20
21
22
23
24
25
Default
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x2
0x1
0x0
0x0
0x1
0x1
0x1
0x1
26
0x1
27
28
29
30
31
0x1
0x1
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-12
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCIE_NBCFG_REG5 - RW - 32 bits - NBMISCIND:0x35
Field Name
STRAP_BIF_ECN1P1_EN_GFX
STRAP_BIF_ECN1P1_EN_GPPSB
B_P90TX_DRV_STR_GFX
NonD0MA_GPPSB
NonD0MA_GFX
Reg_Turn_Off_Both_PLLs
spare_10_8
B_P90RX_CRFRSIZE_GFX
spare_13
B_P90PLL_CLKF_GFX
B_P90RX_INCAL_GFX
spare_31_29
PCIE_NBCFG register 5
Bits
0
1
3:2
4
5
7:6
10:8
12:11
13
20:14
28:21
31:29
Default
0x1
0x1
0x1
0x0
0x0
0x2
0x0
0x1
0x0
0x7
0x0
0x0
Description
PCIE_NBCFG_REG6 - RW - 32 bits - NBMISCIND:0x36
Field Name
B_P90PLL_ENSAT_GFX
B_P90PLL_ENSAT_GPPSB
spare_3_2
B_P90PLL_IBIAS_GFX
B_P90RX_CRCTRL_GFX
B_P90RX_CRCTRL_BPASS_GFX
B_P90PLL_RESET_EN_GFX
B_P90PLL_TEST_GFX
STRAP_BIF_STAGGER_CNTL_GFX
STRAP_BIF_STAGGER_CNTL_GPPSB
spare_29_28
REG_RXCLK_RESET_2
REG_RXCLK_RESET_3
PCIE_NBCFG register 6
Bits
0
1
3:2
13:4
20:14
21
22
23
25:24
27:26
29:28
30
31
Default
0x1
0x1
0x0
0xa
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
PCIE_NBCFG_REG7 - RW - 32 bits - NBMISCIND:0x37
Field Name
PCIE_MUX_SEL0_GFX
PCIE_MUX_SEL1_GFX
PCIE_MUX_SEL2_GFX
PCIE_MUX_SEL3_GFX
PCIE_MUX_SEL_LEVEL2_GFX
PCIE_lane_reversal_GFX
STRAP_BIF_2VC_EN_GPPSB
reconfig_gppsb_en_GPPSB
reconfig_gppsb_reg_idle_force_en_GPPS
B
reconfig_gppsb_GPPSB
reconfig_gppsb_link_config_xfer_mode_G
PPSB
reconfig_gppsb_use_link_up_en_GPPSB
reconfig_gppsb_atomic_reset_dis_GPPS
B
spare_31_18
PCIE_NBCFG register 7
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
1:0
3:2
5:4
7:6
9:8
10
11
12
13
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
14
15
0x0
0x0
16
17
0x0
0x0
31:18
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-13
PCIE_NBCFG_REG8 - RW - 32 bits - NBMISCIND:0x38
Field Name
PCIE_Reserved
PCIE_NBCFG register 8
Field Name
PCIE_STRAP_REG_Reserved
Bits
31:0
Default
0x0
Description
PCIE_STRAP_REG2 - RW - 32 bits - NBMISCIND:0x39
Bits
31:0
Default
0x0
Description
NB_FDHC - RW - 8 bits - nbconfig:0x68
Field Name
MEM_HOLE_ENABLE
Bits
Default
7:6
0x0
Description
Hole Enable.
00=No hole
01=Hole at 512KB - 640KB
10=Hole at 15MB - 16MB
11=Reserved
0=No hole
1=Hole at 512KB - 640KB
2=Hole at 15MB - 16MB
3=Reserved
Fixed SDRAM Hole Control required for Slot-1 operation.
NB_SMRAM - RW - 8 bits - nbconfig:0x69
Field Name
SMM_LOCATION
Bits
2:0
Default
0x2
Description
0x2: SMM space at 640KB-768KB. Any other encoding
disables this area.
GLOBAL_SMRAM_ENABLE
3
0x0
SMM Space globally enabled.
Once the SMM_SPACE_LOCKED bit is set, this cannot be
changed until after reset.
0=Disable
1=Enable
SMM_SPACE_LOCKED
4
0x0
SMM Space Locked
If set, SMM_LOCATION cannot be changed until after
reset. It can only be written to once.
0=Unlocked
1=Locked
SMM_SPACE_OPEN
6:5
0x0
SMM Space Opened/Closed
Once the SMM_SPACE_LOCKED bit is set, bit 6 cannot be
changed until after reset.
0=Open for CPU transactions to SMM memory.
1=Closed
2=Open
3=Reserved
System Management RAM configuration. This Register is only used in Slot-1 interface mode.
AMD RS690 ASIC Family Register Reference Manual
2-14
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_EXSMRAM - RW - 8 bits - nbconfig:0x6A
Field Name
TSEG_ENABLE
Bits
0
Default
0x0
Description
Enables TSEG space.
Two possible locations (based on HI_SMRAM_ENABLE)
(TOM-TSEG_SIZE) - TOM or
(256MB+TOM-TSEG_SIZE) - (256MB+TOM)
0=Disable
1=Enable
TSEG_SIZE
2:1
0x0
0=2MB
1=8MB
2=512KB
3=1MB
Reserved0
5
0x1
Reserved for future use.
EX_SMRAM_ERROR
6
0x0
This bit is set if an access is attempted while the extended
SMM area is disabled
HI_SMRAM_ENABLE
7
0x0
Enable high SMM/TSEG space.
For SMM: (256MB+640KB) - (256MB+1MB). Maps to
(640KB - 1MB).
For TSEG: (256MB+TOM-TSEG_SIZE) - (256MB+TOM).
Maps to (TOM-TSEG_SIZE) - TOM.
0=Disable
1=Enable
Extended System Management RAM control register. This register controls access to the extended SMM range in system
memory. It is only used in Slot-1 interface mode.
NB_PMCR - RW - 8 bits - nbconfig:0x6B
Field Name
ACPI_CTL_REG_EN (R)
Bits
Default
0
0x0
Description
Always forced to 0.
0=Disable
1=Enable
Power Management Control
NB_STRAP_READ_BACK - R - 32 bits - nbconfig:0x6C
Bits
0
3
Default
0x0
0x0
HDCP_KEY_VALID
4
0x0
AUDIO_DISABLE
5
0x0
MOBILE_GFX
6
0x0
DEVICE_ID
INTGFX_EN
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Hardware Configuration Bit. Indicates Device ID.
Hardware Configuration Bit. Indicates that Internal Graphics
has been enabled.
0=Disable
1=Enable
Hardware Configuration Bit. Indicates that HDMI - HDCP
keys have been programmed into the e-fuses.
0=not programmed
1=programmed
Hardware Configuration Bit. Indicates that High Resolution
Audio is not available.
0=Enable
1=Disable
Hardware Configuration Bit. Indicates that the NB is a
Mobile Part. This will affect the GFX controller Device ID.
AMD RS690 ASIC Family Register Reference Manual
2-15
iSTRAP_SIDE_PORT_ENb
7
0x0
STRAP_SMS_BYPASS
8
0x0
STRAP_DEBUG_BUS_EN
9
0x0
LOAD_EEPROM_STRAPS
10
0x0
STRAP_PCIE_GPP_MODE
13:11
0x0
EFUSE_CF_DISABLE
14
0x0
DISABLE_EFUSE_PGM
15
0x0
STRAP_FASTBOOT_L
16
0x0
This is Pin Strap GPIO[0]. Indicates that the Side Port
Memory has been enabled.
0=Enable
1=Disable
This is an EEPROM Strap. Indicates that SMS bypass has
been selected.
This is Pin Strap GPIO[5]. Indicates that the Debug Bus has
been enabled by pin strap GPIO[5]
0=Disable
1=Enable
This is Pin Strap GPIO[1]. Indicates that EEPROM based
straps for NB has been selected.
0=Disable
1=Enable
This is Pin Strap GPIO[4:2]. Indicates PCIe GPP mode of
operation.
0=Use register value
1=Use register value
2=4-1-1-1-1
3=4-2-1-1
4=4-2-2
5=4-4
6=4-0-0-0-0
7=Use register value
Hardware Configuration Bit. Indicates that CrossFire mode
of operation is not allowed.
0=Enable
1=Disable
Hardware Configuration Bit. Indicates that the e-fuse
programming is disabled.
0=Disable
1=Enable
Hardware Configuration Bit from JTAG. When LOW,
indicates shorten reset timers for testing purposes.
0=Short Timers for Production Test
1=Normal Operation
RS690 Strap Read Back Register
SCRATCH_NBCFG - RW - 32 bits - nbconfig:0x78
Field Name
SCRATCH
Bits
Default
Description
31:0
0x0
All of the bits in this register can be both written to, and read
from, but the register does not control anything.
This register is used for scratch reading and writing.
SCRATCH_1_NBCFG - RW - 32 bits - nbconfig:0x54
Field Name
SCRATCH_1
Bits
Default
31:0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-16
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
SCRATCH_2_NBCFG - RW - 32 bits - nbconfig:0x98
Field Name
SCRATCH_2
Bits
Default
31:0
0x0
Description
NB_HT_TRANS_COMP_CNTL - RW - 32 bits - nbconfig:0x94
Field Name
TXP_COMPDATA
Bits
4:0
Default
0x5
TXP_CTL
6:5
0x0
TXP_CALCCOMP (R)
RESERVED_15_13
12:8
15:13
0x5
0x0
TXN_COMPDATA
TXN_CTL
20:16
22:21
0x4
0x0
TXT_CALCCOMP (R)
28:24
0x4
RESERVED_31to29
HT transmitter comp control
31:29
0x0
Description
Calculates the compensation value for the transmitter falling
edge
Transmitter falling edge PHY control value
00=Apply TXP_CALCCOMP directly
01=Apply TXP_COMPDATA directly
10=Apply the sum of TXP_CALCCOMP and
TXP_COMPDATA
11=Apply the diff of TXP_CALCCOMP and
TXP_COMPDATA
Transmitter falling edge compensation circuitry data value
Bit [15]=CfgHTiu_HT_EMP_EN_TST
Bit [14]=CfgHTiu_HT_TX_COMPOVR
Bit [13]=CfgHTiu_HT_TX_FCOMPCYC
Transmitter falling edge compensation circuitry data value
Transmitter falling edge PHY control value
00=Apply TXN_CALCCOMP directly
01=Apply TXN_COMPDATA directly
10=Apply the sum of TXN_CALCCOMP and
TXN_COMPDATA
11=Apply the diff of TXN_CALCCOMP and
TXN_COMPDATA
Calculates the compensation value for the transmitter falling
edge
NB_HT_CLK_CNTL_RECEIVER_COMP_CNTL - RW - 32 bits - nbconfig:0x80
Field Name
RX_COMPDATA
RX_CTL
RESERVED_7
RX_CALCCOMP (R)
RESERVED_14_13
SUCU
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
4:0
6:5
Default
0x9
0x0
7
12:8
14:13
0x0
0x9
0x0
15
0x0
Description
Transmitter rising edge compensation circuitry data value
Receiver rising edge PHY control value
00=Apply RX_CALCOMP directly as the compensation
01=Apply RX_COMPDATA directly as the compensation
10=Apply the sum of RX_CALCOMP and
RX_COMPDATA
11=Apply the diff of RX_CALCOMP and RX_COMPDATA
Calculated compensation value for the receiver
Bit [14]=CfgHTiu_HT_RX_COMPOVR
Bit [13]=CfgHTiu_HT_RX_FCOMPCYC
Speeda up the compensation update
0=Link PHY compensation values are allowed to changed
every 1ms
1=Link PHY compensation values are allowed to changed
every 1us
AMD RS690 ASIC Family Register Reference Manual
2-17
ICGSMAF
23:16
0x0
REVERVED_25to24 (R)
RESERVED_29to26
SULS
25:24
29:26
30
0x0
0x0
0x0
31
0x0
CGEN
Internal clock gating system management
0=No power reduction
1=IC power is reduced through gatind of internal clocks
Speeds up the connection sequence for frequency change
0=PLL lock timer is 100 us
1=PLL lock timer is 1us
Enables clock gating
0=Internal clock gating is disabled
1=Internal clock gating is enabled
NB_HT_LINK_COMMAND - RW - 32 bits - nbconfig:0xC4
CAP_ID (R)
NEXT_PTR
Field Name
Bits
7:0
15:8
Default
0x8
0x0
BASE_UNIT_ID
20:16
0x0
UNIT_ID_COUNT (R)
MASTER_HOST (R)
DEFAULT_DIRECTION (R)
DROP_ON_UNINIT_LINK
SLAVE_PRIMARY_TYPE (R)
HT Link command
25:21
26
27
28
31:29
0xc
0x0
0x0
0x0
0x0
Description
Specifies the capability ID for the link configuration space
Read only register pointing to the next item in the capability
list
Specifies the link protocol base Unit ID. Relocating the base
Unit ID is not supported
Specifies the number of Unit IDs used by the chip
Should always be set to 0
Should always be set to 0
Should always be set to 0
Read only
NB_HT_LINK_CONF_CNTL - RW - 32 bits - nbconfig:0xC8
Field Name
CRC_FLOOD_ENABLE
Bits
1
Default
0x0
CRC_ERROR_COMMAND
3
0x0
LINK_FAILURE
4
0x0
INIT_COMPLETE
5
0x0
END_OF_CHAIN (R)
6
0x1
TRANSMITTER_OFF
7
0x0
9:8
0x0
CRC_ERROR_DETECTED
AMD RS690 ASIC Family Register Reference Manual
2-18
Description
Flood enable
0=CRC errors do not result in a sync flood
1=CRC errors result in a sync flood
CRC error command
0=Transmitter CRC value match the values calculated per
the link specification
1=The link tranmission logic generates erroneous CRC
value
This bit is set when a CRC error is detected. It is cleared by
PWROK
This bit is set when low level link initialization has
successfully completed. If the device on the other side is
unable to properly perform link initilization, then the bit is not
set.
Read write 1 only
1=Fix to 1
Read-write 1 only
1=No output signals on the link toggle. The input link
receivers are disabled and pins may float
Read. Set by hardware. Bit [9] applies to upper byte of the
link, and bit [8] applies to the lower byte. When this bit is
one, the hardware has detected a CRC error on the
incoming link. It is cleared by PWROK
© 2007 Advanced Micro Devices, Inc.
Proprietary
LDT3S_ENABLE
13
0x0
EXTENDED_CNTL_TIME
14
0x0
MAX_LINK_WIDTH_IN (R)
18:16
0x1
MAX_LINK_WIDTH_OUT (R)
22:20
0x1
LINK_WIDTH_IN
26:24
0x0
LINK_WIDTH_OUT
30:28
0x0
HT link configuration control
Link three state enable
0=During disconnect sequence. The link transmitter is
driven but in underfined state
1=During disconnect sequence. The link transmitter is
placed into high impedance state. It is cleared by
PWROK
Specifies the time in which the control is held
0=At least 16 bit time
1=About 50 microseconds. It is cleared by PWROK
Specifies the operating width of the incoming to be 16 bits
for side A
Specifies the operating width of the outgoing to be 16 bits
for side A
Specifies the operating of the input width
000=8 bits
001=16 bits
100=2 bits
101=4 bits
111=Not connect. It is cleared by PWROK
Specifies the operating of the output width
000=8 bits
001=16 bits
100=2 bits
101=4 bits
111=Not connected. It is cleared by PWROK
NB_HT_LINK_END - R - 32 bits - nbconfig:0xCC
Field Name
LINK_FAILURE
END_OF_CHAIN
TRANSMITTER_OFF
RESERVED_8_31
Bits
4
6
7
31:8
Default
0x1
0x1
0x1
0x0
Description
Device implement one link in the chain. Hardwired to 1
Device implement one link in the chain. Hardwired to 1
Device implement one link in the chain. Hardwired to 1
NB_HT_LINK_FREQ_CAP_A - RW - 32 bits - nbconfig:0xD0
Field Name
MINOR_REVISION (R)
MAJOR_REVISION (R)
LINK_FREQUENCY_A
Bits
4:0
7:5
11:8
Default
0x5
0x1
0x0
LINK_FREQ_CAP_A
31:16
0x65
HT link frequency channel A
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Specifies the link side A frequency
0h=200Mhz
2h=400Mhz
5h=800Mhz
6h=1000MHz. Cleared by PWROK
Other selection (that are not shown) are reserved
Indicates that A side of channel supports 200, 400, 800,
and 1000 Mhz link frequency
AMD RS690 ASIC Family Register Reference Manual
2-19
NB_HT_LINK_FREQ_CAP_B - R - 32 bits - nbconfig:0xD4
Field Name
LINK_DEVICE_FEATURE_CAP
Bits
7:0
Default
0x2
RESERVED
31:8
0x0
Description
Indicates which optional features are supported by the
device
NB_HT_MEMORY_BASE_UPPER - RW - 32 bits - nbconfig:0xDC
Field Name
MEMORY_BASE_UPPER_8BIT
MEMORY_LIMIT_UPPER_8BIT
BUS_NUMBER (R)
Bits
7:0
15:8
23:16
Default
0x0
0x0
0x0
Description
NB_PCI_ARB - RW - 32 bits - nbconfig:0x84
Field Name
RCRB_ENABLE
Bits
0
Default
0x0
PM2_SB_ENABLE
2
0x0
EV6MODE
4
0x0
_14M_HOLE
5
0x0
_15M_HOLE
6
0x0
PM_REG_ENABLE
7
0x0
AMD RS690 ASIC Family Register Reference Manual
2-20
Description
Enables RCRB memory mapped cfg access through BAR1
0=Disable
1=Enable
Enables PM2_CNTL(BAR2) IO mapped cfg write access to
be broadcast to both NB and SB.
0=Disable
1=Enable
EV6 Mode:
Indicates that the PCI interfaces have to decode memory
range from 640K to 1M.
0=Enable
1=Disable
14M Memory Hole:
Creates a hole in memory from 14 Mb to 15 Mb. This
register is used by the PCI decode logic to know when to
accept a cycle from an external PCI master. When set, the
PCI decode logic does not assert a match for addresses
falling in this range.
0=Disable
1=Enable
15M Memory Hole:
Creates a hole in memory from 15 Mb to 16 Mb. This
register is used by the PCI decode logic to know when to
accept a cycle from an external PCI master. When set, the
PCI decode logic does not assert a match for addresses
falling in this range.
0=Disable
1=Enable
Power Management Register Enable:
Enables BAR2 IO access decoding.
0=Disable
1=Enable
© 2007 Advanced Micro Devices, Inc.
Proprietary
PMEMode
8
0x0
PMETurnOff
9
0x0
READ_DATA_ERROR_DISABLE
12
0x0
MDA_DEBUG
15
0x0
BAR3BusRange
18:16
0x0
AGP_VGA_BIOS
31:24
0x3
PME message mode:
0 means PME_Turn_Off is triggered by STP_GNT(S3)
request from BIU.
1 means PME_Turn_Off is triggered by writing 1 to
PMETurnOff bit(0x84[9]).
0=Disable
1=Enable
PME_Turn_Off message trigger:
In case PMEMode is set, write 1 to this bit will trigger a
PME_Turn_Off messages to all downstream devices. This
bit is reset only then the system power is off.
0=Disable
1=Enable
Not used in the RS690.
0=Enable
1=Disable
MDA Debug:
This bit allows monochrome display adapters (MDA) to be
used simultaneously with AGP cards for debug of AGP
device drivers. The behavior of RS690 display adapters is a
function of this bit and the VGA Enable in (D1:0x3C[19]) as
follows:
MDA Address Ranges:
Memory: 0B0000h-0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh
VGA=0, MDA=0: All MDA and VGA references go to PCI
VGA=0, MDA=1: Operation undefined
VGA=1, MDA=0: All VGA references go to AGP, MDA only
(I/O 3BFh) go to PCI
VGA=1, MDA=1: All VGA references go to AGP, All MDA
(including memory) go to PCI
0=Disable
1=Enable
0 means BAR3[27:20] are all used for bus number decoding
so BAR3 memory map range is [39:28]
1 means BAR3[20] is used for bus number decoding so
memory map range is [39:21]
2 means BAR3[21:20] are used for bus number decoding
so memory map range is [39:22]
3 means BAR3[22:20] are used for bus number decoding
so memory range is [39:23]
...
7 means [26:20] are used for bus number decoding so
memory map range is [39:27]
0=Disable
1=Enable
AGP VGA BIOS:
Indicates that the corresponding (16K) segment should be
mapped to AGP's PCI bus. Bit 24 corresponds to the
addresses 0xC0000-0xC3FFF and bit 31 maps addresses
0xDC000-0xDFFFF to AGP's PCI interface. One or more of
these bits should be set if the AGP graphics card has a
ROM BIOS.
This register provides general PCI arbiter mode control
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-21
NB_GC_STRAPS - RW - 32 bits - nbconfig:0x8C
Field Name
EXTGFX_ENABLE
Bits
0
Default
0x1
INTGFX_ENABLE (R)
1
0x1
VGA_DISABLE
2
0x0
ID_DISABLE
3
0x0
6:4
0x3
F1_MULTI_FUNC_ENABLE
F2_MULTI_FUNC_ENABLE
GFX_DEBUG_BAR_ENABLE
GFX_DEBUG_DECODE_ENABLE
ENINTb
VE (R)
EXT_MEM_EN
BLANK_ROM
POWER_ON_STRAPS
MOBILE (R)
7
8
9
10
11
12
13
14
27:16
28
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
CHG_ID (R)
Graphics Controller strap access register
31:29
0x0
APERTURE_SIZE
Description
External Graphic optimization Enable.
1=HTiu external graphic optimization supported
0=HTiu external graphic optimization disable
0=Disable
1=Enable
This bit is read only and it is the value of the e-fuse HW
config bit.
0=The internal graphics logic is disabled
1=The internal graphics logic is enabled.
0=Enable
1=Disable
0=Enable
1=Disable
0=128MB
1=256MB
2=64MB
3=32MB
4=512MB
5=1GB
6=Reserved
7=Reserved
Extra strapping signals
This is the value of the pin strap on the DAC_VSYNC pin
during strap capture. The strap name is
STRAP_MOBILE_GFX. This pinstrap changes the Device
ID of the Internal Graphics Device and allows C3
functionality (STP_AGP#/AGP_BUSY#).
When Pinstrap is 1, it selects the mobile graphics device ID.
When Pinstrap is 0, it selects the desktop graphics device
ID.
CHANGE_ID from nb_efuse.
NB_TOP_OF_DRAM_SLOT1 - RW - 32 bits - nbconfig:0x90
Field Name
TOP_OF_DRAM
Bits
31:23
Default
0x0
Description
PCI Memory Top:
This 8-bit field is compared to the incoming PCI Bus master
address to determine if a memory cycle falls within the
RS690's DRAM region. The BIOS should write to this field
following the completion of the memory sizing algorithm,
after it has determined the total size of the installed
memory.
This register is used to define the top of main system memory. It is used to compare the memory addresses of an external PCI
master to determine if it is in the range of the RS690's system DRAM. If the address compares then the RS690 will respond to
the bus master access by asserting DEVSEL#.
AMD RS690 ASIC Family Register Reference Manual
2-22
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_AGP_ADDRESS_SPACE_SIZE - RW - 32 bits - nbconfig:0xF8
Description
GART Enable.
When clear, GART is not valid in this system. The SBIOS
will not allocate virtual address space for GART because
the Host-PCI Bridge (Device 0) AGP Virtual Address Space
(BAR1), offset 0x10, will be internally forced to 0. This bit
must be set by the BIOS PCI enumeration routines. When
set, GART is valid in this system. The SBIOS allocates
virtual address space for GART based upon the value in
bits [3:1] above.
0=Disable
1=Enable
VA_SIZE
3:1
0x0
Virtual Address Size.
This field defines the virtual address space size to be
allocated to GART by the SBIOS. Prior to the execution of
the SBIOS memory mapping software, the SBIOS gets the
amount of GART virtual address space required by the
graphics controller. It sets these bits to the required value.
Changing these bits automatically changes bits [30:25] in
the Host-PCI Bridge (Device0) AGP Virtual Address Space
Register (BAR1), offset 0x10. The size of GART virtual
address space is always greater than, or equal to, the
amount of physical system memory allocated to AGP in
non-contiguous 4KB blocks. The amount of physical
memory allocated to AGP is determined by the operating
system software.
[3] [2] [1] VA_Size
0 0 0 32 MB
0 0 1 64 MB
0 1 0 128 MB
0 1 1 256 MB
1 0 0 512 MB
1 0 1 1 Gig
1 1 0 2 Gig
1 1 1 Undefined
VGA_IA_EN
16
0x0
0=Disable
1=Enable
This register controls the size of the AGP aperture allocated by the BIOS, the GART functionality and the granularity of VGA
address decoding.
GART_EN
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-23
NB_AGP_MODE_CONTROL - RW - 32 bits - nbconfig:0xFC
Bits
Default
Description
POST_GART_Q_SIZE
Field Name
18
0x0
Post GART Queue Size.
When set, this bit forces the post GART queue structures to
implement half the entry depth (for debug/performance
analysis).
0=8 Entries
1=4 Entries
NONGART_SNOOP
19
0x0
Non GART Snoop.
When set, this bit forces AGP accesses that are not in the
GART range to cause system bus probes to the
processor(s). When clear, AGP addresses that fall outside
of the GART range do not cause probes.
0=Disable
1=Enable
AGP_RD_BUF_SIZE
20
0x0
AGP Read Buffer Size.
When clear, the AGP read buffer contains 64 QWs of
storage. When set, the AGP read buffer contains 32 QWs of
storage (for debug/performance analysis).
0=64 QW
1=32 QW
This register controls specific features of the RS690's AGP implementation.
NB_PCIE_INDX_ADDR - RW - 32 bits - nbconfig:0xE0
Bits
Default
NB_PCIE_INDX_ADDR
Field Name
7:0
0x0
Index register for the PCI Express common indirect
registers
Description
GFX_GPPSB_SEL
16
0x0
Select the PCIE core whose common indirect space is to be
accessed.
0=External GFX PCIE core
1=General Purpose Port and southbridge PCIE core
Index register for the PCI Express common indirect registers.
NB_PCIE_INDX_DATA - RW - 32 bits - nbconfig:0xE4
Field Name
NB_PCIE_INDX_DATA
Bits
Default
Description
31:0
0x0
Data register for the PCI Express common indirect registers
Data Register used for the PCI Express common indirect registers.
NB_MC_INDEX - RW - 32 bits - nbconfig:0xE8
Field Name
NB_MC_IND_ADDR
NB_MC_IND_WR_EN
Bits
Default
8:0
0x0
9
0x0
Description
0=Disable writes to NB_MC_DATA
1=Enable writes to NB_MC_DATA
Memory controller index register address.
AMD RS690 ASIC Family Register Reference Manual
2-24
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_MC_DATA - RW - 32 bits - nbconfig:0xEC
Field Name
NB_MC_DATA
Bits
Default
31:0
0x0
Description
Memory controller index register data.
NB_CFG_Q_F1000_800 - RW - 8 bits - nbconfig:0x9C
Field Name
CFG_Q_F1000_800
Bits
0
Default
0x0
spare_1
1
0x0
F1000_800_en
2
0x0
7:3
0x0
spare_7_3
Description
Set this bit, and 0x6 in LINK_FREQUENCY_A, to enable
1GHz mode during the next link frequency/width switch
0=Disable
1=Enable
Spare bit. Presently not used
0=Disable
1=Enable
0=Disable
1=Enable
Spare bit. Presently not used
0=Disable
1=Enable
Control bit
PCIE_PDNB_CNTL - RW - 32 bits - NBMISCIND:0x7
Field Name
ENABLE_CLKGATE_GFX_TXCLK
ENABLE_CLKGATE_GFX_TXCLK_L0S
ENABLE_CLKGATE_GFX_TXCLK_SND_
RCV
GFX_PERM2_TXCLK_STOP
ENABLE_CLKGATE_GPPSB_TXCLK
ENABLE_CLKGATE_GPPSB_TXCLK_L0
S
ENABLE_CLKGATE_GPPSB_TXCLK_S
ND_RCV
GPPSB_PERM2_TXCLK_STOP
GFX_TXCLK_SND_RCV_0_SEL
spare_9
GFX_TXCLK_SND_RCV_1_SEL
spare_11
GFX_TXCLK_SND_RCV_2_SEL
spare_13
GFX_TXCLK_SND_RCV_3_SEL
spare_15
GFX_TXCLK_SEL
spare_17
GPPSB_PDNB_DLY_SEL_GPPSB
GFX_PDNB_DLY_SEL_GPPSB
ALL_ELEC_IDLE_GPPSB
ENABLE_PLL_LOCK_TIME_GPPSB
IO_TXCLK0_CNTL
ALL_ELEC_IDLE_GFX
IO_TXCLK1_CNTL
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
1
2
Default
0x0
0x0
0x0
3
4
5
0x0
0x0
0x0
6
0x0
7
8
9
10
11
12
13
14
15
16
17
19:18
21:20
22
23
24
25
26
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-25
spare_27
IO_TXCLK2_CNTL
spare_29
IO_TXCLK3_CNTL
spare_31
PCIE control register
27
28
29
30
31
0x0
0x0
0x0
0x0
0x0
HTIU_NB_INDEX - RW - 32 bits - nbconfig:0xA8
Field Name
HTIU_NB_IND_ADDR
HTIU_NB_IND_WR_EN
Bits
6:0
8
Default
0x0
0x0
Description
0=Disable writes to HTIU_NB_DATA
1=Enable writing to HTIU_NB_DATA
HTIU_NB_DATA - RW - 32 bits - nbconfig:0xAC
Field Name
HTIU_NB_DATA
Bits
31:0
Default
0x0
Description
NB_BAR1_RCRB - RW - 32 bits - nbconfig:0x14
MEM_IO (R)
Field Name
TYPE (R)
Bits
0
Default
0x0
2:1
0x0
3
0x0
31:12
0x0
PREFETCH_EN (R)
RCRB_BASE
Description
Memory:
This bit is hardwired to 0 to indicate that this base address
register maps into memory space
0=Memory
1=I/O
Type:
This bit field is hardwired to indicate that this base register
is 32 bits wide and mapping can be performed anywhere in
the 32-bit address space
Unprefetchable:
This bit is hardwired to 0 to indicate that this range is
un-prefetchable
Base Address High[31:12]
This filed is used to define a 4K memory mapped root
complex register block
Descriptor for memory mapped RCRB registers
NB_ECC_CTRL - R - 32 bits - nbconfig:0x48
Field Name
NOT_IMPLEMENTED
Bits
31:0
Default
0x0
Description
The RS690 will not support ECC for system memory
accesses.
Northbridge ECC Control Register
AMD RS690 ASIC Family Register Reference Manual
2-26
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_IOC_DEBUG - RW - 32 bits - NBMISCIND:0x1
Field Name
SLI_OVERWRITE_EN
NB_IOC_DEBUG_RW
IOC_MultiReqVldErr (R)
IOC_MemMapCfgErr (R)
NB_IOC_DEBUG_RO (R)
IOC Debugging purpose registers
Bits
0
Default
0x0
15:1
16
17
31:18
0x0
0x0
0x0
0x0
Description
1=Overwrite SLI strap inputs (enable dev3 p2p bridge
access)
0=Takes SLI inputs to control dev3 bridge access.
Note: dev3 access is also controlled by
IOC_P2P_CNTL:Dev3BridgeDis(nbmiscind0x0C). If only
IOC_P2P_CNTL:Dev3BridgeDis is 0, access to dev3 bridge
is possible.
Spare Read/Write Control Bits
Detect Multiple CPU Downstream Request Valid Error
Detect Memory Map Cfg Access Format Error
Spare Read Only Status Bits
DFT_CNTL0 - RW - 32 bits - NBMISCIND:0x5
Field Name
TEST_DEBUG_EN
TEST_DEBUG_OUT_EN
TEST_DEBUG_IDSEL
TEST_DEBUG_MUX
GPIO_DEBUG_BUS_MUX_SEL0
GPIO_DEBUG_BUS_MUX_SEL1
GPIO_DEBUG_BUS_MUX_SEL2
GPIO_DEBUG_BUS_MUX_SEL3
DFT control 0 register
Bits
0
3:1
9:4
15:10
19:16
23:20
27:24
31:28
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x2
0x3
Description
DFT_CNTL1 - RW - 32 bits - NBMISCIND:0x6
Field Name
TEST_DEBUG_COUNTER_EN
TEST_DEBUG_IN_EN
DEBUG_TESTCLKIN
TEST_CLK0_INV
DFT_MISC
COM_PORT_OE
COM_PORT_OUT
COM_PORT_IN (R)
DFT control 1 register
Bits
0
1
2
3
15:4
17:16
19:18
21:20
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
IOCIsocMapAddr_LO - RW - 32 bits - NBMISCIND:0xE
Field Name
IsocMapAdd_LO
isoc channel address mapping
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:6
Default
0x0
Description
If the dma isoc address is invalid, it maps to this pre-defined
address.
AMD RS690 ASIC Family Register Reference Manual
2-27
IOCIsocMapAddr_HI - RW - 32 bits - NBMISCIND:0xF
Field Name
IsocMapAdd_HI
Bits
7:0
Default
0x0
isoc channel address mapping
Description
If the dma isoc address is invalid, it maps to this pre-defined
address
DFT_CNTL2 - R - 32 bits - NBMISCIND:0x10
Field Name
TEST_DEBUG_READBACK
DFT control 2 register
Bits
15:0
Default
0x0
Description
NB_TOM_PCI - RW - 32 bits - NBMISCIND:0x16
Field Name
SAME_AS_TOM_BIU
TOM_FOR_PCI
TOM for PCI
Bits
0
31:16
Default
0x1
0x0
Description
TOM of PCI equals TOM of BIU if this bit is 1
TOM for PCI
NB_MMIOBASE - RW - 32 bits - NBMISCIND:0x17
Field Name
MMIOBASE
Bits
31:8
Default
0x0
Lower MMIO base
Description
Register bits [31:8] define MMIOBASE [39:16], which is the
MMIO base address.
NB_MMIOLIMIT - RW - 32 bits - NBMISCIND:0x18
Field Name
MMIOLIMIT
Bits
31:8
Default
0x0
High MMIO base
Description
Register bits [31:8] define MMIOLIMIT [39:16], which is the
MMIO LIMIT address.
NB_INTERRUPT_PIN - RW - 32 bits - NBMISCIND:0x1F
Field Name
REG_AP_SIZE
Bits
1:0
Default
0x1
GFX_INTERRUPT_PIN
2
0x0
F2_INTERRUPT_PIN
3
0x0
Description
Sets the size of the core graphics memory mapped register
aperture
11=256K
10=128K
01=64k
00=32K
0=Set the graphics interrupt pin to INTA#
1=Set the graphics interrupt pint to INTB#
0=Set the F2 interrupt pin to INTA#
1=Set the F2 interrupt pint to INTB#
INTERRUPT register
AMD RS690 ASIC Family Register Reference Manual
2-28
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_PROG_DEVICE_REMAP_0 - RW - 32 bits - NBMISCIND:0x20
Field Name
NB_PROG_DEVMAP_EN
IOC_PCIE_Dev_Remap_Dis
GPP_PORTB_DEVMAP
GPP_PORTC_DEVMAP
GPP_PORTD_DEVMAP
GPP_PORTE_DEVMAP
Bits
0
1
7:4
11:8
15:12
19:16
Default
0x0
0x1
0x0
0x0
0x0
0x0
Description
IOC_LAT_PERF_CNTR_CNTL - RW - 32 bits - NBMISCIND:0x30
Field Name
LAT_PERF_CNTR_EN
LAT_PERF_CNTR_FREEZE
LAT_PERF_PATH_SEL
Bits
0
1
4:2
Default
0x0
0x0
0x0
LAT_PERF_CNTR_SEL
7:5
0x0
DMA Latency counter control register
Description
Enables counter.
Freezes average counter.
Selects path (snoop0, snoop1, nonsnoop0, nonsnoop1) to
bring out to read back register.
Selects counter (max, min, total reads, total time) to bring
out to read back register.
IOC_LAT_PERF_CNTR_OUT - R - 32 bits - NBMISCIND:0x31
Field Name
LAT_PERF_CNTR
DMA Latency read back register
Bits
31:0
Default
0x0
Description
DMA Latency read back bits.
PCIE_STRAP_REG2 - RW - 32 bits - NBMISCIND:0x39
Field Name
PCIE_STRAP_REG_Reserved
Bits
31:0
Default
0x0
Description
NB_BROADCAST_BASE_LO - RW - 32 bits - NBMISCIND:0x3A
Field Name
GPU_FB_BROADCAST_BASE_LO
Broadcast bass low address
Bits
31:20
Default
0x0
Description
Broadcast base address [31:20].
NB_BROADCAST_BASE_HI - RW - 32 bits - NBMISCIND:0x3B
Field Name
GPU_FB_BROADCAST_BASE_HI
Broadcast base high address
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
Broadcast base address [63:32]
AMD RS690 ASIC Family Register Reference Manual
2-29
NB_BROADCAST_CNTL - RW - 32 bits - NBMISCIND:0x3C
Field Name
GPU_FB_BROADCAST_SIZE
GPU_FB_BROADCAST_PRIMARY
GPU_FB_BROADCAST_EN
GPU_FB_BROADCAST_OFFSET
Bits
7:0
Default
0x0
8
0x0
9
31:12
0x0
0x0
Description
Broadcast range size, unit is 8MB.
0x01=8MBytes
0x02=16Mbytes
Define primary graphics device
0=Dev2 P2P bridge connects to primary
1=Dev3 P2P bridge
Enables broadcast range
Offset between prefetchable base address and translated
broadcast base.
Broadcast control register
NB_APIC_P2P_CNTL - RW - 32 bits - NBMISCIND:0x3D
Field Name
APIC_D2_Enable
APIC_D3_Enable
APIC_D4_Enable
APIC_D5_Enable
APIC_D6_Enable
APIC_D7_Enable
PCI bridge APIC control register
Bits
0
Default
0x0
1
2
3
4
5
0x0
0x0
0x0
0x0
0x0
Description
Enables Dev2 PCI bridge APIC range decoding. The CPU
memory request with address[39:12] = 0x00_FECx_x is
decoded and issued to each P2P bridge, depending on
each bridge's APIC range setting. What is left in this
range(0x00_FECx_x) that is not declared by any bridge is
forwarded to the SB.
Enables Dev3 PCI bridge APIC range decoding
Enables Dev4 PCI bridge APIC range decoding
Enables Dev5 PCI bridge APIC range decoding
Enables Dev6 PCI bridge APIC range decoding
Enables Dev7 PCI bridge APIC range decoding
NB_APIC_P2P_RANGE_0 - RW - 32 bits - NBMISCIND:0x3E
Field Name
APIC_D2_Range
Bits
7:0
Default
0x0
APIC_D3_Range
15:8
0x0
APIC_D4_Range
23:16
0x0
APIC_D5_Range
31:24
0x0
PCI bridge APIC range 0
Description
Defines bits [19:12] for Dev2 APIC range. Dev2 APIC range
is Addr[39:12] = 20'h00_FEC, APIC_D2_Range[7:0]
Defines bits[19:12] for Dev3 APIC range. Dev3 APIC range
is Addr[39:12] = 12'h00_FEC, APIC_D3_Range[7:0]
Defines bits [19:12] for Dev4 APIC range. Dev4 APIC range
is Addr[39:12] = 12'h00_FEC, APIC_D4_Range[7:0]
Defines bits [19:12] for Dev5 APIC range. Dev5 APIC range
is Addr[39:12] = 12'h00_FEC, APIC_D5_Range[7:0]
NB_APIC_P2P_RANGE_1 - RW - 32 bits - NBMISCIND:0x3F
Field Name
APIC_D6_Range
Bits
7:0
Default
0x0
APIC_D7_Range
15:8
0x0
PCI bridge APIC range 1
AMD RS690 ASIC Family Register Reference Manual
2-30
Description
Defines bits [19:12] for Dev6 APIC range. Dev6 APIC range
is Addr[39:12] = 20'h00_FEC, APIC_D6_Range[7:0]
Defines bits [19:12] for Dev7 APIC range. Dev7 APIC range
is Addr[39:12] = 20'h00_FEC, APIC_D7_Range[7:0]
© 2007 Advanced Micro Devices, Inc.
Proprietary
GPIO_PAD - RW - 32 bits - NBMISCIND:0x40
Field Name
GPIO_TMDS_HPD_OR
GPIO_DDC_DATA_OR
GPIO_I2C_CLK_OR
GPIO_I2C_DATA_OR
GPIO_STRP_DATA_OR
GPIO_DAC_SDA_OR
GPIO_DAC_HSYNC_OR
GPIO_DAC_VSYNC_OR
GPIO_LVDS_ENA_BL_OR
GPIO_LVDS_DIGON_OR
GPIO_LVDS_BLON_OR
GPIO_CPU_SLPb_OR
PAD_0_spare_15_12
GPIO_TMDS_HPD_A
GPIO_DDC_DATA_A
GPIO_I2C_CLK_A
GPIO_I2C_DATA_A
GPIO_STRP_DATA_A
GPIO_DAC_SDA_A
GPIO_DAC_HSYNC_A
GPIO_DAC_VSYNC_A
GPIO_LVDS_ENA_BL_A
GPIO_LVDS_DIGON_A
GPIO_LVDS_BLON_A
GPIO_CPU_SLPb_A
PAD_0_spare_31_28
GPIO_PAD
Bits
0
1
2
3
4
5
6
7
8
9
10
11
15:12
16
17
18
19
20
21
22
23
24
25
26
27
31:28
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
GPIO_PAD_CNTL_PU_PD - RW - 32 bits - NBMISCIND:0x41
Field Name
GPIO_TMDS_HPD_PU
GPIO_DDC_DATA_PU
GPIO_I2C_CLK_PU
GPIO_I2C_DATA_PU
GPIO_STRP_DATA_PU
GPIO_DAC_SDA_PU
GPIO_DAC_HSYNC_PU
GPIO_DAC_VSYNC_PU
GPIO_LVDS_ENA_BL_PU
GPIO_LVDS_DIGON_PU
GPIO_LVDS_BLON_PU
GPIO_CPU_SLPb_PU
spare_15_12
GPIO_TMDS_HPD_PD
GPIO_DDC_DATA_PD
GPIO_I2C_CLK_PD
GPIO_I2C_DATA_PD
GPIO_STRP_DATA_PD
GPIO_DAC_SDA_PD
GPIO_DAC_HSYNC_PD
GPIO_DAC_VSYNC_PD
GPIO_LVDS_ENA_BL_PD
GPIO_LVDS_DIGON_PD
GPIO_LVDS_BLON_PD
GPIO_CPU_SLPb_PD
spare_31_28
GPIO_PAD_CNTL_PU_PD
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
1
2
3
4
5
6
7
8
9
10
11
15:12
16
17
18
19
20
21
22
23
24
25
26
27
31:28
Default
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-31
GPIO_PAD_SCHMEM_OE - RW - 32 bits - NBMISCIND:0x42
Field Name
GPIO_TMDS_HPD_SCHMEN
GPIO_DDC_DATA_SCHMEN
GPIO_I2C_CLK_SCHMEN
GPIO_I2C_DATA_SCHMEN
GPIO_STRP_DATA_SCHMEN
GPIO_DAC_SDA_SCHMEN
GPIO_DAC_HSYNC_SCHMEN
GPIO_DAC_VSYNC_SCHMEN
GPIO_LVDS_ENA_BL_SCHMEN
GPIO_LVDS_DIGON_SCHMEN
GPIO_LVDS_BLON_SCGMEN
GPIO_CPU_SLPb_SCHMEN
spare_15_12
GPIO_TMDS_HPD_OE
GPIO_DDC_DATA_OE
GPIO_I2C_CLK_OE
GPIO_I2C_DATA_OE
GPIO_STRP_DATA_OE
GPIO_DAC_SDA_OE
GPIO_DAC_HSYNC_OE
GPIO_DAC_VSYNC_OE
GPIO_LVDS_ENA_BL_OE
GPIO_LVDS_DIGON_OE
GPIO_LVDS_BLON_OE
GPIO_CPU_SLPb_OE
spare_31_28
GPIO_PAD_SCHMEM_OE
Bits
0
1
2
3
4
5
6
7
8
9
10
11
15:12
16
17
18
19
20
21
22
23
24
25
26
27
31:28
Default
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
GPIO_PAD_SP_SN - RW - 32 bits - NBMISCIND:0x43
Field Name
GPIO_SRP
GPIO_SRN
GPIO_SP_3
GPIO_SP_2
GPIO_SP_1
GPIO_SP_0
GPIO_SN_3
GPIO_SN_2
GPIO_SN_1
GPIO_SN_0
GPIO_PAD_SP_SN
Bits
0
1
2
3
4
5
6
7
8
9
Default
0x1
0x1
0x0
0x0
0x1
0x1
0x0
0x0
0x1
0x1
Description
DFT_VIP_IO_GPIO - RW - 32 bits - NBMISCIND:0x44
Field Name
DFT_GPIO_OE
DFT_GPIO_A
DFT_GPIO_Y (R)
VIP_IO_TVCLKIN_GPIO_EN
VIP_IO_TVCLKIN_GPIO_A
VIP_IO_TVCLKIN_GPIO_Y (R)
Bits
5:0
13:8
21:16
24
25
26
Default
0x0
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-32
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
DFT_VIP_IO_GPIO_OR - RW - 32 bits - NBMISCIND:0x45
Field Name
DFT_GPIO_OR
VIP_IO_TVCLKIN_GPIO_OR
Bits
5:0
8
Default
0x0
0x0
Description
NB_MC_IND_INDEX - RW - 32 bits - nbconfig:0x70
Field Name
MC_IND_ADDR
MC_IND_SEQ_RBS_0
Bits
15:0
16
Default
0x0
0x0
Description
0=Do not access sequencer+gfx return bus block 0
(channels A+B)
1=Access sequencer+gfx return bus block 0 (channels
A+B)
MC_IND_SEQ_RBS_1
17
0x0
0=Do not access sequencer+gfx return bus block 1
(channels C+D)
1=Access sequencer+gfx return bus block 1 (channels
C+D)
MC_IND_SEQ_RBS_2
18
0x0
0=Do not access sequencer+gfx return bus block 2
(channels E+F)
1=Access sequencer+gfx return bus block 2 (channels
E+F)
MC_IND_SEQ_RBS_3
19
0x0
0=Do not access sequencer+gfx return bus block 3
(channels G+H)
1=Access sequencer+gfx return bus block 3 (channels
G+H)
MC_IND_AIC_RBS
20
0x0
0=Do not access aic+cpvf and glb return bus block
1=Access aic+cpvf and glb return bus block
MC_IND_CITF_ARB0
21
0x0
0=Do not access client MCT interface+arbitration block
1=Access client MCT interface+arbitration block
MC_IND_CITF_ARB1
22
0x0
0=Do not access client MCB interface+arbitration block
1=Access client MCB interface+arbitration block
MC_IND_WR_EN
23
0x0
0=Disable write capability (read only)
1=Enable write capability
MC_IND_RD_INV
24
0x0
0=Do not invert data on return bus
1=Invert data on return bus
Index register for accessing MC indirect registers in mmreg (mcind) space. Note: Only mcind 0x10-38 are accessible
NB_MC_IND_DATA - RW - 32 bits - nbconfig:0x74
Field Name
Bits
Default
Description
MC_IND_DATA
31:0
0x0
Data register for accessing MC indirect registers in mmreg (mcind) space. Note: Only mcind 0x10-38 are accessible
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-33
NB_IOC_CFG_CNTL - RW - 32 bits - nbconfig:0x7C
Field Name
FORCE_INTGFX_DISABLE
Bits
0
Default
0x0
spare_29_0
NB_BAR3_PCIEXP_REG_WREN
29:1
30
0x0
0x0
IOC CFG control register
Description
When set to 1 this bit will override the e-fuse HW Config bit
to disable the internal GFX bridge, regardless of the actual
state of the e-fuse bit. This will disable the APC bridge
access if present.
0=Normal
1=Disable
Enables writes to the BAR3 register.
0=Disable
1=Enable
IOC_PCIE_D2_CSR_Count - RW - 32 bits - NBMISCIND:0x50
Field Name
CsrDelayCount
CsrLimitCount
Bits
23:0
31:24
Default
0x0
0x0
Description
IOC_PCIE_D2_CNTL - RW - 32 bits - NBMISCIND:0x51
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
IOC_PCIE_D3_CSR_Count - RW - 32 bits - NBMISCIND:0x52
Field Name
CsrDelayCount
CsrLimitCount
Bits
23:0
31:24
Default
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-34
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
IOC_PCIE_D3_CNTL - RW - 32 bits - NBMISCIND:0x53
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
IOC_PCIE_D4_CSR_Count - RW - 32 bits - NBMISCIND:0x54
Field Name
CsrDelayCount
CsrLimitCount
Bits
23:0
31:24
Default
0x0
0x0
Description
IOC_PCIE_D4_CNTL - RW - 32 bits - NBMISCIND:0x55
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
IOC_PCIE_D5_CSR_Count - RW - 32 bits - NBMISCIND:0x56
Field Name
CsrDelayCount
CsrLimitCount
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
23:0
31:24
Default
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-35
IOC_PCIE_D5_CNTL - RW - 32 bits - NBMISCIND:0x57
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
IOC_PCIE_D6_CSR_Count - RW - 32 bits - NBMISCIND:0x58
Field Name
CsrDelayCount
CsrLimitCount
Bits
23:0
31:24
Default
0x0
0x0
Description
IOC_PCIE_D6_CNTL - RW - 32 bits - NBMISCIND:0x59
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-36
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
IOC_PCIE_D7_CSR_Count - RW - 32 bits - NBMISCIND:0x5A
Field Name
CsrDelayCount
CsrLimitCount
Bits
23:0
31:24
Default
0x0
0x0
Description
IOC_PCIE_D7_CNTL - RW - 32 bits - NBMISCIND:0x5B
Field Name
DmaFixRelaxOrder
DmaForceSnoop
DmaFixAttrEn
P2pDis
BMSetDis
XactOrder
BlockNonSp
BlockSnoop
MstRelaxOrder
MstRelaxOrderEn
MstNSoopEn
ExtDevPlug
ExtDevCsrEn
CsrEnable
IntSelMod
SetPowEn
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
StrapsOutputMux_0 - RW - 32 bits - NBMISCIND:0x60
Field Name
StrapsOutputMux_0
StrapsOutputMux_0
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_1 - RW - 32 bits - NBMISCIND:0x61
Field Name
StrapsOutputMux_1
StrapsOutputMux_1
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_2 - RW - 32 bits - NBMISCIND:0x62
Field Name
StrapsOutputMux_2
StrapsOutputMux_2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
AMD RS690 ASIC Family Register Reference Manual
2-37
StrapsOutputMux_3 - RW - 32 bits - NBMISCIND:0x63
Field Name
StrapsOutputMux_3
StrapsOutputMux_3
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_4 - RW - 32 bits - NBMISCIND:0x64
Field Name
StrapsOutputMux_4
StrapsOutputMux_4
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_5 - R - 32 bits - NBMISCIND:0x65
Field Name
Spare
GPIO_GRP_SEL
DEBUG_TESTMUX
DEBUG_TESTSEL
DEBUG_MEM_A_ENABLE
STRAP_DEBUG_ENABLE
EEP_TEST_DEBUG_BUS_EN
EEP_IO_PLLS_STRAP_EN
StrapsOutputMux_5
Bits
13:0
15:14
21:16
27:22
28
29
30
31
Default
0x3400
0x0
0x0
0x5
0x0
0x0
0x0
0x0
Description
StrapsOutputMux_6 - RW - 32 bits - NBMISCIND:0x66
Field Name
Enable_Pattern_Detector
B_PRX_TOGGLE_EN
B_PRX_PDNB
B_PTX_PDNB
STRAP_BIF_SYMALIGN_DIS_ELIDLE_G
PPSB
STRAP_BIF_SYMALIGN_MODE_GPPSB
STRAP_BIF_ELAST_WATERMARK_GP
PSB
STRAP_BIF_TEST_TOGGLE_MODE_GF
X
STRAP_BIF_TEST_TOGGLE_MODE_G
PPSB
STRAP_BIF_BYPASS_SCRAMBLER_GP
PSB
STRAP_PHY_RX_INCAL_FORCE_GPPS
B
STRAP_BIF_SKIP_INTERVAL_SB
STRAP_BIF_EXIT_LATENCY_SB
STRAP_BIF_REVERSE_LC_LANES_SB
STRAP_BIF_REVERSE_LANES_SB
STRAP_BIF_REVERSE_ALL_GPPSB
STRAP_BIF_FTS_yTSx_COUNT_SB
STRAP_BIF_SHORT_yTSx_COUNT_SB
STRAP_BIF_MED_yTSx_COUNT_SB
Bits
0
1
2
3
4
Default
0x0
0x0
0x0
0x0
0x1
5
7:6
0x1
0x0
8
0x0
9
0x0
10
0x0
11
0x0
14:12
18:15
19
20
21
23:22
25:24
27:26
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-38
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
STRAP_BIF_LONG_yTSx_COUNT_SB
STRAP_BIF_BACKGROUND_IMP_CAL_
GPPSB
INCAL_STRAP_GPPSB
StrapsOutputMux_6
29:28
30
0x0
0x0
31
0x0
StrapsOutputMux_7 - RW - 32 bits - NBMISCIND:0x67
Field Name
STRAP_BIF_BYPASS_RCVR_DET_SB
STRAP_BIF_COMPLIANCE_DIS_SB
STRAP_BIF_FORCE_COMPLIANCE_SB
STRAP_BIF_FORCE_COMPLIANCE_GP
P
STRAP_BIF_LINK_CONFIG_GPPSB
B_P90PLL_IBIAS_RD_GPPSB
STRAP_BIF_RXC_THRESH
spare_11
STRAP_BIF_PHY_RCVRDET_3NF_GPP
SB
B_P90RX_INCAL_FORCE_GPPSB
B_P90RX_CRFR_GPPSB
B_P90RX_CRPHSIZE_GPPSB
B_P90RX_CRFR_ON_GPPSB
B_P90RX_CRFRSIZE_GPPSB
B_P90RX_CLKG_EN_GPPSB
B_PTX_PWRS_ENB_GPPSB
B_PRX_LBACK_EN_GFX
B_PRX_LBACK_EN_GPPSB
B_P90RX_CROUT_SEL
B_P90PLL_IBIAS_SEL_GPPSB
StrapsOutputMux_7
Bits
0
1
2
3
Default
0x0
0x0
0x0
0x0
7:4
9:8
11:10
12
13
0x4
0x1
0x0
0x0
0x1
14
20:15
22:21
23
25:24
26
27
28
29
30
31
0x0
0x0
0x2
0x1
0x0
0x1
0x1
0x0
0x0
0x1
0x1
Description
StrapsOutputMux_8 - RW - 32 bits - NBMISCIND:0x68
Field Name
STRAP_INC_PLLCAL_PHASE
B_PTX_DEEMPH_EN_GPPSB
B_P90TX_DRV_STR_GPPSB
B_P90TX_DEEMPH_STR_GFX
B_P90TX_DEEMPH_STR_GPPSB
B_P90TX_CLKG_EN_GPPSB
B_P90RX_CRFR_BPASS_GFX
B_P90RX_CRFR_BPASS_GPPSB
B_P90PLL_FASTEN_GFX
B_P90PLL_FASTEN_GPPSB
B_P90RX_INCAL_GPPSB
B_P90PLL_CLKF_GPPSB
STRAP_BIF_BACKGROUND_IMP_CAL_
GFX
StrapsOutputMux_8
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
3:0
4
6:5
8:7
10:9
11
12
13
14
15
23:16
30:24
31
Default
0x0
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x1
0x1
0x0
0x7
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-39
StrapsOutputMux_9 - RW - 32 bits - NBMISCIND:0x69
Field Name
B_P90PLL_IBIAS_GPPSB
B_P90RX_CRCTRL_GPPSB
B_P90RX_CRCTRL_BPASS_GPPSB
B_P90PLL_CLKR_GPPSB
B_P90PLL_RESET_GPPSB
B_P90PLL_RESET_EN_GPPSB
B_P90PLL_TEST_GPPSB
STRAP_BIF_PAD_TX_MANUAL_IMPED
ANCE_GPPSB
STRAP_BIF_PAD_RX_MANUAL_IMPED
ANCE_GPPSB
INCAL_DONE_CONTROL
StrapsOutputMux_9
Bits
9:0
16:10
17
19:18
20
21
22
26:23
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
30:27
0x0
31
0x0
Description
StrapsOutputMux_A - RW - 32 bits - NBMISCIND:0x6A
Field Name
StrapsOutputMux_A
StrapsOutputMux_A
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_B - RW - 32 bits - NBMISCIND:0x6B
Field Name
StrapsOutputMux_B
StrapsOutputMux_B
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_C - RW - 32 bits - NBMISCIND:0x6C
Field Name
StrapsOutputMux_C
StrapsOutputMux_C
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_D - RW - 32 bits - NBMISCIND:0x6D
Field Name
StrapsOutputMux_D
StrapsOutputMux_D
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-40
Description
Registered straps from strap block.
© 2007 Advanced Micro Devices, Inc.
Proprietary
StrapsOutputMux_E - RW - 32 bits - NBMISCIND:0x6E
Field Name
StrapsOutputMux_E
StrapsOutputMux_E
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
StrapsOutputMux_F - RW - 32 bits - NBMISCIND:0x6F
Field Name
StrapsOutputMux_F
StrapsOutputMux_F
Bits
31:0
Default
0x0
Description
Registered straps from strap block.
scratch_0 - RW - 32 bits - NBMISCIND:0x70
scratch_0
Field Name
Bits
31:0
Default
0x0
Description
scratch_1 - RW - 32 bits - NBMISCIND:0x71
scratch_1
Field Name
Bits
31:0
Default
0x0
Description
scratch_2 - RW - 32 bits - NBMISCIND:0x72
scratch_2
Field Name
Bits
31:0
Default
0x0
Description
scratch_3 - RW - 32 bits - NBMISCIND:0x73
scratch_3
Field Name
Bits
31:0
Default
0x0
Description
SCRATCH_4 - RW - 32 bits - NBMISCIND:0x74
SCRATCH_4
Field Name
SCRATCH_4
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
AMD RS690 ASIC Family Register Reference Manual
2-41
SCRATCH_5 - RW - 32 bits - NBMISCIND:0x75
SCRATCH_5
Field Name
Bits
31:0
Default
0x0
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
SCRATCH_5
SCRATCH_6 - RW - 32 bits - NBMISCIND:0x76
SCRATCH_6
Field Name
Bits
31:0
Default
0x0
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
SCRATCH_6
SCRATCH_7 - RW - 32 bits - NBMISCIND:0x77
SCRATCH_7
Field Name
Bits
31:0
Default
0x0
SCRATCH_7
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
SCRATCH_8 - RW - 32 bits - NBMISCIND:0x78
SCRATCH_8
Field Name
Bits
31:0
Default
0x0
SCRATCH_8
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
SCRATCH_9 - RW - 32 bits - NBMISCIND:0x79
SCRATCH_9
Field Name
Bits
31:0
Default
0x0
SCRATCH_9
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
SCRATCH_A - RW - 32 bits - NBMISCIND:0x7A
SCRATCH_A
Field Name
Bits
31:0
Default
0x0
SCRATCH_A
AMD RS690 ASIC Family Register Reference Manual
2-42
Description
All of the bits in this register can be written to and read from,
but it does not control anything.
© 2007 Advanced Micro Devices, Inc.
Proprietary
DFT_SPARE - RW - 32 bits - NBMISCIND:0x7F
Field Name
Bits
31:0
DFT_SPARE
Default
0x0
Description
HTIU_CNTL_1 - RW - 32 bits - HTIUNBIND:0x0
Field Name
HTIU_CONTROL_FIELDS
HTIU control 1
Bits
31:0
Default
0x0
Description
Reserved
HTIU_CNTL_2 - RW - 32 bits - HTIUNBIND:0x1
Field Name
HTIU_CONTROL_FIELDS
HTIU control 2
Bits
31:0
Default
0x0
Reserved
Description
HTIU_PERF_CNTL - RW - 32 bits - HTIUNBIND:0x2
Field Name
Bits
© 2007 Advanced Micro Devices, Inc.
Proprietary
Default
See register information below
Description
AMD RS690 ASIC Family Register Reference Manual
2-43
HTIU_PERF_EVENT_0
7:0
0x0
Select HTIU performance counter event 0
1 - Clocks
2 - Number of HT posted writes
3 - Number of HT non-posted writes
4 - Number of HT reads
5 - Command bus utilization between lra and ht_ioc_master
6 - Data bus utilization between lra and ht_ioc_master
7 - Number of HT read responses
8 - Number of HT tgtdone
9 - Clocks that posted write buffer is full
10 - Clocks that non-posted write buffer is full
11 - Number of times posted writes were split into multiple transactions
12 - Number of times non-posted writes were split into multiple transactions
13 - Clocks that ht_ioc_master stalled due to a lack of free command buffers in ioc
14 - Number of times a non-posted memory write was converted into a posted memory write
15 - Clocks that non-posted state machine was busy
16 - Clocks that response state machine was busy doing read response
17 - Clocks that response state machine was busy doing tgtdone
18 - Clocks that ht_ioc_master was idle
19 - Number of SCAS writes
20 - Number of clock cycles for which LDTSTOP is de-asserted i.e. LDTSTOP=1
21 - Number of HT upstream request (read/write)
22 - Number of HT upstream response (to K8)
23 - Number of HT upstream GFX request (read/write)
24 - Number of HT upstream DISP request (read)
25 - Number of HT upstream BIF request (read/write)
26 - Number of HT upstream Ext GFX request (read/write)
27 - Number of HT upstream SB request (read/write)
28 - Number of HT upstream PCIE3 request (read/write)
29 - Number of HT upstream PCIE4 request (read/write)
30 - Number of HT upstream PCIE5 request (read/write)
31 - Number of HT upstream PCIE6 request (read/write)
32 - Number of HT upstream PCIE7 request (read/write)
33 - Number of HT upstream IOC request (all ioc clients read/write)
34 - Number of HT upstream Target Done response (to K8)
35 - Number of HT upstream Read response (to K8)
36 - Number of HT upstream Posted request (write)
37 - Number of HT upstream Non-Posted request (read)
38 - Number of HT upstream ISOC request (read)
39 - Number of HT upstream Read request
40 - Number of HT upstream Byte Write request
41 - Number of GFX request accepted
42 - Clocks that GFX request waited on the interface
43 - Number of DISP request accepted
44 - Clocks that DISP request waited on the interface
45 - Number of IOC request accepted
46 - Clocks that IOC request waited on the interface
47 - Number of IOC response accepted
48 - Clocks that IOC response waited on the interface
49 - Number of HT upstream GFX DW optimized write
50 - Number of HT upstream IOC optimized byte write
51 - Number of HT upstream Posted request (write) with size =< 16 bytes
52 - Number of HT upstream Posted request (write) with size =< 32 bytes and > 16 bytes
53 - Number of HT upstream Posted request (write) with size =< 48 bytes and > 32 bytes
54 - Number of HT upstream Posted request (write) with size =< 64 bytes and > 48 bytes
55 - Number of HT upstream Non-Posted request (read) with size =< 16 bytes
56 - Number of HT upstream Non-Posted request (read) with size =< 32 bytes and > 16 bytes
57 - Number of HT upstream Non-Posted request (read) with size =< 48 bytes and > 32 bytes
58 - Number of HT upstream Non-Posted request (read) with size =< 64 bytes and > 48 bytes
59 - Number of HT upstream ISOC request (read) with size =< 16 bytes
60 - Number of HT upstream ISOC request (read) with size =< 32 bytes and > 16 bytes
61 - Number of HT upstream ISOC request (read) with size =< 48 bytes and > 32 bytes
62 - Number of HT upstream ISOC request (read) with size =< 64 bytes and > 48 bytes
63 - Number of HT upstream Read response (to K8) with size =< 16 bytes
64 - Number of HT upstream Read response (to K8) with size =< 32 bytes and > 16 bytes
65 - Number of HT upstream Read response (to K8) with size =< 48 bytes and > 32 bytes
66 - Number of HT upstream Read response (to K8) with size =< 64 bytes and > 48 bytes
67 - Number of HT upstream Byte Write request with size = 16 bytes
68 - Number of HT upstream Byte Write request with size = 32 bytes
69 - Number of HT upstream Ext GFX Coherent request (read/write)
70 - Number of HT upstream Ext GFX Non-Coherent request (read/write)
71 - Number of HT upstream SB + BIF + PCIE[7:3] Coherent request (read/write)
72 - Number of HT upstream SB + BIF + PCIE[7:3] Non-Coherent request (read/write)
73 - Clock that Upstream state machines are IDLE
74 - 79 - Reserved
80 - Response Command Bus utilization between lra and resp_path
81 - Response Data Bus utilization between lra and resp_path
82 - Number of MC dma responses
83 - Number of IOC dma responses
84 - Number of merged MC dma responses
85 - Number of MC 64-byte responses
86 - Number of MC 32-byte responses
87 - Number of MC 16-byte responses
88 - Number of IOC 64-byte responses
89 - Number of IOC 48-byte responses
90 - Number of IOC 32-byte responses
91 - Number of IOC 16-byte responses
92 - Clocks resp_path is idle
93 - 119 Reserved
120 - Master writes with 0->4 bytes of data (including mask)
121 - Master writes with 5->8 bytes of data (including mask)
122 - Master writes with 9->16 bytes of data (including mask)
123 - Master writes with 17->32 bytes of data (including mask)
124 - Master writes with 33->64 bytes of data (including mask)
125 - Master reads of 0->4 bytes
126 - Master reads of 5->8 bytes
127 - Master reads of 9->16 bytes
AMD RS690 ASIC Family Register Reference Manual
2-44
© 2007 Advanced Micro Devices, Inc.
Proprietary
HTIU_PERF_EVENT_1
15:8
0x0
HTIU_PERF_COUNT_UPPE
R_0 (R)
HTIU_PERF_COUNT_UPPE
R_1 (R)
HTIU performance control
23:16
0x0
31:24
0x0
More performance counter events
128 - Master reads of 17->32 bytes
129 - Master reads of 33->64 bytes
130 - HTiu_CT_RPBusy: clock gating signal is Busy
131 - HTiu_CT_HTMBusy: clock gating signal is Busy
132 - HTiu_CT_RPIdle: clock gating signal is Idle
133 - HTiu_CT_HTMIdle: clock gating signal is Idle
134 - HTiu_CT_FCBIdle: clock gating signal is Idle
135 - HTiu_CT_FCBBusy: clock gating signal is Busy
136 - HTiu_CT_GCMIdle: clock gating signal is Idle
137 - HTiu_CT_GCMBusy: clock gating signal is Busy
138 - HTiu_CT_IOCMasterBusy: clock gating signal is Busy
139 - HTiu_CT_IOCBusy: clock gating signal is Busy
140 - HTiu_CT_IOCIdle: clock gating signal is Idle
141 - HTiu_CT_MCBusy: clock gating signal is Busy
142 - HTiu_CT_MCIdle: clock gating signal is Idle
143 - 149 - Reserved
150 - PerfCnt_SrcTag0UID1Rsp: indicates receipt of Response for UnitID 1 and SrcTag 0
151 - PerfCnt_SrcTag0UID2Rsp: indicates receipt of Response for UnitID 2 and SrcTag 0
152 - PerfCnt_SrcTag0UID3Rsp: indicates receipt of Response for UnitID 3 and SrcTag 0
153 - PerfCnt_SrcTag0UID4Rsp: indicates receipt of Response for UnitID 4 and SrcTag 0
154 - PerfCnt_SrcTag0UID5Rsp: indicates receipt of Response for UnitID 5 and SrcTag 0
155 - PerfCnt_SrcTag0UID6Rsp: indicates receipt of Response for UnitID 6 and SrcTag 0
156 - PerfCnt_SrcTag0UID7Rsp: indicates receipt of Response for UnitID 7 and SrcTag 0
157 - PerfCnt_SrcTag0UID8Rsp: indicates receipt of Response for UnitID 8 and SrcTag 0
158 - PerfCnt_SrcTag0UID9Rsp: indicates receipt of Response for UnitID 9 and SrcTag 0
159 - PerfCnt_SrcTag0UID10Rsp: indicates receipt of Response for UnitID 10 and SrcTag 0
160 - PerfCnt_SrcTag0UID11Rsp: indicates receipt of Response for UnitID 11 and SrcTag 0
161 - PerfCnt_SrcTag0UID12Rsp: indicates receipt of Response for UnitID 12 and SrcTag 0
162 - 223 - Reserved
224 - PerfCnt_read_GFX: DMA Read Request from GFX (to calculate per-request read latency)
225 - PerfCnt_read_DISP: DMA Read Request from DISP (to calculate per-request read latency)
226 - PerfCnt_read_BIF: DMA Read Request from BIF (to calculate per-request read latency)
227 - PerfCnt_read_PCIEGFX0: DMA Read Request from PCIEGFX0 (to calculate per-request read
latency)
228 - PerfCnt_read_PCIEGFX1: DMA Read Request from PCIEGFX1 (to calculate per-request read
latency)
229 - PerfCnt_read_PCIE4: DMA Read Request from PCIE4 (to calculate per-request read latency)
230 - PerfCnt_read_PCIE5: DMA Read Request from PCIE5 (to calculate per-request read latency)
231 - PerfCnt_read_PCIE6: DMA Read Request from PCIE6 (to calculate per-request read latency)
232 - PerfCnt_read_PCIE7: DMA Read Request from PCIE7 (to calculate per-request read latency)
233 - PerfCnt_read_SB: DMA Read Request from SB (to calculate per-request read latency)
234 - PerfCnt_read_AZALIA: DMA Read Request from AZALIA (to calculate per-request read latency)
235 - upto 255 Reserved
Latency_240 - Counts the number of outstanding GFX Requests by adding all allocated tags
Latency_241 - Counts the number of outstanding DSP Requests by adding all allocated tags
Latency_242 - Counts the number of outstanding BIF Requests by adding all allocated tags
Latency_243 - Counts the number of outstanding GFX0 Requests by adding all allocated tags
Latency_244 - Counts the number of outstanding GFX1 Requests by adding all allocated tags
Latency_245 - Counts the number of outstanding PCIE1X0 Requests by adding all allocated tags
Latency_246 - Counts the number of outstanding PCIE1X1 Requests by adding all allocated tags
Latency_247 - Counts the number of outstanding PCIE1X2 Requests by adding all allocated tags
Latency_248 - Counts the number of outstanding PCIE1X3 Requests by adding all allocated tags
Latency_249 - Counts the number of outstanding PCIESB Requests by adding all allocated tags
Latency_250 - Counts the number of outstanding AZALIA Requests by adding all allocated tags
Latency_251 - upto 255 Reserved
Upper 8 bits of HTIU performance counter 0
Upper 8 bits of HTIU performance counter 1
HTIU_PERF_COUNT_0 - R - 32 bits - HTIUNBIND:0x3
Field Name
HTIU_PERF_COUNT_0
HTIU performance counter 0
Bits
31:0
Default
0x0
Description
Lower 32 bits of HTIU performance counter 0
HTIU_PERF_COUNT_1 - R - 32 bits - HTIUNBIND:0x4
Field Name
HTIU_PERF_COUNT_1
HTIU performance counter 1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
Lower 32 bits of HTIU performance counter 1
AMD RS690 ASIC Family Register Reference Manual
2-45
HTIU_DEBUG - RW - 32 bits - HTIUNBIND:0x5
Field Name
HTIU_DEBUG
Bits
31:0
Default
0x0
Description
Bits [31:5]=Reserved
Bit [4]=Enable identifying GFX requests as GSM requests
Bit [3]=Enable blocking of AllowLdtStop during HT link
synchronization
Bit [2]=Enable GSM mode fix to wait for outstanding reads
to complete before allowing LDTSTOP to be
asserted
Bit [1]=Use 500ns LDTSTOP reconnection timer
Bit [0]=Use 1.0us LDTSTOP reconnection timer
HTIU debug
HTIU_DOWNSTREAM_CONFIG - RW - 32 bits - HTIUNBIND:0x6
Bits
0
Default
0x1
1
0x0
CfgHTiuRdRspPassPWMode
3:2
0x0
CfgHTiuTgtDonePassPWMode
5:4
0x0
CfgHTiuReqPassPWMode
7:6
0x0
CfgHTiuDisableNPDWait
CfgHTiuPDStage2En
8
9
0x0
0x0
CfgHTiuLockIOCArb
CfgHTiuHtdNoErr
10
11
0x0
0x0
CfgHtiuTxMaxRspCnt
12
0x0
CfgHTiuLargeRspCnt
ReqCompatModeDis
13
14
0x0
0x0
FIDStpGntDetect
15
0x0
C3StpGntDetect
16
0x0
AllowNPPassPW
17
0x0
HTdSafeIssue
Field Name
HTdPStreamEn
AMD RS690 ASIC Family Register Reference Manual
2-46
Description
Causes outstanding non-posted transactions to block the
posted channel. It should be cleared to avoid a deadlock
scenario
0=PW before NP done
1=PW after NP done
Downstream posted-write streaming
0=Disabled
1=Enable for higher performance
PassPW for upstream read responses
0=00 - From request packet
1=01 - From IOC
2=10 - Always 0
3=11 - Always 1
PassPW for upstream tgtdone
0=00 - From request packet
1=01 - Normally 1 but 0 for I/O cycle
2=10 - Always 0
3=11 - Always 1
PassPW for downstream requests to IOC
0=00 - From request packet
1=01 - Reserved
2=10 - Always 0
3=11 - Always 1
This bit should always be set to 0 for proper operation
Enables larger buffer for downstream posted data and
higher performance
Lock IOC arbiter. Should always be set to 0
Prevents the chipset from sending error bits in upstream
responses to the CPU
Enables infinite response buffers. Setting this bit wastes
upstream bandwidth
Enables 63 response buffer mode
Disables Compat bit decoding in htiu. Should be set to 0 for
proper operation
Enables wait for display on StpGnt with FID SMAF
detection. Should be disabled if no internal gfx
Enables wait for display on StpGnt with C3 SMAF detection.
Should be disabled if no internal gfx
Enables PassPW functionality in non-posted transactions
© 2007 Advanced Micro Devices, Inc.
Proprietary
FastNPAvail
18
0x1
GCMDelay
21:19
0x2
GCMPCDelay
24:22
0x2
DispIntAck
25
0x0
PCIE_HT_NP_MEM_WRITE
26
0x0
SCAS_EN
27
0x0
28
31:29
0x0
0x0
DbgCntrMode
Reserved_31_29
Enables faster turnaround of NP buffer availability. Should
be set to 1
Delay between back-to-back transactions issued by GCM.
Should not be set lower than 0x2
Delay between back-to-back PC transactions issued by
GCM. Should not be set lower than 0x2
Ignores ACK from Display on StpGnt wait and generate
ACK internally
Enables NP protocol over PCIE for memory-mapped writes
targeting LPC. Set this bit to avoid a deadlock condition
Enables SCAS feature. All traffic between 1 and 2GB is
mapped onto a special 64 byte storage space. Should be
used for testing only
Enables rotating htiu debug bus
Bit [29]=Enables wider read to write pointer spacing in the
CFF. This requires a link freq/width change
Bit [30]=Enables a fix for tagging downstream NP requests
Bit [31]=Enables HT Link operation in 600 MHz mode.
Transmit Clock: 600 MHz; LCLK: 150 MHz
1=Enable
0=Disable (normal operating modes for link)
HTIU downstream configuration
HTIU_UPSTREAM_CONFIG_0 - RW - 32 bits - HTIUNBIND:0x7
Bits
0
Default
0x0
delay_STPCLK_en
1
0x1
delay_FID_en
2
0x1
c3_delay_gfx_count_en
3
0x1
ups_igp_arb_en
4
0x0
IGP_ALL_en
5
0x0
IGP_ALL_PFC_en
6
0x1
GCM_flush_urgent_np_disp
7
0x1
ioc_bw_opt_en
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Optimizes IOC byte write by detecting Consecutive DW
mask and translate the request to DW write
0=Disable
1=Enable
Holds off upstream SMC STPCLK for FID message until
DISP_ALLOW_LDTSTOP is asserted. During this time,
only DISP can issue request
0=Disable
1=Enable
Holds off upstream SMC FID message until
DISP_ALLOW_LDTSTOP is asserted. This bit should
always be set to 0
0=Disable
1=Enable
Blocks off GFX client for only 128 cycles when holding SMC
STPCLK for FID message
0=Disable
1=Enable
Selects between GCM/IGP arbitration mode
0=GCM Mode (default)
1=IGP Mode
Selects between IGP AFC/ALL arbitration mode
0=IGP_AFC Mode
1=IGP_ALL Mode
Enables Early Posted Buffer check in IGP_ALL mode
0=Disable
1=Enable
Flush all Non-Posted DISP request first when received
DISP urgent signal. This bit should always be set to 1.
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
2-47
Disp_Rsv_BufCnt
10:8
0x1
drop_zero_mask_req
11
0x0
disp_delay_en
12
0x0
spare_15_13
15:13
0x0
disp_delay_cnt
23:16
0x10
disp_req_cnt
spare_31_30
29:24
31:30
0x7
0x0
HTIU upstream configuration 0
Number of Non-Posted buffer reserved for DISP request
Min=0
Max=7
Note The default is 1.
Drop byte write request that have all zero mask
0=Disable
1=Enable
Blocks off DISP request after N request sends for T amount
of cycles to allow other client to process their request
0=Disable
1=Enable
Bit [13]=Enable qualification of DISP urgent signal with its
RTS signal
Bit [14]=Force DISP request to be always urgent
T amount of Cycle that DISP request will wait. (Each unit
here represent 16 LCLK)
N DISP request send before wait
Bit [30]=Enable Normal UnitID for STPCLK (FID or SB-Th)
message
Bit [31]=GFX Write Request PassPW enable
HTIU_UPSTREAM_CONFIG_1 - RW - 32 bits - HTIUNBIND:0x8
Field Name
NP_DISP_urgt_pri
Bits
3:0
Default
0x1
NP_DISP_tout_pri
7:4
0x5
NP_DISP_norm_pri
11:8
0x9
NP_GFX_urgt_pri
15:12
0x2
NP_GFX_tout_pri
19:16
0x6
NP_GFX_norm_pri
23:20
0xa
NP_IOC_tout_pri
27:24
0x4
NP_IOC_norm_pri
31:28
0x8
HTIU upstream configuration 1
Description
DISP urgent request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 1)
DISP timeout request priority in GCM Non-Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = 5)
DISP normal request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 9)
GFX urgent request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 2)
GFX timeout request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 6)
GFX normal request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = a)
IOC timeout request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 4)
IOC normal request priority in GCM Non-Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 8)
HTIU_UPSTREAM_CONFIG_2 - RW - 32 bits - HTIUNBIND:0x9
Bits
3:0
Default
0xf
NP_RR_1_pri
7:4
0x3
NP_RR_2_pri
11:8
0x7
NP_RR_0_pri
Field Name
AMD RS690 ASIC Family Register Reference Manual
2-48
Description
Round Robin 0 or Efficient 0 priority in GCM Non-Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = f)
Round Robin 1 or Efficient 1 priority in GCM Non-Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = 3)
Round robin 2 or Efficient 2 priority in GCM Non-Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = 7)
© 2007 Advanced Micro Devices, Inc.
Proprietary
NP_rr_1_en
12
0x0
NP_rr_2_en
13
0x0
NP_Eff_1_en
14
0x0
NP_Eff_2_en
15
0x0
19:16
23:20
0xb
0xb
NP_rr_1_len
NP_rr_2_len
HTIU upstream configuration 2
Enables NP Round Robin 1 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enables NP Round Robin 2 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enables NP Efficiency 1 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enable NP Efficiency 2 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
NP Round Robin 1 or NP Efficiency 1 pattern length
NP Round Robin 2 or NP Efficiency 2 pattern length
HTIU_UPSTREAM_CONFIG_3 - RW - 32 bits - HTIUNBIND:0xA
NP_rr_1_pat
Field Name
Bits
31:0
Default
0xaa550
0
Description
NP Round Robin 1 or Efficiency 1 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
HTIU upstream configuration 3
HTIU_UPSTREAM_CONFIG_4 - RW - 32 bits - HTIUNBIND:0xB
NP_rr_2_pat
Field Name
Bits
31:0
Default
0xaa550
0
Description
NP Round Robin 2 or Efficiency 2 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
HTIU upstream configuration 4
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-49
HTIU_UPSTREAM_CONFIG_5 - RW - 32 bits - HTIUNBIND:0xC
Field Name
P_GFX_urgt_pri
Bits
3:0
Default
0x2
P_GFX_tout_pri
7:4
0x6
P_GFX_norm_pri
11:8
0xa
P_IOC_tout_pri
15:12
0x4
P_IOC_norm_pri
19:16
0x8
P_RR_0_pri
23:20
0xf
P_RR_1_pri
27:24
0x3
P_RR_2_pri
31:28
0x7
Description
GFX urgent request priority in GCM Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 2)
GFX timeout request priority in GCM Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 6)
GFX normal request priority in GCM Posted arbitration
(High = 0, Low = e, Don't care = f, Default = a)
IOC timeout request priority in GCM Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 4)
IOC normal request priority in GCM Posted arbitration
(High = 0, Low = e, Don't care = f, Default = 8)
Round Robin 0 or Efficent 0 priority in GCM Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = f)
Round Robin 1 or Efficent 1 priority in GCM Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = 3)
Round robin 2 or Efficent 2 priority in GCM Posted
arbitration
(High = 0, Low = e, Don't care = f, Default = 7)
HTIU upstream configuration 5
HTIU_UPSTREAM_CONFIG_6 - RW - 32 bits - HTIUNBIND:0xD
Bits
0
Default
0x0
1
0x0
P_rr_1_len
P_rr_1_client_a
7:4
11:8
0xb
0x6
P_rr_1_client_b
15:12
0x1
P_rr_1_client_c
19:16
0x4
P_rr_1_client_d
23:20
0xf
P_rr_1_en
Field Name
P_Eff_1_en
HTIU upstream configuration 6
AMD RS690 ASIC Family Register Reference Manual
2-50
Description
Enables P Round Robin 1 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enables P Efficiency 1 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
P Round Robin 1 or P Efficiency 1 pattern length
NP/P Round Robin 1 Client A ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
NP/P Round Robin 1 Client B ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=OC Normal
NP/P Round Robin 1 Client C ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
NP/P Round Robin 1 Client D ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
© 2007 Advanced Micro Devices, Inc.
Proprietary
HTIU_UPSTREAM_CONFIG_7 - RW - 32 bits - HTIUNBIND:0xE
P_rr_1_pat
Field Name
Bits
31:0
Default
0xaa550
0
Description
P Round Robin 1 or Efficiency 1 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
HTIU upstream configuration 7
HTIU_UPSTREAM_CONFIG_8 - RW - 32 bits - HTIUNBIND:0xF
Bits
0
Default
0x0
1
0x0
P_rr_2_len
P_rr_2_client_a
7:4
11:8
0xb
0x7
P_rr_2_client_b
15:12
0x2
P_rr_2_client_c
19:16
0x5
P_rr_2_client_d
23:20
0xf
P_rr_2_en
Field Name
P_Eff_2_en
HTIU upstream configuration 8
Description
Enables P Round Robin 2 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enables P Efficiency 2 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
P Round Robin 2 or P Efficiency 2 pattern length
NP/P Round Robin 2 Client A ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
NP/P Round Robin 2 Client B ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
NP/P Round Robin 2 Client C ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
NP/P Round Robin 2 Client D ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
HTIU_UPSTREAM_CONFIG_9 - RW - 32 bits - HTIUNBIND:0x10
P_rr_2_pat
Field Name
HTIU upstream configuration 9
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0xaa550
0
Description
P Round Robin 2 or Efficiency 2 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
AMD RS690 ASIC Family Register Reference Manual
2-51
HTIU_UPSTREAM_CONFIG_10 - RW - 32 bits - HTIUNBIND:0x11
Bits
2:0
Default
0x3
GCM_ISOC_pri
6:4
0x0
GCM_RSP_pri
10:8
0x1
GCM_P_pri
14:12
0x4
GCM_RR_0_pri
18:16
0x2
GCM_NP_pri
Field Name
HTIU upstream configuration 10
Description
GCM Non-Posted Request Priority
(High = 0, Low = 6, Don't care = 7, Default = 3)
GCM Isochronous Request Priority
(High = 0, Low = 6, Don't care = 7, Default = 0)
GCM Response Priority
(High = 0, Low = 6, Don't care = 7, Default = 1)
GCM Posted Request Priority
(High = 0, Low = 6, Don't care = 7, Default = 4)
GCM Round Robin 0 Priority
(High = 0, Low = 6, Don't care = 7, Default = 2)
HTIU_UPSTREAM_CONFIG_11 - RW - 32 bits - HTIUNBIND:0x12
Bits
0
Default
0x0
1
0x0
GCM_rr_0_len
GCM_rr_0_client_a
7:4
11:8
0x7
0x1
GCM_rr_0_client_b
15:12
0x3
GCM_rr_0_client_c
19:16
0x7
GCM_rr_0_client_d
23:20
0x7
GCM_rr_0_en
Field Name
GCM_Eff_0_en
Description
Enables GCM Round Robin 0 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enables GCM Efficiency 0 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
GCM Round Robin 0 or GCM Efficiency 0 pattern length
GCM Round Robin 0 Client A ID
0=Isoc, 1=Non-Posted, 2=Response
3=Posted, 4=RR0/EFF0
GCM Round Robin 0 Client B ID
0=Isoc, 1=Non-Posted, 2=Response,
3=Posted, 4=RR0/EFF0
GCM Round Robin 0 Client C ID
0=Isoc, 1=Non-Posted, 2=Response,
3=Posted, 4=RR0/EFF0
GCM Round Robin 0 Client D ID
0=Isoc, 1=Non-Posted, 2=Response,
3=Posted, 4=RR0/EFF0
HTIU upstream configuration 11
HTIU_UPSTREAM_CONFIG_12 - RW - 32 bits - HTIUNBIND:0x13
GCM_rr_0_pat
Field Name
Bits
31:0
Default
0x55005
500
HTIU upstream configuration 12
AMD RS690 ASIC Family Register Reference Manual
2-52
Description
GCM Round Robin 0 or GCM Efficiency 0 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
© 2007 Advanced Micro Devices, Inc.
Proprietary
HTIU_UPSTREAM_CONFIG_13 - RW - 32 bits - HTIUNBIND:0x14
Field Name
AFC_DISP_urgt_pri
Bits
3:0
Default
0x1
AFC_DISP_tout_pri
7:4
0x5
AFC_DISP_norm_pri
11:8
0x9
AFC_GFX_urgt_pri
15:12
0x2
AFC_GFX_tout_pri
19:16
0x6
AFC_GFX_norm_pri
23:20
0xa
AFC_IOC_tout_pri
27:24
0x4
AFC_IOC_norm_pri
31:28
0x8
Description
DISP urgent request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 1)
DISP timeout request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 5)
DISP normal request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 9)
GFX urgent request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 2)
GFX timeout request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 6)
GFX normal request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = a)
IOC timeout request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 4)
IOC normal request priority in IGP AFC/ALL arbitration
(High = 0, Low = e, Don't care = f, Default = 8)
HTIU upstream configuration 13
HTIU_UPSTREAM_CONFIG_14 - RW - 32 bits - HTIUNBIND:0x15
Field Name
AFC_RR_0_pri
Bits
3:0
Default
0x0
AFC_RR_1_pri
7:4
0x3
AFC_RR_2_pri
11:8
0x7
12
0x0
AFC_rr_0_len
AFC_rr_0_client_a
15:13
19:16
0x7
0x0
AFC_rr_0_client_b
23:20
0x3
AFC_rr_0_pat
31:24
0xf0
AFC_rr_0_en
HTIU upstream configuration 14
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Round Robin 0 or Efficent 0 priority in IGP AFC/ALL
arbitration
(High = 0, Low = e, Don't care = f, Default = f)
Round Robin 1 or Efficent 1 priority in IGP AFC/ALL
arbitration
(High = 0, Low = e, Don't care = f, Default = 3)
Round robin 2 or Efficent 2 priority in IGP AFC/ALL
arbitration
(High = 0, Low = e, Don't care = f, Default = 7)
Enables AFC/ALL Round Robin 0 Arbiter
0=Disable
1=Enable
AFC/ALL Round Robin 0 or Efficiency 0 pattern length
AFC/ALL Round Robin 0 Client A ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
AFC/ALL Round Robin 0 Client B ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
AFC/ALL Round Robin 0 or Efficiency 0 select pattern
0=RR order is Client A, B
1=RR order is Client B, A.
AMD RS690 ASIC Family Register Reference Manual
2-53
HTIU_UPSTREAM_CONFIG_15 - RW - 32 bits - HTIUNBIND:0x16
Field Name
FCBBypassEn
CRCDecodeFix
Bits
0
1
Default
0x0
0x0
SplitTxPhyEn
2
0x0
SplitRxPhyEn
3
0x0
TxClkGateEn
4
0x0
31:5
0x0
HTIU_DEBUG2
HTIU upstream configuration 15
Description
This bit controls no hardware.
Enables the CRC Decoding fix
0=CRC Decoding fix is disabled
1=CRC Decoding fix is enabled
Automatically disables the upper half of the HT transmitter
when running in 8-bit output mode
0=In 8-bit mode the upper HT bus drives logical 0
1=In 8-bit mode the upper HT bus is tristated
Automatically disables the upper half of the HT receiver
when running in 8-bit input mode
0=In 8-bit mode, the upper HT receiver is enabled
1=In 8-bit mode, the upper HT receiver is disabled
Dynamically gates the clock to the HT TX PHY
0=The clock to the HT TX PHY is always on
1=The clock to the HT TX PHY is shut off when LDTSTOP
is asserted
This register is used to hold debug features
Bit [0]=Enable GSM All mode where any DMA request will
wake up the HT link (including display and graphics)
Bits [26:1]=Reserved (controls no hardware)
HTIU_UPSTREAM_CONFIG_16 - RW - 32 bits - HTIUNBIND:0x17
Field Name
AFC_rr_1_pat
Bits
31:0
Default
0xaa550
0
HTIU upstream configuration 16
Description
AFC/ALL Round Robin 1 or Efficiency 1 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
HTIU_UPSTREAM_CONFIG_17 - RW - 32 bits - HTIUNBIND:0x18
AFC_rr_2_en
Field Name
Bits
0
Default
0x0
AFC_Eff_2_en
1
0x0
AFC_rr_2_len
7:4
0xb
AMD RS690 ASIC Family Register Reference Manual
2-54
Description
Enables AFC/ALL Round Robin 2 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
Enables AFC/ALL Efficiency 1 Arbiter
Note: The RR and EFF arbiter cannot be enabled at the
same time.
0=Disable
1=Enable
AFC/ALL Round Robin 2 or Efficiency 2 pattern length
© 2007 Advanced Micro Devices, Inc.
Proprietary
AFC_rr_2_client_a
11:8
0x7
AFC_rr_2_client_b
15:12
0x2
AFC_rr_2_client_c
19:16
0x5
AFC_rr_2_client_d
23:20
0xf
AFC/ALL Round Robin 2 Client A ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
AFC/ALL Round Robin 2 Client B ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
AFC/ALL Round Robin 2 Client C ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
AFC/ALL Round Robin 2 Client D ID
0=DISP Urgent, 1=DISP Timeout, 2=DISP Normal
3=GFX Urgent, 4=GFX Timeout, 5=GFX Normal
6=IOC Timeout, 7=IOC Normal
HTIU upstream configuration 17
HTIU_UPSTREAM_CONFIG_18 - RW - 32 bits - HTIUNBIND:0x19
Field Name
AFC_rr_2_pat
Bits
31:0
Default
0xaa550
0
HTIU upstream configuration 18
Description
AFC/ALL Round Robin 2 or Efficiency 2 select pattern
(Every 2 bits represent 1 pattern)
00=RR order is Client A, B, C, D
01=RR order is Client B, C, D, A
10=RR order is Client C, D, A, B
11=RR order is Client D, A, B, C
HTIU_UPSTREAM_CONFIG_19 - RW - 32 bits - HTIUNBIND:0x1A
Field Name
IGP_ALLAFC_pri
Bits
0
Default
0x1
IGP_RSP_pri
1
0x0
ioc_timeout_en
4
0x1
gfx_timeout_en
5
0x1
ioc_timeout_cnt
11:8
0x7
gfx_timeout_cnt
15:12
0x7
ioc_non_zero_SeqID
16
0x0
gfx_non_zero_SeqID
17
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Priority for AFC or ALL (request) in IGP mode
0=Highest
1=Lowest
Priority for Response in IGP mode
0=Highest
1=Lowest
Internal IOC request timeout
0=Disable
1=Enable
Internal GFX request timeout
0=Disable
1=Enable
Internal IOC timeout counter value (each unit here
represent 16 LCLK cycles)
Internal IOC timeout counter value (each unit here
represent 16 LCLK cycles)
Changes IOC SeqID to match UnitID
0=Disable
1=Enable
Change GFX SeqID to match UnitID
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
2-55
ioc_only_mode_en
20
0x0
P_Rsv_BufCnt
21
0x1
HTIU upstream configuration 19
Bypasses buffer stage in GCM arb mode to improve
latency. This feature is only available when in external GFX
mode.
0=Disable
1=Enable
Reserves Posted buffer for IGP ALL mode to improve
performance
0=Reserve None
1=Reserve One
HTIU_UPSTREAM_CONFIG_20 - RW - 32 bits - HTIUNBIND:0x1B
PPG_EN
Field Name
PPG_CTL
spare_31_12
HTIU upstream configuration 20
Bits
0
Default
0x0
11:4
31:12
0x0
0x0
Description
Enables HT TX PHY pattern generator. Used for testing
only.
Pattern generator CTL bits for 8 bit-times
Reserved. Should be set to 0
HTIU_UPSTREAM_CONFIG_21 - RW - 32 bits - HTIUNBIND:0x1C
Field Name
PPG_CAD0
HTIU upstream configuration 21
Bits
31:0
Default
0x0
Description
Pattern generator CAD bits [31:0]
HTIU_UPSTREAM_CONFIG_22 - RW - 32 bits - HTIUNBIND:0x1D
Field Name
PPG_CAD1
HTIU upstream configuration 22
Bits
31:0
Default
0x0
Description
Pattern generator CAD bits [63:32]
HTIU_UPSTREAM_CONFIG_23 - RW - 32 bits - HTIUNBIND:0x1E
Field Name
PPG_CAD2
HTIU upstream configuration 23
Bits
31:0
Default
0x0
Description
Pattern generator CAD bits [95:64]
HTIU_UPSTREAM_CONFIG_24 - RW - 32 bits - HTIUNBIND:0x1F
Field Name
PPG_CAD3
HTIU upstream configuration 24
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-56
Description
Pattern generator CAD bits [128:96]
© 2007 Advanced Micro Devices, Inc.
Proprietary
NB_LOWER_TOP_OF_DRAM2 - RW - 32 bits - HTIUNBIND:0x30
Field Name
ENABLE
LOWER_TOM2
Top of lower Extended RAM
Bits
0
31:23
Default
0x0
0x0
Description
NB_UPPER_TOP_OF_DRAM2 - RW - 32 bits - HTIUNBIND:0x31
Field Name
UPPER_TOM2
Top of upper Extended RAM
Bits
7:0
Default
0x0
Description
NB_HTIU_CFG - RW - 32 bits - HTIUNBIND:0x32
Field Name
spare_27_0
NB_BAR3_PCIEXP_ENABLE
Bits
27:0
28
Default
0x0
0x0
spare_31_29
HTIU control
31:29
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Enables PCI-E memory mapped register
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
2-57
PCI Express Registers
2.2
PCI Express Registers
PCIE_RESERVED - R - 32 bits - PCIEIND:0x0
Field Name
PCIE_RESERVED
Bits
31:0
Default
0xffffffff
Description
This register field is reserved.
PCIE_SCRATCH - RW - 32 bits - PCIEIND:0x1
Field Name
PCIE_SCRATCH
Software test register.
Bits
31:0
Default
0x0
Software test register
Description
PCIE_CNTL - RW - 32 bits - PCIEIND:0x10
Field Name
HWINIT_WR_LOCK
UR_ERR_REPORT_DIS
TX_CPU_HYPER_DIS
PCIE_HT_NP_MEM_WRITE
RX_SB_ADJ_PAYLOAD_SIZE
RX_SB_COMPLETE_FULL_FIX
RX_SB_REJECT_IF_FULL
RX_RCB_REORDER_EN
RX_RCB_INVALID_SIZE_DIS
RX_RCB_UNEXP_CPL_DIS
RX_RCB_CPL_TIMEOUT_TEST_MODE
TX_CPL_DEBUG
RX_CPL_POSTED_REQ_ORD_EN
Bits
0
Default
0x0
7
8
9
12:10
0x0
0x0
0x0
0x2
13
14
16
0x1
0x0
0x1
17
18
19
29:24
31
0x1
0x0
0x0
0x0
0x1
PCIExpress control register
Description
Hardware write lock.
0=HWInit registers unlocked
1=Lock HWInit registers
UR error reporting disable for TX
Disable HyperTransport compatibility features
Memory write mapping enable
SB payload size
2=16 bytes
3=32 bytes
4=64 bytes
RCB ordering enable
0=No re-ordering
1=Re-ordering
RCB invalid size disable
RCB unexpect cpl disable
RCB cpl timeout test mode
CPL debug
CPL request ordering enable
0=Disable RX request ordering
1=Enable RX request ordering
PCIE_CONFIG_CNTL - RW - 32 bits - PCIEIND:0x11
Field Name
CFG_ATI_REV_ID (R)
DYN_CLK_LATENCY
PCIExpress Configuration Control register.
Bits
3:0
7:4
Default
0x0
0x7
AMD RS690 ASIC Family Register Reference Manual
2-58
Description
Metal mask programmable
Dynamic Clock Latency
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_CI_CNTL - RW - 32 bits - PCIEIND:0x20
Field Name
CI_BE_SPLIT_MODE
Bits
1:0
Default
0x0
CI_SLAVE_SPLIT_MODE
2
0x0
CI_SLAVE_GEN_USR_DIS
3
0x0
CI_MST_CMPL_DUMMY_DATA
4
0x1
CI_MST_TAG_MODE
5
0x0
7:6
0x1
CI_SLV_ORDERING_DIS
8
0x0
CI_RC_ORDERING_DIS
9
0x0
CI_SLV_CPL_ALLOC_DIS
10
0x0
CI_SLV_RC_RD_REQ_SIZE
Chip interface control register
Field Name
BUS_DBL_RESYNC
Description
Byte enable splitting mode for master interface
0=Normal byte splitting rules for PCI-Express 1.0A
1=Force a split on QW boundary with maximum packet
length = 2
2=Bypass mode that forces full byte enables
Completions split on Channels
0=RC - Full completions from Channel A or B
1=RC - Completions split on Channel A and B evenly
Sends USR for invalid addresses
0=Sends USR for invalid addresses
1=Disables slave from sending USR, and instead sends a
successful CMPLT_D with dummy data.
0xDEADBEEF or 0xFFFFFFFF
0=0xDEADBEEF
1=0xFFFFFFFF
Incremental tag or first available tag
0=Incremental tag
1=First available tag
Slave read requests supported size to client.
0=32/64 byte requests supported
1=64 byte requests only
2=16/32/64
Disables slave ordering logic
0=Enable slave ordering logic
1=Disable slave ordering logic
Disables RC ordering logic
0=Enable RC ordering logic
1=Disable RC ordering logic
Slave CPL buffer is sub-divided or not
0=Slave CPL buffer is sub-divided between ports based
on number of lanes active
1=Slave CPL buffer is not sub-divided
PCIE_BUS_CNTL - RW - 32 bits - PCIEIND:0x21
Bits
0
Default
0x1
PMI_BM_DIS
5
0x0
PMI_INT_DIS
6
0x0
IMMEDIATE_PMI_DIS
7
0x0
PCI Express Bus Control register.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Double flop the sync module.
0=Normal
1=Add extra resynchronizing clock
PMI Bus Master Disable
0=Normal
1=Disable
PMI Interrupt Disable
0=Normal
1=Disable
Immediate PMI Disable
0=Enable
1=Disable
AMD RS690 ASIC Family Register Reference Manual
2-59
PCI Express Registers
PCIE_P_CNTL - RW - 32 bits - PCIEIND:0x40
Field Name
P_PWRDN_EN
Bits
0
Default
0x0
P_SYMALIGN_MODE
1
0x0
P_PLL_TEST_MODE
P_PLL_PWRDN_IN_L1L23
2
3
0x0
0x0
P_PLL_BUF_PDNB
4
0x1
P_TXCLK_SND_PWRDN
5
0x0
P_TXCLK_RCV_PWRDN
6
0x0
PI_SYMALIGN_DIS_ELIDLE
7
0x0
P_MASK_RCVR_EIDLE_EN
P_PLL_PDNB
8
9
0x0
0x1
17:16
19:18
21:20
23:22
0x0
0x1
0x2
0x3
RXP_XBAR_MUX0
RXP_XBAR_MUX1
RXP_XBAR_MUX2
RXP_XBAR_MUX3
PHY Control Register
AMD RS690 ASIC Family Register Reference Manual
2-60
Description
Enables powering down transmitter and receiver pads
along with PLL macros.
Data Valid generation bit:
iMODE=0 (Relax Mode): Update its symbol right away
when detect any bit shift (i.e. data_valid will always assert).
iMODE=1 (Aggressive Mode): Need confirmation before
muxing out the data.
Enables PLL powerdown in L1 or L23 Ready states, only if
all the associated LC's are in Sates L1 / L23 corresponding
to 4 / 2 lanes based on mpConfig and architecture.
Disables 10X clock pad on a per PLL basis. It should be
1'b0 in order to activate this powersafe feature.
Enables powering down TXCLK clock pads on the transmit
side. Each clock pad corresponds to logic associated with 4
lanes.
Enables powering down TXCLK clock pads on the receive
side. Each clock pad corresponds to logic associated with 4
lanes.
Symbol Alignment Statemachine control signal:
iDIS_ELIDLE=0: ElectIdle assertion will be effective in state
machine re-initialization.
iDIS_ELIDLE=1: ElectIdle will be ineffective in state
machine re-initialization
Enables EIDLE mask for powered down receivers.
Enables PLL only (not the buffer) to power down in L1 or
L23ready states.
Data routing cross bar mux - default 1'b0
Data routing cross bar mux - default 1'b1
Data routing cross bar mux - default 1'b2
Data routing cross bar mux - default 1'b3
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_P_BUF_STATUS - RW - 32 bits - PCIEIND:0x41
Field Name
P_ELASTIC_BUF_OVERFLOW_0
Bits
0
Default
0x0
P_ELASTIC_BUF_OVERFLOW_1
1
0x0
P_ELASTIC_BUF_OVERFLOW_2
2
0x0
P_ELASTIC_BUF_OVERFLOW_3
3
0x0
P_ELASTIC_BUF_OVERFLOW_4
4
0x0
P_ELASTIC_BUF_OVERFLOW_5
5
0x0
P_ELASTIC_BUF_OVERFLOW_6
6
0x0
P_ELASTIC_BUF_OVERFLOW_7
7
0x0
P_ELASTIC_BUF_OVERFLOW_8
8
0x0
P_ELASTIC_BUF_OVERFLOW_9
9
0x0
P_ELASTIC_BUF_OVERFLOW_10
10
0x0
P_ELASTIC_BUF_OVERFLOW_11
11
0x0
P_ELASTIC_BUF_OVERFLOW_12
12
0x0
P_ELASTIC_BUF_OVERFLOW_13
13
0x0
P_ELASTIC_BUF_OVERFLOW_14
14
0x0
P_ELASTIC_BUF_OVERFLOW_15
15
0x0
P_DESKEW_BUF_OVERFLOW_0
P_DESKEW_BUF_OVERFLOW_1
P_DESKEW_BUF_OVERFLOW_2
P_DESKEW_BUF_OVERFLOW_3
P_DESKEW_BUF_OVERFLOW_4
P_DESKEW_BUF_OVERFLOW_5
P_DESKEW_BUF_OVERFLOW_6
P_DESKEW_BUF_OVERFLOW_7
P_DESKEW_BUF_OVERFLOW_8
P_DESKEW_BUF_OVERFLOW_9
P_DESKEW_BUF_OVERFLOW_10
P_DESKEW_BUF_OVERFLOW_11
P_DESKEW_BUF_OVERFLOW_12
P_DESKEW_BUF_OVERFLOW_13
P_DESKEW_BUF_OVERFLOW_14
P_DESKEW_BUF_OVERFLOW_15
PHY Buffer Status register.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Rx to Tx time domain hand-off buffer under/over flow: lane
0.
Rx to Tx time domain hand-off buffer under/over flow: lane
1.
Rx to Tx time domain hand-off buffer under/over flow: lane
2.
Rx to Tx time domain hand-off buffer under/over flow: lane
3.
Rx to Tx time domain hand-off buffer under/over flow: lane
4.
Rx to Tx time domain hand-off buffer under/over flow: lane
5.
Rx to Tx time domain hand-off buffer under/over flow: lane
6.
Rx to Tx time domain hand-off buffer under/over flow: lane
7.
Rx to Tx time domain hand-off buffer under/over flow: lane
8.
Rx to Tx time domain hand-off buffer under/over flow: lane
9.
Rx to Tx time domain hand-off buffer under/over flow: lane
10.
Rx to Tx time domain hand-off buffer under/over flow: lane
11.
Rx to Tx time domain hand-off buffer under/over flow: lane
12.
Rx to Tx time domain hand-off buffer under/over flow: lane
13.
Rx to Tx time domain hand-off buffer under/over flow: lane
14.
Rx to Tx time domain hand-off buffer under/over flow: lane
15.
Symbol skew buffer over/underflow: lane 0.
Symbol skew buffer over/underflow: lane 1.
Symbol skew buffer over/underflow: lane 2.
Symbol skew buffer over/underflow: lane 3.
Symbol skew buffer over/underflow: lane 4.
Symbol skew buffer over/underflow: lane 5.
Symbol skew buffer over/underflow: lane 6.
Symbol skew buffer over/underflow: lane 7.
Symbol skew buffer over/underflow: lane 8.
Symbol skew buffer over/underflow: lane 9.
Symbol skew buffer over/underflow: lane 10.
Symbol skew buffer over/underflow: lane 11.
Symbol skew buffer over/underflow: lane 12.
Symbol skew buffer over/underflow: lane 13.
Symbol skew buffer over/underflow: lane 14.
Symbol skew buffer over/underflow: lane 15.
AMD RS690 ASIC Family Register Reference Manual
2-61
PCI Express Registers
PCIE_P_DECODER_STATUS - RW - 32 bits - PCIEIND:0x42
Field Name
P_DECODE_ERR_0
Bits
0
Default
0x0
P_DECODE_ERR_1
1
0x0
P_DECODE_ERR_2
2
0x0
P_DECODE_ERR_3
3
0x0
P_DECODE_ERR_4
4
0x0
P_DECODE_ERR_5
5
0x0
P_DECODE_ERR_6
6
0x0
P_DECODE_ERR_7
7
0x0
P_DECODE_ERR_8
8
0x0
P_DECODE_ERR_9
9
0x0
P_DECODE_ERR_10
10
0x0
P_DECODE_ERR_11
11
0x0
P_DECODE_ERR_12
12
0x0
P_DECODE_ERR_13
13
0x0
P_DECODE_ERR_14
14
0x0
P_DECODE_ERR_15
15
0x0
P_DISPARITY_ERR_0
16
0x0
P_DISPARITY_ERR_1
17
0x0
P_DISPARITY_ERR_2
18
0x0
P_DISPARITY_ERR_3
19
0x0
P_DISPARITY_ERR_4
20
0x0
AMD RS690 ASIC Family Register Reference Manual
2-62
Description
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the decoding error, i.e., can't
decode the incoming data.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
P_DISPARITY_ERR_5
21
0x0
P_DISPARITY_ERR_6
22
0x0
P_DISPARITY_ERR_7
23
0x0
P_DISPARITY_ERR_8
24
0x0
P_DISPARITY_ERR_9
25
0x0
P_DISPARITY_ERR_10
26
0x0
P_DISPARITY_ERR_11
27
0x0
P_DISPARITY_ERR_12
28
0x0
P_DISPARITY_ERR_13
29
0x0
P_DISPARITY_ERR_14
30
0x0
P_DISPARITY_ERR_15
31
0x0
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
Indicates which lane has the link error.
Bit 15 => Lane 15 (0 = OK, 1 = Error), etc.
PHY Decoder Status register.
PCIE_P_PLL_CNTL - RW - 32 bits - PCIEIND:0x44
P_VCOREF
Field Name
P_CALREF
Bits
1:0
Default
0x0
3:2
0x0
PHY PLL Control register.
Description
Controls the signal generation used in calibrating PLL's
0=OFF
1=VDD/4
2=VDD/2
3=3VDD/4
Controls the signal generation used in calibrating PLL's
0=OFF
1=VDD/2
2=2VDD/3
3=5VDD/6
PCIE_P_IMP_CNTL_STRENGTH - RW - 32 bits - PCIEIND:0x60
Field Name
P_TX_STR_CNTL_READ_BACK (R)
P_TX_IMP_CNTL_READ_BACK (R)
P_RX_IMP_CNTL_READ_BACK (R)
P_TX_STR_CNTL
P_TX_IMP_CNTL
P_RX_IMP_CNTL
PI_HALT_IMP_CAL
P_PAD_MANUAL_OVERRIDE
Bits
3:0
7:4
11:8
19:16
23:20
27:24
28
31
Default
0x0
0x0
0x0
0x7
0x7
0x7
0x0
0x0
Description
Stores the readback value of current controller.
Stores the readback value of TX impedance controller.
Stores the readback value of RX impedance controller.
Sets the initial default current strength to 4'b0111.
Default TX impedance control value.
Default RX impedance control value.
Enables Current and Impedance control values to override
0=Allow normal impedance compensation operation
1=Default to manual settings
PHY Impedance Control Strength register.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-63
PCI Express Registers
PCIE_P_IMP_CNTL_UPDATE - RW - 32 bits - PCIEIND:0x61
Field Name
P_IMP_PAD_UPDATE_RATE
P_IMP_PAD_SAMPLE_DELAY
P_IMP_PAD_INC_THRESHOLD
P_IMP_PAD_DEC_THRESHOLD
Impedance PAD defaults.
Bits
4:0
Default
0xf
12:8
20:16
28:24
0x1
0x18
0x8
Description
PAD's update interval.
0=PHY130 (default 0xf)
1=PHY90 (default 0xe)
Sampling window.
Incremental resolution.
Decremental resolution.
PCIE_P_STR_CNTL_UPDATE - RW - 32 bits - PCIEIND:0x62
Field Name
P_STR_PAD_UPDATE_RATE
P_STR_PAD_SAMPLE_DELAY
P_STR_PAD_INC_THRESHOLD
P_STR_PAD_DEC_THRESHOLD
Current PAD defaults.
Bits
4:0
Default
0xf
12:8
20:16
28:24
0x1
0x18
0x8
Description
PAD's update interval.
0=PHY130 (default 0xf)
1=PHY90 (default 0xe)
Sampling window.
Incremental resolution.
Decremental resolution.
PCIE_P_PAD_MISC_CNTL - RW - 32 bits - PCIEIND:0x63
Field Name
P_PAD_I_DUMMYOUT (R)
P_PAD_IMP_DUMMYOUT (R)
P_PAD_IMP_TESTOUT (R)
P_LINK_RETRAIN_ON_ERR_EN
Bits
0
1
2
3
Default
0x0
0x0
0x0
0x0
Description
Input from analog - 0 if PMOS cur is stronger.
Input from analog - 0 if PMOS imp is stronger.
Input from analog - 1 if NMOS imp is stronger.
Disables error counts in LaneDeskew if Symbol unlocking,
Code Errors or Deskew Errors are detected.
Pad Miscellaneous Control registers.
Field Name
B_PTX_PDNB_FEN
B_PRX_PDNB_FEN
B_PPLL_PDNB_FEN
B_PPLL_BUF_PDNB_FEN
B_PI_DREN_FEN
B_PBG_PDNB_FEN
PCIE_P_PAD_FORCE_EN - RW - 32 bits - PCIEIND:0x64
Bits
7:0
15:8
19:16
23:20
24
25
Default
0x0
0x0
0x0
0x0
0x0
0x0
B_PIMP_TX_PDNB_FEN
26
0x0
B_PIMP_RX_PDNB_FEN
27
0x0
Powerdown enable signals used by the wrapper.
AMD RS690 ASIC Family Register Reference Manual
2-64
Description
Forces B_PTX_PDNB to enable TX pad.
Forces B_PRX_RDNB to enable RX pad.
Forces B_PPLL_PDNB to enable PLL.
Forces B_PPLL_BUF_PDNB to enable 10x driver in PLL.
Forces B_PI_DREN to enable current calibration pad.
Forces B_PBG_PDNB to enable Bandgap circuit in current
calibration pad.
Forces B_PIMP_TX_PDNB to enable TX impedance
calibration pad.
Forces B_PIMP_RX_PDNB to enable RX impedance
calibration pad.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_P_PAD_FORCE_DIS - RW - 32 bits - PCIEIND:0x65
Field Name
B_PTX_PDNB_FDIS
B_PRX_PDNB_FDIS
B_PPLL_PDNB_FDIS
B_PPLL_BUF_PDNB_FDIS
B_PI_DREN_FDIS
B_PBG_PDNB_FDIS
Bits
7:0
15:8
19:16
23:20
24
25
Default
0x0
0x0
0x0
0x0
0x0
0x0
B_PIMP_TX_PDNB_FDIS
26
0x0
B_PIMP_RX_PDNB_FDIS
27
0x0
Powerdown disable signals used by the wrapper.
Description
Forces B_PTX_PDNB to disable TX pad.
Forces B_PRX_PDNB to disable RX pad.
Forces B_PPLL_PDNB to disable PLL.
Forces B_PPLL_BUF_PDNB to disable 10x driver in PLL.
Forces B_PI_DREN to disable current calibration pad.
Forces B_PBG_PDNB to disable Bandgap circuit in current
calibration pad.
Forces B_PIMP_TX_PDNB to disable TX impedance
calibration pad.
Forces B_PIMP_TX_PDNB to disable RX impedance
calibration pad.
PCIEP_RESERVED - R - 32 bits - PCIEIND_P:0x0
Field Name
PCIEP_RESERVED
Bits
31:0
Default
0xffffffff
Description
This register field is reserved.
PCIEP_SCRATCH - RW - 32 bits - PCIEIND_P:0x1
Field Name
PCIEP_SCRATCH
Scratch register.
Bits
31:0
Default
0x0
Scratch register.
Description
PCIEP_PORT_CNTL - RW - 32 bits - PCIEIND_P:0x10
Field Name
SLV_PORT_REQ_EN
Bits
0
Default
0x1
CI_SNOOP_OVERRIDE
1
0x0
HOTPLUG_MSG_EN
2
0x0
NATIVE_PME_EN
3
0x1
SEQNUM_DEBUG_MODE
4
0x0
Description
Suspends all slave requests to client
0=Allow slave to be suspended
1=Ignore slave suspend signal
Forces all slave requests to be snoop requests
0=Do not force all slave requests to be snoop requests
1=Force all slave requests to be snoop requests
Enables hot-plug messages
0=Disable hot-plug messages
1=Enable hot-plug messages
Enables native PME
0=Disable native PME
1=Enable native PME
Enables debug sequence number
0=Normal operation
1=Enable debug sequence number test mode
Port Control Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-65
PCI Express Registers
PCIE_TX_CNTL - RW - 32 bits - PCIEIND_P:0x20
Field Name
TX_REPLAY_NUM_COUNT (R)
Bits
9:0
Default
0x0
TX_SNR_OVERRIDE
11:10
0x0
TX_RO_OVERRIDE
13:12
0x0
TX_PACK_PACKET_DIS
14
0x0
TX_GENERATE_CRC_ERR
15
0x0
18:16
19
0x0
0x1
TX_CPL_PASS_P
20
0x1
TX_NP_PASS_P
21
0x0
TX_FC_UPDATE_TIMEOUT_SEL
25:24
0x2
TX_FC_UPDATE_TIMEOUT
TX Control Register
31:26
0x7
TX_GAP_BTW_PKTS
TX_FLUSH_TLP_DIS
Description
TX Replay Number Counter.
Counter to keep track of the number of replays that have
occurred.
Snoop Not Required Override.
Controls the Snoop bit for master requests
0=Generate bit as normal
1=Override equation, and always set bit
2=Override equation, and always clear bit
3=Invalid
Relaxed Ordering Override.
Controls relaxed ordering bit for master requests
0=Generate bit as normal
1=Override equation, and always set bit
2=Override equation, and always clear bit
3=Invalid
Packet Packing Disable.
Back-to-back packing of TLP and DLLP
0=Place packets as close as allowable
1=Place STP/SDP in lane 0 only
Generates CRC errors from TX by zeroing CRC field.
0=Generate proper CRC
1=Generate bad CRC
Number of idle cycles between DLLP and TLP
Disables flushing TLPs when Data Link is down
0=Normal
1=Disable
Ordering rule: Let Completion Pass Posted
0=No pass
1=CPL pass
Ordering rule: Let Non-Posted Pass Posted
0=no pass
1=NP pass
Adjusts the length of the timeout interval before sending out
flow control update
0=Disable flow control
1=4x clock cycle
2=1024x clock cycle
3=4096x clock cycle
Interval length to send flow control update
PCIE_TX_REQUESTER_ID - RW - 32 bits - PCIEIND_P:0x21
Field Name
TX_REQUESTER_ID
Bits
15:0
Default
0x0
TX Requester ID Register
AMD RS690 ASIC Family Register Reference Manual
2-66
Description
Requester ID for Master transactions or Completer ID for
Slave Completions
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_TX_VENDOR_SPECIFIC - RW - 32 bits - PCIEIND_P:0x22
Field Name
TX_VENDOR_DATA
Bits
23:0
Default
0x0
TX Vendor Specific DLLP
Description
Writing to this register generates a Vendor Specific DLLP
using Vendor Data for the payload
PCIE_TX_REQUEST_NUM_CNTL - RW - 32 bits - PCIEIND_P:0x23
Field Name
TX_NUM_P_ACK
TX_NUM_P_ACK_EN
TX_NUM_NP_ACK
TX_NUM_NP_ACK_EN
Bits
5:0
7
13:8
15
Default
0x10
0x0
0x2
0x0
TX_NUM_CPL_ACK
TX_NUM_CPL_ACK_EN
TX_NUM_OUTSTANDING_NP
21:16
23
29:24
0x1c
0x0
0x2
31
0x0
TX_NUM_OUTSTANDING_NP_EN
TX Request Num Control Register
Description
Number of Posted requests sent out before ACK.
Enable for number of Posted requests sent out before ACK.
Number of Non-Posted requests sent out before ACK.
Enable for number of Non-Posted requests sent out before
ACK.
Number of Completions sent out before ACK.
Enable for number of Completions sent out before ACK.
Number of Non-posted requests sent out before
completion.
Enable for number of Non-posted requests sent out before
completion.
PCIE_TX_SEQ - R - 32 bits - PCIEIND_P:0x24
Field Name
TX_NEXT_TRANSMIT_SEQ
TX_ACKD_SEQ
TX Sequence Register
Bits
11:0
27:16
Default
0x0
0x0
Description
Next Transmit Sequence Number to send out.
Last Acknowledged Sequence Number.
PCIE_TX_REPLAY - RW - 32 bits - PCIEIND_P:0x25
Field Name
TX_REPLAY_NUM
TX_REPLAY_TIMER_OVERWRITE
TX_REPLAY_TIMER
TX Replay Register
Bits
9:0
15
31:16
Default
0x3
0x0
0x90
Description
Controls Replay Number before Link goes to Retrain.
Trigger for Replay Timer.
Replay Timer. When expired do Replay.
PCIE_TX_ACK_LATENCY_LIMIT - RW - 32 bits - PCIEIND_P:0x26
Field Name
TX_ACK_LATENCY_LIMIT
TX_ACK_LATENCY_LIMIT_OVERWRITE
Bits
7:0
8
Default
0x0
0x0
Description
ACK Latency Limit for scheduling ACK DLLP transmission
Uses the register value instead of the hardware value from
the link width.
TX ACK Latency Limit
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-67
PCI Express Registers
PCIE_P_PORT_LANE_STATUS - RW - 32 bits - PCIEIND_P:0x50
Field Name
PORT_LANE_REVERSAL (R)
Bits
0
Default
0x0
PHY_LINK_WIDTH (R)
6:1
0x0
Description
Reverses lanes and controls signals associated with a port
0=Port Lane order is normal
1=Port Lane order is reversed
Link Width
0=6'b00_0000 disabled
1=6'b00_0001 x1
2=6'b00_0010 x2
3=6'b00_0100 x4
4=6'b00_1000 x8
5=6'b01_0000 x12
6=6'b10_0000 x16
Port-Lane Status register.
PCIE_FC_P - RW - 32 bits - PCIEIND_P:0x60
Field Name
Bits
7:0
15:8
PD_CREDITS
PH_CREDITS
Posted Flow Control registers.
Default
0x8
0x2
Description
Posted Data Flow Control Advertised Credits.
Posted Header Flow Control Advertised Credits.
PCIE_FC_NP - RW - 32 bits - PCIEIND_P:0x61
Field Name
NPD_CREDITS
NPH_CREDITS
Non-Posted Flow Control registers.
Field Name
CPLD_CREDITS
CPLH_CREDITS
Completion Flow Control registers.
Bits
7:0
15:8
Default
0x2
0x2
Description
Non-Posted Data Flow Control Advertised Credits.
Non-Posted Header Flow Control Advertised Credits.
PCIE_FC_CPL - RW - 32 bits - PCIEIND_P:0x62
Bits
7:0
15:8
Default
0x0
0x0
Description
Completion Data Flow Control Credits.
Completion Header Flow Control Credits.
PCIE_ERR_CNTL - RW - 32 bits - PCIEIND_P:0x6A
Field Name
ERR_REPORTING_DIS
ERR_GEN_INTERRUPT
SYM_UNLOCKED_EN
Bits
0
1
2
Default
0x0
0x0
0x0
Error Control registers.
AMD RS690 ASIC Family Register Reference Manual
2-68
Description
Disables PCI Express Advanced Error Reporting.
Enables Interrupt Generation for errors.
Enables Reporting of Symbol Unlocked Errors.
0=Disable reporting unlocked symbol errors
1=Report unlocked symbol errors
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_RX_CNTL - RW - 32 bits - PCIEIND_P:0x70
Field Name
RX_IGNORE_IO_ERR
RX_IGNORE_BE_ERR
RX_IGNORE_MSG_ERR
RX_IGNORE_CRC_ERR
RX_IGNORE_CFG_ERR
RX_IGNORE_CPL_ERR
RX_IGNORE_EP_ERR
RX_IGNORE_LEN_MISMATCH_ERR
RX_IGNORE_MAX_PAYLOAD_ERR
RX_IGNORE_TC_ERR
RX_IGNORE_CFG_UR
RX_IGNORE_IO_UR
RX_IGNORE_VEND0_UR
RX_NAK_IF_FIFO_FULL
RX_GEN_ONE_NAK
RX_FC_INIT_FROM_REG
RX_RCB_CPL_TIMEOUT
RX_RCB_CPL_TIMEOUT_MODE
RX Control Register
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
18:16
0x0
19
0x0
Description
Ignores Malformed I/O TLP Errors.
Ignores Malformed Byte Enable TLP Errors.
Ignores Malformed Message Error.
Ignores CRC Errors.
Ignores Malformed Configuration Errors.
Ignores Malformed Completion Errors.
Ignores Malformed EP Errors.
Ignores Malformed Length Mismatch Errors.
Ignores Malformed Maximum Payload Errors.
Ignores Malformed Traffic Class Errors.
Reserved.
Reserved.
Ignores Vendor Type 0 Messages.
Sends NAK if RX internal FIFO is full.
Generates NAK only for the first bad packet until replayed.
Flow Control Initialization from registers.
0=Init FC from FIFO sizes
1=Init FC from registers
RCB cpl timeout.
0=Disable
1=50us
2=10ms
3=25ms
4=50ms
5=100ms
6=500ms
7=1ms
PCIE_RX_LASTACK_SEQNUM - R - 32 bits - PCIEIND_P:0x84
Field Name
RX_LASTACK_SEQNUM
RX Last Acked Sequence Number register.
Bits
11:0
Default
0x0
Description
Last Acked sequence number.
PCIE_LC_CNTL - RW - 32 bits - PCIEIND_P:0xA0
Field Name
LC_CM_HI_ENABLE_COUNT
LC_DONT_ENTER_L23_IN_D0
LC_RESET_L_IDLE_COUNT_EN
LC_RESET_LINK
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
Default
0x0
1
2
3
0x1
0x0
0x0
Description
Enables count for CM_HIGH. When transmitter is to be
turned on stop when the counter reaches
CM_HI_COUNT_LIMIT_ON.
If number of lanes = 1 or 2: CM_HI_COUNT_LIMIT_ON =
12 or 10.
If number of lanes = 3 or 4: CM_HI_COUNT_LIMIT_ON =
10 or 12.
If number of lanes > 4: CM_HI_COUNT_LIMIT_ON = 10 or
15.
Do not enter L23 in D0 state.
Enables reset of electrical idle counter.
AMD RS690 ASIC Family Register Reference Manual
2-69
PCI Express Registers
LC_L0S_INACTIVITY
11:8
0x0
LC_L1_INACTIVITY
15:12
0x0
LC_PMI_TO_L1_DIS
16
0x0
LC_INC_N_FTS_EN
17
0x0
19:18
0x0
LC_FACTOR_IN_EXT_SYNC
20
0x0
LC_WAIT_FOR_PM_ACK_DIS
21
0x0
LC_WAKE_FROM_L23
LC_L1_IMMEDIATE_ACK
22
23
0x0
0x0
24
26:25
0x0
0x0
27
28
29
30
31
0x0
0x0
0x1
0x0
0x0
LC_LOOK_FOR_IDLE_IN_L1L23
LC_ASPM_TO_L1_DIS
LC_DELAY_COUNT
LC_DELAY_L0S_EXIT
LC_DELAY_L1_EXIT
LC_EXTEND_WAIT_FOR_EL_IDLE
LC_ESCAPE_L1L23_EN
LC_GATE_RCVR_IDLE
Link Control Register
AMD RS690 ASIC Family Register Reference Manual
2-70
L0s inactivity timer setting.
0=25000000
1=10
2=20
3=30
4=50
5=100
6=250
7=500
8=1000
9=2500
10=10000
11=25000
12=100000
13=250000
14=1000000
L1 inactivity timer setting.
0=250000000
1=250
2=500
3=1000
4=2500
5=5000
6=10000
7=25000
8=100000
9=250000
10=1000000
11=2500000
12=10000000
13=25000000
14=100000000
Disables the transition to L1 caused by programming
PMI_STATE to non-D0.
Enables incrementing N_FTS for each transition to
recovery.
Controls the number of clocks to wait for Electrical Idle set
in L1, L23.
0=250
1=100
2=10000
3=3000000
Factors in the extended sync bit in the calculation for the
replay timer adjustment.
Disables waiting for PM_ACK in L23 ready entry
handshake.
For upstream component, wake the link from L23 ready
Always ACK an ASPM L1 entry DLLP (i.e., never generate
PM_NAK).
Disables ASPM L1.
Controls the minimum amount of time to stay in L0s or L1.
0=255/ 4095 (Power-down)
1=1250 / 16383 (Power-down)
2=5000/ 65535 (Power-down)
3=25000 / 262143 (Power-down)
Enables staying in L0s for a minimum time.
Enables staying in L1 for a minimum time.
Waits for Electrical idle in L1/L23 ready value.
Enables L1/L23 entry escape arcs.
Ignores PHY Electrical idle detector.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_LC_STATE0 - R - 32 bits - PCIEIND_P:0xA5
Field Name
LC_CURRENT_STATE
LC_PREV_STATE1
LC_PREV_STATE2
LC_PREV_STATE3
Link Control State register.
Bits
5:0
13:8
21:16
29:24
Default
0x0
0x0
0x0
0x0
Description
Current LC State.
1st Previous LC State.
2nd Previous LC State.
3rd Previous LC State.
PCIE_LC_STATE1 - R - 32 bits - PCIEIND_P:0xA6
Field Name
LC_PREV_STATE4
LC_PREV_STATE5
LC_PREV_STATE6
LC_PREV_STATE7
Link Control State register.
Bits
5:0
13:8
21:16
29:24
Default
0x0
0x0
0x0
0x0
4th Previous LC State.
5th Previous LC State.
6th Previous LC State.
7th Previous LC State.
Description
PCIE_LC_STATE2 - R - 32 bits - PCIEIND_P:0xA7
Field Name
LC_PREV_STATE8
LC_PREV_STATE9
LC_PREV_STATE10
LC_PREV_STATE11
Link Control State register.
Field Name
LC_PREV_STATE12
LC_PREV_STATE13
LC_PREV_STATE14
LC_PREV_STATE15
Link Control State register.
Bits
5:0
13:8
21:16
29:24
Default
0x0
0x0
0x0
0x0
Description
8th Previous LC State.
9th Previous LC State.
10th Previous LC State.
11th Previous LC State.
PCIE_LC_STATE3 - R - 32 bits - PCIEIND_P:0xA8
Bits
5:0
13:8
21:16
29:24
Default
0x0
0x0
0x0
0x0
Description
12th Previous LC State.
13th Previous LC State.
14th Previous LC State.
15th Previous LC State.
PCIE_LC_STATE4 - R - 32 bits - PCIEIND_P:0xA9
Field Name
LC_PREV_STATE16
LC_PREV_STATE17
LC_PREV_STATE18
LC_PREV_STATE19
Link Control State register.
Bits
5:0
13:8
21:16
29:24
Default
0x0
0x0
0x0
0x0
Description
16th Previous LC State.
17th Previous LC State.
18th Previous LC State.
19th Previous LC State.
PCIE_LC_STATE5 - R - 32 bits - PCIEIND_P:0xAA
Field Name
LC_PREV_STATE20
LC_PREV_STATE21
LC_PREV_STATE22
LC_PREV_STATE23
Link Control State register.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
5:0
13:8
21:16
29:24
Default
0x0
0x0
0x0
0x0
Description
20th Previous LC State.
21st Previous LC State.
22nd Previous LC State.
23rd Previous LC State.
AMD RS690 ASIC Family Register Reference Manual
2-71
PCI Express Registers
PCIE_LC_TRAINING_CNTL - RW - 32 bits - PCIEIND_P:0xA1
Field Name
LC_TRAINING_CNTL
LC_LOOK_FOR_MORE_NON_MATCHIN
G_TS1
LC_POWER_STATE (R)
LC_EXTEND_WAIT_FOR_SKP
Bits
3:0
Default
0x0
4
0x0
10:8
16
0x0
0x1
LC Training Control Register
Description
Training control bits in training sets.
0=Reserved
1=Disable Link
2=Loopback
3=Disable Scrambling.
The training control signal will be asserted in the TS when
the associated bit is set to 1.
Looks for more non-matching TS1 ordered sets.
Link Power state.
Extends the timer when in Rcv_L0s_Skp state. The bit is
inverted before being used.
PCIE_LC_LINK_WIDTH_CNTL - RW - 32 bits - PCIEIND_P:0xA2
Field Name
LC_LINK_WIDTH
LC_LINK_WIDTH_RD (R)
LC_RECONFIG_ARC_MISSING_ESCAPE
LC_RECONFIG_NOW
LC_RECONFIG_LATER
LC_SHORT_RECONFIG_EN
Link Width Control.
Bits
2:0
6:4
7
8
9
11
Default
0x6
0x0
0x0
0x0
0x0
0x0
Reserved.
Read back link width.
Reserved.
Reserved.
Reserved.
Reserved.
Description
PCIE_LC_N_FTS_CNTL - RW - 32 bits - PCIEIND_P:0xA3
Field Name
LC_XMIT_N_FTS
LC_XMIT_N_FTS_OVERRIDE_EN
LC_XMIT_N_FTS_LIMIT
Bits
7:0
8
23:16
Default
0xc
0x0
0xff
LC_N_FTS (R)
LC Number of FTS Control
31:24
0x0
Description
Number of FTS to override the strap value
Enables the previous field to override the strap value.
Limits the number of FTS that can increment to when
incrementing is enabled.
Number of FTS captured from the other end of the link.
PCIE_VENDOR_ID - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x0]
Field Name
VENDOR_ID (R)
Bits
15:0
Default
0x1002
AMD RS690 ASIC Family Register Reference Manual
2-72
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_DEVICE_ID - R - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x2]
Field Name
DEVICE_ID
Bits
15:0
Default
0x0
Description
PCIE_COMMAND - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x4]
Field Name
IO_ACCESS_EN
Bits
0
Default
0x0
MEM_ACCESS_EN
1
0x0
BUS_MASTER_EN
2
0x0
SPECIAL_CYCLE_EN (R)
3
0x0
MEM_WRITE_INVALIDATE_EN (R)
4
0x0
PAL_SNOOP_EN (R)
5
0x0
PARITY_ERROR_RESPONSE
6
0x0
AD_STEPPING (R)
7
0x0
SERR_EN
8
0x0
FAST_B2B_EN (R)
9
0x0
INT_DIS
10
0x0
Description
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
PCIE_STATUS - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x6]
Field Name
INT_STATUS (R)
CAP_LIST (R)
PCI_66_EN (R)
UDF_EN (R)
FAST_BACK_CAPABLE (R)
MASTER_DATA_PARITY_ERROR (R)
DEVSEL_TIMING (R)
SIGNAL_TARGET_ABORT (R)
RECEIVED_TARGET_ABORT (R)
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
3
4
5
6
Default
0x0
0x1
0x0
0x0
7
8
0x0
0x0
10:9
11
0x0
0x0
12
0x0
Description
0=Disable
1=Enable
0=Inactive
1=Active
0=No Abort
1=Target Abort
0=Inactive
1=Active
AMD RS690 ASIC Family Register Reference Manual
2-73
PCI Express Registers
RECEIVED_MASTER_ABORT (R)
13
0x0
SIGNALED_SYSTEM_ERROR
14
0x0
PARITY_ERROR_DETECTED (R)
15
0x0
0=Inactive
1=Active
0=No Error
1=SERR assert
PCIE_REVISION_ID - R - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x8]
Field Name
MINOR_REV_ID
MAJOR_REV_ID
Bits
3:0
7:4
Default
0x0
0x0
Description
PCIE_REGPROG_INF - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x9]
Field Name
REG_LEVEL_PROG_INF (R)
Bits
7:0
Default
0x0
Description
PCIE_SUB_CLASS - R - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xA]
Field Name
SUB_CLASS_INF
Bits
7:0
Default
0x0
Description
PCIE_BASE_CODE - R - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xB]
Field Name
BASE_CLASS_CODE
Bits
7:0
Default
0x0
Description
PCIE_CACHE_LINE - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xC]
Field Name
CACHE_LINE_SIZE
Bits
7:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-74
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_LATENCY - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xD]
Field Name
LATENCY_TIMER (R)
Bits
7:0
Default
0x0
Description
PCIE_HEADER - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xE]
Field Name
HEADER_TYPE (R)
DEVICE_TYPE (R)
Bits
6:0
7
Default
0x1
0x0
Description
0=Single-Function Device
1=Multi-Function Device
PCIE_BIST - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xF]
Field Name
BIST_COMP (R)
BIST_STRT (R)
BIST_CAP (R)
Bits
3:0
6
7
Default
0x0
0x0
0x0
Description
SUB_BUS_NUMBER_LATENCY - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x18]
Field Name
PRIMARY_BUS
Bits
7:0
Default
0x0
SECONDARY_BUS
15:8
0x0
SUB_BUS_NUM
23:16
0x0
SECONDARY_LATENCY_TIMER (R)
31:24
0x0
Subordinate Bus Number Latency
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Primary Bus Number register records the bus number of the
PCI bus segment to which the primary interface of the
bridge is connected.
Secondary Bus Number register records the bus number of
the PCIE bus segment to which the secondary interface of
the bridge is connected.
Subordinate Bus Number register records the bus number
of the highest numbered PCI bus segment which is behind
the bridge.
The register field does not apply to PCI Express. It is
hardwired to 0.
AMD RS690 ASIC Family Register Reference Manual
2-75
PCI Express Registers
IO_BASE_LIMIT - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x1C]
Field Name
IO_BASE_TYPE (R)
Bits
3:0
Default
0x1
Description
0=16-bit
1=32-bit
IO_BASE
7:4
0x0
I/O Base Register
IO_LIMIT_TYPE (R)
11:8
0x1
0=16-bit
1=32-bit
IO_LIMIT
15:12
0x0
I/O Limit Register
I/O Base Register Limit is used by the bridge to determine when to forward I/O transactions from one interface to the other.
SECONDARY_STATUS - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x1E]
Description
Indicates the presence of an extended capability list item.
Since all PCI Express devices are required to implement
the PCI Express capability structure, this bit must be set to
1.
PCI_66_EN (R)
5
0x0
This bit does not apply to PCI Express. It is hardwired to 0.
UDF_EN (R)
6
0x0
User Defined Status Enable.
0=Disable
1=Enable
FAST_BACK_CAPABLE (R)
7
0x0
This bit does not apply to PCI Express. It is hardwired to 0.
MASTER_DATA_PARITY_ERROR
8
0x0
This bit is set by Requestor if its Parity Error Enable bit is
set and either of the following two conditions occurs:
1) Requestor receives a Completion marked poisoned
2) Requestor poisons a write Request
0=No error
1=Parity error
DEVSEL_TIMING (R)
10:9
0x0
This register field does not apply to PCI Express. It is
hardwired to 0.
SIGNAL_TARGET_ABORT (R)
11
0x0
This bit is set when a device completes a Request using
Completer Abort Completion Status.
0=No Abort
1=Target Abort asserted
RECEIVED_TARGET_ABORT
12
0x0
This bit is set when a Requestor receives a Completion with
Unsupported Request Completion Status.
0=No CA Received
1=Received Completion Abort
RECEIVED_MASTER_ABORT
13
0x0
This bit is set when a Requestor receives a Completion with
Unsupported Request Completion Status.
0=No UR Received
1=Received Unsupported Request
RECEIVED_SYSTEM_ERROR
14
0x0
This bit reports the detection of an system error on the
secondary interface of the bridge. 1 is asserted if a system
error has been detected.
0=No Error
1=Sent Error Message
PARITY_ERROR_DETECTED
15
0x0
This bit is set when a device sends an ERR_FATAL or
ERR_NONFATAL Message, and the SERR Enable bit in
the Command register is 1.
0=No Error
1=Received Poisoned TLP
Secondary Status Register. These bits reflect status conditions of the secondary interface
CAP_LIST (R)
Field Name
Bits
4
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-76
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
MEM_BASE_LIMIT - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x20]
Field Name
MEM_BASE_TYPE (R)
Bits
3:0
Default
0x0
MEM_BASE_31_20
MEM_LIMIT_TYPE (R)
15:4
19:16
0x0
0x0
Description
0=32-bit
1=64-bit
0=32-bit
1=64-bit
MEM_LIMIT_31_20
31:20
0x0
Memory Limit Register defines a memory mapped I/O address range which is used by the bridge to determine when to forward
memory transactions from one interface to the other.
PREF_BASE_LIMIT - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x24]
Field Name
PREF_MEM_BASE_TYPE (R)
Bits
3:0
Default
0x1
PREF_MEM_BASE_31_20
PREF_MEM_LIMIT_TYPE (R)
15:4
19:16
0x0
0x1
Description
0=32-bit
1=64-bit
0=32-bit
1=64-bit
PREF_MEM_LIMIT_31_20
31:20
0x0
Prefetchable Memory Base Limit indicates 64-bit addresses are supported.
PREF_BASE_UPPER - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x28]
Field Name
PREF_BASE_UPPER
Bits
31:0
Default
0x0
Description
PREF_LIMIT_UPPER - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x2C]
Field Name
PREF_LIMIT_UPPER
Bits
31:0
Default
0x0
Description
IO_BASE_LIMIT_HI - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x30]
Field Name
IO_BASE_31_16
IO_LIMIT_31_16
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
15:0
31:16
Default
0x0
0x0
Description
Note: Bits [15:9] of this field are hardwired to 0.
Note: Bits [15:9] of this field are hardwired to 0.
AMD RS690 ASIC Family Register Reference Manual
2-77
PCI Express Registers
IRQ_BRIDGE_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x3E]
Field Name
PARITY_RESPONSE_EN
Bits
0
Default
0x0
SERR_EN
1
0x0
ISA_EN
2
0x0
VGA_EN
3
0x0
MASTER_ABORT_MODE (R)
5
0x0
SECONDARY_BUS_RESET
6
0x0
FAST_B2B_EN (R)
7
0x0
Description
Parity Error Response Enable controls the response to
Poisoned TLPs.
System Error Enable controls the forwarding of ERR_COR,
ERR_NONFATAL and ERR_FATAL from secondary to
primary
ISA Enable modifies the response by the bridge to ISA I/O
addresses.
VGA Enable modifies the response by the bridge to VGA
compatible addresses.
Master Abort Mode does not apply to PCI Express.
Hardwired to 0.
Secondary Bus Reset triggers a hot reset on the
corresponding PCI Express Port.
0=Run
1=Reset
Fast Back-to-Back Transactions Enable does not apply to
PCI Express. Hardwired to 0.
0=Disable
1=Enable
Bridge Control Register
CAP_PTR - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x34]
Field Name
CAP_PTR (R)
Bits
7:0
Default
0x50
Capability Pointer
Description
Pointer to a linked list of additional capabilities implemented
by this device.
50=Point to PM Capability
PCIE_INTERRUPT_LINE - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x3C]
Field Name
INTERRUPT_LINE
Bits
7:0
Default
0xff
Description
PCIE_INTERRUPT_PIN - RW - 8 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x3D]
Field Name
INTERRUPT_PIN
Bits
7:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-78
Description
Note: Bits [7:3] of this field are hardwired to 0.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PMI_CAP_LIST - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x50]
CAP_ID (R)
Field Name
NEXT_PTR (R)
Power Management Capbility List
Bits
7:0
Default
0x1
15:8
0x58
Description
Capability ID Must be set to 01h.
1=PCIE Power Management Registers
Next Capability Pointer.
PMI_CAP - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x52]
VERSION (R)
Field Name
Bits
2:0
Default
0x3
PME_CLOCK (R)
DEV_SPECIFIC_INIT (R)
AUX_CURRENT
D1_SUPPORT (R)
3
5
8:6
9
0x0
0x0
0x0
0x0
D2_SUPPORT (R)
10
0x0
15:11
0x19
PME_SUPPORT (R)
Power Management Capabilities Register
Description
Version.
3=PMI Spec 1.2
This bit does not apply to PCI Express. It is hardwired to 0.
Device Specific Initialization
AUX Current
D1 Support
1=Support D1 PM State.
D2 Support
1=Support D2 PM State.
For a device, this indicates the power states in which the
device may generate a PME.
PMI_STATUS_CNTL - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x54]
Field Name
POWER_STATE
NO_SOFT_RESET (R)
PME_EN
DATA_SELECT
DATA_SCALE (R)
PME_STATUS
B2_B3_SUPPORT (R)
BUS_PWR_EN (R)
Bits
1:0
3
8
12:9
14:13
15
22
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
23
0x0
PMI_DATA (R)
31:24
Power Management Status/Control Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
0x0
Description
Power State.
PME Enable.
Data Select.
Data Scale.
PME Status.
B2/B3 support does not apply to PCI Express. It is
hardwired to 0.
Bus Power/Clock Control Enable Does not apply to PCI
Express. Hardwired to 0.
Data.
AMD RS690 ASIC Family Register Reference Manual
2-79
PCI Express Registers
PCIE_CAP_LIST - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x58]
Field Name
Description
Indicates the PCI Express Capability structure. This field
must return a Capability ID of 10h indicating that this is a
PCI Express Capability structure.
10=PCI Express capable
NEXT_PTR (R)
15:8
0x80
Next Capability Pointer. The offset to the next PCI capability
structure or 00h if no other items exist in the linked list of
capabilities.
The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 2.3 configuration space
capability list.
CAP_ID (R)
Bits
7:0
Default
0x10
PCIE_CAP - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x5A]
Description
Indicates PCI-SIG defined PCI Express capability structure
version number.
0=PCI Express Cap Version
DEVICE_TYPE (R)
7:4
0x4
Indicates the type of PCI Express logical device.
0=PCI Express Endpoint
4=PCI Express RootComplex
SLOT_IMPLEMENTED
8
0x0
Indicates that the PCI Express Link associated with this
Port is connected to a slot
INT_MESSAGE_NUM (R)
13:9
0x0
Interrupt Message Number.
The PCI Express Capabilities register identifies PCI Express device type and associated capabilities.
VERSION (R)
Field Name
Bits
3:0
Default
0x1
DEVICE_CAP - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x5C]
Field Name
MAX_PAYLOAD_SUPPORT (R)
Bits
2:0
Default
0x0
PHANTOM_FUNC (R)
4:3
0x0
EXTENDED_TAG (R)
5
0x1
L0S_ACCEPTABLE_LATENCY (R)
8:6
0x0
L1_ACCEPTABLE_LATENCY (R)
11:9
0x0
15
0x0
ROLE_BASED_ERR_REPORTING (R)
AMD RS690 ASIC Family Register Reference Manual
2-80
Description
Indicates the maximum payload size that the device can
support for TLPs.
0=128B size
Indicates the support for use of unclaimed function numbers
to extend the number of outstanding transactions allowed
by logically combining unclaimed function numbers with the
Tag identifier.
0=No Phantom Functions
Indicates the maximum supported size of the Tag field as a
Requester.
0=8 Bit Tag Supported
Indicates the acceptable total latency that an Endpoint can
withstand due to the transition from L0s state to the L0
state.
Indicates the acceptable latency that an Endpoint can
withstand due to the transition from L1 state to the L0 state.
0=Role-Based Error Reporting Disabled
1=Role-Based Error Reporting Enabled
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
CAPTURED_SLOT_POWER_LIMIT (R)
25:18
0x0
(Upstream Ports only) In combination with the Slot Power
Limit Scale value, specifies the upper limit on power
supplied by slot.
CAPTURED_SLOT_POWER_SCALE (R)
27:26
0x0
Specifies the scale used for the Slot Power Limit Value.
The Device Capabilities register identifies PCI Express device specific capabilities.
DEVICE_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x60]
Field Name
CORR_ERR_EN
Bits
0
Default
0x0
NON_FATAL_ERR_EN
1
0x0
FATAL_ERR_EN
2
0x0
USR_REPORT_EN
3
0x0
RELAXED_ORD_EN
4
0x1
MAX_PAYLOAD_SIZE
7:5
0x0
EXTENDED_TAG_EN
8
0x0
PHANTOM_FUNC_EN (R)
9
0x0
AUX_POWER_PM_EN (R)
10
0x0
NO_SNOOP_EN
11
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Controls the reporting of correctable errors. The default
value of this field is 0.
0=Disable
1=Enable
Controls the reporting of Non-fatal errors. The default value
of this field is 0.
0=Disable
1=Enable
Controls the reporting of Fatal errors. The default value of
this field is 0.
0=Disable
1=Enable
Enables the reporting of Unsupported Requests. The
default value of this field is 0.
0=Disable
1=Enable
If this bit is set, the device is permitted to set the Relaxed
Ordering bit in the Attributes field of transactions it initiates
that do not require strong write ordering. The default value
of this bit is 1.
0=Disable
1=Enable
Sets maximum TLP payload size for the device. The default
value of this field is 000b.
0=128B size
Enables a device to use an 8-bit Tag field as a requester. If
the bit is cleared, the device is restricted to a 5-bit Tag field.
The default value of this field is 0.
0=Disable
1=Enable
Enables a device to use unclaimed functions as Phantom
Functions to extend the number of outstanding transaction
identifiers. If the bit is cleared, the device is not allowed to
use Phantom Functions.
0=Disable
1=Enable
Enables a device to draw AUX power independent of PME
AUX power.
0=Disable
1=Enable
If this bit is set to 1, the device is permitted to set the No
Snoop bit in the Requester Attributes of transactions it
initiates that do not require hardware enforced cache
coherency. The default value of this bit is 1.
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
2-81
PCI Express Registers
MAX_REQUEST_SIZE (R)
14:12
0x0
Sets the maximum Read Request size for the Device as a
Requester. The default value of this field is 010b.
0=128B size
BRIDGE_CFG_RETRY_EN (R)
15
0x0
0=Disable
1=Enable
The Device Control register controls PCI Express device specific parameters.
DEVICE_STATUS - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x62]
Field Name
CORR_ERR
NON_FATAL_ERR
FATAL_ERR
USR_DETECTED
AUX_PWR
Bits
0
1
2
3
4
Default
0x0
0x0
0x0
0x0
0x0
Description
Indicates status of correctable errors detected.
Indicates status of Nonfatal errors detected.
Indicates status of Fatal errors detected.
Indicates that the device received an Unsupported Request.
Devices that require AUX power report this bit as set if AUX
power is detected by the device.
TRANSACTIONS_PEND (R)
5
0x0
Endpoints: This bit, when set, indicates that the device has
issued Non-Posted Requests which have not been
completed.
Root and Switch Ports: This bit, when set, indicates that a
Port has issued Non-Posted Requests on its own behalf
(using the Port's own Requester ID) which have not been
completed.
The Device Status register provides information about PCI Express device specific parameters.
LINK_CAP - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x64]
Field Name
LINK_SPEED (R)
Bits
3:0
Default
0x1
LINK_WIDTH (R)
9:4
0x0
PM_SUPPORT (R)
11:10
0x3
L0S_EXIT_LATENCY (R)
14:12
0x1
L1_EXIT_LATENCY (R)
17:15
0x2
18
19
0x0
0x0
20
31:24
0x1
0x0
CLOCK_POWER_MANAGEMENT (R)
SURPRISE_DOWN_ERR_REPORTING_
EN (R)
DL_ACTIVE_REPORTING_CAPABLE (R)
PORT_NUMBER (R)
Description
Indicates the maximum Link speed of the given PCI
Express Link.
1=2.5 Gb/s
Indicates the maximum width of the given PCI Express Link.
1=x1
2=x2
4=x4
8=x8
12=x12
16=x16
32=x32
Indicates the level of ASPM supported on the given PCI
Express Link.
Indicates the L0s exit latency for the given PCI Express
Link. The value reported indicates the length of time this
Port requires to complete transition from L0s to L0.
Indicates the L0s exit latency for the given PCI Express
Link. The value reported indicates the length of time this
Port requires to complete transition from L0s to L0.
Indicates the PCI Express Port number for the given PCI
Express Link.
The Link Capabilities register identifies PCI Express Link specific capabilities.
AMD RS690 ASIC Family Register Reference Manual
2-82
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
LINK_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x68]
Field Name
PM_CONTROL
Bits
1:0
Default
0x0
READ_CPL_BOUNDARY (R)
3
0x0
LINK_DIS
4
0x0
RETRAIN_LINK (W)
5
0x0
COMMON_CLOCK_CFG
6
0x0
EXTENDED_SYNC
7
0x0
Description
Controls the level of ASPM supported on the given PCI
Express Link. Defined encodings are as follows:
00b=Disabled
01b=L0s Entry Enabled
10b=L1 Entry Enabled
11b=L0s and L1 Entry Enabled
Read Completion Boundary. Indicates the RCB value for
the Root Port.
0=64 Byte
1=128 Byte
Disables the Link when set to 1b. The default value of this
field is 0b.
A write of 1b to this bit initiates Link retraining by directing
the Physical Layer LTSSM to the Recovery state. Reads of
this bit always return 0b.
Indicates that this component and the component at the
opposite end of this Link are operating with a distributed
common reference clock. The default value of this field is
0b.
Forces the transmission of 4096 FTS ordered sets in the
L0s state, followed by a single SKP ordered set.
CLOCK_POWER_MANAGEMENT_EN
8
0x0
(R)
The Link Control register controls PCI Express Link specific parameters.
LINK_STATUS - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x6A]
Field Name
NEGOTIATED_LINK_SPEED (R)
Bits
3:0
Default
0x1
NEGOTIATED_LINK_WIDTH (R)
9:4
0x0
LINK_TRAINING (R)
11
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Indicates the negotiated Link speed of the given PCI
Express Link
0=2.5 Gb/s
This field indicates the negotiated width of the given PCI
Express Link. The defined encodings are as follows:
000001b X1, 000010b X2, 000100b X4, 001000b X8,
001100b X12, 010000b X16, and 100000b X32. All other
encodings are reserved.
1=x1
2=x2
4=x4
8=x8
12=x12
16=x16
32=x32
This read-only bit indicates that Link training is in progress
(Physical Layer LTSSM in Configuration or
Recovery state), or that 1b was written to the Retrain Link
bit but Link training has not yet begun. The hardware clears
this bit once Link training is complete.
AMD RS690 ASIC Family Register Reference Manual
2-83
PCI Express Registers
SLOT_CLOCK_CFG (R)
12
0x1
This bit indicates that the component uses the same
physical reference clock that the platform provides on the
connector. If the device uses an independent clock,
irrespective of the presence of a reference on the
connector, this bit must be clear.
0=Diff Clock
1=Same Clock
DL_ACTIVE (R)
13
0x0
The Link Status register provides information about PCI Express Link specific parameters.
SLOT_CAP - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x6C]
Field Name
ATTN_BUTTON_PRESENT (R)
Bits
0
Default
0x0
PWR_CONTROLLER_PRESENT (R)
1
0x0
MRL_SENSOR_PRESENT (R)
2
0x0
ATTN_INDICATOR_PRESENT (R)
3
0x0
PWR_INDICATOR_PRESENT (R)
4
0x0
HOTPLUG_SURPRISE
5
0x0
HOTPLUG_CAPABLE
6
0x0
SLOT_PWR_LIMIT_VALUE
14:7
0x0
SLOT_PWR_LIMIT_SCALE
ELECTROMECH_INTERLOCK_PRESEN
T
NO_COMMAND_COMPLETED_SUPPO
RTED
PHYSICAL_SLOT_NUM
16:15
17
0x0
0x0
18
0x0
31:19
0x0
Description
Indicates that an Attention Button is implemented on the
chassis for this slot.
Indicates that a Power Controller is implemented for this
slot.
Indicates that an Manually-operated Retention Latch
Sensor is implemented on the chassis for this slot.
Indicates that an Attention Indicator is implemented on the
chassis for this slot.
Indicates that a Power Indicator is implemented on the
chassis for this slot.
Indicates that a device present in this slot might be removed
from the system without any prior notification.
Indicates that this slot is capable of supporting Hot-Plug
operations.
In combination with the Slot Power Limit Scale value, this
register field specifies the upper limit on power supplied by
slot.
Specifies the scale used for the Slot Power Limit Value
This hardware initialized field indicates the physical slot
number attached to this Port.
The Slot Capabilities register identifies PCI Express slot specific capabilities.
SLOT_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x70]
Field Name
ATTN_BUTTON_PRESSED_EN
Bits
0
Default
0x0
PWR_FAULT_DETECTED_EN (R)
MRL_SENSOR_CHANGED_EN (R)
PRESENCE_DETECT_CHANGED_EN
1
2
3
0x0
0x0
0x0
COMMAND_COMPLETED_INTR_EN
4
0x0
HOTPLUG_INTR_EN
5
0x0
AMD RS690 ASIC Family Register Reference Manual
2-84
Description
Enables the generation of Hot-Plug interrupt or wakeup
event on an attention button pressed event.
Enables the generation of Hot-Plug interrupt or wakeup
event on a presence detect changed event.
Enables the generation of Hot-Plug interrupt when a
command is completed by the Hot-Plug Controller.
Enables the generation of Hot-Plug interrupt on enabled
Hot-Plug events.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
ATTN_INDICATOR_CNTL
7:6
0x3
PWR_INDICATOR_CNTL
9:8
0x3
PWR_CONTROLLER_CNTL (R)
10
0x0
Reads to this register return the current state of the
Attention Indicator. Writes to this register set the Attention
Indicator.
Reads to this register return the current state of the Power
Indicator. Writes to this register set the Power Indicator.
When read this register returns the current state of the
Power applied to the slot. When written it sets the power
state of the slot per the defined encodings.
ELECTOMECH_INTERLOCK_CNTL (R)
11
0x0
DL_STATE_CHANGED_EN
12
0x0
The Slot Control register controls PCI Express Slot specific parameters
SLOT_STATUS - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x72]
Field Name
ATTN_BUTTON_PRESSED
PRESENCE_DETECT_CHANGED
COMMAND_COMPLETED
Bits
0
3
4
Default
0x0
0x0
0x0
Description
This bit is set when the attention button is pressed.
This bit is set when a Presence Detect change is detected.
This bit is set when the Hot-Plug Controller completes an
issued command.
Indicates the presence of a card in the slot.
PRESENCE_DETECT_STATE (R)
6
0x0
7
0x0
ELECTROMECH_INTERLOCK_STATUS
(R)
DL_STATE_CHANGED
8
0x0
The Slot Status register provides information about PCI Express Slot specific parameters
ROOT_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x74]
Field Name
SERR_ON_CORR_ERR_EN
Bits
0
Default
0x0
SERR_ON_NONFATAL_ERR_EN
1
0x0
SERR_ON_FATAL_ERR_EN
2
0x0
PM_INTERRUPT_EN
3
0x0
Description
System Error on Correctable Error Enable.
indicates that a System Error should be generated if a
correctable error is reported by any of the devices in the
hierarchy associated with this Root Port.
System Error on Non-Fatal Error Enable.
Indicates that a System Error should be generated if a
Non-fatal error is reported by any of the devices in the
hierarchy associated with this Root Port.
System Error on Fatal Error Enable.
Indicates that a System Error should be generated if a Fatal
error is reported by any of the devices in the hierarchy
associated with this Root Port.
PME Interrupt Enable.
Enables interrupt generation upon receipt of a PME
Message.
CRS_SOFTWARE_VISIBILITY_EN
4
0x0
The Root Control register controls PCI Express Root Complex specific parameters.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-85
PCI Express Registers
ROOT_STATUS - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x78]
Field Name
PME_REQUESTOR_ID (R)
PME_STATUS
Bits
15:0
16
Default
0x0
0x0
Description
Indicates the PCI requestor ID of the last PME requestor.
Indicates that PME was asserted by the requestor ID
indicated in the PME Requestor ID field.
PME_PENDING (R)
17
0x0
This read-only bit indicates that another PME is pending
when the PME Status bit is set.
The Root Status register provides information about PCI Express device specific parameters.
MSI_CAP_LIST - R - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x80]
Field Name
Bits
CAP_ID
7:0
NEXT_PTR
15:8
Message Signaled Interrupt Capability Registers
Default
0x5
0xb0
Description
Identifies if a device function is MSI capable.
Pointer to the next item on the capabilities list.
PCIE_MSI_MSG_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x82]
Bits
0
Default
0x0
MSI_MULTI_CAP (R)
3:1
0x0
MSI_MULTI_EN
6:4
0x0
7
0x0
MSI_EN
MSI_64BIT (R)
Field Name
AMD RS690 ASIC Family Register Reference Manual
2-86
Description
0=Disable
1=Enable
0=1 message allocated
1=2 messages allocated
2=4 messages allocated
3=8 messages allocated
4=16 messages allocated
5=32 messages allocated
6=Reserved
7=Reserved
0=1 message allocated
1=2 messages allocated
2=4 messages allocated
3=8 messages allocated
4=16 messages allocated
5=32 messages allocated
6=Reserved
7=Reserved
0=Not capable of generating 1 64-bit message address
1=Capable of generating 1 64-bit message address
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_MSI_MSG_ADDR_LO - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x84]
Field Name
MSI_MSG_ADDR_LO
Bits
31:2
Default
0x0
Description
PCIE_MSI_MSG_ADDR_HI - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x88]
Field Name
MSI_MSG_ADDR_HI (R)
Bits
31:0
Default
0x0
Description
PCIE_MSI_MSG_DATA_64 - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x8C]
Field Name
MSI_DATA_64 (R)
Bits
15:0
Default
0x0
Description
PCIE_MSI_MSG_DATA - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x88]
MSI_DATA
Field Name
Bits
15:0
Default
0x0
Description
CRS_TIMER - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x90]
Field Name
CRS_DELAY
CRS_LIMIT
Configuration Request Retry Status Timer
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
23:0
31:24
Default
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-87
PCI Express Registers
IOC_CNTL - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x94]
Field Name
SLV_FORCE_RO
SLV_FORCE_SNOOP
SLV_FORCE_ATTR_ENABLE
SLV_P2P_DIS
BM_SET_DIS
MST_STRICT_ORDER
MST_BLOCK_NSNOOP
MST_BLOCK_SNOOP
MST_RO_FORCE
MST_RO_ENABLE
MST_NS_ENABLE
EXT_DEV_PRESENCE_DET
EXT_DEV_CRC_ENABLE
CRS_ENABLE
INT_ABCD_EFGH
SET_PWR_MSG_ENABLE
I/O Control
Bits
0
1
2
3
7
8
9
10
11
12
13
16
17
18
19
20
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
Slave Force Relaxed Ordering.
Slave Force Snoop / Non-Snoop.
Slave Force Attribute Enable.
Slave Peer-to-Peer Disable.
Bus Master Set Disable.
Master Strict Ordering.
Master Block Non-Snoop.
Master Block Snoop.
Master Force Relaxed Ordering.
Master Enable Relaxed Ordering.
Master Non-Snoop Enable.
Interrupt Vector.
SSID_CAP_LIST - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xB0]
Field Name
CAP_ID (R)
NEXT_PTR (R)
Subsystem ID Capability List
Bits
7:0
15:8
Default
0xd
0xb8
Description
Capability ID.
Pointer to next capability register.
SSID_ID - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xB4]
Field Name
SUBSYSTEM_VENDOR
SUBSYSTEM_ID
Subsystem ID
Bits
15:0
31:16
Default
0x0
0x0
Subsystem Vendor.
Subsystem ID.
Description
MSI_MAP - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xB8]
Bits
7:0
Default
0x8
NEXT_PTR (R)
15:8
0x0
EN (R)
FIXD (R)
CAP_TYPE (R)
MSI Mapping Capability Register
16
17
31:27
0x1
0x1
0x15
CAP_ID (R)
Field Name
AMD RS690 ASIC Family Register Reference Manual
2-88
Description
Identifies the function as message signaled interrupt
capable. This field is read only
Pointer to the next item in the capabilities list. Must be
NULL for the final item in the list. This field is read only.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_PORT_INDEX - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xE0]
Field Name
Bits
Default
PCIE_INDEX
7:0
0x0
Index register for the PCI Express port indirect registers
Index of bifdecp.
Description
PCIE_PORT_DATA - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xE4]
Field Name
Bits
Default
PCIE_DATA
31:0
0x0
Data register for the PCI Express port indirect registers
Data of bifdecp.
Description
PCIE_ENH_ADV_ERR_RPT_CAP_HDR - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x140]
CAP_ID (R)
Field Name
Bits
15:0
Default
0x1
CAP_VER (R)
19:16
0x1
NEXT_PTR (R)
31:20
0x0
Description
This field is a PCI-SIG defined ID number that indicates the
nature and format of the extended capability.
This field is a PCI-SIG defined version number that
indicates the version of the capability structure present.
This field contains the offset to the next PCI Express
capability structure or 000h if no other items exist in the
linked list of capabilities.
Advanced Error Reporting Enhanced Capability header
PCIE_UNCORR_ERR_STATUS - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x144]
Field Name
Bits
Default
Description
DLP_ERR_STATUS
4
0x0
Data Link Protocol Error Status.
SURPDN_ERR_STATUS
5
0x0
PSN_ERR_STATUS
12
0x0
Poisoned TLP Status.
FC_ERR_STATUS
13
0x0
Flow Control Protocol Error Status.
CPL_TIMEOUT_STATUS
14
0x0
Completion Timeout Status.
CPL_ABORT_ERR_STATUS
15
0x0
Completer Abort Status.
UNEXP_CPL_STATUS
16
0x0
Unexpected Completion Status.
RCV_OVFL_STATUS
17
0x0
Receiver Overflow Status.
MAL_TLP_STATUS
18
0x0
Malformed TLP Status.
ECRC_ERR_STATUS
19
0x0
ECRC Error Status.
UNSUPP_REQ_ERR_STATUS
20
0x0
Unsupported Request Error Status.
The Uncorrectable Error Status register reports error status of individual error sources on a PCI Express device.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-89
PCI Express Registers
PCIE_UNCORR_ERR_MASK - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x148]
Field Name
Bits
Default
Description
DLP_ERR_MASK
4
0x0
Data Link Protocol Error Mask.
SURPDN_ERR_MASK
5
0x0
PSN_ERR_MASK
12
0x0
Poisoned TLP Mask.
FC_ERR_MASK
13
0x0
Flow Control Protocol Error Mask.
CPL_TIMEOUT_MASK
14
0x0
Completion Timeout Mask.
CPL_ABORT_ERR_MASK
15
0x0
Completer Abort Mask.
UNEXP_CPL_MASK
16
0x0
Unexpected Completion Mask.
RCV_OVFL_MASK
17
0x0
Receiver Overflow Mask.
MAL_TLP_MASK
18
0x0
Malformed TLP Mask.
ECRC_ERR_MASK
19
0x0
ECRC Error Mask.
UNSUPP_REQ_ERR_MASK
20
0x0
Unsupported Request Error Mask
The Uncorrectable Error Mask register controls the reporting of individual errors by the device to the PCI Express Root Complex
via a PCI Express error Message.
PCIE_UNCORR_ERR_SEVERITY - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x14C]
Field Name
Bits
Default
Description
DLP_ERR_SEVERITY
4
0x1
Data Link Protocol Error Severity.
SURPDN_ERR_SEVERITY
5
0x1
PSN_ERR_SEVERITY
12
0x0
Poisoned TLP Severity.
FC_ERR_SEVERITY
13
0x1
Flow Control Protocol Error Severity.
CPL_TIMEOUT_SEVERITY
14
0x0
Completion Timeout Error Severity.
CPL_ABORT_ERR_SEVERITY
15
0x0
Completer Abort Error Severity.
UNEXP_CPL_SEVERITY
16
0x0
Unexpected Completion Error Severity.
RCV_OVFL_SEVERITY
17
0x1
Receiver Overflow Error Severity.
MAL_TLP_SEVERITY
18
0x1
Malformed TLP Severity.
ECRC_ERR_SEVERITY
19
0x0
ECRC Error Severity.
UNSUPP_REQ_ERR_SEVERITY
20
0x0
Unsupported Request Error Severity.
The Uncorrectable Error Severity register controls whether an individual error is reported as a Nonfatal or Fatal error.
PCIE_CORR_ERR_STATUS - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x150]
Field Name
Bits
Default
Description
RCV_ERR_STATUS
0
0x0
Receiver Error Status.
BAD_TLP_STATUS
6
0x0
Bad TLP Status.
BAD_DLLP_STATUS
7
0x0
Bad DLLP Status.
REPLAY_NUM_ROLLOVER_STATUS
8
0x0
REPLAY_NUM Rollover Status.
REPLAY_TIMER_TIMEOUT_STATUS
12
0x0
Replay Timer Timeout Status.
ADVISORY_NONFATAL_ERR_STATUS
13
0x0
The Correctable Error Status register reports error status of individual correctable error sources on a PCI Express device.
AMD RS690 ASIC Family Register Reference Manual
2-90
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_CORR_ERR_MASK - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x154]
Field Name
Bits
Default
Description
RCV_ERR_MASK
0
0x0
Receiver Error Mask.
BAD_TLP_MASK
6
0x0
Bad TLP Mask.
BAD_DLLP_MASK
7
0x0
Bad DLLP Mask.
REPLAY_NUM_ROLLOVER_MASK
8
0x0
REPLAY_NUM Rollover Mask.
REPLAY_TIMER_TIMEOUT_MASK
12
0x0
Replay Timer Timeout Mask.
ADVISORY_NONFATAL_ERR_MASK
13
0x1
The Correctable Error Mask register controls reporting of individual correctable errors by device to the PCI Express Root
Complex via a PCI Express error Message.
PCIE_ADV_ERR_CAP_CNTL - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x158]
Field Name
FIRST_ERR_PTR (R)
Bits
4:0
ECRC_GEN_CAP (R)
5
ECRC_GEN_EN
6
ECRC_CHECK_CAP (R)
7
ECRC_CHECK_EN
8
Advanced Error Capabilities and Control Register
Default
0x0
0x0
0x0
0x0
0x0
Description
The First Error Pointer is a read-only register that identifies
the bit position of the first error reported in the
Uncorrectable Error Status register.
Indicates that the device is capable of generating ECRC.
Enables ECRC generation. Default value of this field is 0.
Indicates that the device is capable of checking ECRC.
Enables ECRC checking. Default value of this field is 0.
PCIE_HDR_LOG0 - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x15C]
Field Name
Bits
Default
TLP_HDR
31:0
0x0
TLP Header 1st DW.
Header Log Register captures the Header for the TLP corresponding to a detected error;
Description
PCIE_HDR_LOG1 - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x160]
Field Name
TLP_HDR
Header Log Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
TLP Header 2nd DW.
Description
AMD RS690 ASIC Family Register Reference Manual
2-91
PCI Express Registers
PCIE_HDR_LOG2 - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x164]
Field Name
TLP_HDR
Header Log Register
Bits
31:0
Default
0x0
Description
TLP Header 3rd DW.
PCIE_HDR_LOG3 - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x168]
Field Name
TLP_HDR
Header Log Register
Bits
31:0
Default
0x0
TLP Header 4th DW.
Description
PCIE_ROOT_ERR_CMD - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x16C]
Field Name
CORR_ERR_REP_EN
Bits
0
Default
0x0
NONFATAL_ERR_REP_EN
1
0x0
FATAL_ERR_REP_EN
2
0x0
Root Error Command Register
Description
Correctable Error Reporting Enable.
Enables the generation of an interrupt when a correctable
error is reported by any of the devices in the hierarchy
associated with this Root Port.
Non-Fatal Error Reporting Enable.
Enables the generation of an interrupt when a Non-fatal
error is reported by any of the devices in the hierarchy
associated with this Root Port.
Fatal Error Reporting Enable.
Enables the generation of an interrupt when a Fatal error is
reported by any of the devices in the hierarchy associated
with this Root Port.
PCIE_ROOT_ERR_STATUS - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x170]
Field Name
ERR_CORR_RCVD
Bits
0
Default
0x0
MULT_ERR_CORR_RCVD
1
0x0
ERR_FATAL_NONFATAL_RCVD
2
0x0
AMD RS690 ASIC Family Register Reference Manual
2-92
Description
Set when a correctable error Message is received and this
bit is not already set. The default value of this field is 0.
Set when a correctable error Message is received and
ERR_COR Received is already set. The default value of
this field is 0.
Set when either a Fatal or a Non-fatal error Message is
received and this bit is not already set. The default value of
this field is 0.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
MULT_ERR_FATAL_NONFATAL_RCVD
3
0x0
FIRST_UNCORRECTABLE_FATAL
4
0x0
NONFATAL_ERROR_MSG_RCVD
5
0x0
FATAL_ERROR_MSG_RCVD
6
0x0
31:27
0x0
ADV_ERR_INT_MSG_NUM (R)
Root Error Status Register
Set when either a Fatal or a Non-fatal error is received and
ERR_FATAL/NONFATAL Received is already set. The
default value of this field is 0.
Set to 1b when the first Uncorrectable error Message
received is for a Fatal error. The default value of this field is
0.
Set to 1b when one or more Non-Fatal Uncorrectable error
Messages have been received. The default value of this
field is 0.
Set to 1b when one or more Fatal Uncorrectable error
Messages have been received. The default value of this
field is 0.
Advanced Error Interrupt Message Number.
PCIE_ERR_SRC_ID - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x174]
Field Name
ERR_COR_SRC_ID (R)
Bits
15:0
Default
0x0
Description
Loaded with the Requestor ID indicated in the received
ERR_COR Message when the ERR_COR Received
register is not already set. The default value of this field is 0.
ERR_FATAL_NONFATAL_SRC_ID (R)
31:16
0x0
Loaded with the Requestor ID indicated in the received
ERR_FATAL or ERR_NONFATAL Message when the
ERR_FATAL/NONFATAL Received register is not already
set. The default value of this field is 0
The Error Source Identification register identifies the source (Requestor ID) of first correctable and uncorrectable
(Non-fatal/Fatal) errors reported in the Root Error Status register.
PCIE_VC0_RESOURCE_CAP - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x110]
Field Name
PORT_ARB_CAP
Bits
7:0
Default
0x0
REJECT_SNOOP_TRANS
15
0x0
MAX_TIME_SLOTS
21:16
0x0
PORT_ARB_TABLE_OFFSET
31:24
0x0
Description
Indicates the types of Port Arbitration supported by the VC
resource.
When set to 0, transactions with or without the No Snoop bit
set within the TLP Header are allowed on this VC.
Indicates the maximum number of time slots that the VC
resource is capable of supporting.
Indicates the location of the Port Arbitration Table
associated with the VC resource.
VC0 Resource Capability Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-93
PCI Express Registers
PCIE_VC0_RESOURCE_CNTL - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x114]
Field Name
TC_VC_MAP_TC0 (R)
TC_VC_MAP_TC1_7
LOAD_PORT_ARB_TABLE (R)
Bits
0
7:1
16
Default
0x1
0x7f
0x0
PORT_ARB_SELECT
19:17
0x0
VC_ID (R)
VC_ENABLE (R)
VC0 Resource Control Register
26:24
31
0x0
0x1
Description
Indicates the TCs that are mapped to the VC resource.
Indicates the TCs that are mapped to the VC resource.
Updates the Port Arbitration logic from the Port Arbitration
Table for the VC resource.
Configures the VC resource to provide a particular Port
Arbitration service.
Assigns a VC ID to the VC resource.
Enables a Virtual Channel.
PCIE_VC0_RESOURCE_STATUS - R - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x11A]
Field Name
PORT_ARB_TABLE_STATUS
Bits
0
Default
0x0
VC_NEGOTIATION_PENDING
1
0x1
VC0 Resource Status Register
Description
Indicates the coherency status of the Port Arbitration Table
associated with the VC resource.
Indicates whether the Virtual Channel negotiation
(initialization or disabling) is in pending state.
PCIE_DEBUG_CNTL - RW - 32 bits - PCIEIND:0x12
Field Name
DEBUG_PORT_EN
DEBUG_SELECT
Bits
7:0
Default
0x1
8
0x0
Debug Bus Control Register
AMD RS690 ASIC Family Register Reference Manual
2-94
Description
Debug Bus Port Enable
1=Port A
2=Port B
4=Port C
8=Port D
16=Port E
32=Port F
64=Port G
128=Port H
Debug Bus Select - for additional muxing (e.g. VC0 vs.
VC1)
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_WPR_CNTL - RW - 32 bits - PCIEIND:0x30
Field Name
WPR_RESET_HOT_RST_EN
WPR_RESET_LNK_DWN_EN
WPR_RESET_LNK_DIS_EN
WPR_RESET_COR_EN
WPR_RESET_REG_EN
WPR_RESET_STY_EN
WPR_RESET_PHY_EN
WPR Control Register
Bits
0
1
2
3
4
5
6
Default
0x1
0x0
0x1
0x0
0x0
0x0
0x0
Description
Enables Hot Reset feature.
Enables Link down reset feature.
Enables Link disable reset feature.
Enables external CORE reset feature.
Enables external REGISTER reset feature.
Enables external Stickybit Register reset feature.
Enables external PHY reset feature.
PCIE_PERF_LATENCY_CNTL - RW - 32 bits - PCIEIND:0x70
Bits
0
Default
0x0
TIMER_SHADOW_WR (W)
1
0x0
TIMER_RESET (W)
2
0x0
6:4
0x0
PORT_MODE
7
0x0
SNOOP
8
0x0
NO_SNOOP
9
0x0
MEM_REQ
10
0x0
CFG_IO_REQ
11
0x0
REQ_ID_MODE
12
0x0
TIMER_EN
Field Name
PORT_NUM
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Enables Latency Timer
0=Disable timer
1=Enable timer
Shadow Register Write.
Write 1 to update shadow registers
0=N/A
1=Write 1 to shadow write
Resets Latency Timer.
Write 1 to clear latency timer counters
0=N/A
1=Write 1 to reset
Port Number.
Should always be programmed to 000
0=Port 0
1=Port 1
2=Port 2
3=Port 3
4=Port 4
5=Port 5
Port Mode.
Should always be programmed to 0
0=All ports
1=Single port
Excludes/Includes Snoop requests
0=Do not include snoop requests
1=Include snoop requests
Excludes/Includes Non-Snoop requests
0=Do not include no snoop requests
1=Include no snoop requests
Excludes/Includes Memory requests
0=Do not include MEM requests
1=Include MEM requests
Excludes/Includes CFG and I/O requests
0=Do not include CFG or I/O requests
1=Include CFG or I/O requests
Requester ID Mode.
Unfiltered/Filtered by Requester ID
0=Do not filter by requester ID
1=Filter by requester ID
AMD RS690 ASIC Family Register Reference Manual
2-95
PCI Express Registers
TAG_MODE
13
0x0
CPL_MODE
14
0x0
23:16
0x0
TRAFFIC_CLASS
Latency Timer Control Register
Tag Mode.
Unfiltered/Filters by Tag
0=Do not filter by tag
1=Filter by tag
Completion Mode.
First Data/Last Data
0=First Data
1=Last Data
Traffic Class filter bits
PCIE_PERF_LATENCY_REQ_ID - RW - 32 bits - PCIEIND:0x71
Field Name
Bits
REQUESTER_ID
15:0
REQUESTER_MASK
31:16
Filter to select requests for a particular Requester ID
Default
0x0
0xffff
Description
Requester ID Value
Requester ID Mask
PCIE_PERF_LATENCY_TAG - RW - 32 bits - PCIEIND:0x72
Field Name
TAG
TAG_MASK
Filter to select requests for a particular Tag
Bits
7:0
15:8
Default
0x0
0xff
Description
Tag Value
Tag Mask
PCIE_PERF_LATENCY_THRESHOLD - RW - 32 bits - PCIEIND:0x73
Field Name
Bits
Default
Description
THRESHOLD
15:0
0xffff
Latency Threshold value in TXCLKs
Latency Threshold used to count requests outside of acceptable time limit
PCIE_PERF_LATENCY_MAX - R - 32 bits - PCIEIND:0x74
Field Name
Bits
PEAK
15:0
REQUESTER_ID
31:16
Current peak latency time with Requester ID
Default
0x0
0x0
Description
Number of TXCLKs for peak latency request
Requester ID for peak latency request
PCIE_PERF_LATENCY_TIMER_LO - R - 32 bits - PCIEIND:0x75
Field Name
Bits
Default
TIMER_LO
31:0
0x0
Counter for cumulative request latency - LOWER BITS
AMD RS690 ASIC Family Register Reference Manual
2-96
Description
Lower 32 bits of cumulative latency timer
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_PERF_LATENCY_TIMER_HI - R - 32 bits - PCIEIND:0x76
TIMER_HI
Field Name
Bits
31:0
Default
0x0
Description
Upper 32 bits of cumulative latency timer.
Note: Bits [31:16] of this field are hardwired to 0.
Counter for cumulative request latency - UPPER BITS
PCIE_PERF_LATENCY_COUNTER0 - R - 32 bits - PCIEIND:0x77
Field Name
NUM_REQ
Counter for number of requests measured
Bits
31:0
Default
0x0
Description
Number of requests measured
PCIE_PERF_LATENCY_COUNTER1 - R - 32 bits - PCIEIND:0x78
Field Name
Bits
Default
NUM_EXCEED
31:0
0x0
Counter for number of requests exceeding latency threshold
Description
Number of requests exceeding latency threshold
PCIE_PRBS23_BITCNT_0 - RW - 32 bits - PCIEIND:0xD0
Field Name
PRBS23_BITCNT_0
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_1 - RW - 32 bits - PCIEIND:0xD1
Field Name
PRBS23_BITCNT_1
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_2 - RW - 32 bits - PCIEIND:0xD2
Field Name
PRBS23_BITCNT_2
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_3 - RW - 32 bits - PCIEIND:0xD3
Field Name
PRBS23_BITCNT_3
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-97
PCI Express Registers
PCIE_PRBS23_BITCNT_4 - RW - 32 bits - PCIEIND:0xD4
Field Name
PRBS23_BITCNT_4
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_5 - RW - 32 bits - PCIEIND:0xD5
Field Name
PRBS23_BITCNT_5
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_6 - RW - 32 bits - PCIEIND:0xD6
Field Name
PRBS23_BITCNT_6
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_7 - RW - 32 bits - PCIEIND:0xD7
Field Name
PRBS23_BITCNT_7
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_8 - RW - 32 bits - PCIEIND:0xD8
Field Name
PRBS23_BITCNT_8
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_9 - RW - 32 bits - PCIEIND:0xD9
Field Name
PRBS23_BITCNT_9
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_10 - RW - 32 bits - PCIEIND:0xDA
Field Name
PRBS23_BITCNT_10
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-98
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_PRBS23_BITCNT_11 - RW - 32 bits - PCIEIND:0xDB
Field Name
PRBS23_BITCNT_11
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_12 - RW - 32 bits - PCIEIND:0xDC
Field Name
PRBS23_BITCNT_12
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_13 - RW - 32 bits - PCIEIND:0xDD
Field Name
PRBS23_BITCNT_13
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_14 - RW - 32 bits - PCIEIND:0xDE
Field Name
PRBS23_BITCNT_14
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_BITCNT_15 - RW - 32 bits - PCIEIND:0xDF
Field Name
PRBS23_BITCNT_15
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_0 - R - 32 bits - PCIEIND:0xE0
Field Name
PRBS23_ERRCNT_0
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_1 - R - 32 bits - PCIEIND:0xE1
Field Name
PRBS23_ERRCNT_1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-99
PCI Express Registers
PCIE_PRBS23_ERRCNT_2 - R - 32 bits - PCIEIND:0xE2
Field Name
PRBS23_ERRCNT_2
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_3 - R - 32 bits - PCIEIND:0xE3
Field Name
PRBS23_ERRCNT_3
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_4 - R - 32 bits - PCIEIND:0xE4
Field Name
PRBS23_ERRCNT_4
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_5 - R - 32 bits - PCIEIND:0xE5
Field Name
PRBS23_ERRCNT_5
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_6 - R - 32 bits - PCIEIND:0xE6
Field Name
PRBS23_ERRCNT_6
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_7 - R - 32 bits - PCIEIND:0xE7
Field Name
PRBS23_ERRCNT_7
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_8 - R - 32 bits - PCIEIND:0xE8
Field Name
PRBS23_ERRCNT_8
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-100
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_PRBS23_ERRCNT_9 - R - 32 bits - PCIEIND:0xE9
Field Name
PRBS23_ERRCNT_9
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_10 - R - 32 bits - PCIEIND:0xEA
Field Name
PRBS23_ERRCNT_10
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_11 - R - 32 bits - PCIEIND:0xEB
Field Name
PRBS23_ERRCNT_11
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_12 - R - 32 bits - PCIEIND:0xEC
Field Name
PRBS23_ERRCNT_12
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_13 - R - 32 bits - PCIEIND:0xED
Field Name
PRBS23_ERRCNT_13
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_14 - R - 32 bits - PCIEIND:0xEE
Field Name
PRBS23_ERRCNT_14
Bits
31:0
Default
0x0
Description
PCIE_PRBS23_ERRCNT_15 - R - 32 bits - PCIEIND:0xEF
Field Name
PRBS23_ERRCNT_15
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-101
PCI Express Registers
PCIE_PRBS23_CLR - RW - 32 bits - PCIEIND:0xF0
Field Name
PRBS23_CLR
Bits
15:0
Default
0x0
Description
PCIE_PRBS23_ERRSTAT - R - 32 bits - PCIEIND:0xF1
Field Name
PRBS23_ERRSTAT
Bits
15:0
Default
0x0
Description
PCIE_PRBS23_LOCKED - R - 32 bits - PCIEIND:0xF2
Field Name
PRBS23_LOCKED
Bits
15:0
Default
0x0
Description
PCIE_PRBS23_FREERUN - RW - 32 bits - PCIEIND:0xF3
Field Name
PRBS23_FREERUN
Bits
15:0
Default
0x0
Description
PCIE_PRBS23_LOCK_CNT - RW - 32 bits - PCIEIND:0xF4
Field Name
PRBS23_LOCK_CNT
Bits
4:0
Default
0x0
Description
PCIE_PRBS23_EN - RW - 32 bits - PCIEIND:0xF5
PRBS23_EN
Field Name
Bits
0
Default
0x0
Description
PCIE_P90RX_PRBS_CLR - RW - 32 bits - PCIEIND:0xF6
Field Name
P90RX_PRBS_CLR
Bits
15:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-102
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_P90_BRX_PRBS_ER - R - 32 bits - PCIEIND:0xF7
Field Name
P90_BRX_PRBS_ER
Bits
15:0
Default
0x0
Description
PCIE_P90TX_PRBS_EN - RW - 32 bits - PCIEIND:0xF8
Field Name
P90TX_PRBS_EN
Bits
15:0
Default
0x0
Description
PCIE_B_P90_CNTL - RW - 32 bits - PCIEIND:0xF9
Field Name
B_P90IMP_BACKUP
B_P90PLL_BACKUP
Bits
3:0
31:12
Default
0x0
0x0
Description
PCIE_TX_VENDOR_SPECIFIC - RW - 32 bits - PCIEIND_P:0x22
Field Name
TX_VENDOR_DATA
Bits
23:0
Default
0x0
TX Vendor Specific DLLP
Description
Writing to this register generates a Vendor Specific DLLP
using Vendor Data for the payload.
PCIE_TX_ACK_LATENCY_LIMIT - RW - 32 bits - PCIEIND_P:0x26
Field Name
TX_ACK_LATENCY_LIMIT
TX_ACK_LATENCY_LIMIT_OVERWRITE
Bits
7:0
8
Default
0x0
0x0
TX ACK Latency Limit
Description
ACK Latency Limit for scheduling ACK DLLP transmission.
Use register value instead of hardware value from link
width.
PCIE_TX_CREDITS_CONSUMED_P - R - 32 bits - PCIEIND_P:0x30
Field Name
TX_CREDITS_CONSUMED_PD
Bits
11:0
Default
0x0
TX_CREDITS_CONSUMED_PH
23:16
0x0
TX Credits Consumed Register (Posted)
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
For posted TLP data, total number of FC units consumed by
TLP transmission made since FC initialization, modulo
4096.
For posted TLP header, total number of FC units consumed
by TLP transmission made since FC initialization, modulo
256.
AMD RS690 ASIC Family Register Reference Manual
2-103
PCI Express Registers
PCIE_TX_CREDITS_CONSUMED_NP - R - 32 bits - PCIEIND_P:0x31
Field Name
TX_CREDITS_CONSUMED_NPD
Bits
11:0
Default
0x0
TX_CREDITS_CONSUMED_NPH
23:16
0x0
TX Credits Consumed Register (Non-Posted)
Description
For non-posted TLP data, total number of FC units
consumed by TLP transmission made since FC
initialization, modulo 4096.
For non-posted TLP header, total number of FC units
consumed by TLP transmission made since FC
initialization, modulo 256.
PCIE_TX_CREDITS_CONSUMED_CPL - R - 32 bits - PCIEIND_P:0x32
Field Name
TX_CREDITS_CONSUMED_CPLD
Bits
11:0
Default
0x0
TX_CREDITS_CONSUMED_CPLH
23:16
0x0
TX Credits Consumed Register (Completion)
Description
For completion TLP data, total number of FC units
consumed by TLP transmission made since FC
initialization, modulo 4096.
For completion TLP header, total number of FC units
consumed by TLP transmission made since FC
initialization, modulo 256.
PCIE_TX_CREDITS_LIMIT_P - R - 32 bits - PCIEIND_P:0x33
Field Name
TX_CREDITS_LIMIT_PD
Bits
11:0
Default
0x0
TX_CREDITS_LIMIT_PH
23:16
0x0
Description
For posted TLP data, total number of FC units advertised by
the receiver since FC initialization, modulo 4096.
For posted TLP header, total number of FC units advertised
by the receiver since FC initialization, modulo 256.
TX Credits Limit Register (Posted)
PCIE_TX_CREDITS_LIMIT_NP - R - 32 bits - PCIEIND_P:0x34
Field Name
TX_CREDITS_LIMIT_NPD
Bits
11:0
Default
0x0
TX_CREDITS_LIMIT_NPH
23:16
0x0
TX Credits Limit Register (Non-Posted)
AMD RS690 ASIC Family Register Reference Manual
2-104
Description
For non-posted TLP data, total number of FC units
advertised by the receiver since FC initialization, modulo
4096.
For non-posted TLP header, total number of FC units
advertised by the receiver since FC initialization, modulo
256.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_TX_CREDITS_LIMIT_CPL - R - 32 bits - PCIEIND_P:0x35
Field Name
TX_CREDITS_LIMIT_CPLD
Bits
11:0
Default
0x0
TX_CREDITS_LIMIT_CPLH
23:16
0x0
TX Credits Limit Register (Completion)
Description
For completion TLP data, total number of FC units
advertised by the receiver since FC initialization, modulo
4096.
For completion TLP header, total number of FC units
advertised by the receiver since FC initialization, modulo
256.
PCIE_RX_VENDOR_SPECIFIC - R - 32 bits - PCIEIND_P:0x72
Field Name
RX_VENDOR_DATA
RX_VENDOR_STATUS
Bits
23:0
Default
0x0
24
0x0
RX Vendor Specific DLLP
Description
Writing to this register will re-arm to capture the next
Vendor Specific DLLP.
Indicates that a Vendor Specific DLLP was decoded, and
Vendor Data was captured.
PCIE_RX_CREDITS_ALLOCATED_P - R - 32 bits - PCIEIND_P:0x80
Field Name
RX_CREDITS_ALLOCATED_PD
Bits
11:0
Default
0x0
RX_CREDITS_ALLOCATED_PH
23:16
0x0
RX Credits Allocated Register (Posted)
Description
For posted TLP data, the number of FC units granted to
transmitter since initialization, modulo 4096.
For posted TLP header, the number of FC units granted to
transmitter since initialization, modulo 256.
PCIE_RX_CREDITS_ALLOCATED_NP - R - 32 bits - PCIEIND_P:0x81
Field Name
RX_CREDITS_ALLOCATED_NPD
Bits
11:0
Default
0x0
RX_CREDITS_ALLOCATED_NPH
23:16
0x0
Description
For non-posted TLP data, the number of FC units granted
to transmitter since initialization, modulo 4096.
For non-posted TLP header, the number of FC units
granted to transmitter since initialization, modulo 256.
RX Credits Allocated Register (Non-Posted)
PCIE_RX_CREDITS_ALLOCATED_CPL - R - 32 bits - PCIEIND_P:0x82
Field Name
RX_CREDITS_ALLOCATED_CPLD
Bits
11:0
Default
0x0
RX_CREDITS_ALLOCATED_CPLH
23:16
0x0
RX Credits Allocated Register (Completion)
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
For completion TLP data, the number of FC units granted to
transmitter since initialization, modulo 4096.
For completion TLP header, the number of FC units granted
to transmitter since initialization, modulo 256.
AMD RS690 ASIC Family Register Reference Manual
2-105
PCI Express Registers
PCIE_RX_CREDITS_RECEIVED_P - R - 32 bits - PCIEIND_P:0x83
Field Name
RX_CREDITS_RECEIVED_PD
Bits
11:0
Default
0x0
RX_CREDITS_RECEIVED_PH
23:16
0x0
RX Credits Received Register (Posted)
Description
For posted TLP data, the number of FC units consumed by
valid TLP received since initialization, modulo 4096.
For posted TLP header, the number of FC units consumed
by valid TLP received since initialization, modulo 256.
PCIE_RX_CREDITS_RECEIVED_NP - R - 32 bits - PCIEIND_P:0x84
Field Name
RX_CREDITS_RECEIVED_NPD
Bits
11:0
Default
0x0
RX_CREDITS_RECEIVED_NPH
23:16
0x0
RX Credits Received Register (Non-Posted)
Description
For non-posted TLP data, the number of FC units
consumed by valid TLP received since initialization, modulo
4096.
For non-posted TLP header, the number of FC units
consumed by valid TLP received since initialization, modulo
256.
PCIE_RX_CREDITS_RECEIVED_CPL - R - 32 bits - PCIEIND_P:0x85
Field Name
RX_CREDITS_RECEIVED_CPLD
Bits
11:0
Default
0x0
RX_CREDITS_RECEIVED_CPLH
23:16
0x0
Description
For completion TLP data, the number of FC units consumed
by valid TLP received since initialization, module 4096.
For completion TLP header, the number of FC units
consumed by valid TLP received since initialization, module
256.
RX Credits Received Register (Completion)
PCIE_LC_N_FTS_CNTL - RW - 32 bits - PCIEIND_P:0xA3
Field Name
LC_XMIT_N_FTS
LC_XMIT_N_FTS_OVERRIDE_EN
LC_XMIT_N_FTS_LIMIT
Bits
7:0
8
23:16
Default
0xc
0x0
0xff
LC_N_FTS (R)
LC Number of FTS Control
31:24
0x0
AMD RS690 ASIC Family Register Reference Manual
2-106
Description
Number of FTS to override the strap values
Enables the previous field to override the strap value.
Limits that the number of FTS can increment to when
incrementing is enabled.
Number of FTS captured from the other end of the link.
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
ROOT_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x74]
Field Name
SERR_ON_CORR_ERR_EN
Bits
0
Default
0x0
SERR_ON_NONFATAL_ERR_EN
1
0x0
SERR_ON_FATAL_ERR_EN
2
0x0
PM_INTERRUPT_EN
3
0x0
Description
System Error on Correctable Error Enable.
Indicates that a System Error should be generated if a
correctable error is reported by any of the devices in the
hierarchy associated with this Root Port.
System Error on Non-Fatal Error Enable.
Indicates that a System Error should be generated if a
Non-fatal error is reported by any of the devices in the
hierarchy associated with this Root Port.
System Error on Fatal Error Enable.
Indicates that a System Error should be generated if a Fatal
error is reported by any of the devices in the hierarchy
associated with this Root Port.
PME Interrupt Enable.
Enables interrupt generation upon receipt of a PME
Message.
CRS_SOFTWARE_VISIBILITY_EN
4
0x0
The Root Control register controls PCI Express Root Complex specific parameters.
ROOT_CAP - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x76]
Field Name
CRS_SOFTWARE_VISIBILITY (R)
Bits
0
Default
0x1
Description
MSI_CAP_LIST - R - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0x80]
Field Name
Bits
CAP_ID
7:0
NEXT_PTR
15:8
Message Signaled Interrupt Capability Registers
Default
0x5
0xb0
Description
Identifies if a device function is MSI capable.
Pointer to the next item on the capabilities list.
PCIE_CFG_SCRATCH - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3 pcieConfigDev4
pcieConfigDev5 pcieConfigDev6 pcieConfigDev7 pcieConfigDev8,pcieConfigDev9:0xC0]
SCRATCH
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
PCI Express Scratch register
AMD RS690 ASIC Family Register Reference Manual
2-107
PCI Express Registers
PCIE_VC_ENH_CAP_HDR - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x100]
Field Name
Bits
15:0
Default
0x2
CAP_VER
19:16
0x1
NEXT_PTR
31:20
0x140
CAP_ID
Virtual Channel Enhanced Capability Header
Description
This field is a PCI-SIG defined ID number that indicates the
nature and format of the extended capability.
This field is a PCI-SIG defined version number that
indicates the version of the capability structure present.
This field contains the offset to the next PCI Express
capability structure or 000h if no other items exist in the
linked list of capabilities.
PCIE_PORT_VC_CAP_REG1 - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x104]
Field Name
EXT_VC_COUNT
Bits
2:0
Default
0x0
LOW_PRIORITY_EXT_VC_COUNT
6:4
0x0
REF_CLK
9:8
0x0
11:10
0x0
PORT_ARB_TABLE_ENTRY_SIZE
Port VC Capability Register 1
Description
Indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device. This
field is valid for all devices.
Indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority VC
group
Indicates the reference clock for Virtual Channels that
support time-based WRR Port Arbitration.
Indicates the size (in bits) of Port Arbitration table entry in
the device.
PCIE_PORT_VC_CAP_REG2 - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x108]
VC_ARB_CAP
Field Name
VC_ARB_TABLE_OFFSET
Port VC Capability Register 2
Bits
7:0
Default
0x0
31:24
0x0
Description
Indicates the types of VC Arbitration supported by the
device for the Low Priority Virtual Channel group
Indicates the location of the VC Arbitration Table.
PCIE_PORT_VC_CNTL - RW - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x10C]
Field Name
LOAD_VC_ARB_TABLE (R)
VC_ARB_SELECT
Bits
0
3:1
Default
0x0
0x0
Port VC Control Register
AMD RS690 ASIC Family Register Reference Manual
2-108
Description
Used for software to update the VC Arbitration Table.
Used for software to configure the VC arbitration by
selecting one of the supported VC Arbitration schemes
© 2007 Advanced Micro Devices, Inc.
Proprietary
PCI Express Registers
PCIE_PORT_VC_STATUS - R - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x10E]
Field Name
VC_ARB_TABLE_STATUS
Port VC Status Register
Bits
0
Default
0x0
Description
Indicates the coherency status of the VC Arbitration Table
PCIE_VC1_RESOURCE_CAP - R - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x11C]
Field Name
PORT_ARB_CAP
Bits
7:0
Default
0x0
REJECT_SNOOP_TRANS
15
0x1
MAX_TIME_SLOTS
21:16
0x0
PORT_ARB_TABLE_OFFSET
31:24
0x0
VC1 Resource Capability Register
Description
Indicates types of Port Arbitration supported by the VC
resource.
When set to zero, transactions with or without the No Snoop
bit set within the TLP Header are allowed on this VC
Indicates the maximum number of time slots that the VC
resource is capable of supporting
Indicates the location of the Port Arbitration Table
associated with the VC resource.
PCIE_VC1_RESOURCE_CNTL - RW - 32 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x120]
Field Name
TC_VC_MAP_TC0 (R)
TC_VC_MAP_TC1_7
LOAD_PORT_ARB_TABLE (R)
Bits
0
7:1
16
Default
0x0
0x0
0x0
PORT_ARB_SELECT
19:17
0x0
VC_ID
VC_ENABLE
VC1 Resource Control Register
26:24
31
0x0
0x0
Description
Indicates the TCs that are mapped to the VC resource
Indicates the TCs that are mapped to the VC resource
Updates the Port Arbitration logic from the Port Arbitration
Table for the VC resource.
Configures the VC resource to provide a particular Port
Arbitration service.
Assigns a VC ID to the VC resource
Enables a Virtual Channel.
PCIE_VC1_RESOURCE_STATUS - R - 16 bits - [pcieConfigDev10 pcieConfigDev2 pcieConfigDev3
pcieConfigDev4 pcieConfigDev5 pcieConfigDev6 pcieConfigDev7
pcieConfigDev8,pcieConfigDev9:0x124]
Field Name
PORT_ARB_TABLE_STATUS
Bits
0
Default
0x0
VC_NEGOTIATION_PENDING
1
0x1
VC1 Resource Status Register
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Indicates the coherency status of the Port Arbitration Table
associated with the VC resource.
Indicates whether the Virtual Channel negotiation
(initialization or disabling) is in pending state.
AMD RS690 ASIC Family Register Reference Manual
2-109
Graphics Controller Configuration Registers
2.3
Graphics Controller Configuration Registers
DEVICE_ID - R - 16 bits - [gcconfig:0x2] [MMReg:0x5002]
DEVICE_ID
Field Name
Bits
15:0
Default
0x0
Device Identification.
Description
VENDOR_ID - R - 16 bits - [gcconfig:0x0] [MMReg:0x5000]
VENDOR_ID
Field Name
Bits
15:0
Default
0x1002
Vendor Identification
Description
COMMAND - RW - 16 bits - [gcconfig:0x4] [MMReg:0x5004]:R
Field Name
IO_ACCESS_EN
MEM_ACCESS_EN
BUS_MASTER_EN
SPECIAL_CYCLE_EN (R)
MEM_WRITE_INVALIDATE_EN (R)
PAL_SNOOP_EN (R)
PARITY_ERROR_EN
SERR_EN
FAST_B2B_EN (R)
INT_DIS
Bits
0
1
2
3
4
5
6
8
9
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
10
0x0
Description
1=Enable IO Space access
1=Enable MEM Space access
1=Enable Core Busmastering
Fix=0. No support for special cycles.
Fix=0. No support for memory write and invalidate.
Fix=0. No palette snooping.
0=PERR# is not asserted. Continue normal operation
0=Disable SERR# driver
1=Master is allowed to generate back-to-back
transactions to different agents
0=Back-to-back transactions only allowed to same agent
0=Enable INTx# assertion
1=Disables the assertion of INTx#
STATUS - RW - 16 bits - [gcconfig:0x6] [MMReg:0x5006]:R
Field Name
INT_STATUS (R)
CAP_LIST (R)
Bits
3
4
Default
0x0
0x1
PCI_66_EN (R)
5
0x0
FAST_BACK_CAPABLE (R)
7
0x0
10:9
0x0
13
0x0
DEVSEL_TIMING (R)
RECEIVED_MASTER_ABORT
AMD RS690 ASIC Family Register Reference Manual
2-110
Description
State of the Interrupt
0=No Capabilities exist
1=Capability pointer found at 0x34
0=33MHz Capable
1=66MHz Capable
0=Not capable of accepted back-to-back transactions
1=Capable of accepting back-to-back transactions
00=Fast
01=Medium
10=Slow
11=Reserved
Master address did not decode. Write '1' to clear.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
REVISION_ID - R - 8 bits - [gcconfig:0x8] [MMReg:0x5008]
Field Name
MINOR_REV_ID
MAJOR_REV_ID
Bits
3:0
7:4
Default
0x0
0x0
Description
Revision Identification
Revision Identification
IO_BASE - RW - 32 bits - [gcconfig:0x20] [MMReg:0x5020]:R
Field Name
BLOCK_IO_BIT (R)
Bits
0
Default
0x1
IO_BASE
31:8
0x0
Description
0=Memory space
1=IO space
Base address register for IO
ADAPTER_ID_W - RW - 32 bits - [gcconfig:0x4C] [MMReg:0x504C]:R
Field Name
SUBSYSTEM_VENDOR_ID
SUBSYSTEM_ID
Bits
15:0
31:16
Default
0x1002
0x7941
Description
Desired subsystem vendor ID.
Desired subsystem ID.
BASE_CODE - R - 8 bits - [gcconfig:0xB] [MMReg:0x500B]
Field Name
BASE_CLASS_CODE
Bits
7:0
Default
0x3
FIXED.
3=Display controller
Description
ADAPTER_ID - R - 32 bits - [gcconfig:0x2C] [MMReg:0x502C]
Field Name
SUBSYSTEM_VENDOR_ID
Bits
15:0
Default
0x0
Device Identification.
31:16
0x0
Device Identification.
Description
(mirror of
ADAPTER_ID_W:SUBSYSTEM_VENDOR_ID)
SUBSYSTEM_ID
(mirror of ADAPTER_ID_W:SUBSYSTEM_ID)
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-111
Graphics Controller Configuration Registers
SUB_CLASS - R - 8 bits - [gcconfig:0xA] [MMReg:0x500A]
Field Name
SUB_CLASS_INF
Bits
7
Default
0x0
FIXED.
0=VGA Compatible
Description
BIST - R - 8 bits - [gcconfig:0xF] [MMReg:0x500F]
BIST_COMP
BIST_STRT
BIST_CAP
Field Name
Bits
3:0
6
7
Default
0x0
0x0
0x0
Description
BIST (Built-in Self Test) register. Not supported.
BIST (Built-in Self Test) register. Not supported.
BIST (Built-in Self Test) register. Not supported.
CAPABILITIES_PTR - R - 32 bits - [gcconfig:0x34] [MMReg:0x5034]
Field Name
Bits
7:0
CAP_PTR
Default
0x50
Description
Capabilities Pointer.
CONFIG_CNTL - RW - 32 bits - [IOReg,MMReg:0xE0]
Field Name
CFG_VGA_RAM_EN
Bits
Default
8
0x0
(mirror of GENMO_WT:VGA_RAM_EN)
Description
Enables Memory cycles to VGA.
0=Disable
1=Enable
CFG_VGA_IO_DIS
9
0x0
Allows register cycles to VGA.
CFG_ATI_REV_ID
19:16
0x0
Core Revision ID.
CONFIG_MEMSIZE - RW - 32 bits - [IOReg,MMReg:0xF8]
Field Name
CONFIG_MEMSIZE
Bits
Default
Description
31:0
0x0
Scratch register for the BIOS to inform driver memory size.
Note: Bits [19:0] of this field are hardwired to 0.
CONFIG_APER_SIZE - R - 32 bits - [MMReg:0x108]
Field Name
APER_SIZE
Bits
Default
31:0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-112
Description
FB Aperture size readback.
Note: Bits [23:0] of this field are hardwired to 0.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CONFIG_REG_APER_SIZE - R - 32 bits - [MMReg:0x114]
Field Name
REG_APER_SIZE
Bits
18:0
Default
0x8000
Description
MMReg Aperture Size readback.
HEADER - R - 8 bits - [gcconfig:0xE] [MMReg:0x500E]
Field Name
HEADER_TYPE
DEVICE_TYPE
Bits
6:0
Default
0x0
7
0x0
Description
FIXED.
0x0=Type 00h space header
FIXED.
1=Multifunction device
INTERRUPT_LINE - RW - 8 bits - [gcconfig:0x3C] [MMReg:0x503C]:R
Field Name
INTERRUPT_LINE
Bits
7:0
Default
0xff
Description
Scratch Register used to communicate routing information.
INTERRUPT_PIN - R - 8 bits - [gcconfig:0x3D] [MMReg:0x503D]
Field Name
INTERRUPT_PIN
Bits
3:0
Default
0x1
1=INTA#
2=INTB#
Description
LATENCY - RW - 8 bits - [gcconfig:0xD] [MMReg:0x500D]:R
Field Name
LATENCY_TIMER
Bits
7:0
Default
0x0
Description
Specifies in units of PCI bus clocks the value of the Latency
Timer.
MAX_LATENCY - R - 8 bits - [gcconfig:0x3F] [MMReg:0x503F]
MAX_LAT
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Description
Desired value for the Latency Timer.
0=No major requirements
AMD RS690 ASIC Family Register Reference Manual
2-113
Graphics Controller Configuration Registers
REGPROG_INF - R - 8 bits - [gcconfig:0x9] [MMReg:0x5009]
Field Name
REG_LEVEL_PROG_INF
Bits
7:0
Default
0x0
Description
FIXED.
0=A_0000 through B_0000. I/O 3B0h to 3BBh, 3C0h to
3DFh and all aliases.
CACHE_LINE - RW - 8 bits - [gcconfig:0xC] [MMReg:0x500C]:R
Field Name
CACHE_LINE_SIZE
Bits
7:0
Default
0x0
Description
Specifies the system cacheline size in units of DWORDs.
MIN_GRANT - R - 8 bits - [gcconfig:0x3E] [MMReg:0x503E]
MIN_GNT
Field Name
Bits
7:0
Default
0x0
Description
Length of desired burst period assuming 33MHz.
0=No major requirements
MEM_BASE_LO - RW - 32 bits - [gcconfig:0x10] [MMReg:0x5010]:R
Field Name
BLOCK_MEM_BIT (R)
BLOCK_MEM_TYPE (R)
PFTCH_MEM_EN (R)
MEM_BASE_LO
Bits
0
Default
0x0
2:1
3
31:25
0x2
0x1
0x0
Description
0=Memory space
1=IO space
10=Locate anywhere in 64 bit address space
1=Prefetchable
Lower Memory Base Address
MEM_BASE_HI - RW - 32 bits - [gcconfig:0x14] [MMReg:0x5014]:R
Field Name
MEM_BASE_HI
Bits
31:0
Default
0x0
Description
Upper Memory Base Address.
REG_BASE_LO - RW - 32 bits - [gcconfig:0x18] [MMReg:0x5018]:R
Field Name
BLOCK_REG_BIT (R)
BLOCK_REG_TYPE (R)
PFTCH_REG_EN (R)
REG_BASE_LO
Bits
0
Default
0x0
2:1
3
31:16
0x2
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-114
Description
0=Memory space
1=IO space
10=locate anywhere in 64 bit address space
0=Not prefetchable
Lower Register Base Address
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
REG_BASE_HI - RW - 32 bits - [gcconfig:0x1C] [MMReg:0x501C]:R
Field Name
REG_BASE_HI
Bits
31:0
Default
0x0
Description
Upper Register Base Address
MSI_CAP_ID - R - 8 bits - [gcconfig:0x80] [MMReg:0x5080]
MSI_CAP_ID
Field Name
Bits
7:0
Default
0x5
MSI Capability ID.
Description
MSI_NXT_CAP_PTR - R - 8 bits - [gcconfig:0x81] [MMReg:0x5081]
Field Name
MSI_NXT_CAP_PTR
Bits
7:0
Default
0x0
Description
The last item in capabilities list.
MSI_MSG_CNTL - RW - 16 bits - [gcconfig:0x82] [MMReg:0x5082]:R
Field Name
MSI_EN
MSI_MULTMSG_CAP (R)
MSI_MULTMSG_EN
MSI_64BIT (R)
Bits
0
3:1
6:4
Default
0x0
0x0
0x0
7
0x1
Description
1=Enable MSI messaging
The number of requested messages.
000=1 message allocated
001=2 messages allocated
010=4 messages allocated
011=8 messages allocated
100=16 messages allocated
101=32 messages allocated
110=Reserved
111=Reserved
64 bit messaging enabled.
MSI_MSG_ADDR_LO - RW - 32 bits - [gcconfig:0x84] [MMReg:0x5084]:R
Field Name
MSI_MSG_ADDR_LO
Bits
31:2
Default
0x0
Description
System-specified message lower address.
MSI_MSG_ADDR_HI - RW - 32 bits - [gcconfig:0x88] [MMReg:0x5088]:R
Field Name
MSI_MSG_ADDR_HI
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
System-specified message upper address.
AMD RS690 ASIC Family Register Reference Manual
2-115
Graphics Controller Configuration Registers
MSI_MSG_DATA - RW - 16 bits - [gcconfig:0x8C] [MMReg:0x508C]:R
MSI_DATA
Field Name
Bits
15:0
Default
0x0
Description
System-specified message.
F1_VENDOR_ID - R - 16 bits - [gcconfig:0x100] [MMReg:0x5100]
Field Name
F1_VENDOR_ID
Bits
15:0
Default
0x1002
Vendor ID register.
Description
F1_DEVICE_ID - R - 16 bits - [gcconfig:0x102] [MMReg:0x5102]
Field Name
F1_DEVICE_ID
Bits
15:0
Default
0x0
Description
Device ID register.
F1_COMMAND - RW - 16 bits - [gcconfig:0x104] [MMReg:0x5104]:R
Field Name
F1_MEM_ACCESS_EN
F1_BUS_MASTER_EN
Bits
1
2
Default
0x0
0x0
Description
1=Enable MEM Space access
1=Enable Core Busmastering
F1_STATUS - R - 16 bits - [gcconfig:0x106] [MMReg:0x5106]
F1_CAP_LIST
Field Name
Bits
4
Default
0x1
Description
0=No Capabilities exist
1=Capability pointer found at 0x34
F1_REVISION_ID - R - 8 bits - [gcconfig:0x108] [MMReg:0x5108]
Field Name
F1_MINOR_REV_ID
F1_MAJOR_REV_ID
Bits
3:0
7:4
Default
0x0
0x0
Revision Identification.
Revision Identification.
Description
F1_REGPROG_INF - R - 8 bits - [gcconfig:0x109] [MMReg:0x5109]
Field Name
F1_REG_LEVEL_PROG_INF
Bits
7:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-116
Description
Reserved.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
F1_SUB_CLASS - R - 8 bits - [gcconfig:0x10A] [MMReg:0x510A]
Field Name
F1_SUB_CLASS_INF
Bits
7
Default
0x1
Fixed.
1=XGA Compatible
Description
F1_BASE_CODE - R - 8 bits - [gcconfig:0x10B] [MMReg:0x510B]
Field Name
F1_BASE_CLASS_CODE
Bits
7:0
Default
0x3
Fixed.
3=Display Controller
Description
F1_CACHE_LINE - RW - 8 bits - [gcconfig:0x10C] [MMReg:0x510C]:R
Field Name
F1_CACHE_LINE_SIZE
Bits
7:0
Default
0x0
Description
Specifies the system cacheline size in units of DWORDs
F1_LATENCY - RW - 8 bits - [gcconfig:0x10D] [MMReg:0x510D]:R
Field Name
F1_LATENCY_TIMER
Bits
7:0
Default
0x0
Description
Specifies in units of PCI bus clocks the value of the Latency
Timer.
F1_HEADER - R - 8 bits - [gcconfig:0x10E] [MMReg:0x510E]
Field Name
F1_HEADER_TYPE
F1_DEVICE_TYPE
Bits
6:0
7
Default
0x0
0x0
Description
Reserved. See F0 configuration space.
Reserved. See F0 configuration space.
F1_BIST - R - 8 bits - [gcconfig:0x10F] [MMReg:0x510F]
Field Name
F1_BIST_COMP
F1_BIST_STRT
F1_BIST_CAP
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
3:0
6
7
Default
0x0
0x0
0x0
Description
BIST (Built-in Self Test) register. Not supported.
BIST (Built-in Self Test) register. Not supported.
BIST (Built-in Self Test) register. Not supported.
AMD RS690 ASIC Family Register Reference Manual
2-117
Graphics Controller Configuration Registers
F1_REG_BASE_LO - RW - 32 bits - [gcconfig:0x110] [MMReg:0x5114]:R
Field Name
F1_BLOCK_REG_BIT (R)
Bits
0
Default
0x0
F1_BLOCK_REG_TYPE (R)
F1_PFTCH_REG_EN (R)
F1_REG_BASE_LO
2:1
3
31:16
0x2
0x0
0x0
Description
0=Memory space
1=IO space
10=locate anywhere in 64 bit address space
0=Not prefetchable
Lower Register Base Address
F1_REG_BASE_HI - RW - 32 bits - [gcconfig:0x114] [MMReg:0x511C]:R
Field Name
F1_REG_BASE_HI
Bits
31:0
Default
0x0
Description
Upper Register Base Address
F1_ADAPTER_ID - R - 32 bits - [gcconfig:0x12C] [MMReg:0x512C]
Field Name
F1_SUBSYSTEM_VENDOR_ID
Bits
15:0
Default
0x0
Device Identification.
31:16
0x0
Device Identification.
Description
(mirror of
ADAPTER_ID_W:SUBSYSTEM_VENDOR_ID)
F1_SUBSYSTEM_ID
(mirror of
F1_ADAPTER_ID_W:F1_SUBSYSTEM_ID)
F1_CAPABILITIES_PTR - R - 32 bits - [gcconfig:0x134] [MMReg:0x5134]
Field Name
F1_CAP_PTR
Bits
7:0
Default
0x50
Description
Capabilities Pointer
F1_INTERRUPT_LINE - RW - 8 bits - [gcconfig:0x13C] [MMReg:0x513C]:R
Field Name
F1_INTERRUPT_LINE
Bits
7:0
Default
0x0
Description
Scratch Register used to communicate routing information.
F1_INTERRUPT_PIN - R - 8 bits - [gcconfig:0x13D] [MMReg:0x513D]
Field Name
F1_INTERRUPT_PIN
Bits
3:0
Default
0x1
AMD RS690 ASIC Family Register Reference Manual
2-118
Description
1=INTA#
2=INTB#
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
F1_MIN_GRANT - R - 8 bits - [gcconfig:0x13E] [MMReg:0x513E]
F1_MIN_GNT
Field Name
Bits
7:0
Default
0x0
Description
Length of desired burst period assuming 33MHz.
0=No major requirements
F1_MAX_LATENCY - R - 8 bits - [gcconfig:0x13F] [MMReg:0x513F]
F1_MAX_LAT
Field Name
Bits
7:0
Default
0x0
Description
Desired value for the Latency Timer
0=No major requirements
F1_PMI_CAP_ID - R - 8 bits - [gcconfig:0x150] [MMReg:0x5150]
Field Name
F1_PMI_CAP_ID
Bits
7:0
Default
0x1
Description
F1_PMI_NXT_CAP_PTR - R - 8 bits - [gcconfig:0x151] [MMReg:0x5151]
Field Name
F1_PMI_NXT_CAP_PTR
Bits
7:0
Default
0x0
The last item.
Description
F1_PMI_PMC_REG - R - 16 bits - [gcconfig:0x152] [MMReg:0x5152]
Field Name
F1_PMI_VERSION
F1_PMI_PME_CLOCK
F1_PMI_DEV_SPECIFIC_INIT
F1_PMI_D1_SUPPORT
F1_PMI_D2_SUPPORT
F1_PMI_PME_SUPPORT
Bits
2:0
3
5
9
10
15:11
Default
0x2
0x0
0x0
0x1
0x1
0x0
Description
F1_PMI_DATA - R - 8 bits - [gcconfig:0x157] [MMReg:0x5157]
Field Name
F1_PMI_DATA
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-119
Graphics Controller Configuration Registers
PMI_STATUS - RW - 16 bits - [gcconfig:0x54] [MMReg:0x5054]:R
Field Name
PMI_POWER_STATE
Bits
1:0
Default
0x0
Description
2-bit field used to determine the current power state and
to set a new power state.
READ_BACK
00=D0 state
01=D1 state
10=D2 state
11=D3 state
PMI_PME_EN (R)
PMI_DATA_SELECT (R)
PMI_DATA_SCALE (R)
PMI_PME_STATUS (R)
8
12:9
14:13
15
0x0
0x0
0x0
0x0
WRITE
00=D0 state
01=D1 state
10=D2 state
11=D3 state
PME not supported
Data select not implemented
Data scale not implemented
PME not supported
F1_ADAPTER_ID_W - RW - 32 bits - [gcconfig:0x14C] [MMReg:0x514C]:R
Field Name
F1_SUBSYSTEM_ID
Bits
31:16
Default
0x7939
Description
Desired F1 subsystem ID.
F1_PMI_STATUS - RW - 16 bits - [gcconfig:0x154] [MMReg:0x5154]:R
Field Name
F1_PMI_POWER_STATE
F1_PMI_PME_EN (R)
F1_PMI_DATA_SELECT (R)
F1_PMI_DATA_SCALE (R)
F1_PMI_PME_STATUS (R)
Bits
1:0
8
12:9
14:13
15
Default
0x0
0x0
0x0
0x0
0x0
Description
F2_VENDOR_ID - R - 16 bits - [gcconfig:0x200] [MMReg:0x5200]
Field Name
F2_VENDOR_ID
Bits
15:0
Default
0x1002
Description
Vendor ID register
F2_DEVICE_ID - R - 16 bits - [gcconfig:0x202] [MMReg:0x5202]
Field Name
F2_DEVICE_ID
Bits
15:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-120
Device ID register
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
F2_COMMAND - RW - 16 bits - [gcconfig:0x204] [MMReg:0x5204]:R
Field Name
F2_MEM_ACCESS_EN
F2_BUS_MASTER_EN
F2_INTR_DIS
Bits
1
2
10
Default
0x0
0x0
0x0
Description
1=Enable MEM Space access
1=Enable Core Busmastering
0=Enable INTx# assertion
1=Disable the assertion of INTx#
F2_STATUS - R - 16 bits - [gcconfig:0x206] [MMReg:0x5206]
Field Name
F2_INT_STATUS
F2_CAP_LIST
Bits
3
4
Default
0x0
0x1
F2_DEVSEL_TIMING
10:9
0x0
Description
State of the Interrupt
0=No Capabilities exist
1=Capability pointer found at 0x34
00=Fast
01=Medium
10=Slow
11=Reserved
F2_REVISION_ID - R - 8 bits - [gcconfig:0x208] [MMReg:0x5208]
Field Name
F2_MINOR_REV_ID
F2_MAJOR_REV_ID
Bits
3:0
7:4
Default
0x0
0x0
Revision ID register
Revision ID register
Description
F2_REGPROG_INF - R - 8 bits - [gcconfig:0x209] [MMReg:0x5209]
Field Name
F2_REG_LEVEL_PROG_INF
Bits
7:0
Default
0x0
Description
Reserved
F2_SUB_CLASS - R - 8 bits - [gcconfig:0x20A] [MMReg:0x520A]
Field Name
F2_SUB_CLASS_INF
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x3
Description
FIXED.
3=Other multimedia device
AMD RS690 ASIC Family Register Reference Manual
2-121
Graphics Controller Configuration Registers
F2_BASE_CODE - R - 8 bits - [gcconfig:0x20B] [MMReg:0x520B]
Field Name
F2_BASE_CLASS_CODE
Bits
7:0
Default
0x4
Description
FIXED.
4 = Multimedia device
F2_CACHE_LINE - RW - 8 bits - [gcconfig:0x20C] [MMReg:0x520C]:R
Field Name
F2_CACHE_LINE_SIZE
Bits
7:0
Default
0x0
Description
CacheLine Size register.
F2_LATENCY - RW - 8 bits - [gcconfig:0x20D] [MMReg:0x520D]:R
Field Name
F2_LATENCY_TIMER
Bits
7:0
Default
0x0
Latency Timer register.
Description
F2_HEADER - R - 8 bits - [gcconfig:0x20E] [MMReg:0x520E]
Field Name
F2_HEADER_TYPE
F2_DEVICE_TYPE
Bits
6:0
7
Default
0x0
0x0
Description
Reserved. See F0 config space
Reserved. See F0 config space
F2_BIST - R - 8 bits - [gcconfig:0x20F] [MMReg:0x520F]
Field Name
F2_BIST_COMP
F2_BIST_STRT
F2_BIST_CAP
Bits
3:0
6
7
Default
0x0
0x0
0x0
Description
BIST (Built-in Self Test) register, not supported
BIST (Built-in Self Test) register, not supported
BIST (Built-in Self Test) register, not supported
F2_REG_BASE_LO - RW - 32 bits - [gcconfig:0x210] [MMReg:0x5210]:R
Field Name
F2_BLOCK_REG_BIT (R)
Bits
0
Default
0x0
F2_BLOCK_REG_TYPE (R)
F2_PFTCH_REG_EN (R)
F2_REG_BASE_LO
2:1
3
31:14
0x2
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-122
Description
0=Memory space
1=IO space
10=Locate anywhere in 64 bit address space
0=Not prefetchable
Lower Register Base Address
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
F2_REG_BASE_HI - RW - 32 bits - [gcconfig:0x214] [MMReg:0x5214]:R
Field Name
F2_REG_BASE_HI
Bits
31:0
Default
0x0
Description
Upper Register Base Address
F2_ADAPTER_ID - R - 32 bits - [gcconfig:0x22C] [MMReg:0x522C]
Field Name
F2_SUBSYSTEM_VENDOR_ID
(mirror of
F2_ADAPTER_ID_W:F2_SUBSYSTEM_VEND
OR_ID)
F2_SUBSYSTEM_ID
Bits
15:0
Default
0x0
Device Identification
31:16
0x0
Device Identification
Description
(mirror of
F2_ADAPTER_ID_W:F2_SUBSYSTEM_ID)
F2_CAPABILITIES_PTR - R - 32 bits - [gcconfig:0x234] [MMReg:0x5234]
F2_CAP_PTR
Field Name
Bits
7:0
Default
0x50
Capabilities Pointer
Description
F2_INTERRUPT_LINE - RW - 8 bits - [gcconfig:0x23C] [MMReg:0x523C]:R
Field Name
F2_INTERRUPT_LINE
Bits
7:0
Default
0x0
Description
Scratch Register used to communicate routing information
F2_INTERRUPT_PIN - R - 8 bits - [gcconfig:0x23D] [MMReg:0x523D]
Field Name
F2_INTERRUPT_PIN
Bits
3:0
Default
0x1
1=INTA#
2=INTB#
Description
F2_MIN_GRANT - R - 8 bits - [gcconfig:0x23E] [MMReg:0x523E]
F2_MIN_GNT
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Description
Length of desired burst period assuming 33MHz
0=No major requirements
AMD RS690 ASIC Family Register Reference Manual
2-123
Graphics Controller Configuration Registers
F2_MAX_LATENCY - R - 8 bits - [gcconfig:0x23F] [MMReg:0x523F]
Field Name
F2_MAX_LAT
Bits
7:0
Default
0x0
Description
Desired value for Latency Timer
0=No major requirements
F2_ADAPTER_ID_W - RW - 32 bits - [gcconfig:0x24C] [MMReg:0x524C]:R
Field Name
F2_SUBSYSTEM_VENDOR_ID
F2_SUBSYSTEM_ID
Bits
15:0
31:16
Default
0x1002
0x0
Description
Desired subsystem vendor ID.
Desired subsystem ID.
F2_PMI_CAP_ID - R - 8 bits - [gcconfig:0x250] [MMReg:0x5250]
Field Name
F2_PMI_CAP_ID
Bits
7:0
Default
0x1
Description
FIX=0x1 per spec
F2_PMI_NXT_CAP_PTR - R - 8 bits - [gcconfig:0x251] [MMReg:0x5251]
Field Name
F2_PMI_NXT_CAP_PTR
Bits
7:0
Default
0x60
Description
Next item is MSI
F2_PMI_PMC_REG - R - 16 bits - [gcconfig:0x252] [MMReg:0x5252]
Field Name
F2_PMI_VERSION
F2_PMI_PME_CLOCK
F2_PMI_DEV_SPECIFIC_INIT
F2_PMI_D1_SUPPORT
F2_PMI_D2_SUPPORT
F2_PMI_PME_SUPPORT
Bits
2:0
3
5
9
10
15:11
Default
0x2
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-124
Description
Revision 1.1 supported
PME clock not required
No special initialization required
D1 state not supported
D2 state not supported
No PME support
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
F2_PMI_STATUS - RW - 16 bits - [gcconfig:0x254] [MMReg:0x5254]:R
Field Name
F2_PMI_POWER_STATE
Bits
1:0
Default
0x0
Description
2-bit field used to determine the current power state and
to set a new power state.
READ_BACK
00=D0 state
01=D1 state
10=D2 state
11=D3 state
F2_PMI_PME_EN (R)
F2_PMI_DATA_SELECT (R)
F2_PMI_DATA_SCALE (R)
F2_PMI_PME_STATUS (R)
8
12:9
14:13
15
0x0
0x0
0x0
0x0
WRITE
00=D0 state
01=D1 state
10=D2 state
11=D3 state
PME not supported
Data select not implemented
Data scale not implemented
PME not supported
F2_PMI_DATA - R - 8 bits - [gcconfig:0x257] [MMReg:0x5257]
F2_PMI_DATA
Field Name
Bits
7:0
Default
0x0
Not implemented
Description
F2_MSI_CAP_ID - R - 8 bits - [gcconfig:0x260] [MMReg:0x5260]
Field Name
F2_MSI_CAP_ID
Bits
7:0
Default
0x5
MSI Capability ID
Description
F2_MSI_NXT_CAP_PTR - R - 8 bits - [gcconfig:0x261] [MMReg:0x5261]
Field Name
F2_MSI_NXT_CAP_PTR
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Description
The last item in capabilities list.
AMD RS690 ASIC Family Register Reference Manual
2-125
Graphics Controller Configuration Registers
F2_MSI_MSG_CNTL - RW - 16 bits - [gcconfig:0x262] [MMReg:0x5262]:R
Field Name
F2_MSI_EN
F2_MSI_MULTMSG_CAP (R)
F2_MSI_MULTMSG_EN
F2_MSI_64BIT (R)
Bits
0
3:1
6:4
Default
0x0
0x0
0x0
7
0x1
Description
1=Enable MSI messaging
The number of requested messages.
000=1 message allocated
001=2 messages allocated
010=4 messages allocated
011=8 messages allocated
100=16 messages allocated
101=32 messages allocated =n110=reserved
111=Reserved
64 messaging enabled
F2_MSI_MSG_ADDR_LO - RW - 32 bits - [gcconfig:0x264] [MMReg:0x5264]:R
Field Name
F2_MSI_MSG_ADDR_LO
Bits
31:2
Default
0x0
Description
System-specified message lower address.
F2_MSI_MSG_ADDR_HI - RW - 32 bits - [gcconfig:0x268] [MMReg:0x5268]:R
Field Name
F2_MSI_MSG_ADDR_HI
Bits
31:0
Default
0x0
Description
System-specified message upper address.
F2_MSI_MSG_DATA - RW - 16 bits - [gcconfig:0x26C] [MMReg:0x526C]:R
F2_MSI_DATA
Field Name
Bits
15:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-126
Description
System-specified message.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
2.4
Bus Interface Control/Status Registers
MM_INDEX - RW - 32 bits - [IOReg,MMReg:0x0]
MM_ADDR
Field Name
Bits
30:0
Default
0x0
MM_APER
31
0x0
Description
Index address to Frame buffer or MM register.
Note: Bits [1:0] of this field are hardwired to 0.
0=Register Aperture
1=Linear Aperture
MM_DATA - RW - 32 bits - [IOReg,MMReg:0x4]
MM_DATA
Field Name
Bits
31:0
Default
0x0
Index Data field
Description
GENENB - R - 8 bits - VGA_IO:0x3C3
Field Name
BLK_IO_BASE
Bits
Default
7:0
0x0
Description
Mirror of F0 IO_BASE.
GENMO_WT - W - 8 bits - [MMReg,VGA_IO:0x3C2]
Field Name
GENMO_MONO_ADDRESS_B
VGA_RAM_EN
VGA_CKSEL
ODD_EVEN_MD_PGSEL
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
Default
0x0
1
0x0
3:2
0x0
5
0x0
Description
VGA addressing mode.
0=Monochrome emulation, regs at 0x3Bx
1=Color/Graphic emulation, regs at 0x3Dx
Enables/disables CPU access to video RAM at VGA
aperture.
0=Disable
1=Enable
Selects pixel clock frequency to use in VGA modes. Used
when CRTC_GEN_CNTL.CRTC_EXT_DISP_EN=0. See
CLOCK_CNTL_INDEX.PPLL_DIV_SEL for non-VGA mode
pixel clock selection.
0=25.1744MHz (640 Pels)
1=28.3212MHz (720 Pels)
2=Reserved
3=Reserved
This bit is used in odd/even display modes (A/N modes: 0,
1, 2, 3, and 7). This bit is ignored when either bit GRA06[1]
or SEQ4[3] are enabled. It is used to determine if the VGA
aperture maps into the lower (even) or upper (odd) page of
memory.
0=Selects odd (high) memory locations
1=Selects even (low) memory locations
AMD RS690 ASIC Family Register Reference Manual
2-127
Graphics Controller Configuration Registers
VGA_HSYNC_POL
6
0x0
VGA_VSYNC_POL
7
0x0
Miscellaneous Output Register (Write)
Determines the polarity of horizontal sync (HSYNC) for
VGA modes.
0=HSYNC pulse active high
1=HSYNC pulse active low
The convention of VGA is to use active low VSYNC for 400
(and 200) and 480 line modes. Active high is normally used
for 350 line modes.
Determines the polarity of vertical sync (VSYNC) for VGA
modes.
0=VSYNC pulse active high
1=VSYNC pulse active low
The convention of VGA is to use active high VSYNC for 400
(and 200) line modes. Active low is normally used for 350
and 480 line modes.
GENMO_RD - R - 8 bits - [MMReg,VGA_IO:0x3CC]
Field Name
GENMO_MONO_ADDRESS_B
(mirror of
GENMO_WT:GENMO_MONO_ADDRESS_B)
VGA_RAM_EN
(mirror of GENMO_WT:VGA_RAM_EN)
VGA_CKSEL
Bits
0
Default
0x0
1
0x0
Enables/disables CPU access to video RAM at VGA
aperture.
3:2
0x0
Selects pixel clock frequency to use.
5
0x0
6
0x0
7
0x0
This bit is used in odd/even display modes (A/N modes: 0,
1, 2, 3, and 7). This bit is ignored when either bit GRA06[1]
or SEQ4[3] are enabled. It is used to determine if the VGA
aperture maps into the lower (even) or upper (odd) page of
memory.
Determines the polarity of horizontal sync (HSYNC) for
VGA modes.
0=HSYNC pulse active high
1=HSYNC pulse active low
The convention of VGA is to use active low VSYNC for 400
(and 200) and 480 line modes. Active high is normally used
for 350 line modes.
Determines the polarity of vertical sync (VSYNC) for VGA
modes.
0=VSYNC pulse active high
1=VSYNC pulse active low
The convention of VGA is to use active high VSYNC for 400
(and 200) line modes. Active low is normally used for 350
and 480 line modes.
VGA addressing mode.
Description
(mirror of GENMO_WT:VGA_CKSEL)
ODD_EVEN_MD_PGSEL
(mirror of
GENMO_WT:ODD_EVEN_MD_PGSEL)
VGA_HSYNC_POL
(mirror of GENMO_WT:VGA_HSYNC_POL)
VGA_VSYNC_POL
(mirror of GENMO_WT:VGA_VSYNC_POL)
Miscellaneous Output Register (Read)
AMD RS690 ASIC Family Register Reference Manual
2-128
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
2.5
Power Management Registers
PMI_CAP_ID - R - 8 bits - [gcconfig:0x50] [MMReg:0x5050]
Field Name
Bits
7:0
PMI_CAP_ID
Default
0x1
Description
FIX=0x1 per spec.
PMI_NXT_CAP_PTR - R - 8 bits - [gcconfig:0x51] [MMReg:0x5051]
Field Name
PMI_NXT_CAP_PTR
Bits
7:0
Default
0x80
Description
Next item is MSI.
PMI_PMC_REG - R - 16 bits - [gcconfig:0x52] [MMReg:0x5052]
Field Name
PMI_VERSION
PMI_PME_CLOCK
PMI_DEV_SPECIFIC_INIT
PMI_D1_SUPPORT
PMI_D2_SUPPORT
PMI_PME_SUPPORT
Bits
2:0
3
5
9
10
15:11
Default
0x2
0x0
0x0
0x1
0x1
0x0
Description
Revision 1.1 supported.
PME clock not required.
No special initialization required.
D1 state supported.
D2 state supported.
No PME support.
PMI_DATA - R - 8 bits - [gcconfig:0x57] [MMReg:0x5057]
PMI_DATA
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Not implemented.
Description
AMD RS690 ASIC Family Register Reference Manual
2-129
Graphics Controller Configuration Registers
2.6
System Clock Configuration Space Registers
OSC_CONTROL - RW - 32 bits - clkconfig:0x40
Bits
0
Default
0x1
XTAL_LOW_GAIN
1
0x0
Reserved0 (R)
3
0x0
CPU_STOP_ENABLE
4
0x0
DC_STOP_ENABLE
5
0x0
GFX_REFCLK_OE_TOGGLE
6
0x0
GPP_REFCLK_OE_TOGGLE
7
0x0
SB_REFCLK_OE_TOGGLE
8
0x0
Reserved1 (R)
11
0x0
CPUCLK_SE_OE_TOGGLE
12
0x0
CPUCLK_DIFF_OE_TOGGLE
13
0x0
REF_14M_OE_TOGGLE
14
0x0
ON_CHIP_CLOCK_GENERATOR (R)
18
0x0
SYSCLK_OE_TOGGLE
19
0x0
MEMCLK_OE_TOGGLE
20
0x0
OSC_EN
Field Name
Description
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Disable
1=Enable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=High Gain
1=Low Gain
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Disable
1=Enable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Disable
1=Enable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=External clock
1=Internal clock
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch register
AMD RS690 ASIC Family Register Reference Manual
2-130
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GC_CLK_CNTRL - RW - 8 bits - clkconfig:0x74
Field Name
CG_BCLKSTATE
Bits
0
Default
0x0
GC_STATE (R)
4:3
0x0
5
0x0
STOP_GC_REQ (R)
Graphics Controller Clock Control
Description
Program the IG register bit as follows:
(1) Set to 0 to force BCLK on within M10.CG block
(2) Set to 1 to allow CG to stop clks for power management
sleep sequencing.
0=Run
1=Allow GC Shutdown Sequence
To restart the GC program the following:
(1) Clear CG_BCLKSTATE to force the internal BCLK (in
GC) to run.
(2) Write BIF:PM_STATUS[PMI_POWER_STATE] to 2'b00
to start WAKEUP sequence.
(3) Wait until GC_STATE reports a value of 2'b00.
(4) Wait 100 us before sending more GC requests to GC.
(5) Set bit CG_BCLKSTATE to allow state transition.
0=GC has transitioned to D0
1=
2=
3=GC has transitioned to suspend and 61us later all
BCLK in the GC will stop
In order to suspend the GC perform the following:
(1) Set bit CG_CLKSTATE to allow state transition
stopping BCLK when SUSPEND is reached.
(2) Set BIF:PM_STATUS[PMI_POWER_STATE] to 0x02 to
start SUSPEND sequence (into D2).
(3) Wait until the state transition is complete, either by
reading BIF:PM_STATUS[PMI_POWER_STATE] and
verifying that it changed to 2'b10, or by checking
GC_STATE for a value of 2'b11. This indicates that the GC
has transitioned to suspend and 61 us later all BCLK in GC
will stop.
(4) This can be verified by reading STOP_GC_REQ - this
bit will be set 61us before GC stops its clocks. When clocks
are stopped, oCG_CT_BCLK_STOPPED=1.
0=GC has not stopped its clocks
1=GCs clocks will stop within 61us
SCRATCH_1_CLKCFG - RW - 32 bits - clkconfig:0x78
Field Name
SCRATCH_1
Bits
Default
31:0
0x0
Description
SCRATCH_2_CLKCFG - RW - 32 bits - clkconfig:0x7C
Field Name
SCRATCH_2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
Default
31:0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-131
Graphics Controller Configuration Registers
SCRATCH_CLKCFG - RW - 32 bits - clkconfig:0x84
Field Name
SCRATCH
Bits
Default
Description
31:0
0x0
All of the bits in this register can be both written to, and read
from, but the register does not control anything.
Scratch register for the CLKCFG register space.
CLKGATE_DISABLE2 - RW - 32 bits - clkconfig:0x8C
Field Name
CLKGATE_DIS_MCB
CLKGATE_DIS_MCGR
CLKGATE_DIS_MCSQA
CLKGATE_DIS_MCSQB
CLKGATE_DIS_MCIOA
CLKGATE_DIS_MCIOB
CLKGATE_DIS_BIU_NB1ACLK
Bits
0
1
2
3
4
5
8
Default
0x1
0x1
0x1
0x1
0x1
0x1
0x1
CLKGATE_DIS_BIU_NB1BCLK
9
0x1
CLKDATE_DIS_BIU_MEMA
10
0x1
CLKDATE_DIS_BIU_MEMB
11
0x1
CLKGATE_DIS_BIU_PAD
12
0x1
CLKGATE_DIS_IOC_CCLK_MST
13
0x1
CLKGATE_DIS_IOC_CCLK_SLV
14
0x1
CLKGATE_DIS_BIU_IOPLL4X
GFX_SCLK_DISABLE
GFX_DISPCLK_DISABLE
CFG_CT_DISABLE_MCCLK1X_SVL
CFG_CT_DISABLE_MCCLK1X_M2C
iCFG_CT_DISABLE_CCLK_BIF
CFG_CT_DISABLE_MCLK_BIF
MC_DELAY_TIMER_EXTEND
18
20
21
22
23
24
25
30
0x1
0x0
0x0
0x1
0x1
0x1
0x1
0x0
Register Description.
Description
Disables clock gating for MCLK1X going to arbiterB and rbs
Disables clock gating for MCLK1X going to cic interface
Disables clock gating for MCLK1X going to sequencerA
Disables clock gating for MCLK1X going to sequencerB
Disables clock gating for MCLK1X going to ioA
Disables clock gating for MCLK1X going to ioB
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Disables clock gating for SCLK4X going to IOPADS
Disables GFX engine clock
Disables GFX display clock
Disables clock gating for CCLK going to BIF branch
Disables clock gating for MCLK going to BIF branch
Extend delay timer for MEMORY clocks
0=16 clocks
1=32 clocks
CLKGATE_DISABLE - RW - 32 bits - clkconfig:0x94
Field Name
CLKGATE_DIS_MCA
Bits
0
Default
0x1
CPUCLK_STOP_MISC
1
0x1
CLKGATE_DIS_MC1
2
0x1
AMD RS690 ASIC Family Register Reference Manual
2-132
Description
Disables clock gating for MCLK1X going to arbiterA and rbs
0=Enable
1=Disable
Disables CPUCLK_STOP stopping CFG and IG2R6 BCLK
and CCLK
0=Enable
1=Disable
This register bit is not used.
0=Enable
1=Disable
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CLKGATE_DIS_MC2
3
0x1
DIS_CPUCLK_STOP_BIU
4
0x1
SPARE_7
7
0x0
ENABLE_ANALOG_DLLs
8
0x1
CLKGATE_DIS_RAMCLK
9
0x1
CLKGATE_DIS_BIU_MEM
10
0x1
CLKGATE_DIS_BIU_NB1CLK
11
0x1
CLKGATE_DIS_BIU_NB2CLK
12
0x1
CLKGATE_DIS_PCIE_GPCLK
13
0x1
CLKGATE_DIS_PCIE_GCLK
14
0x1
CLKGATE_DIS_PCIE_SBCLK
15
0x1
CLKGATE_DIS_GFX_TXCLK
16
0x1
CLKGATE_DIS_GPP_TXCLK
17
0x1
CLKGATE_DIS_SB_TXCLK
18
0x1
CLKGATE_DIS_GFX_TXCLK_L0S
19
0x1
CLKGATE_DIS_SB_TXCLK_L0S
20
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Disables clock gating for MCLK1X to NB
0=Enable
1=Disable
Disables CPUCLK_STOP stopping BIU clocks
0=Enable
1=Disable
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Disable
1=Enable
This register bit is not used.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
AMD RS690 ASIC Family Register Reference Manual
2-133
Graphics Controller Configuration Registers
CLKGATE_DIS_GPP_TXCLK_L0S
21
0x1
CLKGATE_DIS_GFX_CCLK
22
0x1
CLKGATE_DIS_GFX_MCLK
23
0x1
CLKGATE_DIS_GPPSB_CCLK
24
0x1
CLKGATE_DIS_GPPSB_MCLK
25
0x1
CLKGATE_DIS_CFG_S1X
28
0x1
CLKGATE_DIS_CFG_B1X
29
0x1
DEEP_S1_DISABLE
30
0x1
Scratch: This register bit can be written to, and read from,
but it does not control anything.
0=Enable
1=Disable
Disables clock gating for PCIE graphics CCLK
0=Enable
1=Disable
Disables clock gating for PCIE graphics MCLK
0=Enable
1=Disable
Disables clock gating for PCIE General Purpose and
southbridge CCLK
0=Enable
1=Disable
Disables clock gating for PCIE General Purpose and
southbridge MCLK
0=Enable
1=Disable
Disables clock gating for SCLK1X going to cfg
0=Enable
1=Disable
0=Enable
1=Disable
If enabled, S1 mode (CPU_STOP active) will power down
SPLL, BPLL, and MPLL; otherwise, S1 mode will gate
clocks only.
0=Enable
1=Disable
Register Description.
AMD RS690 ASIC Family Register Reference Manual
2-134
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CLK_TOP_PERF_CNTL - RW - 32 bits - clkconfig:0xAC
Field Name
CLK_TOP_EVENT_SEL_0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x0
Description
Performance counter 0 event select
0 = Counter disable
1 = MCLK cycles
2 = MC graphics MCLK idle
3 =
4 = MC arbiter A MCLK idle
5 = MC arbiter B MCLK idle
6 = MC sequencer A MCLK idle
7 = MC sequencer B MCLK idle
8 = MC northbridge MCLK idle
9 = MC arbiter A MCLK stop
a = MC arbiter B MCLK stop
b = MC controller MCLK stop
c = MC northbridge MCLK stop
d = BIU MCLK stop
e = MC graphics MCLK stop
f = MC sequencer A MCLK stop
10 = MC sequencer B MCLK stop
11 = MC IO A MCLK stop
12 = MC IO B MCLK stop
13 =
14 =
15 = BIU MCLK stop
16 = BIU MCLK A stop
17 = BIU MCLK B stop
18 = Core voltage at low state
19 = BIU to MC channel A RTS
1a = BIU to MC channel B RTS
1b = MC to BIU channel A RTR
1c = MC to BIU channel B RTR
1d = (BIU to MC channel A RTS) & (MC to BIU channel A RTR)
1e = (BIU to MC channel B RTS) & (MC to BIU channel B RTR)
1f = (MC arbiter A MCLK idle) & (MC sequencer A MCLK idle)
20 = (MC arbiter B MCLK idle) & (MC sequencer B MCLK idle)
21 = (MC graphics MCLK idle) & (MC northbridge MCLK idle)
22 = (MC sequencer A MCLK idle) & (MC sequencer B MCLK idle)
23 = IOC MCLK stop
24 = PCIE GFX MCLK stop
25 = PCIE GPPSB MCLK stop
26-3f = Reserved
40 = Counter disable
41 = CCLK cycles
42 = BIU CCLK idle
43 = BIU CCLK busy
44 = CPU STOP assertion
45 = BIU S2K CCLK stop
46 = BIU NB1 A CCLK stop
47 = BIU NB1 B CCLK stop
48 = IOPAD CCLK stop
49 = IOSPLL CCLK4X stop
4a = BIU PII CCLK stop
4b = EXTCPU CCLK stop
4c =
4d =
4e = IG2R6 CCLK stop
4f = CFG CCLK stop
50 =
51 =
52 =
53 =
54 = (BIU CCLK idle) & not(BIU CCLK BUSY)
55 = (BIU NB1 A CCLK stop) & (BIU NB1 B CCLK stop)
56 = (BIU S2K CCLk stop) & (BIU PII CCLK stop)
57-7f = Reserved
80 = counter disable
81 = BCLK cycles
82 =
83 =
84 =
85 =
86 =
87 =
88 =
89 =
8a =
8b =
8c =
8d =
8e =
8f = IG2R6 BCLK stop
90 =
91 =
92 =
93 =
94 =
95-ff = Reserved
AMD RS690 ASIC Family Register Reference Manual
2-135
Graphics Controller Configuration Registers
CLK_TOP_EVENT_SEL_1
15:8
0x0
CLK_TOP_UPPER_COUNT_0 (R)
CLK_TOP_UPPER_COUNT_1 (R)
Performance counter event select.
23:16
31:24
0x0
0x0
Performance counter 1 event select. Note: It has the same
definition as above.
Performance counter 0 upper bits readback.
Performance counter 1 upper bits readback.
CLK_CFG_HTPLL_CNTL - RW - 32 bits - clkconfig:0xD4
Field Name
Bits
Default
CLK_CFG_HTPLL_IPCP
2:0
0x4
CLK_CFG_HTPLL_IDB1CLK0SC
5:3
0x5
CLK_CFG_HTPLL_IDB1CLK3SC
8:6
0x5
CLK_CFG_HTPLL_IDB4CLKSC
11:9
0x5
CLK_CFG_HTPLL_ITXCLKSC
14:12
0x7
CLK_CFG_HTPLL_IVCO_MODE
16:15
0x0
CLK_CFG_HTPLL_IPLL_CTL
21:17
0x0
CLK_CFG_HTPLL_ITMONEN
22
0x0
CLK_CFG_HTPLL_PWDN
23
0x0
iCFG_HT_HTPLL_ITXCLKINV
24
0x0
iCFG_HT_HTPLL_ICLK0SEL
25
0x0
iCFG_HT_HTPLL_ICLK3SEL
26
0x0
iCFG_HT_HTPLL_IVCOREF
28:27
0x0
iCFG_HT_HTPLL_ICALREF
30:29
0x0
iCFG_HT_HTPLL_ITSTCLK
31
0x0
Description
CLK_TOP_SPARE_A - RW - 32 bits - clkconfig:0xE0
Field Name
MCLK_SWITCH_GFX_EN
spare_7_1
Bits
0
7:1
Default
0x0
0x0
CFG_B1X_CPUSTOP_DIS
8
0x0
CFG_S1X_CPUSTOP_DIS
9
0x0
15:10
16
0x0
0x1
OSC_PD
17
0x0
OSC_SRP
18
0x1
OSC_SRN
19
0x1
OSC_SP
23:20
0x4
OSC_SN
27:24
0x7
spare_31_28
Misc. register for clk_top.
31:28
0x0
spare_15_10
OSC_PU
AMD RS690 ASIC Family Register Reference Manual
2-136
Description
Bit [1]=REG_ENABLE_ASYNC_OPT
Bit [2]=Switch MC GUI & HOST IDLES to 1
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CLK_TOP_SPARE_B - RW - 32 bits - clkconfig:0xE4
Field Name
CLK_TOP_SPARE_B_0
CLKGATE_DIS_MCSQA_DEBUG
Bits
0
1
Default
0x0
0x0
CLKGATE_DIS_MCSQB_DEBUG
2
0x0
OSCOUT_OE
3
0x0
TESTCLK_MODO
4
0x0
TESTCLK_OE
5
0x0
31:6
0x0
CLK_TOP_SPARE_B
Description
Stops permanent MCLK branch
Disables extra gating condition for MCLK1X going to MC
Sequencer A
Disables extra gating condition for MCLK1X going to MC
Sequencer B
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Scratch: This register bit can be written to, and read from,
but it does not control anything.
Bit [14]: Vertical blanking switch select for mclk switching
0=Prim display
1=Sec display
Bit [15]: Enable mclk switching synced with vertical blank
from display
Bits [31:16]: To be defined
Misc. register for clk_top.
CLK_TOP_SPARE_C - RW - 32 bits - clkconfig:0xE8
Field Name
EXTEND_IOC_PM_TIMER
SPARE_1
HTPLL_IBIAS_AND_IOVERCLOCK
SPARE_11to9
CT_DISABLE_CLKGATE_HTIU_LCLK_RX
CT_DISABLE_DYNAMIC_CLKGATE_HTIU_
LCLK_RX
DISABLE_TXPHY_LCLK_GATING
SPARE_15
HTPLL_IPCP_BIT3
SPARE_31to17
Misc. register for clk_top.
Bits
0
1
8:2
11:9
12
13
Default
0x0
0x0
0x0
0x0
0x0
0x0
14
15
16
31:17
0x0
0x0
0x0
0x0
Description
CLK_TOP_SPARE_D - RW - 32 bits - clkconfig:0xEC
Field Name
OSCOUT_OUT (R)
CLK_TOP_SPARE_D (R)
Misc. status register for clk_top.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
31:1
Default
0x0
0x0
Description
OSCOUT pad readback.
To be defined.
AMD RS690 ASIC Family Register Reference Manual
2-137
Graphics Controller Configuration Registers
CFG_CT_CLKGATE_HTIU - RW - 32 bits - clkconfig:0xF8
Field Name
DISABLE_CLKGATE_HTIU_LCLK_HTM
DISABLE_DYNAMIC_CLKGATE_HTIU_L
CLK_HTM
DISABLE_CLKGATE_HTIU_LCLK_RP
DISABLE_DYNAMIC_CLKGATE_HTIU_L
CLK_RP
DISABLE_CLKGATE_HTIU_LCLK_FCB
DISABLE_DYNAMIC_CLKGATE_HTIU_L
CLK_FCB
DISABLE_CLKGATE_HTIU_LCLK_GCM
DISABLE_DYNAMIC_CLKGATE_HTIU_L
CLK_GCM
DISABLE_CLKGATE_HTIU_LCLK_NB1
DISABLE_DYNAMIC_CLKGATE_HTIU_L
CLK_NB1
DISABLE_CLKGATE_HTIU_LCLK_NB2
DISABLE_DYNAMIC_CLKGATE_HTIU_L
CLK_NB2
ILF_MODE
Bits
0
1
Default
0x1
0x1
2
3
0x1
0x1
4
5
0x1
0x1
6
7
0x1
0x1
8
9
0x1
0x1
10
11
0x1
0x1
13:12
0x0
Description
CPLL_CONTROL - RW - 32 bits - clkconfig:0x44
Field Name
CPLL_REFSEL
Bits
0
Default
0x0
CPLL_REF_DELAY
CPLL_VCO_DELAY
CPLL_SKEW4X
CPLL_SKEW2X
CPLL_SKEW1X_CORE
CPLL_CTL
1
2
5:3
8:6
11:9
16:12
0x0
0x0
0x0
0x0
0x0
0x0
CDLL_FREQ_SEL
CPLL_LF_MODE
RESERVED
CPLL_MODE (R)
20:17
24:21
27:25
31:28
0x0
0x0
0x0
0x0
Description
CPU PLL reference clock select
Default is 100MHz PCIE reference clock
not used
not used
4X output clock skew control
2X output clock skew control
not used
IPLL_CTL[4] enables calibration override. When
IPLL_CTL[4]=0, the four calibration bits are set by the
calibration loop. When IPLL_CTL[4]=1, the four bits are set
through IPLL_CTL[3:0].
Not used
Loop filter mode setting
VCO operating mode flags
CLK_TOP_PWM4_CTRL - RW - 32 bits - clkconfig:0x4C
Field Name
CT_PWM4_NumberOfCyclesInPeriod
CT_PWM4_NumberOfHighCyclesInPerio
d
CT_PWM4_en
CT_PWM4_io_oe
Bits
11:0
23:12
Default
0x0
0x0
24
25
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-138
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CLK_TOP_PWM5_CTRL - RW - 32 bits - clkconfig:0x50
Field Name
CT_PWM5_NumberOfCyclesInPeriod
CT_PWM5_NumberOfHighCyclesInPerio
d
CT_PWM5_en
CT_PWM5_io_oe
Bits
11:0
23:12
Default
0x0
0x0
24
25
0x0
0x0
Description
DELAY_SET_IOC_CCLK - RW - 32 bits - clkconfig:0x5C
Field Name
DELAY_SET_ioc_cclk_mst
DELAY_SET_ioc_cclk_slv
Delay register
Bits
4:0
9:5
Default
0x2
0x2
Description
CT_DISABLE_BIU - RW - 32 bits - clkconfig:0x68
Field Name
BIU_NB1_CPUSTOP_DIS
BIU_NB2_CPUSTOP_DIS
BIU_CCLK_C3
BIU_MCLK_C3
BIU_CCLK_IO_PAD
SYNC_DBL_FLP_EN
DELAY_SET_gpp_cclk
DELAY_SET_gpp_mclk
iCFG_CT_DISABLE_BIU_IO_CCLK4X_P
iCFG_CT_DISABLE_BIU_IO_CCLK4X_N
Disable BIU Control
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
1
2
3
4
5
10:6
15:11
16
17
Default
0x1
0x1
0x1
0x1
0x1
0x0
0x2
0x2
0x1
0x1
Description
AMD RS690 ASIC Family Register Reference Manual
2-139
Graphics Controller Configuration Registers
CPLL_CONTROL3 - RW - 32 bits - clkconfig:0x70
Bits
2:0
Default
0x1
DLL_CPP
DLL_CPN
VCOREF
4:3
6:5
8:7
0x0
0x0
0x0
CALREF
10:9
0x0
SKEW_REF
SKEW_FB
REF_DELAY
FB_DELAY
RESERVED
12:11
14:13
19:15
24:20
31:25
0x0
0x0
0x0
0x0
0x1
DLL_BIAS
Field Name
CPP control3
Description
Bias current trim. IBIAS[1:0].
00=-9%
01=0%
10=+12%
11=+25%
Default=01
Control charge pump source current, 0 off, 1 on
Control charge pump sink current, 0 off, 1 on
VCO input reference voltage setting. Controlled dynamically
during calibration.
2nd VCO input reference voltage setting. Controlled
dynamically during calibration.
1X reference clock (O1XT) skew control
1X feedback clock (O1XT) skew control
Reference frequency delay setting
Feedback clock delay setting
Bit [0] Select calibration or manual setting for charge pump
current mirror.
0=Select manual setting
1=Select calibration setting
CPLL_CONTROL2 - RW - 32 bits - clkconfig:0x98
Field Name
CPLL_SKEW1XA
CPLL_SKEW1XB
CPLL_IOBUFSEL
CPLL_SPARE
CPLL_FLOAT
RESERVED
CPLL_CP_RB (R)
CPLL_VCO_MODE_RB (R)
CPLL_FWDIV_RB (R)
Bits
2:0
5:3
6
11:7
16:12
20:17
24:21
26:25
28:27
Default
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
STRAP_FREQ_SPEED (R)
31:29
0x0
CPPL control2
AMD RS690 ASIC Family Register Reference Manual
2-140
Description
1XA output clock (O1XA) skew control
1XB output clock (O1XB) skew control
Not used
Not used
Not used
Reserved
Charge-pump current setting read back
VCO mode setting read back
Divide by 1/2/3/4 forward divider ratio read back.
00=Divide by 1
01=Divide by 2
10=Divide by 3
11=Divide by 4
Frequency detector read back.
000=100MHz
001=133MHz
010=166MHz
011=200MHz
100=266MHz
101=333MHz
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
clk_top_pwm1_ctrl - RW - 32 bits - clkconfig:0xB0
Field Name
ct_pwm1_NumberOfCyclesInPeriod
ct_pwm1_NumberOfHighCyclesInPeriod
ct_pwm1_en
ct_pwm1_io_oe
clk_top_pwm1_ctrl
Bits
11:0
23:12
24
25
Default
0x0
0x0
0x0
0x0
Description
clk_top_pwm2_ctrl - RW - 32 bits - clkconfig:0xB4
Field Name
ct_pwm2_NumberOfCyclesInPeriod
ct_pwm2_NumberOfHighCyclesInPeriod
ct_pwm2_en
ct_pwm2_io_oe
clk_top_pwm2_ctrl
Bits
11:0
23:12
24
25
Default
0x0
0x0
0x0
0x0
Description
clk_top_test_ctrl - RW - 32 bits - clkconfig:0xB8
Field Name
ct_test_clk_sel
ct_test_clk_en
ct_test_clk_oe
ct_test_clk_spare
clk_top_test_ctrl
Bits
5:0
6
7
31:16
Default
0x0
0x0
0x0
0x0
Description
CLK_TOP_THERMAL_ALERT_INTR_EN - RW - 32 bits - clkconfig:0xC0
Field Name
Bits
THERMAL_ALERT_INTR_EN
0
spare_1_31
31:1
This register is for THERMAL_ALERT_INTR_EN
Default
0x0
0x0
Description
CLK_TOP_THERMAL_ALERT_STATUS - RW - 32 bits - clkconfig:0xC4
Field Name
Bits
THERMAL_ALERT_STATUS
0
spare_1_31
31:1
This regsister is for THERMAL_ALERT_STATUS
© 2007 Advanced Micro Devices, Inc.
Proprietary
Default
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-141
Graphics Controller Configuration Registers
CLK_TOP_THERMAL_ALERT_WAIT_WINDOW - RW - 32 bits - clkconfig:0xC8
Field Name
Bits
Default
THERMAL_ALERT_WAIT_WINDOW
29:0
0x0
spare_30_31
31:30
0x0
This register is for THERMAL_ALERT_WAIT_WINDOW
Description
clk_top_pwm3_ctrl - RW - 32 bits - clkconfig:0xCC
Field Name
ct_pwm3_en
ct_pwm3_NumberOfCyclesInPeriod
ct_pwm3_NumberOfHighCyclesInPeriod
ct_pwm3_io_oe
This register is for pwm3_ctrl
Bits
0
12:1
24:13
25
Default
0x0
0x0
0x0
0x0
Description
clk_top_spare_pll - RW - 32 bits - clkconfig:0xD0
Field Name
ct_spare_pll_ctl
This register is spare
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-142
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
2.7
APC Configuration Space Registers
PCI Bus 0 - Device 1 Registers
APC_VENDOR_ID - R - 16 bits - apcconfig:0x0
Field Name
VENDOR_ID
Bits
Default
15:0
0x1002
Description
Vendor ID.
This 16-bit field identifies the manufacturer of the device:
Advanced Micro Devices, Inc.
APC_DEVICE_ID - R - 16 bits - apcconfig:0x2
DEVICE_ID
Field Name
Bits
15:0
Default
0x7912
Description
Device Identifier
This 16-bit field is assigned by the device manufacturer and
identifies the type of device. The current northbridge Device
ID assignment is 7912.
APC_COMMAND - RW - 16 bits - apcconfig:0x4
Bits
Default
Description
IO_ACCESS_EN
Field Name
0
0x0
I/O Access Enable.
This bit is always 0 because the RS690 does not respond to
I/O cycles on the PCI Bus.
0=Disable
1=Enable
MEM_ACCESS_EN
1
0x0
Memory Access Enable.
Controls whether PCI memory accesses to system memory
are accepted.
0=Disable
1=Enable
BUS_MASTER_EN
2
0x0
Bus Master Enable.
This bit is always set, indicating that the RS690 is allowed
to act as a bus master on the PCI Bus.
0=Disable
1=Enable
SPECIAL_CYCLE_EN (R)
3
0x0
Special Cycle.
This bit is always 0 because the RS690 ignores PCI special
cycles.
0=Disable
1=Enable
MEM_WRITE_INVALIDATE_EN (R)
4
0x0
Memory Write and Invalidate Enable.
This bit is always 0 because the RS690 does not generate
memory write and invalidate commands.
0=Disable
1=Enable
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-143
Graphics Controller Configuration Registers
PAL_SNOOP_EN (R)
5
0x0
VGA Palette Snoop Enable.
This bit is always 0 indicating that the RS690 does not
snoop the VGA palette address range.
0=Disable
1=Enable
PARITY_ERROR_EN (R)
6
0x0
Parity Error Response.
This bit is always 0 because the RS690 does not report
data parity errors.
0=Disable
1=Enable
Reserved0 (R)
7
0x0
SERR_EN
8
0x0
System Error Enable.
Controls the assertion of SERR#.
0=Disable
1=Enable
FAST_B2B_EN (R)
9
0x0
Fast Back-to-Back to Different Devices Enable.
This bit is always 0, because the RS690 does not allow the
generation of fast back-to-back transactions to different
agents.
0=Disable
1=Enable
15:10
0x0
This bit is reserved in PCI 2.3. It is hardwired to 0.
Reserved (R)
0=Disable
1=Enable
The AGP/PCI Command and Status register provides coarse control over the PCI-PCI bridge function within the RS690. This
register controls the ability to generate and respond to PCI cycles on both the AGP bus and the PCI bus.
APC_STATUS - RW - 16 bits - apcconfig:0x6
Bits
3:0
4
Default
0x0
0x1
PCI_66_EN (R)
5
0x1
UDF_EN (R)
6
0x0
FAST_BACK_CAPABLE (R)
7
0x0
10:9
0x1
11
0x0
Reserved (R)
CAP_LIST (R)
Field Name
DEVSEL_TIMING (R)
SIGNAL_TARGET_ABORT (R)
AMD RS690 ASIC Family Register Reference Manual
2-144
Description
Capabilities List
This bit is set to indicate that this device's configuration
space supports a capabilities list.
66-MHz Capable
Indicate that the RS690 supports 66 MHz PCI operation
User-Definable Features
This bit is always 0 indicating that UDF is not supported by
the RS690.
0=Disable
1=Enable
Fast Back-to-Back Capable
This bit is always 0 indicating that the RS690 as a target is
not capable of accepting fast back-to-back transactions
when the transactions are not to the same agent.
DEVSEL# Timing
This bit field defines the timing of DEVSEL# on the RS690.
The device only supports medium DEVSEL# timing.
Signaled Target Abort
This bit is always 0 because the RS690 does not terminate
transactions with target aborts.
0=No Abort
1=Target Abort asserted
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
RECEIVED_TARGET_ABORT (R)
12
0x0
Received Target Abort
This bit is set by whenever a CPU to PCI transaction
(except for a special cycle) is terminated due to a
target-abort. This bit is cleared by writing a 1.
0=Inactive
1=Active
RECEIVED_MASTER_ABORT (R)
13
0x0
Received Master Abort
This bit is set whenever a CPU to PCI transaction (except
for a special cycle) is terminated due to a master-abort. This
bit is cleared by writing a 1.
0=Inactive
1=Active
SIGNALED_SYSTEM_ERROR
14
0x0
Signaled System Error
This bit is set whenever the RS690 generates a System
Error and asserts the SERR# line (currently only GART
Error). This bit is cleared by writing a 1.
0=No Error
1=SERR asserted
PARITY_ERROR_DETECTED (R)
15
0x0
Detected Parity Error
This bit is always 0 because the RS690 does not support
data parity checking.
The AGP/PCI Command and Status register provides coarse control over the PCI-PCI bridge function within the RS690. This
register controls the ability to generate and respond to PCI cycles on both the AGP bus and the PCI bus.
APC_REVISION_ID - R - 8 bits - apcconfig:0x8
Bits
Default
MINOR_REV_ID
Field Name
3:0
0x0
Identifies the stepping number of the device.
Description
MAJOR_REV_ID
7:4
0x0
Identifies the revision number of the device.
Revision Identification.
APC_REGPROG_INF - R - 8 bits - apcconfig:0x9
Field Name
REG_LEVEL_PROG_INF
Bits
Default
7:0
0x0
Description
Indicates a PCI/PCI bridge.
Program Interface.
APC_SUB_CLASS - R - 8 bits - apcconfig:0xA
Field Name
SUB_CLASS_INF
Bits
Default
7:0
0x4
Description
4=Indicates a PCI/PCI bridge
Sub-Class Code.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
APC_BASE_CODE - R - 8 bits - apcconfig:0xB
Field Name
BASE_CLASS_CODE
Bits
Default
7:0
0x6
Description
Indicates a general bridge device.
Class Code.
APC_CACHE_LINE - R - 8 bits - apcconfig:0xC
Field Name
CACHE_LINE_SIZE
Bits
Default
7:0
0x0
Description
Cache Line Size.
APC_LATENCY - RW - 8 bits - apcconfig:0xD
Field Name
LATENCY_TIMER
Bits
Default
Description
7:0
0x0
This bit field defines the minimum amount of time in PCI
clock cycles that the bus master can retain ownership of the
bus. This is mandatory for masters that are capable of
performing a burst consisting of more than two data phases.
Latency Timer.
APC_HEADER - R - 8 bits - apcconfig:0xE
Field Name
HEADER_TYPE
Bits
Default
Description
7:0
0x1
Bits [6:5] are 0, indicating that Type 00 Configuration Space
Header format is supported.
Header Type.
APC_BIST - R - 8 bits - apcconfig:0xF
Field Name
Bits
Default
BIST_COMP
3:0
0x0
BIST_STRT
6
0x0
BIST_CAP
7
0x0
Description
Built-in-self-test.
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
APC_SUB_BUS_NUMBER_LATENCY - RW - 32 bits - apcconfig:0x18
Bits
Default
Description
PRIMARY_BUS
Field Name
7:0
0x0
Primary Bus Number:
Records the number of the PCI bus that the primary
interface of the bridge is connected to. The bridge uses this
to decode type 1 configuration transactions on the
secondary interface that should be converted to Special
Cycle transactions on the primary interface.
SECONDARY_BUS
15:8
0x0
Secondary Bus Number:
Records the number of the PCI bus that the secondary
interface of the bridge is connected to. The bridge uses this
to determine when to respond to type 1 configuration
transactions on the primary interface and convert them to
type 0 transactions on the secondary interface.
SUB_BUS_NUMBER
23:16
0x0
Sub-Bus Number:
Records the number of the highest numbered PCI bus that
is behind (or subordinate to) a bridge. The bridge uses this
in conjunction with the Secondary Bus Number register to
determine when to respond to type 1 configuration
transactions on the primary interface and to pass them on to
the secondary interface.
SECONDARY_LATENCY_TIMER
31:24
0x0
Secondary Latency Timer:
Adheres to the definition of the Latency Timer in the PCI
Local Bus Specification, but only applies to the secondary
interface of a PCI to PCI bridge.
Sub bus number and secondary bus latency timer.
APC_AGP_PCI_IOBASE_LIMIT - RW - 16 bits - apcconfig:0x1C
Field Name
Bits
Default
IO_BASE_R (R)
3:0
0x1
IO_BASE
7:4
0x0
11:8
0x1
15:12
0x0
IO_LIMIT_R (R)
IO_LIMIT
Description
APC_AGP_PCI_STATUS - RW - 16 bits - apcconfig:0x1E
CAP_LIST (R)
_66M (R)
UDF_EN (R)
Field Name
Bits
4
5
6
Default
0x0
0x1
0x0
FAST_B2B_CAPABLE (R)
DATA_PERR (R)
DEVSEL_TIMING (R)
SIGNAL_TARGET_ABORT (R)
7
8
10:9
11
0x0
0x0
0x1
0x0
12
0x0
TARGET_ABORT
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Disable
1=Enable
0=No Abort
1=Target Abort asserted
0=Inactive
1=Active
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Graphics Controller Configuration Registers
MASTER_ABORT
13
0x0
SYSTEM_ERROR
14
0x0
PARITY_ERROR (R)
15
0x0
0=Inactive
1=Active
0=No Error
1=SERR asserted
APC_AGP_PCI_MEMORY_LIMIT_BASE - RW - 32 bits - apcconfig:0x20
Field Name
Bits
Default
MEM_BASE_31_20
15:4
0x0
MEM_LIMIT_31_20
31:20
0x0
Description
APC_AGP_PCI_PREFETCHABLE_LIMIT_BASE - RW - 32 bits - apcconfig:0x24
Field Name
PREF_MEM_BASE_R (R)
Bits
3:0
Default
0x1
Description
0h=32-bit memory decoder,
1h=64-bit memory decoder.
PREF_MEM_BASE_31_20
15:4
0x0
Prefetchable Memory Base Address:
Prefetchable Memory Base Address defines the base
address of the prefetchable address range used by the
AGP target (graphics controller) where control registers and
FIFO-like communication interfaces are mapped. Bits [15:4]
correspond to address bits [31:20]. The lower 20 bits of the
address are assumed to be 0. The memory address range
adheres to 1-Mbyte alignment and granularity.
PREF_MEM_LIMIT_R (R)
19:16
0x1
0h=32-bit memory decoder,
1h=64-bit memory decoder.
PREF_MEM_LIMIT_31_20
31:20
0x0
Prefetchable Memory Limit Address:
Prefetchable Memory Limit Address defines the top address
of the prefetchable address range used by the AGP target
(graphics controller) where control registers and FIFO-like
communication interfaces are mapped. The lower 20
bits of address are assumed to be 0xFFFFF. The memory
address range adheres to 1-Mbyte alignment and
granularity.
This register defines the base and the size of the prefetchable memory area within the AGP address space.
APC_AGP_PCI_PREFETCHABLE_BASE_Upper - RW - 32 bits - apcconfig:0x28
Field Name
Bits
Default
PREF_MEM_BASE_39_32
7:0
0x0
This register defines the upper base of prefetchable memory area.
Description
APC_AGP_PCI_PREFETCHABLE_LIMIT_Upper - RW - 32 bits - apcconfig:0x2C
Field Name
Bits
Default
PREF_MEM_LIMIT_39_32
7:0
0x0
This register defines the upper limit of prefetchable memory area.
AMD RS690 ASIC Family Register Reference Manual
2-148
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
APC_AGP_PCI_IO_LIMIT_BASE_HI - RW - 32 bits - apcconfig:0x30
Field Name
Bits
Default
Description
IO_BASE_31_16
15:0
0x0
I/O Base:
This field defines the base (inclusive) of 25-bit I/O
addresses that are passed to the AGP/PCI bus.
Note: Bits [9:15] of this field are hardwired to 0.
IO_LIMIT_31_16
31:16
0x0
I/O Limit:
This field defines the upper limit (inclusive) of 25-bit I/O
addresses that are passed to the AGP/PCI bus.
Note: Bits [9:15] of this field are hardwired to 0.
This set of registers define the valid range of 32-bit I/O addresses that are allowed to be forwarded from the host to the
AGP/PCI. Note: if this register is 0, 32-bit addressing mode is effectively disabled.
APC_CAPABILITIES_PTR - R - 32 bits - apcconfig:0x34
CAP_PTR
Field Name
Bits
7:0
Default
0x44
Description
This field contains a byte offset into a device's configuration
space containing the first item in the capabilities list. If no
next item exists, then it is set to null. It is hardwired to 0xB0
to indicate SSID capabilities.
Capabilities Pointer
APC_AGP_PCI_IRQ_BRIDGE_CTRL - RW - 32 bits - apcconfig:0x3C
Bits
Default
Description
INT_LINE
Field Name
7:0
0x0
Interrupt Line.
Communicates interrupt line routing information. This field
is a simple R/W field that allows the BIOS to program to the
required value.
INT_PIN
15:8
0x0
Interrupt Pin.
Indicates which interrupt pin the PCI to PCI bridge uses.
Note: This field is R/W depending on the value of the
IntPinCntl bit (Bit [1] of Dev 1:0x40). Refer to Dev1:0x40 for
more details. The ability to write to this field is supported in
order to allow the BIOS to program to the required value.
The RS690 HW does not use this field internally in any way.
PARITY_RESPONSE_EN (R)
16
0x0
Parity Response Enable.
The RS690 does not support parity.
SERR_EN
17
0x0
SERR Enable.
Forwards the secondary interface SERR# assertions to the
primary interface. This bit must be set, along with the SERR
Enable bit (Dev 1:F0:0x04), to allow an AGP SERR# to be
propagated to the RS690 PCI SERR# pin.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
ISA_EN
18
0x0
ISA Enable.
Modifies the response by the bridge to ISA I/O addresses.
This applies only to I/O addresses that are enabled by the
I/O Base and I/O Limit registers, and are in the first 64
Kbytes of PCI I/O address space (0000 0000h to 0000
FFFFh).
When set, the bridge will block any forwarding from primary
to secondary of I/O transactions addressing the last 768
bytes in each 1-Kbyte block. In the opposite direction
(secondary to primary), I/O transactions are forwarded if
they address the last 768 bytes in each 1-Kbyte block.
0=Forwards all I/O addresses in the address range
defined by the I/O Base and I/O Limit registers.
1=Blocks forwarding of ISA I/O addresses in the address
range defined by the I/O Base & I/O Limit registers that
are in the first 64 Kbytes of PCI I/O address space (top
768 bytes of each 1-Kbyte block).
VGA_EN
19
0x0
VGA Enable.
Affects the response by the bridge to compatible VGA
addresses. When it is set, the bridge will decode and
forward the following accesses on the primary interface to
the secondary interface.
Memory accesses in the range: 0xA0000 to 0xBFFFF.
I/O Address where AD[9:0] are in the ranges: 0x3B0 to
0x3BB and 0x3C0 to 0x3DF (inclusive of ISA address
aliases - AD[15:10] are not decoded).
VGA_16_EN
20
0x0
VGA IO 16-bit decoding enable.
When set, the northbridge decodes address [15:10] for the
VGA IO space. When cleared, the address [15:10] is not
decoded for the VGA IO space.
MASTER_ABORT_MODE
21
0x0
Master Abort Mode.
Determines the behavior of the PCI to PCI bridge when a
master abort termination occurs on either interface when
the bridge is the master of the transaction.
SECONDARY_BUS_RESET
22
0x0
Secondary Bus Reset.
Forces the assertion on the RST# secondary interface.
00=Run
01=Reset
FAST_B2B_CAPABLE
23
0x0
Fast Back-to-Back Capable:
This bit is always 0 indicating that the RS690, as a master,
is not capable of generating fast back-to-back transactions
to different agents on the secondary bus.
00=Not Capable
01=Capable
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
APC_MISC_DEVICE_CTRL - RW - 32 bits - apcconfig:0x40
Field Name
INT_PIN_CTRL
Bits
0
Default
0x0
ApcOrderDisable
1
0x0
ApcP2PDis
2
0x0
ApcIntSelMode
StpAgpMode
3
4
0x0
0x0
ApcBMSetDis
5
0x0
ApcBMSetDis_AGPBUSY
6
0x0
Description
0=Read-Only
1=Read-Writeable
If not set, the APC ordering rule is forced. If set, then the
APC ordering rule is not forced.
0=Enable
1=Disable
If not set, P2P memory writes target at internal graphics is
enabled.
0=Enable
1=Disable
If set, Interrupt ABCE will be mapped as EFGH.
If not set, PMArbDis = STP_AGP. If set, only
STP_AGP_Assert message could trigger STP_AGP.
If not set, the falling edge of BIF_MST_IDLE# will trigger
BM_Set message if BM_STS was 0. (Note: BMMsgEn has
to be set first to enable BM_Set message generation)
0=Enable
1=Disable
If not set, AGP_BUSY will trigger BM_Set message if
BM_STS is 0. (Note: BMMsgEn has to be set first to enable
BM_Set message generation)
0=Enable
1=Disable
APC_HT_MSI_CAP - R - 32 bits - apcconfig:0x44
Field Name
CAP_ID
CAP_POINTER
EN
Fixd
RESERVED_26_18
CAPABILITY_TYPE
Bits
7:0
15:8
16
17
26:18
31:27
Default
0x8
0xb0
0x1
0x1
0x0
0x15
Description
APC_ADAPTER_ID_W - RW - 32 bits - apcconfig:0x4C
Field Name
Bits
Default
SUBSYSTEM_VENDOR_ID
15:0
0x1002
SUBSYSTEM_ID
31:16
0x7912
Description
Subsystem Vendor ID and Subsystem ID write register.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-151
Graphics Controller Configuration Registers
APC_SSID_CAP_ID - R - 32 bits - apcconfig:0xB0
Field Name
Bits
Default
7:0
0xd
CapID
NEXT_PTR
15:8
0x80
Pointer to the next item in the capabilities list.
Reserved
31:16
0x0
CAP_ID
Description
This read-only register describes the SSID implemented (1.2).
APC_SSID - R - 32 bits - apcconfig:0xB4
Field Name
SUBSYSTEM_VENDOR_ID
Bits
Default
15:0
0x0
31:16
0x0
Description
(mirror of
APC_ADAPTER_ID_W:SUBSYSTEM_VENDO
R_ID)
SUBSYSTEM_ID
(mirror of
APC_ADAPTER_ID_W:SUBSYSTEM_ID)
Subsystem Vendor ID and Subsystem ID register.
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
2.8
Side-Port Memory Controller Registers
MC_GENERAL_PURPOSE - RW - 32 bits - NBMCIND:0x0
Field Name
MEM_AIC_CONT_REQ_G1
Bits
3:0
Default
0x0
MEM_AIC_CONT_REQ_G2
7:4
0x0
MEM_GART_SYNCHRO_FIFO
MEM_GART_2DW
MEM_SUS_STAT_EN
8
9
10
0x1
0x1
0x0
11
12
13
18:16
19
31
0x0
0x0
0x0
0x3
0x0
0x0
MEM_D3_RBS_IDLE
MEM_D3_MCB_IDLE
RBS_SP_64BYTE_RTR4
REG_RD_DELAY
STUTTER_IGNORE_C3
MC_INIT_COMPLETE
Memory controller general purpose register.
Description
Number of consecutive AGP/PCI requests for group 1
clients (G3D0R, G3D0W, G3D1R, G3D1W, GTX0R)
0=Single request
15=16 requests in row
Number of consecutive AGP/PCI requests for group 2
clients (HDPW, CPW, DISP2R, HDPR, CPR, OVLYR,
DISPR, IDCTR)
0=Single request
15=16 requests in row
N/A
N/A
When TVCLKIN is used as the SUS_STATb signal this bit
must be set to 1; else this bit is set to 0
As long as this bit is 0, the MC will not accept requests from
the clients. This is used primarily to block requests when
the MC might mishandle them, such as when the FB or
AGP apertures are undefined or unstable.
0=Register Initialization Not Complete
1=Register Initialization Complete
MC_MISC_CNTL - RW - 32 bits - NBMCIND:0x18
Field Name
DISABLE_GTW
DBL_FLOP_EN
GART_INDEX_REG_EN
BLOCK_GFX_D3_EN
DEBUGBUS_CYCLE_EN
Miscellaneous controls for memory controller
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
1
2
12
Default
0x0
0x0
0x0
14
31
0x1
0x0
N/A
Description
This bit switches between MMGART registers and MCIND
GART registers when NOT in AGP3.x/enhanced mode.
Bits [4:3] of NBCFG:NBCNTL, NBMISCIND 0x0
(AGP30ENHANCED, AGP30ENHANCED) must be 00 for
this register to take effect.
0=Use mmgart registers.
1=Use mcind gart registers.
Enables all available debug bus signals to cycle every 16
clocks.
0=Disable
1=Enable
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Graphics Controller Configuration Registers
K8_FB_LOCATION - RW - 32 bits - NBMCIND:0x1E
Field Name
K8_FB_START
Bits
31:0
Default
0x0
Start of frame buffer in shared K8 system memory.
Description
This register indicates the start of the frame buffer in the
K8's system memory. The frame buffer in system memory is
not allowed to span across 4G boundaries.
Note: Bits [4:0] of this field are hardwired to 0.
NB_MC_DEBUG - RW - 32 bits - NBMCIND:0x1F
Field Name
Reserved0
RBS_STALL_FIFO
Bits
2:0
3
Default
0x0
0x0
Reserved1
NC_DEBUG_MUX
MC_DEBUG_EN
4
14:8
15
0x0
0x0
0x0
TESTBUS_INT (R)
31:16
0x0
Description
0=Reserved
0=Normal operation
1=Do not pop data out of read_bus_switch FIFO
0=Reserved
0=Debug bus mux select
0=Disable
1=Enable
Read back of the debug bus value.
MC_PM_CNTL - RW - 32 bits - NBMCIND:0x26
Field Name
AUTO_CLOCK_THROTTLING
Bits
0
Default
0x0
1
0x0
3:2
0x0
AUTO_CLOCK_THROTTLING_NB
4
0x0
CLOCK_THROTTLING_EN_NB
5
0x0
CLOCK_THROTTLING_EN
THROTTLE_STATE_SETTING
AMD RS690 ASIC Family Register Reference Manual
2-154
Description
For internal graphic clients.
0=Clock throttling state is set by
THROTTLE_STATE_SETTING register
1=Clock throttling state is set by the input signals from
clk top.
For internal graphic clients.
0=Disable clock throttling function
1=Enable clock throttling function
For internal graphic clients.
00=No blocking
01=Block the incoming requests 64 clock cycles every
128 clock cycles.
10=Block the incoming requests 96 clock cycles every
128 clock cycles.
11=Block the incoming requests 112 clock cycles every
128 clock cycles.
For internal graphic clients.
0=Clock throttling state is set by
THROTTLE_STATE_SETTING_NB register
1=Clock throttling state is set by the input signals from
clk_top
For NB clients
0=Disable clock throttling function
1=Enable clock throttling function
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
THROTTLE_STATE_SETTING_NB
7:6
0x0
BLACKOUT_NB_DELAY
8
0x0
THROTTLE_READ_EN
9
0x0
THROTTLE_WRITE_EN
10
0x0
THROTTLE_DISP_EN
11
0x0
For NB clients
00=No blocking
01=Block the incoming requests 64 clock cycles every
128 clock cycles.
10=Block the incoming requests 96 clock cycles every
128 clock cycles.
11=Block the incoming requests 112 clock cycles every
128 clock cycles.
Delay the NB blackout request from clk_top
0=Delay 1 clock cycle
1=Delay 2 clock cycles.
Enables clock throttling feature to block both NB and
graphic read requests (except display and display2
requests).
0=Disable
1=Enable
Enables clock throttling feature to block both NB and
graphic write requests.
0=Disable
1=Enable
Enables clock throttling feature to block both display and
display2 requests.
0=Disable
1=Enable
Power management refresh control & clock throttling.
GART_FEATURE_ID - RW - 32 bits - NBMCIND:0x2B
Bits
7:0
Default
0x0
VAL_CAP
8
0x0
LINK_CAP
9
0x0
P2P_CAP
10
0x0
HANG_EN
11
0x0
GARV_ERR_EN
16
0x0
REV_ID
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
This field contains the Revision ID.
Read Only = 01
Note: Bits [1:0] of this field are hardwired to 0.
This bit is set to indicate that the RS690 supports the
detection of Valid Bit errors
Read Only = 1
0=N/A
This bit is always low, indicating that GART Entry Multiple
Pages are not Supported
Read Only = 0
00=N/A
This bit is hardwired to 0 to indicate that the RS690 only
implements those PCI-PCI Bridge commands required to
implement AGP (the RS690 does not implement a complete
PCI2.2 compliant PCI-PCI bridge between PCI and AGP).
00=N/A
When set, illegal GART entries fetched by the GTW logic
will force the RS690 to hang.
0=Do not hang state machine on invalid page table
1=Hang state machine
When set, the RS690 will assert SERR when a graphics
device attempts to access a page in AGP memory which is
not valid (Valid Bit Error). A valid bit error will cause the
GART Table walk state machine to hang. The processor
can still access memory after that if it does not use GART
address space
00=N/A
AMD RS690 ASIC Family Register Reference Manual
2-155
Graphics Controller Configuration Registers
SB_STB_TOGGLE_DETECT_DISABLE
17
0x0
TLB_ENABLE
18
0x0
P2P_ENABLE
19
0x0
VAL_ERROR (R)
24
0x0
GTW_LAC_EN
25
0x0
GART_CACHE_STATUS
26
0x0
P2P_STATUS
27
0x0
29:28
0x0
LV1_INDEX
30
0x0
PDC_EN
31
0x0
VALID_BIT_ERROR_ID (R)
GART Feature and Capability Register
AMD RS690 ASIC Family Register Reference Manual
2-156
When set, this bit disables the AGP Sideband strobe toggle
detect logic. This bit must be set for normal operation.
00=N/A
When set, this bit enables the caching of GART TLB
entries.
0=TLB caching disabled
1=TLB caching enabled
This bit is hardwired to 0 to indicate that the RS690 only
implements those PCI-PCI Bridge commands required to
implement AGP (the RS690 does not implement a complete
PCI2.2 compliant PCI-PCI bridge between PCI and AGP)
00=N/A
When set, this bit indicates that a Valid Bit Error has been
detected and SERR has been asserted.
Initial State=0.
0=OK
1=Valid Bit Error
When set, this bit turns on the GTW's Look-Ahead_Cache,
which caches previous 32-byte Page Table Access.
0=Disable GTW's LAC
1=Enable GTW's LAC
When set, the GART cache has been enabled by software.
When clear, the GART cache is disabled.
Initial State=0.
00=N/A
This bit is hardwired to zero to indicate that the RS690 only
implements those PCI-PCI Bridge commands required to
implement AGP (RS690) does not implement a complete
PCI 2.2 compliant PCI-PCI bridge between PCI and AGP)
0=N/A
These bits are used to determine the source of the valid bit
error. The values are as follows.
00=AGP
01=CPU 0
10=Undefined
11=PCI / AGP's PCI
Initial State=00
0=00 - PDQry
1=01 - PTQry
2=10 - GtwLACHit
3=11 - GtwQWait
Level 1 Index:
GART Index Scheme Control. When set to 1, this bit
enables the 1-level GART Mode. When cleared to 0, 2-level
GART Mode is enabled
0=2 Level GART
1=1 Level GART
Page Directory Cache Enable:
GART Page Directory Cache Enable. This bit is used only
in the 2-Level GART Mode. It has no effect in the 1-Level
GART Mode. The GART Directory is enabled only when
both this bit and the AGP Features Control Register (offset
02h of the memory-mapped Features and Capabilities
Register) bit 2, 'GART Cache Enable' are 1s. This bit is
included for performance studies and debug.
0=Disable Page Directory Cache
1=Enable Page Directory Cache
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GART_BASE - RW - 32 bits - NBMCIND:0x2C
Field Name
Bits
DIRECTORY_BASE_HI
11:4
DIRECTORY_BASE_LO
31:12
GART Directory Base Address, 4 kB granularity.
Default
0x0
0x0
Description
Bits [39:32] of GART directory base.
Bits [31:12] of GART directory base.
GART_CACHE_SZBASE - R - 32 bits - NBMCIND:0x2D
Field Name
GART_CACHE_SIZE
GART Cache Size Number of entries.
Bits
31:0
Default
0x10
Description
Hardwired to 0x00000010
GART_CACHE_CNTRL - RW - 32 bits - NBMCIND:0x2E
Field Name
GART_CACHE_INVALIDATE_W (W)
Bits
0
Default
0x0
GART_CACHE_INVALIDATE_R (R)
0
0x0
GART Cache Control Register
Description
When set to 1, the entire GART Directory and Table Cache
is invalidated. When the operation is completed, set this bit
to 0.
0=No change
1=Clear Tlb
When GART_CACHE_INVALIDATE_W is set to 1,
GART_CACHE_INVALIDATE_R will toggle from 1 to 0
when the operation is completed.
0=Done Clear
1=Clear Pending
GART_CACHE_ENTRY_CNTRL - RW - 32 bits - NBMCIND:0x2F
Field Name
TlB_INV_ENT_R (R)
Description
0=Invalidate Done
1=Invalidate Pending
TlB_INV_ENT_W (W)
0
0x0
0=No Invalidate
1=Invalidate Tlb
TlB_UPDATE_R (R)
1
0x0
0=Update Done
1=Update Pending
TlB_UPDATE_W (W)
1
0x0
0=No Update
1=Update Tlb
GART_TABLE_ENTRY_ADDRESS
31:12
0x0
Virtual address of GART entry to invalidate/update.
This register allows the driver to update/invalidate specific entries in the GART cache.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
GART_ERROR_0 - RW - 32 bits - NBMCIND:0x30
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that hit an invalid aperture
page.
GART_ERROR_1 - RW - 32 bits - NBMCIND:0x31
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that hit an invalid aperture
page.
GART_ERROR_2 - RW - 32 bits - NBMCIND:0x32
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that his an invalid aperture
page.
GART_ERROR_3 - RW - 32 bits - NBMCIND:0x33
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
AMD RS690 ASIC Family Register Reference Manual
2-158
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that his an invalid aperture
page.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GART_ERROR_4 - RW - 32 bits - NBMCIND:0x34
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that hit an invalid aperture
page.
GART_ERROR_5 - RW - 32 bits - NBMCIND:0x35
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that hit an invalid aperture
page.
GART_ERROR_6 - RW - 32 bits - NBMCIND:0x36
Field Name
INVALID_WRITE (R)
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
Field Name
INVALID_WRITE (R)
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that hit an invalid aperture
page.
GART_ERROR_7 - RW - 32 bits - NBMCIND:0x37
Bits
1:0
Default
0x0
INVALID_WRITE_ADDR (R)
15:2
0x0
INVALID_READ (R)
17:16
0x0
INVALID_READ_ADDR (R)
31:18
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Write attempted to addr with WrValid not set
1=No error
Address of an AGP write request that hit an invalid aperture
page.
0=Read attempted to addr with RdValid not set
1=No error
Address of an AGP read request that hit an invalid aperture
page.
AMD RS690 ASIC Family Register Reference Manual
2-159
Graphics Controller Configuration Registers
AGP_ADDRESS_SPACE_SIZE - RW - 32 bits - NBMCIND:0x38
GART_EN
VA_SIZE
Field Name
VGA_IA_EN
Bits
0
3:1
Default
0x0
0x0
16
0x0
N/A
0=32 MB
1=64 MB
2=128 MB
3=256 MB
4=512 MB
5=1 GB
6=2 GB
7=Undefined
N/A
Description
AGP_MODE_CONTROL - RW - 32 bits - NBMCIND:0x39
Field Name
POST_GART_Q_SIZE
NONGART_SNOOP
AGP_RD_BUF_SIZE
REQ_TYPE_SNOOP
REQ_TYPE_SNOOP_EN
Bits
18
19
20
23:22
24
Default
0x0
0x0
0x0
0x1
0x1
Description
N/A
N/A
N/A
N/A
0=Enable snoop of gart-mapped physical address
1=Disable snoop
AIC_CTRL_SCRATCH - RW - 32 bits - NBMCIND:0x3A
Field Name
TRANSLATE_EN
Bits
0
Default
0x0
DIS_OUT_OF_PCI_GART_ACCESS
1
0x0
RBB_AGP3X_LacDisable
2
0x0
RBB_AGP3X_TlbDisable
3
0x0
GART_LAC_EN_OVERIDE
4
0x0
GART_SNOOP_EN_OVERRIDE
5
0x0
GART_INVALIDATE_OVERRIDE
6
0x0
AMD RS690 ASIC Family Register Reference Manual
2-160
Description
N/A.
0=N/A
0=Out of PCI GART access enabled.
1=Out of PCI GART access disabled.
0=GART LAC controlled by APC_AGP_CONTROL,
TlbEn when in AGP3X mode.
1=GART LAC DISABLED when in AGP3X mode.
0=GART client TLB controlled by
APC_AGP_CONTROL, TlbEn when in AGP3X mode.
1=GART client TLB DISABLED when in AGP3X mode.
0=Use LAC enable register bit of GART’s mode of
operation (mmgart or apcconfig).
1=Over-ride mmgart or apcconfig LAC enable register
bits and use nbmcind 0.2B, GART_FEATURE_ID, bit [25].
0=Use snoop enable register bit of GART’s mode of
operation (mmgart or apcconfig).
1=Over-ride mmgart or apcconfig snoop enable register
bits and use nbmcind 0x39, AGP_MODE_CONTROL, bit
[24].
0=Use cache invalidate register bit of GART’s mode of
operation (mmgart or apcconfig).
1=Over-ride mmgart or apcconfig cache invalidate
register bits and use nbmcind 0x2E,
GART_CACHE_CNTRL, bit [0].
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GART_HANG_EN_OVERRIDE
7
0x0
DIS_ARB_AGP_FB
8
0x0
0=Use hang enable register bit of gart's mode of
operation (mmgart).
1=Over-ride mmgart or apcconfig hang enable register
bits and use nbmcind 0x2E, GART_CACHE_CNTRL, bit
[0].
0=Enable mix APG and framebuffer
1=Disable mix APG and framebuffer
MC_GART_ERROR_ADDRESS - RW - 32 bits - NBMCIND:0x3B
Field Name
MC_GART_ERROR_ADDRESS
Bits
31:0
Default
0x0
Bits [31:0] of gart error_address.
Description
Bits [31:0] of gart_error_address. Address that GART sends
to mc arbiters or bif when clients try to access an invalid
physical address.
MC_GART_ERROR_ADDRESS_HI - RW - 32 bits - NBMCIND:0x3C
Field Name
MC_GART_ERROR_ADDRESS_HI
Bits [39:40] of gart_error_address.
Bits
7:0
Default
0x0
Description
Bits [39:40] of gart_error_address
MC_MISC_CNTL2 - RW - 32 bits - NBMCIND:0x4E
Field Name
AGP_LATENCY_TIMER
AGP_FIFO_LEVEL_URG_EN
Bits
3:0
4
Default
0x0
0x0
AGP_FIFO_LEVEL_MAX
8:5
0x0
AGP_FIFO_LEVEL_DRAIN
12:9
0x0
DELAY_EMPTY
DELAY_NOT_FULL
GFX_IDLE_LIMIT
21
22
28:23
0x0
0x0
0x4
31
0x0
AgpPriorEn
Miscellaneous controls(2) for memory controller
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Sets the latency timer for internal AGP.
Enables internal AGP urgency based on FIFO level
0=Disable
1=Enable
Specifies the FIFO level that triggers internal AGP as the
urgent client. AgpFifoLevelUrgEn needs to be enabled.
Specifies to what level FIFO needs to be drained before
urgency for the internal AGP is turned off. AgpFifoLev
Masks the bank for GFX_IDLE_LIMIT * 4 cycles in second
level arbiter.
Enables internal AGP as a priority client.
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
MC_MISC_UMA_CNTL - RW - 32 bits - NBMCIND:0x5F
Field Name
K8_40BIT_ADDR_EXTENSION
Bits
7:0
Default
0x0
8
0x0
GFX_64BYTE_MODE
GFX_64BYTE_LAT
GTW_COHERENCY
9
14:10
15
0x0
0x0
0x0
READ_BUFFER_SIZE
23:16
0x80
HDR_ROUTE_TO_DSP
24
0x0
GTW_ROUTE_TO_DSP
25
0x0
DSP_ROUTE_TO_GFX
26
0x0
USE_HDPW_LAT_INIT
27
0x0
USE_GFXW_LAT_INIT
28
0x0
MCIFR_COHERENT
NON_SNOOP_AZR_AIC_BP
SIDE_PORT_PRESENT_W (W)
29
30
31
0x0
0x0
0x0
SIDE_PORT_PRESENT_R (R)
31
0x0
GART_BYPASS
Description
Upper fixed 8-bits of the 40-bit K8 address space. All
addresses that are directed at the K8 frame buffer memory
will be prefixed with this value.
0=Enable gart table translations on chipset
1=Bypass gart table on chipset
0=GTW requests will not be issued as a coherent request
1=GTW requests will be issued as a coherent request
Defines the size of Read Data Return Buffer in the
read-bus-switch (max = 128, min = 8).
1=HDP requests routed to display pipe.
0=HDP requests routed to graphics pipe. Def=0
1=GTW requests routed to display pipe.
0=GTW requests routed to graphics pipe. Def=0
0=Disable
1=Enable
1=Display requests routed to graphics pipe.
0=Display requests routed to display pipe. Def=0
1=Route HDP reads to isochronous display pipe after
being block by HDP writes for a certain number of clocks
(HDR_LAT_INIT_HDPW).
0=Disable.
1=Route HDP reads to isochronous display pipe after
being block by any GFX writes for a certain number of
clocks (HDR_LAT_INIT_GFXW).
0=Disable.
0=Sideport not present
1=Sideport present
0=Sideport not present
1=Sideport present
K8_DRAM_CS0_BASE - RW - 32 bits - NBMCIND:0x63
Bits
0
Default
0x1
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x0
CSBE
Field Name
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
This field is only used in optimized case (interleave mode)
when all chip select banks are the same size and the type
and the number of chip selects is a power of two. In this
case, the memory is interleaved differently to avoid page
conflicts.
This field defines the top 11 address bits of a 40-bit address
that defines the memory address space. These bits decode
32-Mbyte blocks of memory. In the non-interleaving mode,
BaseAddrLo has a value of 0.
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 40h. Refer to BKDG for AMD64 and
AMD Opteron.
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
K8_DRAM_CS1_BASE - RW - 32 bits - NBMCIND:0x64
Bits
0
Default
0x1
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x20
CSBE
Field Name
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 44h. Refer to BKDG for AMD64 and
AMD Opteron.
K8_DRAM_CS2_BASE - RW - 32 bits - NBMCIND:0x65
Bits
0
Default
0x1
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x40
CSBE
Field Name
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 48h. Refer to BKDG for AMD64 and
AMD Opteron.
K8_DRAM_CS3_BASE - RW - 32 bits - NBMCIND:0x66
CSBE
Field Name
Bits
0
Default
0x1
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x60
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 4Ch. Refer to BKDG for AMD64 and
AMD Opteron.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
K8_DRAM_CS4_BASE - RW - 32 bits - NBMCIND:0x67
Bits
0
Default
0x0
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x80
CSBE
Field Name
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 50h. Refer to BKDG for AMD64 and
AMD Opteron.
K8_DRAM_CS5_BASE - RW - 32 bits - NBMCIND:0x68
Bits
0
Default
0x0
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x80
CSBE
Field Name
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 54h. Refer to BKDG for AMD64 and
AMD Opteron.
K8_DRAM_CS6_BASE - RW - 32 bits - NBMCIND:0x69
CSBE
Field Name
Bits
0
Default
0x0
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x80
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 58h. Refer to BKDG for AMD64 and
AMD Opteron.
AMD RS690 ASIC Family Register Reference Manual
2-164
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
K8_DRAM_CS7_BASE - RW - 32 bits - NBMCIND:0x6A
CSBE
Field Name
Bits
0
Default
0x0
BaseAddrLo_Ext_RevF
BaseAddrLo
8:5
15:9
0x0
0x0
BaseAddrHi_Ext_RevF
BaseAddrHi
20:19
31:21
0x0
0x80
Description
0=Chip-Select Bank not enabled
1=Chip-Select Bank enabled
See the description for the corresponding field in
K8_DRAM_CS0_BASE
See the description for the corresponding field in
K8_DRAM_CS0_BASE
Mirror image of Opteron processor DRAM_CS_Base_Address register, Function 2: Offset 5Ch. Refer to BKDG for AMD64 and
AMD Opteron.
K8_DRAM_CS0_MASK - RW - 32 bits - NBMCIND:0x6B
Field Name
AddrMaskLo_Ext_RevF
AddrMaskLo
Bits
8:5
15:9
Default
0xf
0x7f
AddrMaskHi_Ext_RevF
AddrMaskHi
20:19
29:21
0x3
0x1f
Description
This field specifies the addresses to be excluded for the
optimized case descried in the Base Address bit definitions
(see description for register K8_DRAM_CS0_BASE).
This field defines the top Address Mask bits. The bits with
an address mask of 1 are excluded from the address
comparison. This allows the memory block size to be larger
than 32 Mbytes. If Address Mask bit 25 is set to 1, the
memory block size is 64 Mbytes.
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2: Offset 60h.
K8_DRAM_CS1_MASK - RW - 32 bits - NBMCIND:0x6C
Field Name
AddrMaskLo_Ext_RevF
AddrMaskLo
Bits
8:5
15:9
Default
0xf
0x7f
AddrMaskHi_Ext_RevF
AddrMaskHi
20:19
29:21
0x3
0x1f
Description
See the description for the corresponding field in
K8_DRAM_CS0_MASK
See the description for the corresponding field in
K8_DRAM_CS0_MASK
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2: Offset 64h. Refer to BKDG for AMD64 and AMD
Opteron.
K8_DRAM_CS2_MASK - RW - 32 bits - NBMCIND:0x6D
Field Name
AddrMaskLo_Ext_RevF
AddrMaskLo
Bits
8:5
15:9
Default
0xf
0x7f
AddrMaskHi_Ext_RevF
AddrMaskHi
20:19
29:21
0x3
0x1f
Description
See the description for the corresponding field in
K8_DRAM_CS0_MASK
See the description for the corresponding field in
K8_DRAM_CS0_MASK
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2: Offset 68h. Refer to BKDG for AMD64 and AMD
Opteron.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-165
Graphics Controller Configuration Registers
K8_DRAM_CS3_MASK - RW - 32 bits - NBMCIND:0x6E
Field Name
AddrMaskLo_Ext_RevF
AddrMaskLo
Bits
8:5
15:9
Default
0xf
0x7f
AddrMaskHi_Ext_RevF
AddrMaskHi
20:19
29:21
0x3
0x1f
Description
See the description for the corresponding field in
K8_DRAM_CS0_MASK
See the description for the corresponding field in
K8_DRAM_CS0_MASK
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2: Offset 6Ch. Refer to BKDG for AMD64 and AMD
Opteron.
K8_DRAM_CS4_MASK - RW - 32 bits - NBMCIND:0x6F
Description
See the description for the corresponding field in
K8_DRAM_CS0_MASK
AddrMaskHi
29:21
0x1ff
See the description for the corresponding field in
K8_DRAM_CS0_MASK
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2: Offset 70h. Refer to BKDG for AMD64 and AMD
Opteron.
AddrMaskLo
Field Name
Bits
15:9
Default
0x7f
K8_DRAM_CS5_MASK - RW - 32 bits - NBMCIND:0x70
Description
Reserved.
See description for corresponding field in
K8_DRAM_CS0_MASK
AddrMaskHi
29:21
0x1ff
See description for corresponding field in
K8_DRAM_CS0_MASK
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2: Offset 74h. Refer to BKDG for AMD64 and AMD
Opteron.
SPARE_70 (R)
AddrMaskLo
Field Name
Bits
7:0
15:9
Default
0x0
0x7f
K8_DRAM_CS6_MASK - RW - 32 bits - NBMCIND:0x71
Description
Reserved
See the description for the corresponding field in
K8_DRAM_CS0_MASK.
AddrMaskHi
29:21
0x1ff
See the description for the corresponding field in
K8_DRAM_CS0_MASK.
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2:Offset 78h. Refer to BKDG for AMD64 and AMD
Opteron.
SPARE_71
AddrMaskLo
Field Name
Bits
7:0
15:9
Default
0x0
0x7f
AMD RS690 ASIC Family Register Reference Manual
2-166
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
K8_DRAM_CS7_MASK - RW - 32 bits - NBMCIND:0x72
Description
Reserved
See the description for the corresponding field in
K8_DRAM_CS0_MASK.
AddrMaskHi
29:21
0x1ff
See the description for the corresponding field in
K8_DRAM_CS0_MASK.
Mirror image of Opteron processor DRAM_CS_Mask register, Function 2:Offset 7Ch. Refer to BKDG for AMD64 and AMD
Opteron.
SPARE_72
AddrMaskLo
Field Name
Bits
7:0
15:9
Default
0x0
0x7f
K8_DRAM_BANK_ADDR_MAPPING - RW - 32 bits - NBMCIND:0x73
Bits
3:0
Default
0x5
CS23
7:4
0x5
CS45
11:8
0x0
CS67
15:12
0x0
CS01
Field Name
© 2007 Advanced Micro Devices, Inc.
Proprietary
0=32MB
1=64MB
2=128MB
3=256MB
4=512MB
5=1GB
6=2GB
7=Reserved
0=32MB
1=64MB
2=128MB
3=256MB
4=512MB
5=1GB
6=2GB
7=Reserved
0=32MB
1=64MB
2=128MB
3=256MB
4=512MB
5=1GB
6=2GB
7=Reserved
0=32MB
1=64MB
2=128MB
3=256MB
4=512MB
5=1GB
6=2GB
7=Reserved
Description
AMD RS690 ASIC Family Register Reference Manual
2-167
Graphics Controller Configuration Registers
SPARE_73
27:16
0x0
SPARE_73 [1:0] are used to select which read client will be
monitored to receive an average value of request latency in
MCLK. The select decode is as follows:
2'b00=gtx0r
2'bx1=g3d1r
2'b10=g3d0r
The programming sequence to turn on the latency monitor
is the same procedure as turning on the performance
counters for channelB: set
MC1_PERF_CNTL.EVENT0_SEL = 8'h7e and
MC1_PERF_CNTL.EVENT1_SEL = 8'h7f which choose the
two performance counters.
To get the average value, divide:
{MC1_PERF_CNTL.COUNTER0_UPPER,
MC1_PERF_COUNT0}
by
{MC1_PERF_CNTL.COUNTER1_UPPER,
MC1_PERF_COUNT1}.
RevF_Mode
AddrDecMode
28
30
0x0
0x1
MemWidth
31
0x0
AMD RS690 ASIC Family Register Reference Manual
2-168
SPARE_73[5:2] are used to XOR (g3d1r and g3d1w)
address[16:13].This is a one-to-one mapping where
SPARE_73[2] is XOR'd with address[13] and SPARE_73[3]
is XOR'd with SPARE_73[14], and so on. The address bit to
XOR will be determined by the address bits used to define
bank select in the K8 memory controller. The purpose of
XOR'ing the address bit is to improve the odds that
requests will go to different banks when multiple clients are
making requests in parallel.
0=RevC
1=RevD
0=64-bit interface
1=128-bit interface
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_MPLL_CONTROL - RW - 32 bits - NBMCIND:0x74
Field Name
MPLL_CAL_TRIGGER
Bits
0
Default
0x0
Description
Memory PLL calibration trigger. Set from 0 to 1 to start
calibration.
MPLL_LOCKED (R)
1
0x0
Memory PLL locking read back status.
0=No lock
1=PLL lock
MPLL_SKEW1X_CORE
4:2
0x0
This register field is not used.
MPLL_SKEW2
7:5
0x0
2X output clock (O2X) skew control
MPLL_SKEW1
10:8
0x0
1X output clock (O1X) skew control
MPLL_SKEW_DLY
14:11
0x0
This register field is not used.
MPLL_DLL_CLEN
15
0x0
This register bit is not used.
MPLL_DLL_PWDN
16
0x0
Core-clock tree cancellation DLL power-down
MPLL_SKEW_TREE
19:17
0x0
This register field is not used.
MPLL_VCOREF
23:20
0x0
VCO input reference voltage setting
MPLL_CALREF
27:24
0x0
2nd VCO input reference voltage setting
MPLL_BYPASS
28
0x0
Bypass mode enable for test clocks.
0=Normal operation
1=Bypass mode
0=Disable
1=Enable
MPLL_POWERDOWN_DLY
30:29
0x0
This register field is not used.
0=1 ms
1=2 ms
2=4 ms
3=8 ms
MPLL_POWERDOWN
31
0x0
Power-down Enable.
0=Normal operation
1=Power down
0=Run
1=Power Down
This register controls the Memory PLL. The divider fields will assume the default values based on power-on-strap options. To
change the frequency, this register can be written by the CPU.
MC_MPLL_CONTROL2 - RW - 32 bits - NBMCIND:0x75
MPLL_FBDIV
Field Name
Bits
8:0
MPLL_REFDIV
13:9
MPLL_POSTDIV
15:14
MPLL_CP
19:16
MPLL_VCO_MODE
21:20
RESERVED
23:22
MPLL_DLL_FRE_SEL
27:24
MPLL_LF_MODE
31:28
This register controls the memory PLL frequency.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
Comprises the 3-bit CMOS divider followed by the 6-bit
CMOS divider. Bits [2:0] control the 3-bit CMOS divider and
bits [8:3] control the 6-bit CMOS divider.
Reference clock input divider ratio from 1 to 32.
Divide by 1/2/3/4 post divider ratio.
Charge-pump current setting.
VCO mode setting
This register field is not used.
Loop filter mode setting.
AMD RS690 ASIC Family Register Reference Manual
2-169
Graphics Controller Configuration Registers
MC_MPLL_CONTROL3 - RW - 32 bits - NBMCIND:0x76
Field Name
MPLL_REF_DELAY
MPLL_VCO_DELAY
MPLL_CTL
Bits
1:0
3:2
8:4
Default
0x0
0x0
0x0
9
10
0x1
0x0
MPLL_BIAS
12:11
0x1
MPLL_SPARE
27:13
0x0
MPLL_MODE (R)
This register controls the memory PLL.
31:28
0x0
MPLL_IOBUFSEL
MPLL_REFCLK_SEL
Description
This register field is not used.
This register field is not used.
Misc. PLL programming bits. IPLL_CTL[4] enables
calibration override. When IPLL_CTL[4] = 0, the four
calibration bits are set by the calibration loop. When
IPLL_CTL[4]=1, the four bits are set through
IPLL_CTL[3:0].
This register bit is not used.
Reference clock input select. 0 chooses IREF_1X, 1
chooses ITCLK_1X
Bias current trim. IBIAS[1:0]. 00=-8%, 01=0%, 10=+12%,
11=+25%
Bit [4:0]=Spare pins reserved for PLL.
Bit [7:5]=Programmable current control for SCL for PLL.
000= -20%
001= -10%
010=0%
011=10%
100=20%
101=30%
110=40%
111=50%
Default=010
Bit [9:8]=Programmable current control for SCL for DLL.
00 = 0%
01=10%
10=20%
11=30%
Default=00
VCO operating mode status flags.
MC_MPLL_FREQ_CONTROL - RW - 32 bits - NBMCIND:0x77
Field Name
MPLL_PM_EN
MPLL_FREQ_SEL
Bits
0
1
Default
0x0
0x0
DISP_BLANK_CNTL
3:2
0x2
DISP_BLANK_VAL
MEM_SELF_REFRESH_ONLY
4
5
0x0
0x0
PM_SWITCHMCLK_BUSY (R)
6
0x0
7
11:8
13:12
15:14
19:16
23:20
0x0
0x0
0x0
0x0
0x0
0x0
PM_FREQ_CNTL_RESET
PM_MPLL_CP
PM_MPLL_VCO_MODE
RESERVED14
PM_MPLL_LF_MODE
PM_MPLL_DLL_FRE_SEL
AMD RS690 ASIC Family Register Reference Manual
2-170
Description
Dynamic MCLK switch enable
0=Use normal MPLL registers to set memory frequency.
1=Use PM MPLL registers to set memory frequency
0=No blanking during frequency switch.
1=Blank assertion only.
2=Blank assertion and deassertion.
3=register control blank.
Register control blank value.
0=Self refresh is followed by frequency switching.
1=Self refresh only.
0=MCLK is stable
1=MCLK switching is in progress
Reset dynamic MCLK state machine
PM mode Charge-pump current setting.
PM mode VCO mode setting
PM mode Loop filter mode setting.
This register field is not used.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
RESERVED24
MPLL_SLOWMCLK
27:24
28
0x0
0x0
PM_MPLL_SLOWMCLK
29
0x0
DLL_CORE_TEST_CLK
RESERVED31
Register Description.
30
31
0x0
0x0
0=MCLK is equal to or faster than CCLK in normal mode
1=MCLK is slower than CCLK in normal mode
0=MCLK is equal to or faster than CCLK in PM mode
1=MCLK is slower than CCLK in PM mode
Bring it out on channel B CKE 3
MC_MPLL_SEQ_CONTROL - RW - 32 bits - NBMCIND:0x78
Field Name
MPLL_RESET_PULSE_WIDTH
MDLL_RESET_PULSE_WIDTH
MPLL_CAL_S_TIME
Bits
3:0
7:4
11:8
Default
0x1
0x1
0x4
MPLL_CAL_H_TIME
15:12
0x5
MPLL_LOCK_TIME
MDLL_LOCK_TIME
Register Description.
23:16
31:24
0x50
0x50
Description
This register field is not used.
This register field is not used.
VCO calibration setup time = MPLL_CAL_S_TIME * 512 *
10 ns
VCO calibration hold time = MPLL_CAL_H_TIME * 4 * 10
ns
MPLL lock time = MPLL_LOCK_TIME * 256 * 10 ns
MDLL lock time = MDLL_LOCK_TIME * 256 * 10 ns
MC_MPLL_DIV_CONTROL - RW - 32 bits - NBMCIND:0x79
Field Name
PM_MPLL_FBDIV
PM_MPLL_REFDIV
PM_MPLL_POSTDIV
MPLL_DLL_CPP
Bits
8:0
13:9
15:14
17:16
Default
0x0
0x0
0x0
0x0
MPLL_DLL_CPN
19:18
0x0
20
0x1
31:21
0x0
MPLL_DLL_CPCAL_SEL
RESERVED
Register Description.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
PM mode feedback divider
PM mode reference divider
PM mode post divider
Control charge pump source current,
0=Off
1=On
Control charge pump sink current,
0=Off
1=On
Select calibration or manual setting for charge pump current
mirror.
0=Select manual setting
1=Select calibration setting
Bits [1:0]: Memory DLL reference clock skew control.
Bits [3:2]: Memory DLL feedback clock skew control.
Bit [4]:
1=Enable pre-clock tree PLL clock on MEMA ODT3 pad.
Bit [5]:
1=Enable post-clock tree PLL clock on MEMA ODT2 pad.
AMD RS690 ASIC Family Register Reference Manual
2-171
Graphics Controller Configuration Registers
MC_MCLK_CONTROL - RW - 32 bits - NBMCIND:0x7A
Field Name
CLKGATE_DIS_MCA
CLKGATE_DIS_MCB
CLKGATE_DIS_MCGR
CLKGATE_DIS_MCSQA
CLKGATE_DIS_MCIOA
MC_DELAY_TIMER_EXTEND
CLKGATE_DIS_LCLK_MC
MPLL_DELAY
SPARE0
DELAY_SET_MCLK
CLKGATE_DIS_MC
CLKGATE_DIS_MCIO
Register Description.
Bits
0
1
2
3
4
5
Default
0x1
0x1
0x1
0x1
0x1
0x0
6
13:8
23:16
28:24
0x1
0x1
0x0
0xf
29
30
0x1
0x1
Description
Disables clock gating for MCLK1X going to arbiterA and rbs
Disables clock gating for MCLK1X going to arbiterB and rbs
Disables clock gating for MCLK1X going to cic interface
Disables clock gating for MCLK1X going to sequencerA
Disables clock gating for MCLK1X going to ioA
Extend delay timer for MEMORY clocks
0=16 clocks
1=32 clocks
Disables clock gating for LCLK_MC going to mc.
Interval of updating MPLL feedback divider.
Reserved.
Extend delay timer for MCLK1X branches from 0 to 32
clocks.
MC_UMA_HDR_LAT_INIT - RW - 32 bits - NBMCIND:0x7B
Field Name
HDR_LAT_INIT_HDPW
Bits
15:0
Default
0x20
HDR_LAT_INIT_GFXW
31:16
0x20
Description
Number of clocks to block HDP reads behind HDP writes
before sending it down isochronous display pipe.
Number of clocks to block HDP reads behind GFX writes
before sending it down isochronous display pipe.
MC_UMA_GRP_CNTL - RW - 32 bits - NBMCIND:0x7C
Bits
2:0
Default
0x7
GRP_BP_RANGE
GRP_BP_ENABLE
GRP_DISABLE
19:4
20
21
0xfffc
0x1
0x0
GRP_GTW_EJECT
22
0x0
GRP_PRI_EJECT
23
0x0
GRP_URG_EJECT
24
0x0
GRP_BP_WM
Field Name
AMD RS690 ASIC Family Register Reference Manual
2-172
Description
There is a 16-entry CAM used for grouping requests, if the
number of occupied entries exceeds GRP_BP_WM*2, all
these entries will be marked as EJT and thus will be popped
whenever they reach the bottom of the CAM and the status
of the timer does not matter.
N/A
N/A
1=Grouping function is disabled.
0=Grouping function is enabled
GTW requests are not grouped since no new request will be
issued until response data is received. Since no grouping is
done, it will be marked as EJT as soon as the request is
entered into the CAM. GTW requests will go through
grouping CAM if we disable DSP_GTW mode
Priority lines from GTW or AGP are qualified with request
valid signals and since these requests are priority, they are
marked EJT and will not have to tolerate higher latency due
to timer (not timing out yet) and will be popped out as soon
as they fall to the bottom of the CAM.
All urgent lines are qualified with request valid signals and
since these requests are urgent, they are marked EJT and
will not have to tolerate higher latency due to timer (not
timing out yet) and will be popped out as soon as they fall to
the bottom of the CAM.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GRP_OPTS
31:25
0x0
xxxxxx1: If the new request finds a match with an entry not
pointed to by the CAM read pointer, and even though this
entry is marked as RDY, grouping will take place. xxxxx10:
If the new request finds a match with an entry not pointed to
by the CAM read pointer and even though this entry is
marked as RDY and EJT, grouping will take place. xxxx1xx:
With this bit set to 1'b1, the timer counts down every clock
on condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. With this
bit set to 1'b0 the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL. xx1xxxx: Mark all valid entries in CAM as
EJT if the number of valid entries equal or exceed a pre-set
watermark. x1xxxxx: Mark the entry as EJT if that entry is
valid and not ready and is not doing the same (read/write)
operation as the latest request.
MC_UMA_GRP_TMR - RW - 32 bits - NBMCIND:0x7D
Field Name
GRP_RREQ_TMR_INIT
Bits
7:0
Default
0x8
GRP_WREQ_TMR_INIT
15:8
0x8
GRP_TX_RREQ_TMR_INIT
23:16
0x8
SPARE0
31:24
0x0
Description
The maximum latency of a read request incurred by
grouping.
The maximum latency of a write request incurred by
grouping.
The maximum latency of texture read request incurred by
grouping.
Reserved.
MC_MISC_UMA_CNTL2 - RW - 32 bits - NBMCIND:0x7E
Field Name
DISP_SLICE_COUNT
Bits
3:0
Default
0x4
SPARE0
GFX_GTW_PRI
7:4
8
0x0
0x0
GFX_GTW_URG
9
0x0
GFX_FIXED_OVER_RRBIN
10
0x0
14:12
0x0
DSP_GTW_PRI
15
0x0
DSP_GTW_URG
16
0x0
GFX_FIXED_PRI_SCHEM
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
In this mode, high priority real-time requesters (display1,
display2, overlay) will win consecutively for N times before
switch to the next requester, where N is the register field.
The order is display1, followed by display2, and followed by
overlay.
Reserved
0=GFX GTW request will not be issued as priority
1=GFX GTW request will be issued to HT arbiter as
priority
0=GFX GTW request will not be issued as urgent
1=GFX GTW request will be issued to HT arbiter as
urgent
0=GFX Round-robbin arbitration scheme is chosen over
fixed priority arbitration
1=GFX Fixed priority arbitration scheme is chosen over
round-robbin arbitration
0=GFX GTW will have priority over GFX
1=Reserved
0=DSP GTW request will not be issued as priority
1=DSP GTW request will be issued to HT arbiter as
priority
0=DSP GTW request will not be issued as urgent
1=DSP GTW request will be issued to HT arbiter as
urgent
AMD RS690 ASIC Family Register Reference Manual
2-173
Graphics Controller Configuration Registers
DSP_FIXED_OVER_RRBIN
17
0x0
21:19
0x0
UMA_SYNC_MODE
22
0x1
LOCK_TO_2CYC
23
0x0
UMA_EFF23
24
0x0
31:25
0x0
DSP_FIXED_PRI_SCHEM
SPARE1
0=DSP Round-robbin arbitration scheme is chosen over
fixed priority arbitration
1=DSP Fixed priority arbitration scheme is chosen over
round-robbin arbitration
0=DSP GTW will have priority over GFX
1=Reserved
0=Asynchronous: MCLK ! = LCLK
1=Synchronous: MCLK = LCLK
0=MC_GFX and MC_DSP streams can issue request to
HTIU anytime
1=MC_GFX and MC_DSP streams' requests are locked
to every other LCLK
0=Original generation of EFF2 and EFF3 in UMA path
1=EFF2 and EFF3 are swapped in UMA path to allow
read/write interleave
Bit [0]:
0=Bypass CurStTup2 double flop.
1=Do not bypass.
Bit [1]:
0=Enable ECO for Rapid flush bug.
1=Disable ECO.
Bit [2]:
0=Enable use of MCGART flush strobe in gtw.
1=Disable.
Bit [3]:
0=Enable Flush ECO.
1=Disable Flush ECO.
Bit [4]:
0=Gate off PmArbDis going into gart state machine.
1=Do not gate off PmArbDis.
MC_UMA_WC_GRP_TMR - RW - 32 bits - NBMCIND:0x80
Field Name
GRP_G3D0W_TMR_INIT
Bits
7:0
Default
0x8
GRP_G3D1W_TMR_INIT
15:8
0x8
AMD RS690 ASIC Family Register Reference Manual
2-174
Description
The maximum latency of a G3D0W write request incurred
by grouping.
The maximum latency of a G3D1W write request incurred
by grouping.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_UMA_WC_GRP_CNTL - RW - 32 bits - NBMCIND:0x81
Field Name
GRP_G3D0W_BP_WM
Bits
2:0
Default
0x7
GRP_G3D0W_URG_EJECT
3
0x0
GRP_G3D0W_GRP_ENABLE
4
0x0
GRP_G3D0W_OPTS
14:8
0x0
GRP_G3D1W_BP_WM
18:16
0x7
20
0x0
GRP_G3D1W_URG_EJECT
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
An 8-entry CAM is used for grouping G3D0W write
requests. If the number of occupied entries exceeds
GRP_G3D0W_BP_WM*2, then all of these entries will be
marked as EJT (eject) and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
1'b1: G3D0W urgent requests will be marked as EJT
(eject), and will be ejected as soon as these marked entries
hit the bottom of CAM FIFO.
1'b0:G3D0W urgent requests will not be marked as
EJT(eject), and they are treated as normal requests.
1'b1: G3D0W write requests will be routed through the
grouper and will be grouped.
1'b0: G3D0W requests will bypass the grouper.
xxxxxx1: If the new G3D0W request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D0W request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
An 8-entry CAM is used for grouping G3D1W write
requests. If the number of occupied entries exceeds
GRP_G3D1W_BP_WM*2, then all these entries will be
marked as EJT (eject), and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
1'b1: G3D1W urgent requests will be marked as EJT
(eject), and will be ejected as soon as these marked entries
hit the bottom of CAM FIFO.
1'b0: G3D0W urgent requests will not be marked as
EJT(eject), and they are treated as normal requests
AMD RS690 ASIC Family Register Reference Manual
2-175
Graphics Controller Configuration Registers
GRP_G3D1W_OPTS
GRP_G3D1W_GRP_ENABLE
30:24
0x0
31
0x0
xxxxxx1: If the new G3D1W request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D1W request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
1'b1: G3D1W write requests will be routed through the
grouper and will be grouped.
1'b0: G3D1W requests will bypass the grouper.
MC_UMA_RW_GRP_TMR - RW - 32 bits - NBMCIND:0x82
Field Name
GRP_G3D0R_TMR_INIT
Bits
7:0
Default
0x8
GRP_G3D1R_TMR_INIT
15:8
0x8
GRP_GTX0R_TMR_INIT
23:16
0x8
GRP_E2R_TMR_INIT
31:24
0x8
Description
The maximum latency of a G3D0R read request incurred by
grouping.
The maximum latency of a G3D1R read request incurred by
grouping.
The maximum latency of a GTX0R read request incurred by
grouping.
The maximum latency of a E2R read request incurred by
grouping.
MC_UMA_RW_G3DR_GRP_CNTL - RW - 32 bits - NBMCIND:0x83
Field Name
GRP_G3D0R_BP_WM
GRP_G3D0R_URG_EJECT
GRP_G3D0R_GRP_ENABLE
Bits
2:0
Default
0x7
3
4
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-176
Description
An 8-entry CAM is used for grouping G3D0R write requests.
If the number of occupied entries exceeds
GRP_G3D0R_BP_WM*2, then all of these entries will be
marked as EJT (eject), and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
This bit is reserved.
1'b1: G3D0R write requests will be routed through the
grouper and will be grouped.
1'b0: G3D0R requests will bypass the grouper.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GRP_G3D0R_OPTS
14:8
0x0
GRP_G3D1R_BP_WM
18:16
0x7
GRP_G3D1R_URG_EJECT
GRP_G3D1R_OPTS
20
30:24
0x0
0x0
31
0x0
GRP_G3D1R_GRP_ENABLE
© 2007 Advanced Micro Devices, Inc.
Proprietary
xxxxxx1: If the new G3D0R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D0R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
An 8-entry CAM is used for grouping G3D1R write requests.
If the number of occupied entries exceeds
GRP_G3D1R_BP_WM*2, then all of these entries will be
marked as EJT (eject), and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
This bit is reserved.
xxxxxx1: If the new G3D1R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D1R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
1'b1: G3D1R write requests will be routed through the
grouper and will be grouped.
1'b0: G3D1R requests will bypass the grouper.
AMD RS690 ASIC Family Register Reference Manual
2-177
Graphics Controller Configuration Registers
MC_UMA_RW_TXR_E2R_GRP_CNTL - RW - 32 bits - NBMCIND:0x84
Field Name
GRP_GTX0R_BP_WM
Bits
2:0
Default
0x7
3
4
0x0
0x0
GRP_GTX0R_OPTS
14:8
0x0
GRP_E2R_BP_WM
18:16
0x7
20
0x0
GRP_GTX0R_URG_EJECT
GRP_GTX0R_GRP_ENABLE
GRP_E2R_URG_EJECT
AMD RS690 ASIC Family Register Reference Manual
2-178
Description
An 8-entry CAM is used for grouping GTX0R write requests.
If the number of occupied entries exceeds
GRP_GTX0R_BP_WM*2, then all of these entries will be
marked as EJT (eject) and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
This bit is reserved.
1'b1: GTX0R write requests will be routed through the
grouper and will be grouped.
1'b0: GTX0R requests will bypass the grouper.
xxxxxx1: If the new GTX0R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new GTX0R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY and EJT (eject),
grouping will take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
An 8-entry CAM is used for grouping E2R write requests. If
the number of occupied entries exceeds
GRP_E2R_BP_WM*2, then all of these entries will be
marked as EJT (eject) and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
1'b1: E2R urgent and priority requests will be marked as
EJT (eject) and will be ejected as soon as these marked
entries hit the bottom of CAM FIFO.
1'b0: E2R urgent and priority requests will not be marked as
EJT(eject) and they are treated as normal requests
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
GRP_E2R_OPTS
GRP_E2R_GRP_ENABLE
30:24
0x0
31
0x0
xxxxxx1: If the new E2R request finds a match with an entry
not pointed to by the CAM read pointer, and even though
this entry is marked as RDY, grouping will take place.
xxxxx10: If the new E2R request finds a match with an entry
not pointed to by the CAM read pointer, and even though
this entry is marked as RDY and EJT (eject), grouping will
take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
1'b1: E2R write requests will be routed through the grouper
and will be grouped.
1'b0: E2R requests will bypass the grouper.
MC_UMA_AGP_GRP_CNTL - RW - 32 bits - NBMCIND:0x85
Field Name
GRP_AGP_BP_WM
Bits
2:0
Default
0x7
GRP_AGP_URG_EJECT
3
0x0
GRP_AGP_GRP_ENABLE
4
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
An 8-entry CAM is used for grouping AGP write requests. If
the number of occupied entries exceeds
GRP_AGP_BP_WM*2, then all of these entries will be
marked as EJT (eject) and will therefore be ejected
whenever they reach the bottom of the CAM, and the status
of the timer does not matter.
1'b1: AGP urgent and priority requests will be marked as
EJT (eject) and will be ejected as soon as these marked
entries hit the bottom of CAM FIFO.
1'b0: AGP urgent and priority requests will not be marked
as EJT(eject) and they are treated as normal requests
1'b1: AGP write requests will be routed through the grouper
and will be grouped.
1'b0: AGP requests will bypass the grouper.
AMD RS690 ASIC Family Register Reference Manual
2-179
Graphics Controller Configuration Registers
GRP_AGP_OPTS
14:8
0x0
GRP_AGP_TMR_INIT
23:16
0x8
xxxxxx1: If the new AGP request finds a match with an entry
not pointed to by the CAM read pointer, and even though
this entry is marked as RDY, grouping will take place.
xxxxx10: If the new AGP request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY and EJT (eject),
grouping will take place.
xxxx1xx: If 1'b1, then the timer counts down every clock on
the condition that the next pipe stage is ready and the
grouping FIFO does not have request to forward. If 1'b0,
then the latency counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT (eject) if the
number of valid entries equal or exceed a pre-set
watermark.
x1xxxxx: Mark the entry as EJT (eject) if that entry is valid,
not ready, and is not doing the same (read/write) operation
as the latest request.
The maximum latency of a AGP read request incurred by
grouping.
MC_UMA_DUALCH_CNTL - RW - 32 bits - NBMCIND:0x86
Field Name
DUAL_CHANNEL_EN
Bits
0
Default
0x0
IO_ORDER_TAG_EN
1
0x0
IO_ORDER_WCH_WACK_EN
2
0x0
IO_ORDER_RWCH_WACK_EN
3
0x0
R1C_W2X_EN
4
0x0
AMD RS690 ASIC Family Register Reference Manual
2-180
Description
1'b1: Enables write-channel path. All G3D0W and G3D1W
requests will be forwarded to this path, and all other client
requests will be forwarded to the default UMA path.
1'b0: All requests will be forwarded to the default UMA path.
1'b1: Requests from both the write-channel path and the
UMA path will be tagged before being forwarded to the
HTIU interface. These request order tags provide the IO
order for the HTIU arbiter.
1'b0: No tagging will be done, and the request order tags
will be ignored by the HTIU arbiter.
1'b1: HTIU will return the WACK signals after arbitrating
IDCTW or HDPW requests to MC. MC keeps track of how
many HDPW or IDCTW are not committed yet.
1'b0: HTIU does not return the WACK signal to the
dedicated write port.
1'b1: HTIU returns WACK signal (for each write-channel
path request committed to the link) to MC. If 1'b0, then MC
ignores the WACK signal.
1'b0: HTIU does not return the WACK signal to the (RW)
graphics port.
1'b1: Read requests will be forwarded every clock cycle at
the MC/HTIU interface, and a 32 byte write request will be
forwarded every clock.
1'b0: Revert back to 2 clocks for each read and write
request.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
ASYNC_FIFO_BYPASS
5
0x0
1'b1: All new mode switching bits will be loaded and take
effect immediately.
1'b0: All new mode switching bits will be loaded upon
seeing internal mc_idle signal.
The new mode switches are as follows:
DUAL_CHANNEL_EN, IO_ORDER_TAG_EN,
IO_ORDER_WCH_WACK_EN,
IO_ORDER_RWCH_WACK_EN, R1C_W2X_EN, and all
client interface GRP_ENABLEs.
NB_MEM_CH_CNTL2 - RW - 32 bits - NBMCIND:0x1B
Field Name
K8_INTERLEAVE_SIZE
Bits
7:0
Default
0x0
Memory Control channel register2
Description
This field is to specify the interleave size of FB on the UMA
side. The unit is 1Mbyte.
NB_MEM_CH_CNTL0 - RW - 32 bits - NBMCIND:0x1C
Field Name
INTERLEAVE_MODE
Bits
1:0
Default
0x0
PRIMARY_CHANNEL
2
0x1
NUMBER_CHANNEL
3
0x0
BANK_2_MAP
7:4
0x6
BANK_0_MAP
15:12
0x4
BANK_1_MAP
19:16
0x5
INTERLEAVE_START
31:20
0x0
Description
This field defines the interleave mode between memory
channels. In 'Coarse interleaved' mode the primary
channel, which is SP, occupies the lower part of system
memory address space. In 'Interleaved' mode memory
access alternates between both channels (every 128 bytes
or 256 bytes).
0=Single Channel
1=Fine Interleaved
2=Reserved
3=Coarse Interleaved
The primary channel will be SP always under dual-channel
configuration. The only case that UMA would be the primary
channel is under the UMA-only configuration. The memory
controller uses that information to properly interleave
accesses between channels.
0=Channel A
1=Channel B
This specifies single/dual memory channel mode
0=One channel
1=Two channels
Memory bank bit 2 mapping, address bits 7 to 20 can be
used, for values being 0 to 13. The default value is 6
meaning address bit 13 is used as bank[0]
Memory bank bit 0 mapping, address bits 7 to 20 can be
used, for values being 0 to 13. The default value is 4
meaning address bit 11 is used as bank[0]
Memory bank bit 1 mapping, address bits 7 to 20 can be
used, for values being 0 to 13. The default value is 5
meaning address bit 12 is used as bank[1]
The address space below Interleave-Start will be mapped
to the Primary-Channel and will be treated as if operating in
single channel mode.
Memory Control channel register0
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-181
Graphics Controller Configuration Registers
NB_MEM_CH_CNTL1 - RW - 32 bits - NBMCIND:0x1D
Field Name
INTERLEAVE_END
Bits
11:0
Default
0x0
INTERLEAVE_RATIO
19:12
0xaa
28
0x0
INTERLEAVE_PAGE_SIZE
Memory Control channel register1
Description
The address space above Interleave-End will be mapped to
the Secondary-Channel, which is UMA, and will be treated
as if operating in single channel mode.
This 8-bit register defines the ratio of arbitration between
SP and UMA. 0 means that SP will win the arbitration and 1
means that UMA will win the arbitration. For example, the
value 11100000 will have SP being selected for 5
consecutive times and UMA being selected for the rest of
the three times.
Every 128 bytes or 256 bytes, the channel select logic will
be activated and re-map the FB requests between two
channels. It will only take effect under the dual-channel
configuration.
0=128 bytes
1=256 bytes
MC_MISC_CNTL3 - RW - 32 bits - NBMCIND:0x4F
Field Name
Bits
GFXR_LAT
7:0
GTXR_LAT
15:8
GFXW_LAT
23:16
GFXR_NOWAIT_MODE
24
GTXR_NOWAIT_MODE
25
GFXW_NOWAIT_MODE
26
Miscellaneous controls(3) for memory controller
Default
0x2
0x2
0x2
0x0
0x0
0x0
Description
Valid range is 0x1 to 0x7E
Valid range is 0x1 to 0x7E
Valid range is 0x1 to 0x7E
MC_UMA_WC_GRP_TMR - RW - 32 bits - NBMCIND:0x80
Field Name
GRP_G3D0W_TMR_INIT
Bits
7:0
Default
0x8
GRP_G3D1W_TMR_INIT
15:8
0x8
AMD RS690 ASIC Family Register Reference Manual
2-182
Description
The maximum latency of a G3D0W write request incurred
by grouping
The maximum latency of a G3D1W write request incurred
by grouping
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_UMA_WC_GRP_CNTL - RW - 32 bits - NBMCIND:0x81
Field Name
GRP_G3D0W_BP_WM
Bits
2:0
Default
0x7
GRP_G3D0W_URG_EJECT
3
0x0
GRP_G3D0W_GRP_ENABLE
4
0x0
GRP_G3D0W_OPTS
14:8
0x0
GRP_G3D1W_BP_WM
18:16
0x7
20
0x0
GRP_G3D1W_URG_EJECT
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
A 8-entry CAM is used for grouping G3D0W write requests,
if the number of occupied entries exceeds
GRP_G3D0W_BP_WM*2, all these entries will be marked
as EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
1'b1: G3D0W urgent requests will be marked as EJT (eject)
and will be ejected as soon as these marked entries hit the
bottom of CAM FIFO.
1'b0:G3D0W urgent requests will not be marked as
EJT(eject) and they are treated as normal requests
1'b1: G3D0W write requests will be routed through the
grouper and will be grouped.
1'b0: G3D0W requests will bypass the grouper.
xxxxxx1: If the new G3D0W request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D0W request finds a match with an
entry not pointed to by the CAM read pointer and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
A 8-entry CAM is used for grouping G3D1W write requests,
if the number of occupied entries exceeds
GRP_G3D1W_BP_WM*2, all these entries will be marked
as EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
1'b1: G3D1W urgent requests will be marked as EJT (eject)
and will be ejected as soon as these marked entries hit the
bottom of CAM FIFO.
1'b0: G3D0W urgent requests will not be marked as
EJT(eject) and they are treated as normal requests.
AMD RS690 ASIC Family Register Reference Manual
2-183
Graphics Controller Configuration Registers
GRP_G3D1W_OPTS
GRP_G3D1W_GRP_ENABLE
30:24
0x0
31
0x0
xxxxxx1: If the new G3D1W request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D1W request finds a match with an
entry not pointed to by the CAM read pointer and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
1'b1: G3D1W write requests will be routed through the
grouper and will be grouped.
1'b0: G3D1W requests will bypass the grouper.
MC_UMA_RW_GRP_TMR - RW - 32 bits - NBMCIND:0x82
Field Name
GRP_G3D0R_TMR_INIT
Bits
7:0
Default
0x8
GRP_G3D1R_TMR_INIT
15:8
0x8
GRP_GTX0R_TMR_INIT
23:16
0x8
GRP_E2R_TMR_INIT
31:24
0x8
AMD RS690 ASIC Family Register Reference Manual
2-184
Description
The maximum latency of a G3D0R read request incurred by
grouping
The maximum latency of a G3D1R read request incurred by
grouping
The maximum latency of a GTX0R read request incurred by
grouping
The maximum latency of a E2R read request incurred by
grouping
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_UMA_RW_G3DR_GRP_CNTL - RW - 32 bits - NBMCIND:0x83
Field Name
GRP_G3D0R_BP_WM
Bits
2:0
Default
0x7
3
4
0x0
0x0
GRP_G3D0R_OPTS
14:8
0x0
GRP_G3D1R_BP_WM
18:16
0x7
20
0x0
GRP_G3D0R_URG_EJECT
GRP_G3D0R_GRP_ENABLE
GRP_G3D1R_URG_EJECT
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
A 8-entry CAM is used for grouping G3D0R write requests,
if the number of occupied entries exceeds
GRP_G3D0R_BP_WM*2, all these entries will be marked
as EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
Reserved
1'b1: G3D0R write requests will be routed through the
grouper and will be grouped.
1'b0: G3D0R requests will bypass the grouper.
xxxxxx1: If the new G3D0R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D0R request finds a match with an
entry not pointed to by the CAM read pointer and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
A 8-entry CAM is used for grouping G3D1R write requests,
if the number of occupied entries exceeds
GRP_G3D1R_BP_WM*2, all these entries will be marked
as EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
Reserved
AMD RS690 ASIC Family Register Reference Manual
2-185
Graphics Controller Configuration Registers
GRP_G3D1R_OPTS
GRP_G3D1R_GRP_ENABLE
30:24
0x0
31
0x0
AMD RS690 ASIC Family Register Reference Manual
2-186
xxxxxx1: If the new G3D1R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new G3D1R request finds a match with an
entry not pointed to by the CAM read pointer and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
1'b1: G3D1R write requests will be routed through the
grouper and will be grouped.
1'b0: G3D1R requests will bypass the grouper.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_UMA_RW_TXR_E2R_GRP_CNTL - RW - 32 bits - NBMCIND:0x84
Field Name
GRP_GTX0R_BP_WM
Bits
2:0
Default
0x7
3
4
0x0
0x0
GRP_GTX0R_OPTS
14:8
0x0
GRP_E2R_BP_WM
18:16
0x7
20
0x0
GRP_GTX0R_URG_EJECT
GRP_GTX0R_GRP_ENABLE
GRP_E2R_URG_EJECT
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
A 8-entry CAM is used for grouping GTX0R write requests,
if the number of occupied entries exceeds
GRP_GTX0R_BP_WM*2, all these entries will be marked
as EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
Reserved
1'b1: GTX0R write requests will be routed through the
grouper and will be grouped.
1'b0: GTX0R requests will bypass the grouper.
xxxxxx1: If the new GTX0R request finds a match with an
entry not pointed to by the CAM read pointer, and even
though this entry is marked as RDY, grouping will take
place.
xxxxx10: If the new GTX0R request finds a match with an
entry not pointed to by the CAM read pointer and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
A 8-entry CAM is used for grouping E2R write requests, if
the number of occupied entries exceeds
GRP_E2R_BP_WM*2, all these entries will be marked as
EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
1'b1: E2R urgent and priority requests will be marked as
EJT (eject) and will be ejected as soon as these marked
entries hit the bottom of CAM FIFO.
1'b0: E2R urgent and priority requests will not be marked as
EJT(eject) and they are treated as normal requests
AMD RS690 ASIC Family Register Reference Manual
2-187
Graphics Controller Configuration Registers
GRP_E2R_OPTS
GRP_E2R_GRP_ENABLE
30:24
0x0
31
0x0
AMD RS690 ASIC Family Register Reference Manual
2-188
xxxxxx1: If the new E2R request finds a match with an entry
not pointed to by the CAM read pointer, and even though
this entry is marked as RDY, grouping will take place.
xxxxx10: If the new E2R request finds a match with an entry
not pointed to by the CAM read pointer and even though
this entry is marked as RDY and EJT, grouping will take
place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
1'b1: E2R write requests will be routed through the grouper
and will be grouped.
1'b0: E2R requests will bypass the grouper.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_UMA_AGP_GRP_CNTL - RW - 32 bits - NBMCIND:0x85
Field Name
GRP_AGP_BP_WM
Bits
2:0
Default
0x7
GRP_AGP_URG_EJECT
3
0x0
GRP_AGP_GRP_ENABLE
4
0x0
GRP_AGP_OPTS
14:8
0x0
GRP_AGP_TMR_INIT
23:16
0x8
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
A 8-entry CAM is used for grouping AGP write requests, if
the number of occupied entries exceeds
GRP_AGP_BP_WM*2, all these entries will be marked as
EJT and thus will be ejected whenever they reach the
bottom of the CAM and the status of the timer does not
matter.
1'b1: AGP urgent and priority requests will be marked as
EJT (eject) and will be ejected as soon as these marked
entries hit the bottom of CAM FIFO.
1'b0: AGP urgent and priority requests will not be marked
as EJT(eject) and they are treated as normal requests
1'b1: AGP write requests will be routed through the grouper
and will be grouped.
1'b0: AGP requests will bypass the grouper.
xxxxxx1: If the new AGP request finds a match with an entry
not pointed to by the CAM read pointer, and even though
this entry is marked as RDY, grouping will take place.
xxxxx10: If the new AGP request finds a match with an
entry not pointed to by the CAM read pointer and even
though this entry is marked as RDY and EJT, grouping will
take place.
xxxx1xx: If 1'b1, the timer counts down every clock on
condition that the next pipe stage is ready and the grouping
FIFO does not have request to forward. If 1'b0 the latency
counter counts down every clock.
xxx1xxx: All entries in the CAM will be ejected if the CAM
becomes FULL.
xx1xxxx: Mark all valid entries in CAM as EJT if the number
of valid entries equal or exceed a pre-set watermark.
x1xxxxx: Mark the entry as EJT if that entry is valid and not
ready and is not doing the same (read/write) operation as
the latest request.
The maximum latency of a AGP read request incurred by
grouping.
AMD RS690 ASIC Family Register Reference Manual
2-189
Graphics Controller Configuration Registers
MC_UMA_DUALCH_CNTL - RW - 32 bits - NBMCIND:0x86
Field Name
DUAL_CHANNEL_EN
Bits
0
Default
0x0
IO_ORDER_TAG_EN
1
0x0
IO_ORDER_WCH_WACK_EN
2
0x0
IO_ORDER_RWCH_WACK_EN
3
0x0
R1C_W2X_EN
4
0x0
ASYNC_FIFO_BYPASS
5
0x0
AMD RS690 ASIC Family Register Reference Manual
2-190
Description
1'b1: enable write-channel path, all G3D0W and G3D1W
requests will be forwarded to this path, and all other clients'
requests will be forwarded to the default UMA path.
1'b0: all requests will be forwarded to the default UMA path.
1'b1: requests from both write-channel path and UMA path
will be tagged before being forwarded to HTIU interface,
these requests order tags provide the IO order for HTIU
arbiter.
1'b0: no tagging will be done and the request order tags will
be ignored by HTIU arbiter.
1'b1: HTIU will return WACK signals after arbitrating IDCTW
or HDPW requests to MC. MC keeps track of how many
HDPW or IDCTW are not committed yet.
1'b0: HTIU does not return WACK signal to dedicated write
port
1'b1: HTIU returns WACK signal (for each write-channel
path request committed to the link) to MC. If 1'b0, MC
ignores the WACK signal.
1'b0: HTIU does not return WACK signal to (RW) graphics
port
1'b1: read requests will be forwarded every clock cycle at
the MC/HTIU interface, and a 32 bytes write request will be
forwarded every clock.
1'b0: revert back to 2 clocks for each read and write
request.
Original intent was to use this bit to bypass some async
FIFO.But it's now used differently.
1'b1: all new mode switching bits will be loaded and take
effect immediately.
1'b0: all new mode switching bits will be loaded upon seeing
internal mc_idle signal.
The new mode switches are: DUAL_CHANNEL_EN,
IO_ORDER_TAG_EN, IO_ORDER_WCH_WACK_EN,
IO_ORDER_RWCH_WACK_EN, R1C_W2X_EN and all
client interface GRP_ENABLE/s
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_SYSTEM_STATUS - RW - 32 bits - NBMCIND:0x90
Field Name
MC_SYSTEM_IDLE (R)
Bits
0
Default
0x0
MC_SEQUENCER_IDLE (R)
1
0x0
MC_ARBITER_IDLE (R)
2
0x0
3
7:4
11:8
15:12
16
0x0
0x0
0x0
0x0
0x0
MCA_IDLE (R)
17
0x0
MCA_SEQ_IDLE (R)
18
0x0
MCA_ARB_IDLE (R)
19
0x0
31:20
0x0
MC_SELECT_PM (R)
RESERVED4 (R)
RESERVED8 (R)
RESERVED12 (R)
MCA_INIT_EXECUTED (R)
RESERVED20 (R)
Memory controller system status
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Indicates that there are no pending or in-process memory
requests.
This includes all pending or in-process requests to system
memory.
0=Not Idle
1=Idle
Indicates that there are no pending or in-process frame
buffer requests.
Does not include status on pending or in-process requests
to system memory.
0=Not Idle
1=Idle
Indicates that there are no pending or in-process frame
buffer requests. Does not include status on pending or
in-process requests to system memory.
0=Not Idle
1=Idle
Memory power management selection read back
Channel A SDRAM Init in Process:
Indicates that the last MCA_INIT_EXECUTE operation has
completed for the A channel. Do not initiate a new
MCA_INIT_EXECUTE operation until 'Ready' is indicated.
0=SDRAM Init in Process
1=Ready
Channel A memory controller idle.
0=Not idle
1=Idle
Channel A memory controller sequencer idle.
0=Not Idle
1=Idle
Channel A memory controller arbiter idle.
0=Not Idle
1=Idle
AMD RS690 ASIC Family Register Reference Manual
2-191
Graphics Controller Configuration Registers
MC_INTFC_GENERAL_PURPOSE - RW - 32 bits - NBMCIND:0x91
Field Name
MC_STARTUP
Bits
0
Default
0x0
MC_RESTART
1
0x0
MC_POWERED_UP
2
0x0
MC_POWERED_UP2
3
0x0
MC_PWRDN_MODE
5:4
0x0
MC_POWER_DOWN
6
0x0
MC_GFX_PWRDN_ENABLE
MC_SUSPEND_DISABLE
7
8
0x0
0x0
MC_SUSPEND_TRISTATE
9
0x1
MC_SUSPEND_CLEAN_MC
10
0x0
MC_SUSPEND_DYNAMIC
11
0x0
MC_SUSPEND_DELAY
15:12
0x8
RESERVED16
MC_TCLKS
19:16
23:20
0x0
0x1
MC_TDLLR
MC_TDLLL
Memory controller general purpose register
27:24
31:28
0x8
0x8
AMD RS690 ASIC Family Register Reference Manual
2-192
Description
Setting this bit forces the MC's SDRAM mode state
machine from the initial power-on state into the 'operating'
state. This bit needs to be set after initial power up, before
the system memory can be accessed.
Setting this bit forces the MC's SDRAM mode state
machine from the initial power-on state into the 'parked'
state. This bit needs to be set after initial power up if the
SDRAM is in self-refresh mode after a 'suspend-to-RAM'
operation. After the mode state machine has reached the
'parked' state, the memory will be taken out of 'self-refresh'
as soon as the hardware signal DC_STOP has been
deasserted and the state machine will transition into the
'operating' state.
All clocks ready. This bit must be set on power up after
initializing all clocks in order to proceed with MC
initialization. When 0, force CKE low, and tristate all other
signals.
All clocks ready. This bit must be set after power up, on self
refresh exit, after initializing all clocks in order to proceed
with MC initialization. When 0, force CKE low, and tristate
all other signals.
Selects the source for the power down event
0=DC_STOP/SUSTAT
1=CPU Special Cycle (AMD)
2=Both
3=None
Setting this bit forces the MC's SDRAM mode state
machine from the 'operating' state into the 'parked' state.
The parking sequence takes a certain time and the
processor needs to monitor the state machine to make sure
that the 'parked' state has been reached before the power
to the NB core is removed.
Enables power down for external graphics
This bit disables suspend
0=Suspend enabled
1=Suspend disabled
This bit enables tristate in suspend
0=Do not tristate in suspend
1=Tristate in suspend
When going to suspend, clean MC, no stuck requests in
MC.
Dynamic self refresh when cpu in s3 and display in shutter
mode.
Delay to enter self refresh when cpu in s3 and display in
shutter mode, x4 clocks.
Memory clock settling time - memory spec - register x16
clocks.
DLL reset pulse - 1us - register x64 clocks.
DLL lock time - 500 clock - register x64 clocks.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_INTFC_IMP_CTRL_CNTL - RW - 32 bits - NBMCIND:0x92
Field Name
MC_IC_UPDATE_RATE
Bits
4:0
Default
0x18
RESERVED5
MC_IC_SAMPLE_RATE
7:5
12:8
0x0
0x10
RESERVED13
MC_IC_SAMPLE_SETTLE
15:13
19:16
0x0
0x8
MC_IC_INC_THRESHOLD
23:20
0x8
MC_IC_DEC_THRESHOLD
27:24
0x8
MC_IC_OSC
28
0x0
MC_IC_SUSPEND
29
0x0
RESERVED30
MC_IC_ENABLE
30
31
0x0
0x0
Memory controller impedance controller setting
Description
Update rate MCLK*2**n
0x0=Minimum
0x1F=Maximum
Sample rate MCLK*2**n
0x0=Minimum
0x1F=Maximum
Sample settle MCLK*2**n
0x0=Minimum
0xF=Maximum
Number of over samples to increase strength
0x0=0
0xF=15
Number of under samples to decrease strength
0x0=0
0xF=15
Impedance controller oscillation mode
0=Stay at higher strength when oscillate
1=Oscillate when oscillate
Impedance controller on/off in self refresh
0=Impedance controller on in self refresh
1=Impedance controller off in self refresh
Impedance controller enable
0=Off
1=On
MC_INTFC_IMP_CTRL_REF - RW - 32 bits - NBMCIND:0x93
Field Name
MC_STRENGTH_N_REF
Bits
3:0
Default
0xb
MC_STRENGTH_P_REF
7:4
0xb
MC_STR_READ_BACK_N_REF (R)
11:8
0x0
MC_STR_READ_BACK_P_REF (R)
15:12
0x0
MC_IC_N_LOCKED (R)
16
0x0
MC_IC_P_LOCKED (R)
17
0x0
MC_IC_N_OSCILLATION (R)
18
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Reference N strength
0x0=Weakest
0xF=Strongest
Reference P strength
0x0=Weakest
0xF=Strongest
Reference N strength read back
0x0=Weakest
0xF=Strongest
Reference P strength read back
0x0=Weakest
0xF=Strongest
Impedance controller N strength locked read back
0x0=Not locked
0x1=Locked
Impedance controller P strength locked read back
0x0=Not locked
0x1=Locked
Impedance controller N strength oscillation read back
0x0=No oscillation
0x1=Oscillation
AMD RS690 ASIC Family Register Reference Manual
2-193
Graphics Controller Configuration Registers
MC_IC_P_OSCILLATION (R)
19
0x0
Impedance controller P strength oscillation read back
0x0=No oscillation
0x1=Oscillation
RESERVED20
31:20
0x0
Memory controller impedance controller reference strength and read back
MC_LATENCY_COUNT_CNTL - RW - 32 bits - NBMCIND:0x94
CLIENT_SEL
Field Name
Bits
3:0
Default
0x0
Description
Select which clients to measure latency.
4'b0000:g3d0r
4'b0001:g3d1r
4'b0010:tx0r
4'b0011:cpr
4'b0100:vfr
4'b0101:idctr
4'b0110:hdpr
4'b0111:e2r
4'b1000:mcifr
4'b1001:dmifr
4'b1010:avpr
4'b1011:ptr
4'b1100:azr
4'b1101:g3d0w
4'b1110:g3d1w
RD_CLI_EOB_DIS
17:4
0x0
WR_CLI_EOB_DIS
27:18
0x0
ALL_CLI_EOB_DIS
28
0x0
RESERVED
31:29
0x0
Controls for latency counter (average latency is measured from sclk performance counter events 0x84 and 0x85
MC_LATENCY_COUNT_EVENT - R - 32 bits - NBMCIND:0x95
Field Name
MIN_LATENCY
Bits
15:0
Default
0x0
MAX_LATENCY
31:16
0x0
Min/Max latency readback from latency counter
Description
Minimum latency during the period of enabling sclk
performance counter events 0x84 and 0x85
Maximum latency during the period of enabling sclk
performance counter events 0x84 and 0x85
MCS_PERF_COUNT0 - R - 32 bits - NBMCIND:0x96
Field Name
Bits
Default
MCS_COUNTER0
31:0
0x0
Memory controller performance counter for Event0 in SCLK
Description
Lower 32 bits of Event0 counter
MCS_PERF_COUNT1 - R - 32 bits - NBMCIND:0x97
Field Name
Bits
Default
MCS_COUNTER1
31:0
0x0
Memory controller performance counter for Event1 in SCLK
AMD RS690 ASIC Family Register Reference Manual
2-194
Description
Lower 32 bits of Event1 counter
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCS_PERF_CNTL - RW - 32 bits - NBMCIND:0x98
Field Name
Bits
Default
MCS_EVENT0_SEL
7:0
0x0
MCS_EVENT1_SEL
15:8
0x0
MCS_COUNTER0_UPPER (R)
23:16
0x0
MCS_COUNTER1_UPPER (R)
31:24
0x0
Memory controller performance counter control for SCLK
Description
Event0 selection: TBD
Event1 selection: Same definition as above
Upper 8 bits of Event0 counter
Upper 8 bits of Event1 counter
MC_AZ_DEFAULT_ADDR - RW - 32 bits - NBMCIND:0x99
Field Name
AZ_DEFAULT_ADDR
Bits
31:0
Default
0x0
Default read/write address for Azalia
Description
Azalia reads or writes that don't match the chipset apertures
will be sent to this address. It represents [39:8] of the
default address and [7:0] are taken to be 0.
MCA_MEMORY_INIT_MRS - RW - 32 bits - NBMCIND:0xA0
Field Name
MCA_MODE_REG
Bits
19:0
Default
0x0
Description
Value to be loaded into the memory mode or the extended
mode register.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
MCA_INIT_CS_MRS
23:20
0xf
MCA_INIT_SEQ
28:24
0x0
MCA_INIT_IDLE
29
0x0
MCA_INIT_COMPLETE
30
0x0
MCA_INIT_EXECUTE
31
0x0
Channel A CS to be initialized
4'b0001=CS0/
4'b0010= CS1/
4'b0100=CS2/
4'b1000=CS3/
Initialization sequence selection for execution
0=Whole initialization sequence selected for execution
1-31=Initialization sequence selected for execution
Forces MC channel A idle before initialization execution.
0=MC not forced idle before initialization execution
1=MC forced idle before initialization execution
As long as this bit is '0', the MCA will not accept requests
from the clients. It is used primarily to block requests when
the MCA might mishandle them, such as when the FB or
AGP apertures are undefined or unstable.
0=Register Initialization Not Complete
1=Register Initialization Complete
The MC will execute software initialization command or
whole hardware initialization sequence on a transition from
0 to 1 for memory controller MCA
0=Normal
1=Execute initialization command
Memory controller A initialization
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-195
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_EMRS - RW - 32 bits - NBMCIND:0xA1
Field Name
MCA_EXT_MODE_REG
Bits
19:0
Default
0x10000
MCA_INIT_CS_EMRS
23:20
0xf
MCA_INIT_DLL
24
0x1
MCA_INIT_OCD
25
0x0
MCA_INIT_ZQC
26
0x0
MCA_INIT_MPR
MCA_INIT_DQSS
27
28
0x0
0x0
MCA_INIT_OCDX
29
0x0
31:30
0x0
RESERVED30
Memory controller A initialization extension
Description
Value to be loaded in memory extended mode register in
nominal mode with initialization sequence. Does not matter
for step by step execution.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
Channel A CS to be initialized
4'b0001=CS0/
4'b0010= CS1/
4'b0100=CS2/
4'b1000=CS3/
Enables the execution of the memory DLL reset mode
register command for the nominal mode initialization
sequence.
Drive 0/1 for OCD drive extended mode register command
for nominal mode initialization sequence.
Initializes ZQC one by one CS (nominal) or all CS together.
0=Increment CS counter for each ZQC command
executed in the same initialization sequence
1=SEND ZQC command to all CS
Enables MPR read.
Strobe sample by internal clock enable
0=Strobe sample by internal clock disabled
1=Strobe sample by internal clock enabled
DDR3 optional OCD execution from EMRS2 A[11:9] instead
of DDR2 OCD execution from MRS A[9:8].
0=DDR2 OCD
1=DDR3 OCD
MCA_MEMORY_INIT_EMRS2 - RW - 32 bits - NBMCIND:0xA2
Field Name
MCA_EXT2_MODE_REG
Bits
19:0
Default
0x20000
MCA_INIT_CS_EMRS2
23:20
0xf
AMD RS690 ASIC Family Register Reference Manual
2-196
Description
Value to be loaded in memory second extended mode
register in nominal mode with initialization sequence. Does
not matter for step by step execution.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
Channel A CS to be initialized
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_TWLODTEN
27:24
0x4
MCA_TWLDQSEN
31:28
0x7
DDR3 ODT write levelization, tDQSS margining, x4 clocks
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
DDR3 ODT write levelization, tDQSS margining, x4 clocks
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Memory controller A initialization extension
MCA_MEMORY_INIT_EMRS3 - RW - 32 bits - NBMCIND:0xA3
Field Name
MCA_EXT3_MODE_REG
Bits
19:0
Default
0x30000
MCA_INIT_CS_EMRS3
23:20
0xf
MCA_TWLMRD
27:24
0xa
MCA_TDLL
Memory controller A initialization extension
31:28
0x4
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Value to be loaded in memory third extended mode register
in nominal mode with initialization sequence. Does not
matter for step by step execution.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
Channel A CS to be initialized
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
DDR3 ODT write levelization, tDQSS margining, x4 clocks
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Channel A DLL reset time, x64 clocks
AMD RS690 ASIC Family Register Reference Manual
2-197
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_SEQUENCE_1 - RW - 32 bits - NBMCIND:0xA4
Field Name
MCA_INIT_SEQ_OP_1
Bits
3:0
Default
0x1
MCA_INIT_SEQ_OP_2
7:4
0x5
MCA_INIT_SEQ_OP_3
11:8
0x8
MCA_INIT_SEQ_OP_4
15:12
0x4
MCA_INIT_SEQ_OP_5
19:16
0x2
MCA_INIT_SEQ_OP_6
23:20
0x2
MCA_INIT_SEQ_OP_7
27:24
0x2
MCA_INIT_SEQ_OP_8
31:28
0x2
Description
Operation #1 to be executed in memory initialization
sequence.
Operation #2 to be executed in memory initialization
sequence.
Operation #3 to be executed in memory initialization
sequence.
Operation #4 to be executed in memory initialization
sequence.
Operation #5 to be executed in memory initialization
sequence.
Operation #6 to be executed in memory initialization
sequence.
Operation #7 to be executed in memory initialization
sequence.
Operation #8 to be executed in memory initialization
sequence.
Memory controller A initialization sequence first chunk.
Initialization operation selection:
0=NOP
1=PRECHARGE ALL
2=REFRESH
3=ZQC
4=MRS
5=EMRS
6=EMRS2
7=EMRS3
8=MRS DLL reset
9=EMRS OCD default
A=OCD adjust
B=OCD drive
C=Write levelization
D=NOP 10 clocks
E=NOP 50 clocks
F=NOP 255 clocks
AMD RS690 ASIC Family Register Reference Manual
2-198
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_SEQUENCE_2 - RW - 32 bits - NBMCIND:0xA5
Field Name
MCA_INIT_SEQ_OP_9
Bits
3:0
Default
0x0
MCA_INIT_SEQ_OP_10
7:4
0x0
MCA_INIT_SEQ_OP_11
11:8
0x0
MCA_INIT_SEQ_OP_12
15:12
0x0
MCA_INIT_SEQ_OP_13
19:16
0x0
MCA_INIT_SEQ_OP_14
23:20
0x0
MCA_INIT_SEQ_OP_15
27:24
0x0
MCA_INIT_SEQ_OP_16
31:28
0x0
Description
Operation #9 to be executed in memory initialization
sequence.
Operation #10 to be executed in memory initialization
sequence.
Operation #11 to be executed in memory initialization
sequence.
Operation #12 to be executed in memory initialization
sequence.
Operation #13 to be executed in memory initialization
sequence.
Operation #14 to be executed in memory initialization
sequence.
Operation #15 to be executed in memory initialization
sequence.
Operation #16 to be executed in memory initialization
sequence.
Memory controller A initialization sequence second chunk.
Initialization operation selection:
0=NOP
1=PRECHARGE ALL
2=REFRESH
3=ZQC
4=MRS
5=EMRS
6=EMRS2
7=EMRS3
8=MRS DLL reset
9=EMRS OCD default
A=OCD adjust
B=OCD drive
C=Write levelization
D=NOP 10 clocks
E=NOP 50 clocks
F=NOP 255 clocks
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-199
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_SEQUENCE_3 - RW - 32 bits - NBMCIND:0xA6
Field Name
MCA_INIT_SEQ_OP_17
Bits
3:0
Default
0x0
MCA_INIT_SEQ_OP_18
7:4
0x0
MCA_INIT_SEQ_OP_19
11:8
0x0
MCA_INIT_SEQ_OP_20
15:12
0x0
MCA_INIT_SEQ_OP_21
19:16
0x0
MCA_INIT_SEQ_OP_22
23:20
0x0
MCA_INIT_SEQ_OP_23
27:24
0x0
MCA_INIT_SEQ_OP_24
31:28
0x0
Description
Operation #17 to be executed in memory initialization
sequence.
Operation #18 to be executed in memory initialization
sequence.
Operation #19 to be executed in memory initialization
sequence.
Operation #20 to be executed in memory initialization
sequence.
Operation #21 to be executed in memory initialization
sequence.
Operation #22 to be executed in memory initialization
sequence.
Operation #23 to be executed in memory initialization
sequence.
Operation #24 to be executed in memory initialization
sequence.
Memory controller A initialization sequence third chunk.
Initialization operation selection:
0=NOP
1=PRECHARGE ALL
2=REFRESH
3=ZQC
4=MRS
5=EMRS
6=EMRS2
7=EMRS3
8=MRS DLL reset
9=EMRS OCD default
A=OCD adjust
B=OCD drive
C=Write levelization
D=NOP 10 clocks
E=NOP 50 clocks
F=NOP 255 clocks
AMD RS690 ASIC Family Register Reference Manual
2-200
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_SEQUENCE_4 - RW - 32 bits - NBMCIND:0xA7
Field Name
MCA_INIT_SEQ_OP_25
Bits
3:0
Default
0x0
MCA_INIT_SEQ_OP_26
7:4
0x0
MCA_INIT_SEQ_OP_27
11:8
0x0
MCA_INIT_SEQ_OP_28
15:12
0x0
MCA_INIT_SEQ_OP_29
19:16
0x0
MCA_INIT_SEQ_OP_30
23:20
0x0
MCA_INIT_SEQ_OP_31
27:24
0x0
MCA_INIT_SEQ_OP_32
31:28
0x0
Description
Operation #25 to be executed in memory initialization
sequence.
Operation #26 to be executed in memory initialization
sequence.
Operation #27 to be executed in memory initialization
sequence.
Operation #28 to be executed in memory initialization
sequence.
Operation #29 to be executed in memory initialization
sequence.
Operation #30 to be executed in memory initialization
sequence.
Operation #31 to be executed in memory initialization
sequence.
Operation #32 to be executed in memory initialization
sequence.
Memory controller A initialization sequence fourth chunk.
Initialization operation selection:
0=NOP
1=PRECHARGE ALL
2=REFRESH
3=ZQC
4=MRS
5=EMRS
6=EMRS2
7=EMRS3
8=MRS DLL reset
9=EMRS OCD default
A=OCD adjust
B=OCD drive
C=Write levelization
D=NOP 10 clocks
E=NOP 50 clocks
F=NOP 255 clocks
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-201
Graphics Controller Configuration Registers
MCA_TIMING_PARAMETERS_1 - RW - 32 bits - NBMCIND:0xA8
Bits
3:0
Default
0x4
MCA_WR_LAT
7:4
0x3
MCA_TRCDR
11:8
0x8
MCA_TRCDW
15:12
0x8
MCA_TRP
19:16
0x8
MCA_TRTP
23:20
0x4
MCA_RD_LAT
Field Name
AMD RS690 ASIC Family Register Reference Manual
2-202
Description
Memory CAS Latency
0=0 clock (not supported)
1=1 clock (not supported)
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory Write Latency
0=0 clock (not supported)
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Active to Read delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Active to Write delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Precharge command period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Internal Read to Precharge command delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_TWR
27:24
0x8
MCA_TRRD
31:28
0x6
Write recovery time
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Active bank A to Active bank B command period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory controller A timing parameters, set 1
MCA_TIMING_PARAMETERS_2 - RW - 32 bits - NBMCIND:0xA9
Bits
7:0
Default
0x18
MCA_TRC
15:8
0x20
MCA_TRFC
23:16
0x28
MCA_TREFI
31:24
0x10
MCA_TRAS
Field Name
Memory controller A timing parameters, set 2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Active to Precharge command
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
29=29 clock
30=30 clock
31=31 clock
Row Cycle time. Active to Active/Auto-Refresh command
period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
125=125 clock
126=126 clock
127=127 clock
Auto-Refresh to Active/Auto-Refresh command period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
125=125 clock
126=126 clock
127=127 clock
1 memory refresh is performed every TREFI*64 MCLK
cycles.
AMD RS690 ASIC Family Register Reference Manual
2-203
Graphics Controller Configuration Registers
MCA_TIMING_PARAMETERS_3 - RW - 32 bits - NBMCIND:0xAA
Field Name
MCA_TRTR_CS
Bits
3:0
Default
0x1
MCA_TRTW
7:4
0x2
MCA_TWTR
11:8
0x4
MCA_TWTR_CS
15:12
0x2
MCA_TWTW_CS
19:16
0x1
MCA_TCCD
23:20
0x2
AMD RS690 ASIC Family Register Reference Manual
2-204
Description
Read to Read command to different CS
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Read to Write bus turnaround
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Internal Write to Read command delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Write to Read command to different CS
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Write to Write command to different CS
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
CAS to CAS command delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_TCKE
27:24
0x3
MCA_TXP
31:28
0x2
CKE minimum high and low pulse width
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Exit precharge power down to any valid command
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory controller A timing parameters, set 3
MCA_TIMING_PARAMETERS_4 - RW - 32 bits - NBMCIND:0xAB
Field Name
MCA_TXARDS
Bits
3:0
Default
0x6
MCA_TAXPD
7:4
0x8
MCA_TRPALL
11:8
0x2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Exit active power down to read command
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
ODT power down exit latency
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Precharge all for 8 bank memories
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
AMD RS690 ASIC Family Register Reference Manual
2-205
Graphics Controller Configuration Registers
MCA_TFAW
15:12
0x2
MCA_TZQCL
19:16
0x8
MCA_TZQCS
MCA_TZQCI
MCA_TMRD
23:20
27:24
31:28
0x4
0x1
0x2
Back to back activate rolling window
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Impedance calibration long timing, can be merged with DLL
time, x64 clocks.
Impedance calibration short timing, x16 clocks.
Impedance calibration interval, x256 refresh cycles.
Mode register set command cycle time
0=0 clock
1=1 clock
...
15=15 clock
Memory controller A timing parameters, set 4
MCA_MEMORY_TYPE - RW - 32 bits - NBMCIND:0xAC
Field Name
MCA_MODE_CS0
Bits
3:0
Default
0x0
4
0x0
RESERVED5
MCA_MODE_CS1
7:5
11:8
0x0
0x0
RESERVED12
MCA_MODE_CS2
15:12
19:16
0x0
0x0
RESERVED20
MCA_MODE_CS3
23:20
27:24
0x0
0x0
RESERVED28
Memory controller A memory size and type
31:28
0x0
MCA_AP_BIT
Description
MCA CS0 memory size
0=Unpopulated chip select
4=32MB (16Mbx16)
5=64MB (32Mbx8)
6=128MB (64Mbx8)
10=256MB (512Mb, x16)
11=512MB (1Gb, x16)
MCA Auto Precharge bit
0=A10
1=A8
MCA CS1 memory size
0=Unpopulated chip select
MCA CS2 memory size
0=Unpopulated chip select
MCA CS3 memory size
0=Unpopulated chip select
MCA_CKE_MUX_SELECT - RW - 32 bits - NBMCIND:0xAD
Field Name
MCA_MUX_SELECT_CKE0
Bits
3:0
Default
0x1
AMD RS690 ASIC Family Register Reference Manual
2-206
Description
Channel A CKE0 mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_MUX_SELECT_CKE1
7:4
0x2
MCA_MUX_SELECT_CKE2
11:8
0x4
MCA_MUX_SELECT_CKE3
15:12
0x8
RESERVED16
Memory controller A mux select CKE
31:16
0x0
Channel A CKE1 mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A CKE2 mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A CKE3 mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
MCA_ODT_MUX_SELECT - RW - 32 bits - NBMCIND:0xAE
Field Name
MCA_MUX_SELECT_ODTR0
Bits
3:0
Default
0x1
MCA_MUX_SELECT_ODTR1
7:4
0x2
MCA_MUX_SELECT_ODTR2
11:8
0x4
MCA_MUX_SELECT_ODTR3
15:12
0x8
MCA_MUX_SELECT_ODTW0
19:16
0x1
MCA_MUX_SELECT_ODTW1
23:20
0x2
MCA_MUX_SELECT_ODTW2
27:24
0x4
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A ODT0 read mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT1 read mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT2 read mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT3 read mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT0 write mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT1 write mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT2 write mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
AMD RS690 ASIC Family Register Reference Manual
2-207
Graphics Controller Configuration Registers
MCA_MUX_SELECT_ODTW3
31:28
0x8
Channel A ODT3 write mux select
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Memory controller A mux select ODT
MCA_SEQ_PERF_CNTL - RW - 32 bits - NBMCIND:0xAF
Field Name
MCA_IDLE_CHANGE_MIN
Bits
4:0
Default
0x0
RESERVED5
MCA_IDLE_CHANGE_MAX
7:5
12:8
0x0
0x0
MCA_CMD_FIFO_EOB_OFF
13
0x0
RESERVED14
MCA_ACTV_HI_PRI
14
15
0x0
0x0
20:16
0x4
MCA_CMD_FIFO_EOB_ON
21
0x0
MCA_EARLY_ACTIVATE
22
0x0
MCA_IDLE_LIMIT_DYNAMIC
23
0x0
25:24
0x0
MCA_BIU_RD_BYPASS_WR
26
0x0
MCA_BIU_RD_BYPASS_STALL
27
0x0
31:28
0x0
MCA_IDLE_LIMIT
MCA_CMD_FIFO_DEPTH
MCA_BIU_RD_BYPASS_MAX
Memory controller A sequencer performance control
AMD RS690 ASIC Family Register Reference Manual
2-208
Description
Channel A idle change minimum. Under dynamic mode this
field and MCA_IDLE_LIMIT specify the lower bound of the
limit.
limit(min) = (4*MCA_IDLE_LIMIT) +
MCA_IDLE_CHNAGE_MIN cycles.
Channel A idle change maximum. Under dynamic mode
this field and MCA_IDLE_LIMIT specify the upper bound of
the limit.
limit(max) = (4*MCA_IDLE_LIMIT) +
MCA_IDLE_CHANGE_MAX cycles.
Channel A command fifo end-of-burst.
0=Command fifo end-of-burst disabled
1=Command fifo end-of-burst enabled
Channel A hi priority activate.
0=Hi priority activate disabled
1=High priority activate enabled
Channel A idle limit. The value of this field determines how
long a page will be kept open after last page hit.
0x1F=No page open limit
Otherwise limit=(4*MCA_IDLE_LIMIT) cycles
Channel A command fifo end-of-burst.
0=Command fifo end-of-burst disabled
1=Command fifo end-of-burst enabled
Channel A early activate.
0=Early activate disabled
1=Early activate enabled
Channel A idle limit dynamic.
0=Dynamic idle limit disabled
1=Dynamic idle limit enabled
Channel A command FIFO depth.
0=1 entry
1=2 entries
2=3 entries
3=4 entries
Channel A BIU read bypass write.
0=Bypass disabled
1=Bypass enabled
Channel A BIU read bypass stall 1 clock until timers OK.
0=Stall disabled
1=Stall enabled
Channel A BIU read bypass maximum number.
0=Disabled BIU read bypass
1-14=Number of BIU read bypass
15=Unlimited number of BIU read bypass
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_SEQ_CONTROL - RW - 32 bits - NBMCIND:0xB0
Field Name
MCA_SEQ_MCIFR_URG_EN
Bits
0
Default
0x0
MCA_SEQ_DMIFR_URG_EN
1
0x0
MCA_SEQ_AZR_URG_EN
2
0x0
MCA_SEQ_BIUW_URG_EN
3
0x0
5:4
0x0
MCA_AP_DISABLE
6
0x0
MCA_CKE_FOR_ODT
7
0x0
MCA_BURST_LENGTH_8
8
0x0
MCA_2T_TIMING
9
0x0
MCA_3T_TIMING
10
0x0
11
19:12
23:20
0x0
0x0
0x8
MCA_DQ_PRE
RESERVED11
RESERVED12
MCA_TCKED
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A urgent MCIF read. If mcif read is urgent and it is
found in the command fifo then flush it out.
0=Disable flushing out of urgent mcif reads
1=Enable flushing out of urgent mcif reads
Channel A urgent DMIF read. If dmif read is urgent and it is
found in the command fifo then flush it out.
0=Disable flushing out of urgent dmif reads
1=Enable flushing out of urgent dmif reads
Channel A urgent AZ read. If az read is urgent and it is
found in the command fifo then flush it out.
0=Disable flushing out of urgent az reads
1=Enable flushing out of urgent az reads
Channel A urgent BIU write. If biu write is urgent and it is
found in the command fifo then flush it out.
0=Disable flushing out of urgent biu writes
1=Enable flushing out of urgent biu writes
Write data preamble / postamble
0=Low
1=High
2=Opposite of first / last data
3=The same as first / last data
Channel A auto precharge disable
0=Auto recharge enabled
1=Auto precharge disabled
Channel A ODT CKE stall
0=No stall
1=Stall
Channel A Burst Length
0=Burst Length 4
1=Burst Length 8
Channel A timing mode
0=1T timing
1=2T timing
Channel A timing mode
0=1T timing
1=3T timing
Channel A CKE time delay, time from CKE condition to
CKE low, x4 clocks
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
AMD RS690 ASIC Family Register Reference Manual
2-209
Graphics Controller Configuration Registers
MCA_TTRSTD
27:24
0x8
MCA_TTRST
31:28
0x4
Channel A tristate time delay, time from tristate condition to
tristate, x4 clocks
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Channel A tristate time, time from tristate to full drive
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory controller A sequencer control
AMD RS690 ASIC Family Register Reference Manual
2-210
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_RECEIVING - RW - 32 bits - NBMCIND:0xB1
Field Name
MCA_DQ_TRANSFER
Bits
3:0
Default
0x4
MCA_DQS_RST_PLS
5:4
0x2
6
0x0
RESERVED7
RESERVED8
MCA_IN_TERM_START_DQ
7
11:8
12
0x0
0x0
0x0
MCA_IN_TERM_STOP_DQ
13
0x0
MCA_IN_TERM_START_DQS
14
0x0
MCA_IN_TERM_STOP_DQS
15
0x0
MCA_IN_TERM_N_DQ
18:16
0x3
RESERVED19
MCA_IN_TERM_P_DQ
19
22:20
0x0
0x3
RESERVED23
MCA_IN_TERM_N_DQS
23
26:24
0x0
0x3
27
0x0
MCA_DQ_DQS_REC_DYNAMIC
RESERVED27
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A read data transfer from strobe flops to core clock
flops
0=CL+0clock
1=CL+1clock
2=CL+2clock
3=CL+3clock
4=CL+4clock
Channel A read strobe reset pulse
0=Quarter pulse, Quarter position
1=Half pulse, Quarter position
2=Half pulse, Half position
3=Reserved
Channel A data and strobe receiver enable control
0=Always enabled
1=Enabled for read only
Channel A data input termination turning on for read
preceded by write
0=Turning on half clock after OE off
1=Turning on full clock after OE off
Channel A data input termination turning off for read
followed by write
0=Turning off half clock before OE on
1=Turning off full clock before OE on
Channel A strobe input termination turning on for read
preceded by write
0=Turning on half clock after OE off
1=Turning on full clock after OE off
Channel A strobe input termination turning off for read
followed by write
0=Turning off half clock before OE on
1=Turning off full clock before OE on
Channel A data input N termination, 3 pull-down resistors
300 Ohm
0=Termination off
1=300 Ohm pull-down
3=150 Ohm pull-down
7=100 Ohm pull-down
Channel A data input P termination, 3 pull-up resistors 300
Ohm
0=Termination off
1=300 Ohm pull-up
3=150 Ohm pull-up
7=100 Ohm pull-up
Channel A strobe input N termination, 3 pull-down resistors
300 Ohm
0=Termination off
1=300 Ohm pull-down
3=150 Ohm pull-down
7=100 Ohm pull-down
AMD RS690 ASIC Family Register Reference Manual
2-211
Graphics Controller Configuration Registers
MCA_IN_TERM_P_DQS
RESERVED31
Memory controller A receiving control
30:28
0x3
31
0x0
Channel A strobe input P termination, 3 pull-up resistors
300 Ohm
0=Termination off
1=300 Ohm pull-up
3=150 Ohm pull-up
7=100 Ohm pull-up
MCA_IN_TIMING_DQS_3210 - RW - 32 bits - NBMCIND:0xB2
Field Name
MCA_DQS_ARRIVAL_0
Bits
4:0
Default
0x6
RESERVED5
MCA_DQS_ARRIVAL_1
7:5
12:8
0x0
0x6
RESERVED13
15:13
0x0
AMD RS690 ASIC Family Register Reference Manual
2-212
Description
Channel A byte 0 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
Channel A byte 1 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_DQS_ARRIVAL_2
20:16
0x6
RESERVED21
MCA_DQS_ARRIVAL_3
23:21
28:24
0x0
0x6
RESERVED29
Channel A input strobe gating timing
31:29
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Channel A byte 2 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
Channel A byte 3 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
AMD RS690 ASIC Family Register Reference Manual
2-213
Graphics Controller Configuration Registers
MCA_IN_TIMING_DQS_7654 - RW - 32 bits - NBMCIND:0xB3
Field Name
MCA_DQS_ARRIVAL_4
Bits
4:0
Default
0x6
RESERVED5
MCA_DQS_ARRIVAL_5
7:5
12:8
0x0
0x6
RESERVED13
15:13
0x0
AMD RS690 ASIC Family Register Reference Manual
2-214
Description
Channel A byte 4 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
Channel A byte 5 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_DQS_ARRIVAL_6
20:16
0x6
RESERVED21
MCA_DQS_ARRIVAL_7
23:21
28:24
0x0
0x6
RESERVED29
Channel A input strobe gating timing
31:29
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Channel A byte 6 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
Channel A byte 7 input strobe reset removal edge
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
AMD RS690 ASIC Family Register Reference Manual
2-215
Graphics Controller Configuration Registers
MCA_DRIVING - RW - 32 bits - NBMCIND:0xB4
Field Name
MCA_CK_ENABLE
Bits
5:0
Default
0x0
MCA_CKE_ENABLE
6
0x0
MCA_CKE_DYNAMIC
7
0x0
MCA_ODT_ENABLE
8
0x0
MCA_ODT_DYNAMIC
9
0x1
MCA_ODT_READ
10
0x0
MCA_ODT_WRITE
11
0x1
MCA_ODTR_POSITION
13:12
0x0
MCA_ODTR_LENGTH
15:14
0x0
MCA_ODTW_POSITION
17:16
0x0
MCA_ODTW_LENGTH
19:18
0x0
MCA_ODT_STALL
20
0x0
MCA_ODTX
21
0x0
MCA_ODTX_1T
22
0x0
AMD RS690 ASIC Family Register Reference Manual
2-216
Description
Channel A clock pair select, enable
0=Particular clock pair disabled
1=Particular clock pair enabled
Channel A CKE enable
0=CKE disabled, forced low
1=CKE enabled, high or dynamic
Channel A CKE dynamic
0=CKE high when enabled
1=CKE dynamic when enabled, high or low depending
on activity, active or precharge power down
Channel A ODT enable
0=ODT forced 0
1=ODT enabled
Channel A ODT dynamic
0=ODT forced 1 if enabled
1=ODT dynamic if enabled
Channel A ODT enable for read
0=ODT disabled for read
1=ODT enabled for read
Channel A ODT enable for write
0=ODT disabled for write
1=ODT enabled for write
Channel A ODT read position
When ODTX 0, read latency dependent
When ODTX 1, read command dependent
0=ODT start at RL-3 for ODTX 0, ODT start at RD for
ODTX1
1=ODT start at RL-2 for ODTX 0, ODT start at RD+1 for
ODTX 1
2/3=1 clock later
Channel A ODT read length
0=ODT length BL/2+1
1=ODT length BL/2+2
2/3=1 clock longer
Channel A ODT write position
When ODTX 0, write latency dependent
When ODTX 1, write command dependent
0=ODT start at WL-3 for ODTX 0, ODT start at WR for
ODTX1
1=ODT start at WL-2 for ODTX 0, ODT start at WR+1 for
ODTX 1
2/3=1 clock later
Channel A ODT write length
0=ODT length BL/2+1
1=ODT length BL/2+2
2/3=1 clock longer
Channel A ODT stall first write
0=No stall
1=Stall
Channel A ODTX enable
0=ODTX disable
1=ODTX enable
Channel A ODTX 1T
0=1T/2T/3T
1=1T
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_ODTX_POSITION
23
0x0
MCA_DQS_PRE
25:24
0x1
MCA_DQS_POST
27:26
0x1
MCA_DQSX_PRE
28
0x0
MCA_DQSX_POST
29
0x0
MCA_DQSX_PRE_HI
30
0x0
RESERVED31
Memory controller A driving control
31
0x0
Channel A ODTX position
0=ODTX start as set with ODT_START
1=ODT start one clock later then set with ODT_START
Channel A strobe output preamble
0=0.5 clock
1=1 clock
2=1.5 clock
3=2 clock
Channel A strobe output postamble
0=0.5 clock
1=1 clock
2=1.5 clock
3=2 clock
Channel A DQS preamble pulse
0=Preamble low
1=Preamble pulse
Channel A DQS postamble pulse
0=As set with DQS_POST
1=One clock extended DQS_POST
Channel A DQS preamble/postamble high
0=Preamble low
1=Preamble high
MCA_OUT_TIMING - RW - 32 bits - NBMCIND:0xB5
Field Name
MCA_OUT_TIMING_CK
Bits
2:0
Default
0x4
MCA_PAD_BYPASS_CK
3
0x1
MCA_OUT_TIMING_CKE
6:4
0x5
MCA_PAD_BYPASS_CKE
7
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A clock output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A clock bypassing pad flops
0=Through pad flops
1=Bypass pad flops
Channel A CKE output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A CKE bypassing pad flops
0=Through pad flops
1=Bypass pad flops
AMD RS690 ASIC Family Register Reference Manual
2-217
Graphics Controller Configuration Registers
MCA_OUT_TIMING_CS
10:8
0x5
MCA_PAD_BYPASS_CS
11
0x1
MCA_OUT_TIMING_CMD
14:12
0x5
MCA_PAD_BYPASS_CMD
15
0x1
MCA_OUT_TIMING_ODT
18:16
0x5
MCA_PAD_BYPASS_ODT
19
0x1
MCA_OUT_TIMING_DQ
22:20
0x3
MCA_PAD_BYPASS_DQ
23
0x1
MCA_OUT_TIMING_DQS
26:24
0x4
MCA_PAD_BYPASS_DQS
27
0x1
AMD RS690 ASIC Family Register Reference Manual
2-218
Channel A CS output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A CS bypassing pad flops
0=Through pad flops
1=Bypass pad flops
Channel A address and command output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A address and command bypassing pad flops
0=Through pad flops
1=Bypass pad flops
Channel A ODT output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A ODT bypassing pad flops
0=Through pad flops
1=Bypass pad flops
Channel A data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A data and mask bypassing pad flops
0=Through pad flops
1=Bypass pad flops
Channel A strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A strobe bypassing pad flops
0=Through pad flops
1=Bypass pad flops
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_OUT_TIMING_XXX
30:28
0x0
MCA_PAD_BYPASS_XXX
31
0x1
Memory controller A output timing
Channel A XXX output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A XXX bypassing pad flops
0=Through pad flops
1=Bypass pad flops
MCA_OUT_TIMING_DQ - RW - 32 bits - NBMCIND:0xB6
Field Name
MCA_OUT_TIMING_DQ_B0
Bits
3:0
Default
0x3
MCA_OUT_TIMING_DQ_B1
7:4
0x3
MCA_OUT_TIMING_DQ_B2
11:8
0x3
MCA_OUT_TIMING_DQ_B3
15:12
0x3
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A byte 0 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 1 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 2 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 3 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
AMD RS690 ASIC Family Register Reference Manual
2-219
Graphics Controller Configuration Registers
MCA_OUT_TIMING_DQ_B4
19:16
0x3
MCA_OUT_TIMING_DQ_B5
23:20
0x3
MCA_OUT_TIMING_DQ_B6
27:24
0x3
MCA_OUT_TIMING_DQ_B7
31:28
0x3
Channel A output data and mask timing
AMD RS690 ASIC Family Register Reference Manual
2-220
Channel A byte 4 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 5 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 6 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 7 data and mask output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_OUT_TIMING_DQS - RW - 32 bits - NBMCIND:0xB7
Field Name
MCA_OUT_TIMING_DQS_0
Bits
3:0
Default
0x4
MCA_OUT_TIMING_DQS_1
7:4
0x4
MCA_OUT_TIMING_DQS_2
11:8
0x4
MCA_OUT_TIMING_DQS_3
15:12
0x4
MCA_OUT_TIMING_DQS_4
19:16
0x4
MCA_OUT_TIMING_DQS_5
23:20
0x4
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A byte 0 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 1 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 2 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 3 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 4 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 5 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
AMD RS690 ASIC Family Register Reference Manual
2-221
Graphics Controller Configuration Registers
MCA_OUT_TIMING_DQS_6
27:24
0x4
MCA_OUT_TIMING_DQS_7
31:28
0x4
Channel A byte 6 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 7 strobe output timing
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A output strobe timing
MCA_STRENGTH_N - RW - 32 bits - NBMCIND:0xB8
Field Name
MCA_STRENGTH_N_CK
Bits
3:0
Default
0xb
MCA_STRENGTH_N_CKE
7:4
0xb
MCA_STRENGTH_N_CS
11:8
0xb
MCA_STRENGTH_N_CMD
15:12
0xb
MCA_STRENGTH_N_ODT
19:16
0xb
MCA_STRENGTH_N_DQ
23:20
0xb
MCA_STRENGTH_N_DQS
27:24
0xb
MCA_STRENGTH_N_XXX
31:28
0xb
Memory controller A strength N
AMD RS690 ASIC Family Register Reference Manual
2-222
Description
Channel A clock (nominal and complement) strength N
driver
0=Minimum strength
15=Maximum strength
Channel A CKE strength N driver
0=Minimum strength
15=Maximum strength
Channel A CS strength N driver
0=Minimum strength
15=Maximum strength
Channel A RAS/CAS/WE and address strength N driver
0=Minimum strength
15=Maximum strength
Channel A ODT strength N driver
0=Minimum strength
15=Maximum strength
Channel A data and mask strength N driver
0=Minimum strength
15=Maximum strength
Channel A strobe (nominal and complement) strength N
driver
0=Minimum strength
15=Maximum strength
Channel A spare strength N driver
0=Minimum strength
15=Maximum strength
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_STRENGTH_P - RW - 32 bits - NBMCIND:0xB9
Field Name
MCA_STRENGTH_P_CK
Bits
3:0
Default
0xb
MCA_STRENGTH_P_CKE
7:4
0xb
MCA_STRENGTH_P_CS
11:8
0xb
MCA_STRENGTH_P_CMD
15:12
0xb
MCA_STRENGTH_P_ODT
19:16
0xb
MCA_STRENGTH_P_DQ
23:20
0xb
MCA_STRENGTH_P_DQS
27:24
0xb
MCA_STRENGTH_P_XXX
31:28
0xb
Description
Channel A clock (nominal and complement) strength P
driver
0=Minimum strength
15=Maximum strength
Channel A CKE strength P driver
0=Minimum strength
15=Maximum strength
Channel A CS strength P driver
0=Minimum strength
15=Maximum strength
Channel A RAS/CAS/WE and address strength P driver
0=Minimum strength
15=Maximum strength
Channel A ODT strength P driver
0=Minimum strength
15=Maximum strength
Channel A data and mask strength P driver
0=Minimum strength
15=Maximum strength
Channel A strobe (nominal and complement) strength P
driver
0=Minimum strength
15=Maximum strength
Channel A spare strength P driver
0=Minimum strength
15=Maximum strength
Memory controller A strength P
MCA_STRENGTH_STEP - RW - 32 bits - NBMCIND:0xBA
Field Name
MCA_STR_STEP_N_CK
Bits
1:0
Default
0x1
MCA_STR_STEP_P_CK
3:2
0x1
MCA_STR_STEP_N_CKE
5:4
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A clock (nominal and complement) impedance
controller adjustment step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A clock (nominal and complement) impedance
controller adjustment step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A CKE impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
AMD RS690 ASIC Family Register Reference Manual
2-223
Graphics Controller Configuration Registers
MCA_STR_STEP_P_CKE
7:6
0x1
MCA_STR_STEP_N_CS
9:8
0x1
MCA_STR_STEP_P_CS
11:10
0x1
MCA_STR_STEP_N_CMD
13:12
0x1
MCA_STR_STEP_P_CMD
15:14
0x1
MCA_STR_STEP_N_ODT
17:16
0x1
MCA_STR_STEP_P_ODT
19:18
0x1
MCA_STR_STEP_N_DQ
21:20
0x1
MCA_STR_STEP_P_DQ
23:22
0x1
MCA_STR_STEP_N_DQS
25:24
0x1
AMD RS690 ASIC Family Register Reference Manual
2-224
Channel A CKE impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A CS impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A CS impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A RAS/CAS/WE and address impedance
controller adjustment step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A RAS/CAS/WE and address impedance
controller adjustment step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A ODT impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A ODT impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A data and mask impedance controller adjustment
step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A data and mask impedance controller adjustment
step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A strobe (nominal and complement) impedance
controller adjustment step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_STR_STEP_P_DQS
27:26
0x1
Channel A strobe (nominal and complement) impedance
controller adjustment step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
MCA_STR_STEP_N_XXX
29:28
0x1
Channel A spare impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
MCA_STR_STEP_P_XXX
31:30
0x1
Channel A spare impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Memory controller A impedance controller adjustment step for strength
MCA_STRENGTH_READ_BACK_N - RW - 32 bits - NBMCIND:0xBB
Field Name
MCA_STR_READ_BACK_N_CK (R)
Bits
3:0
Default
0x0
MCA_STR_READ_BACK_N_CKE (R)
7:4
0x0
MCA_STR_READ_BACK_N_CS (R)
11:8
0x0
MCA_STR_READ_BACK_N_CMD (R)
15:12
0x0
MCA_STR_READ_BACK_N_ODT (R)
19:16
0x0
MCA_STR_READ_BACK_N_DQ (R)
23:20
0x0
MCA_STR_READ_BACK_N_DQS (R)
27:24
0x0
MCA_STR_READ_BACK_N_XXX (R)
31:28
0x0
Memory controller A strength N read back
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A clock (nominal and complement) read back
strength N driver
0=Minimum strength
15=Maximum strength
Channel A CKE read back strength N driver
0=Minimum strength
15=Maximum strength
Channel A CS read back strength N driver
0=Minimum strength
15=Maximum strength
Channel A RAS/CAS/WE and address read back strength
N driver
0=Minimum strength
15=Maximum strength
Channel A ODT read back strength N driver
0=Minimum strength
15=Maximum strength
Channel A data and mask read back strength N driver
0=Minimum strength
15=Maximum strength
Channel A strobe (nominal and complement) read back
strength N driver
0=Minimum strength
15=Maximum strength
Channel A spare read back strength N driver
0=Minimum strength
15=Maximum strength
AMD RS690 ASIC Family Register Reference Manual
2-225
Graphics Controller Configuration Registers
MCA_STRENGTH_READ_BACK_P - RW - 32 bits - NBMCIND:0xBC
Field Name
MCA_STR_READ_BACK_P_CK (R)
Bits
3:0
Default
0x0
MCA_STR_READ_BACK_P_CKE (R)
7:4
0x0
MCA_STR_READ_BACK_P_CS (R)
11:8
0x0
MCA_STR_READ_BACK_P_CMD (R)
15:12
0x0
MCA_STR_READ_BACK_P_ODT (R)
19:16
0x0
MCA_STR_READ_BACK_P_DQ (R)
23:20
0x0
MCA_STR_READ_BACK_P_DQS (R)
27:24
0x0
MCA_STR_READ_BACK_P_XXX (R)
31:28
0x0
Description
Channel A clock (nominal and complement) read back
strength P driver
0=Minimum strength
15=Maximum strength
Channel A CKE read back strength P driver
0=Minimum strength
15=Maximum strength
Channel A CS read back strength P driver
0=Minimum strength
15=Maximum strength
Channel A RAS/CAS/WE and address read back strength P
driver
0=Minimum strength
15=Maximum strength
Channel A ODT read back strength P driver
0=Minimum strength
15=Maximum strength
Channel A data and mask read back strength P driver
0=Minimum strength
15=Maximum strength
Channel A strobe (nominal and complement) read back
strength P driver
0=Minimum strength
15=Maximum strength
Channel A spare read back strength P driver
0=Minimum strength
15=Maximum strength
Memory controller A strength P read back
MCA_PREAMP - RW - 32 bits - NBMCIND:0xBD
Field Name
MCA_PREAMP_EN_CK
Bits
0
Default
0x1
MCA_PREAMP_ALWAYS_CK
1
0x1
MCA_PREAMP_HALF_CLK_CK
2
0x0
MCA_PREAMP_TWO_CLK_CK
3
0x0
MCA_PREAMP_EN_CKE
4
0x1
AMD RS690 ASIC Family Register Reference Manual
2-226
Description
Channel A clock (nominal and complement)
preamplification enable
0=Preamplification disabled
1=Preamplification enabled
Channel A clock (nominal and complement)
preamplification always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A clock (nominal and complement)
preamplification duration, if enabled and not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A clock (nominal and complement)
preamplification condition, if enabled and not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A CKE preamplification enable
0=Preamplification disabled
1=Preamplification enabled
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_PREAMP_ALWAYS_CKE
5
0x1
MCA_PREAMP_HALF_CLK_CKE
6
0x0
MCA_PREAMP_TWO_CLK_CKE
7
0x0
MCA_PREAMP_EN_CS
8
0x1
MCA_PREAMP_ALWAYS_CS
9
0x1
MCA_PREAMP_HALF_CLK_CS
10
0x0
MCA_PREAMP_TWO_CLK_CS
11
0x0
MCA_PREAMP_EN_CMD
12
0x1
MCA_PREAMP_ALWAYS_CMD
13
0x1
MCA_PREAMP_HALF_CLK_CMD
14
0x0
MCA_PREAMP_TWO_CLK_CMD
15
0x0
MCA_PREAMP_EN_ODT
16
0x1
MCA_PREAMP_ALWAYS_ODT
17
0x1
MCA_PREAMP_HALF_CLK_ODT
18
0x0
MCA_PREAMP_TWO_CLK_ODT
19
0x0
MCA_PREAMP_EN_DQ
20
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Channel A CKE preamplification always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A CKE preamplification duration, if enabled and
not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A CKE preamplification condition, if enabled and
not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A CS preamplification enable
0=Preamplification disabled
1=Preamplification enabled
Channel A CS preamplification always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A CS preamplification duration, if enabled and not
always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A CS preamplification condition, if enabled and not
always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A RAS/CAS/WE and address preamplification
enable
0=Preamplification disabled
1=Preamplification enabled
Channel A RAS/CAS/WE and address preamplification
always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A RAS/CAS/WE and address preamplification
duration, if enabled and not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A RAS/CAS/WE and address preamplification
condition, if enabled and not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A ODT preamplification enable
0=Preamplification disabled
1=Preamplification enabled
Channel A ODT preamplification always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A ODT preamplification duration, if enabled and
not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A ODT preamplification condition, if enabled and
not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A data and mask preamplification enable
0=Preamplification disabled
1=Preamplification enabled
AMD RS690 ASIC Family Register Reference Manual
2-227
Graphics Controller Configuration Registers
MCA_PREAMP_ALWAYS_DQ
21
0x1
MCA_PREAMP_HALF_CLK_DQ
22
0x0
MCA_PREAMP_TWO_CLK_DQ
23
0x0
MCA_PREAMP_EN_DQS
24
0x1
MCA_PREAMP_ALWAYS_DQS
25
0x1
MCA_PREAMP_HALF_CLK_DQS
26
0x0
MCA_PREAMP_TWO_CLK_DQS
27
0x0
MCA_PREAMP_EN_XXX
28
0x1
MCA_PREAMP_ALWAYS_XXX
29
0x1
MCA_PREAMP_HALF_CLK_XXX
30
0x0
MCA_PREAMP_TWO_CLK_XXX
31
0x0
Channel A data and mask preamplification always on when
enabled
0=Preamplification conditional
1=Preamplification always on
Channel A data and mask preamplification duration, if
enabled and not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A data and mask preamplification condition, if
enabled and not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A strobe (nominal and complement)
preamplification enable
0=Preamplification disabled
1=Preamplification enabled
Channel A strobe (nominal and complement)
preamplification always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A strobe (nominal and complement)
preamplification duration, if enabled and not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A clock strobe (nominal and complement)
preamplification condition, if enabled and not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Channel A XXX preamplification enable
0=Preamplification disabled
1=Preamplification enabled
Channel A XXX preamplification always on when enabled
0=Preamplification conditional
1=Preamplification always on
Channel A XXX preamplification duration, if enabled and
not always on
0=Preamplification for one 2x clock
1=Preamplification for half 2x clock
Channel A XXX preamplification condition, if enabled and
not always on
0=Preamplification when signal stable for one 1x clock
1=Preamplification when signal stable for two 1x clock
Memory controller A driver preamplification control
AMD RS690 ASIC Family Register Reference Manual
2-228
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_PREAMP_N - RW - 32 bits - NBMCIND:0xBE
Field Name
MCA_PREAMP_N_CK
Bits
3:0
Default
0xb
MCA_PREAMP_N_CKE
7:4
0xb
MCA_PREAMP_N_CS
11:8
0xb
MCA_PREAMP_N_CMD
15:12
0xb
MCA_PREAMP_N_ODT
19:16
0xb
MCA_PREAMP_N_DQ
23:20
0xb
MCA_PREAMP_N_DQS
27:24
0xb
MCA_PREAMP_N_XXX
31:28
0xb
Description
Channel A clock (nominal and complement) preamp
strength N driver
0=Minimum strength
15=Maximum strength
Channel A CKE preamp strength N driver
0=Minimum strength
15=Maximum strength
Channel A CS preamp strength N driver
0=Minimum strength
15=Maximum strength
Channel A RAS/CAS/WE and address preamp strength N
driver
0=Minimum strength
15=Maximum strength
Channel A ODT preamp strength N driver
0=Minimum strength
15=Maximum strength
Channel A data and mask preamp strength N driver
0=Minimum strength
15=Maximum strength
Channel A strobe (nominal and complement) preamp
strength N driver
0=Minimum strength
15=Maximum strength
Channel A spare preamp strength N driver
0=Minimum strength
15=Maximum strength
Memory controller A preamp strength N
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-229
Graphics Controller Configuration Registers
MCA_PREAMP_P - RW - 32 bits - NBMCIND:0xBF
Field Name
MCA_PREAMP_P_CK
Bits
3:0
Default
0xb
MCA_PREAMP_P_CKE
7:4
0xb
MCA_PREAMP_P_CS
11:8
0xb
MCA_PREAMP_P_CMD
15:12
0xb
MCA_PREAMP_P_ODT
19:16
0xb
MCA_PREAMP_P_DQ
23:20
0xb
MCA_PREAMP_P_DQS
27:24
0xb
MCA_PREAMP_P_XXX
31:28
0xb
Description
Channel A clock (nominal and complement) preamp
strength P driver
0=Minimum strength
15=Maximum strength
Channel A CKE preamp strength P driver
0=Minimum strength
15=Maximum strength
Channel A CS preamp strength P driver
0=Minimum strength
15=Maximum strength
Channel A RAS/CAS/WE and address preamp strength P
driver
0=Minimum strength
15=Maximum strength
Channel A ODT preamp strength P driver
0=Minimum strength
15=Maximum strength
Channel A data and mask preamp strength P driver
0=Minimum strength
15=Maximum strength
Channel A strobe (nominal and complement) preamp
strength P driver
0=Minimum strength
15=Maximum strength
Channel A spare preamp strength P driver
0=Minimum strength
15=Maximum strength
Memory controller A preamp strength P
MCA_PREAMP_STEP - RW - 32 bits - NBMCIND:0xC0
Field Name
MCA_PRE_STEP_N_CK
Bits
1:0
Default
0x1
MCA_PRE_STEP_P_CK
3:2
0x1
MCA_PRE_STEP_N_CKE
5:4
0x1
AMD RS690 ASIC Family Register Reference Manual
2-230
Description
Channel A clock (nominal and complement) impedance
controller adjustment step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A clock (nominal and complement) impedance
controller adjustment step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A CKE impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_PRE_STEP_P_CKE
7:6
0x1
MCA_PRE_STEP_N_CS
9:8
0x1
MCA_PRE_STEP_P_CS
11:10
0x1
MCA_PRE_STEP_N_CMD
13:12
0x1
MCA_PRE_STEP_P_CMD
15:14
0x1
MCA_PRE_STEP_N_ODT
17:16
0x1
MCA_PRE_STEP_P_ODT
19:18
0x1
MCA_PRE_STEP_N_DQ
21:20
0x1
MCA_PRE_STEP_P_DQ
23:22
0x1
MCA_PRE_STEP_N_DQS
25:24
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Channel A CKE impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A CS impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A CS impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A RAS/CAS/WE and address impedance
controller adjustment step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A RAS/CAS/WE and address impedance
controller adjustment step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A ODT impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A ODT impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A data and mask impedance controller adjustment
step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A data and mask impedance controller adjustment
step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Channel A strobe (nominal and complement) impedance
controller adjustment step for strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
AMD RS690 ASIC Family Register Reference Manual
2-231
Graphics Controller Configuration Registers
MCA_PRE_STEP_P_DQS
27:26
0x1
Channel A strobe (nominal and complement) impedance
controller adjustment step for strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
MCA_PRE_STEP_N_XXX
29:28
0x1
Channel A spare impedance controller adjustment step for
strength N driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
MCA_PRE_STEP_P_XXX
31:30
0x1
Channel A spare impedance controller adjustment step for
strength P driver
0=0 step, no adjustment
1=1 step, adjustment the same as reference
2=2 step, higher than reference adjustment
3=3 step, higher than reference adjustment
Memory controller A impedance controller adjustment step for preamp
MCA_PREBUF_SLEW_N - RW - 32 bits - NBMCIND:0xC1
Field Name
MCA_PREBUF_SLEW_N_CK
Bits
3:0
Default
0x0
MCA_PREBUF_SLEW_N_CKE
7:4
0x0
MCA_PREBUF_SLEW_N_CS
11:8
0x0
MCA_PREBUF_SLEW_N_CMD
15:12
0x0
MCA_PREBUF_SLEW_N_ODT
19:16
0x0
MCA_PREBUF_SLEW_N_DQ
23:20
0x0
MCA_PREBUF_SLEW_N_DQS
27:24
0x0
MCA_PREBUF_SLEW_N_XXX
31:28
0x0
Channel A prebuffer slew N control
AMD RS690 ASIC Family Register Reference Manual
2-232
Description
Channel A clock (nominal and complement) prebuffer slew
N control
0=Slow edge
15=Fast edge
Channel A CKE prebuffer slew N control
0=Slow edge
15=Fast edge
Channel A CS prebuffer slew N control
0=Slow edge
15=Fast edge
Channel A RAS/CAS/WE and address prebuffer slew N
control
0=Slow edge
15=Fast edge
Channel A ODT prebuffer slew N control
0=Slow edge
15=Fast edge
Channel A data and mask prebuffer slew N control
0=Slow edge
15=Fast edge
Channel A strobe (nominal and complement) prebuffer slew
N control
0=Slow edge
15=Fast edge
Channel A spare prebuffer slew N control
0=Slow edge
15=Fast edge
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_PREBUF_SLEW_P - RW - 32 bits - NBMCIND:0xC2
Field Name
MCA_PREBUF_SLEW_P_CK
Bits
3:0
Default
0x0
MCA_PREBUF_SLEW_P_CKE
7:4
0x0
MCA_PREBUF_SLEW_P_CS
11:8
0x0
MCA_PREBUF_SLEW_P_CMD
15:12
0x0
MCA_PREBUF_SLEW_P_ODT
19:16
0x0
MCA_PREBUF_SLEW_P_DQ
23:20
0x0
MCA_PREBUF_SLEW_P_DQS
27:24
0x0
MCA_PREBUF_SLEW_P_XXX
31:28
0x0
Description
Channel A clock (nominal and complement) prebuffer slew
P control
0=Slow edge
15=Fast edge
Channel A CKE prebuffer slew P control
0=Slow edge
15=Fast edge
Channel A CS prebuffer slew P control
0=Slow edge
15=Fast edge
Channel A RAS/CAS/WE and address prebuffer slew P
control
0=Slow edge
15=Fast edge
Channel A ODT prebuffer slew P control
0=Slow edge
15=Fast edge
Channel A data and mask prebuffer slew P control
0=Slow edge
15=Fast edge
Channel A strobe (nominal and complement) prebuffer slew
P control
0=Slow edge
15=Fast edge
Channel A spare prebuffer slew P control
0=Slow edge
15=Fast edge
Channel A prebuffer slew P control
MCA_GENERAL_PURPOSE - RW - 32 bits - NBMCIND:0xC3
Field Name
MCA_TRST_FORCE
Bits
0
Default
0x0
MCA_TRST_DYNAMIC
1
0x0
MCA_TRST_CK
2
0x0
MCA_TRST_DLL
3
0x0
MCA_TRST_SELFREF
4
0x0
MCA_DQ_DQS_FORCE_TERM
5
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A all signals tristate force
0=Nominal
1=Tristate
Channel A all signals tristate when dynamic CKE low,
except clock running and ODT low
0=Nominal
1=Tristate
Channel A tristate clock when tristate dynamic CKE low
0=Nominal
1=Tristate
Channel A reset memory DLL after exiting tristate dynamic
CKE low with clock tristate
0=Do not reset memory DLL
1=Reset memory DLL
Channel A enter self refresh when tristate dynamic CKE low
0=Do not do anything
1=Enter self refresh
Channel A force ASIC DQ and DQS pads termination force
0=Nominal operation, termination on during read only
1=Termination on always
AMD RS690 ASIC Family Register Reference Manual
2-233
Graphics Controller Configuration Registers
MCA_DQ_DQS_FORCE_LOW
6
0x0
MCA_DQ_DQS_FORCE_HIGH
7
0x0
MCA_DLL_PWRDN
8
MCA_DLL_RESET
9
MCA_DLL_TEST
10
MCA_REF_DISABLE
11
MCA_REF_URGENCY
15:12
MCA_IO_BIAS_CK
16
MCA_IO_BIAS_CKE
17
MCA_IO_BIAS_CS
18
MCA_IO_BIAS_CMD
19
MCA_IO_BIAS_ODT
20
MCA_IO_BIAS_DQ
21
MCA_IO_BIAS_DQS
22
MCA_IO_BIAS_XXX
23
MCA_REF_HI_PRI
24
MCA_OE_CKE
25
MCA_OE_ODT
26
RESERVED25
31:27
Memory controller A general purpose control
0x1
0x1
0x0
0x1
0x6
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
Channel A force ASIC DQ and DQS pads drive low
0=Nominal operation
1=Force drive low DQ/DQS
Channel A force ASIC DQ and DQS pads drive high
0=Nominal operation
1=Force drive high DQ/DQS
Channel A all DLL master power down
Channel A all DLL master reset
Channel A all DLL master test
Disables refreshing when set
Number of pending refreshes until refresh becomes urgent.
Enables MC IO CK bias current.
Enables MC IO CKE bias current.
Enables MC IO CS bias current.
Enables MC IO CMD bias current.
Enables MC IO ODT bias current.
Enables MC IO DQ bias current.
Enables MC IO DQS bias current.
Enables MC IO XXX bias current.
Enables hi priority refreshes.
Enables MC IO CKE OE: 0 = tristate CKE, 1 = output CKE
Enables MC IO CKE ODT: 0 = tristate CKE, 1 = output ODT
MCA_GENERAL_PURPOSE_2 - RW - 32 bits - NBMCIND:0xC4
Field Name
Bits
RESERVED
31:0
Memory controller A general purpose control 2
Default
0x0
Description
MCA_OCD_CONTROL - RW - 32 bits - NBMCIND:0xC5
Field Name
MCA_OCD_CONTROL_BYTE0
MCA_OCD_CONTROL_BYTE1
MCA_OCD_CONTROL_BYTE2
MCA_OCD_CONTROL_BYTE3
MCA_OCD_CONTROL_BYTE4
MCA_OCD_CONTROL_BYTE5
MCA_OCD_CONTROL_BYTE6
MCA_OCD_CONTROL_BYTE7
Memory controller A OCD control data
Bits
3:0
7:4
11:8
15:12
19:16
23:20
27:24
31:28
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-234
Description
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
Channel A OCD control data BYTE 0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_DQ_DQS_READ_BACK - RW - 32 bits - NBMCIND:0xC6
Field Name
MCA_READ_BACK_BYTE0 (R)
Bits
0
Default
0x0
MCA_READ_BACK_BYTE1 (R)
1
0x0
MCA_READ_BACK_DQS0 (R)
8
0x0
MCA_READ_BACK_DQS1 (R)
9
0x0
MCA_READ_BACK_DQ_LSB (R)
23:16
0x0
MCA_READ_BACK_DQ_MSB (R)
31:24
0x0
Memory controller A data and strobe read back
Description
Channel A read back data byte 0
0=All 0 when OCD drive 0, some 0 when OCD drive 1
1=Some 1 when OCD drive 0, all 1 when OCD drive 1
Channel A read back data byte 1
0=All 0 when OCD drive 0, some 0 when OCD drive 1
1=Some 1 when OCD drive 0, all 1 when OCD drive 1
Channel A read back strobe byte 0
0=0
1=1
Channel A read back strobe byte 1
0=0
1=1
Channel A read back data LSB bits 7:0
0=0
1=1
Channel A read back data MSB bits 15:8
0=0
1=1
MCA_DQS_CLK_READ_BACK - RW - 32 bits - NBMCIND:0xC7
Field Name
MCA_SAMPLE_RISE1_DQS0 (R)
Bits
0
Default
0x0
MCA_SAMPLE_FALL1_DQS0 (R)
1
0x0
MCA_SAMPLE_RISE2_DQS0 (R)
2
0x0
MCA_SAMPLE_FALL2_DQS0 (R)
3
0x0
MCA_SAMPLE_RISE1_DQS1 (R)
4
0x0
MCA_SAMPLE_FALL1_DQS1 (R)
5
0x0
MCA_SAMPLE_RISE2_DQS1 (R)
6
0x0
MCA_SAMPLE_FALL2_DQS1 (R)
7
0x0
MCA_SAMPLE_RISE1_DQS2 (R)
8
0x0
MCA_SAMPLE_FALL1_DQS2 (R)
9
0x0
MCA_SAMPLE_RISE2_DQS2 (R)
10
0x0
MCA_SAMPLE_FALL2_DQS2 (R)
11
0x0
MCA_SAMPLE_RISE1_DQS3 (R)
12
0x0
MCA_SAMPLE_FALL1_DQS3 (R)
13
0x0
MCA_SAMPLE_RISE2_DQS3 (R)
14
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A read strobe 0 sampled with first internal clock
rising edge.
Channel A read strobe 0 sampled with first internal clock
falling edge.
Channel A read strobe 0 sampled with second internal clock
rising edge.
Channel A read strobe 0 sampled with second internal clock
falling edge.
Channel A read strobe 1 sampled with first internal clock
rising edge.
Channel A read strobe 1 sampled with first internal clock
falling edge.
Channel A read strobe 1 sampled with second internal clock
rising edge.
Channel A read strobe 1 sampled with second internal clock
falling edge.
Channel A read strobe 2 sampled with first internal clock
rising edge.
Channel A read strobe 2 sampled with first internal clock
falling edge.
Channel A read strobe 2 sampled with second internal clock
rising edge.
Channel A read strobe 2 sampled with second internal clock
falling edge.
Channel A read strobe 3 sampled with first internal clock
rising edge.
Channel A read strobe 3 sampled with first internal clock
falling edge.
Channel A read strobe 3 sampled with second internal clock
rising edge.
AMD RS690 ASIC Family Register Reference Manual
2-235
Graphics Controller Configuration Registers
MCA_SAMPLE_FALL2_DQS3 (R)
15
Channel A read strobe 3 sampled with second internal clock
falling edge.
MCA_SAMPLE_RISE1_DQS4 (R)
16
0x0
Channel A read strobe 4 sampled with first internal clock
rising edge.
MCA_SAMPLE_FALL1_DQS4 (R)
17
0x0
Channel A read strobe 4 sampled with first internal clock
falling edge.
MCA_SAMPLE_RISE2_DQS4 (R)
18
0x0
Channel A read strobe 4 sampled with second internal clock
rising edge.
MCA_SAMPLE_FALL2_DQS4 (R)
19
0x0
Channel A read strobe 4 sampled with second internal clock
falling edge.
MCA_SAMPLE_RISE1_DQS5 (R)
20
0x0
Channel A read strobe 5 sampled with first internal clock
rising edge.
MCA_SAMPLE_FALL1_DQS5 (R)
21
0x0
Channel A read strobe 5 sampled with first internal clock
falling edge.
MCA_SAMPLE_RISE2_DQS5 (R)
22
0x0
Channel A read strobe 5 sampled with second internal clock
rising edge.
MCA_SAMPLE_FALL2_DQS5 (R)
23
0x0
Channel A read strobe 5 sampled with second internal clock
falling edge.
MCA_SAMPLE_RISE1_DQS6 (R)
24
0x0
Channel A read strobe 6 sampled with first internal clock
rising edge.
MCA_SAMPLE_FALL1_DQS6 (R)
25
0x0
Channel A read strobe 6 sampled with first internal clock
falling edge.
MCA_SAMPLE_RISE2_DQS6 (R)
26
0x0
Channel A read strobe 6 sampled with second internal clock
rising edge.
MCA_SAMPLE_FALL2_DQS6 (R)
27
0x0
Channel A read strobe 6 sampled with second internal clock
falling edge.
MCA_SAMPLE_RISE1_DQS7 (R)
28
0x0
Channel A read strobe 7 sampled with first internal clock
rising edge.
MCA_SAMPLE_FALL1_DQS7 (R)
29
0x0
Channel A read strobe 7 sampled with first internal clock
falling edge.
MCA_SAMPLE_RISE2_DQS7 (R)
30
0x0
Channel A read strobe 7 sampled with second internal clock
rising edge.
MCA_SAMPLE_FALL2_DQS7 (R)
31
0x0
Channel A read strobe 7 sampled with second internal clock
falling edge.
Memory controller A read strobe sampled by internal clock read back
AMD RS690 ASIC Family Register Reference Manual
2-236
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_MRS_PM - RW - 32 bits - NBMCIND:0xC8
Field Name
MCA_MODE_REG_PM
Bits
19:0
Default
0x0
MCA_INIT_CS_MRS_PM
23:20
0xf
MCA_DQ_TRANSFER_PM
27:24
0x4
MCA_REF_URGENCY_PM
31:28
0x6
Memory controller power management control MRS
Description
Value to be loaded in memory mode register in power
management mode.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
Channel A CS to be initialized in power management mode.
4'b0001=CS0/
4'b0010= CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel N read data transfer from strobe flops to core clock
flops in power management mode.n 0 = CL+0clock
1=CL+1clock
2=CL+2clock
3=CL+3clock
4=CL+4clock
Number of pending refreshes until refresh becomes urgent
in power management mode.
MCA_MEMORY_INIT_EMRS_PM - RW - 32 bits - NBMCIND:0xC9
Field Name
MCA_EXT_MODE_REG_PM
Bits
19:0
Default
0x10000
MCA_INIT_CS_EMRS_PM
23:20
0xf
MCA_INIT_DLL_PM
24
0x1
MCA_CKE_DYNAMIC_PM
25
0x0
MCA_TRST_DYNAMIC_PM
26
0x0
MCA_TRST_CK_PM
27
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Value to be loaded in memory extended mode register in
power management mode.
[14:0] = Address [14:0]
[15] = Reserved
[18:16] = Bank [2:0]
[19] = Reserved
Channel A CS to be initialized in power management mode.
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Enables execution of memory DLL reset mode register
command for power management mode initialization
sequence
Channel A CKE dynamic in power management
0=CKE high when enabled
1=CKE dynamic when enabled, high or low depending on
activity, active or precharge power down
Channel A all signals tristate when CKE low, except clock
running and ODT low, active and precharge power down in
power management mode
0=Nominal
1=Tristate
Channel A tristate clock when tristate dynamic CKE low in
power management mode
0=Nominal
1=Tristate
AMD RS690 ASIC Family Register Reference Manual
2-237
Graphics Controller Configuration Registers
MCA_TRST_SELFREF_PM
28
0x0
MCA_ODT_STALL_PM
29
0x0
MCA_2T_TIMING_PM
30
0x0
MCA_3T_TIMING_PM
31
0x0
Channel A enter self refresh when tristate dynamic CKE low
in power management mode
0=Do not do anything
1=Enter self refresh
Channel A ODT stall first write in power management mode
0=No stall
1=Stall
Channel A timing in power management mode.
0=1T timing
1=2T timing
Channel A timing in power management mode.
0=1T timing
1=3T timing
Memory controller power management control EMRS
MCA_MEMORY_INIT_EMRS2_PM - RW - 32 bits - NBMCIND:0xCA
Field Name
MCA_EXT2_MODE_REG_PM
Bits
19:0
Default
0x20000
MCA_INIT_CS_EMRS2_PM
23:20
0xf
MCA_ODTR_POSITION_PM
25:24
0x0
MCA_ODTW_POSITION_PM
27:26
0x0
RESERVED28
31:28
Memory controller power management control EMRS2
AMD RS690 ASIC Family Register Reference Manual
2-238
0x0
Description
Value to be loaded in memory extended mode register in
power management mode.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
Channel A CS to be initialized in power management mode.
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
Channel A ODT read position
When ODTX 0, read latency dependent
When ODTX 1, read command dependent
0=ODT start at RL-3 for ODTX 0, ODT start at RD for
ODTX1
1=ODT start at RL-2 for ODTX 0, ODT start at RD+1 for
ODTX 1
2/3=1 clock later
Channel A ODT write position
When ODTX 0, write latency dependent
When ODTX 1, write command dependent
0=ODT start at WL-3 for ODTX 0, ODT start at WR for
ODTX1
1=ODT start at WL-2 for ODTX 0, ODT start at WR+1 for
ODTX 1
2/3=1 clock later
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_MEMORY_INIT_EMRS3_PM - RW - 32 bits - NBMCIND:0xCB
Field Name
MCA_EXT3_MODE_REG_PM
Bits
19:0
Default
0x30000
MCA_INIT_CS_EMRS3_PM
23:20
0xf
RESERVED24
31:24
Memory controller power management control EMRS3
0x0
Description
Value to be loaded in memory extended mode register in
power management mode.
[14:0]=Address [14:0]
[15]=Reserved
[18:16]=Bank [2:0]
[19]=Reserved
Channel A CS to be initialized in power management mode.
4'b0001=CS0/
4'b0010=CS1/
4'b0100=CS2/
4'b1000=CS3/
MCA_TIMING_PARAMETERS_1_PM - RW - 32 bits - NBMCIND:0xCC
Field Name
MCA_RD_LAT_PM
Bits
3:0
Default
0x4
MCA_WR_LAT_PM
7:4
0x3
MCA_TRCDR_PM
11:8
0x8
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Memory CAS Latency
0=0 clock (not supported)
1=1 clock (not supported)
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory Write Latency
0=0 clock (not supported)
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Active to Read delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
AMD RS690 ASIC Family Register Reference Manual
2-239
Graphics Controller Configuration Registers
MCA_TRCDW_PM
15:12
Active to Write delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
MCA_TRP_PM
19:16
0x8
Precharge command period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
MCA_TRTP_PM
23:20
0x4
Internal Read to Precharge command delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
MCA_TWR_PM
27:24
0x8
Write recovery time
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
MCA_TRRD_PM
31:28
0x6
Active bank A to Active bank B command period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory controller A timing parameters in power management mode, set 1
AMD RS690 ASIC Family Register Reference Manual
2-240
0x8
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_TIMING_PARAMETERS_2_PM - RW - 32 bits - NBMCIND:0xCD
Field Name
MCA_TRAS_PM
Description
Active to Precharge command
0=0 clock
1= clock
2=2 clock
3=3 clock
…
29=29 clock
30=30 clock
31=31 clock
MCA_TRC_PM
15:8
0x20
Row Cycle time, Active to Active/Auto-Refresh command
period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
125=125 clock
126=126 clock
127=127 clock
MCA_TRFC_PM
23:16
0x28
Auto-Refresh to Active/Auto-Refresh command period
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
125=125 clock
126=126 clock
127=127 clock
MCA_TREFI_PM
31:24
0x10
1 memory refresh is performed every TREFI*64 MCLK
cycles.
Memory controller A timing parameters in power management mode, set 2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
7:0
Default
0x18
AMD RS690 ASIC Family Register Reference Manual
2-241
Graphics Controller Configuration Registers
MCA_TIMING_PARAMETERS_3_PM - RW - 32 bits - NBMCIND:0xCE
Field Name
MCA_TRTR_CS_PM
Bits
3:0
Default
0x1
MCA_TRTW_PM
7:4
0x2
MCA_TWTR_PM
11:8
0x4
MCA_TWTR_CS_PM
15:12
0x2
MCA_TWTW_CS_PM
19:16
0x1
MCA_TCCD_PM
23:20
0x2
AMD RS690 ASIC Family Register Reference Manual
2-242
Description
Read to Read command to different CS
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Read to Write bus turnaround
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Internal Write to Read command delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Write to Read command to different CS
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Write to Write command to different CS
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
CAS to CAS command delay
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_TCKE_PM
27:24
0x3
CKE minimum high and low pulse width
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
MCA_TXP_PM
31:28
0x3
Exit precharge power down to any valid command
0=0 clock
1=1 clock
2=2 clock
3=3 clock
4=4 clock
5=5 clock
6=6 clock
7=7 clock
Memory controller A timing parameters in power management mode, set 3
MCA_TIMING_PARAMETERS_4_PM - RW - 32 bits - NBMCIND:0xCF
Field Name
MCA_TXARDS_PM
Bits
3:0
Default
0x6
MCA_TAXPD_PM
7:4
0x8
MCA_TRPALL_PM
11:8
0x2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Exit active power down to read command
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
ODT power down exit latency
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
Precharge all for 8 bank memories
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
AMD RS690 ASIC Family Register Reference Manual
2-243
Graphics Controller Configuration Registers
MCA_TFAW_PM
15:12
0x2
Back to back activate rolling window
0=0 clock
1=1 clock
2=2 clock
3=3 clock
…
13=13 clock
14=14 clock
15=15 clock
MCA_TZQCL_PM
19:16
0x8
Impedance calibration long timing, can be merged with DLL
time, x64 clocks.
MCA_TZQCS_PM
23:20
0x4
Impedance calibration short timing, x16 clocks.
MCA_TZQCI_PM
27:24
0x1
Impedance calibration interval, x256 refresh cycles.
MCA_TMRD_PM
31:28
0x2
Mode register set command cycle time
0=0 clock
1=1 clock
...
15=15 clock
Memory controller A timing parameters in power management mode, set 4
MCA_IN_TIMING_DQS_3210_PM - RW - 32 bits - NBMCIND:0xD0
Field Name
MCA_DQS_ARRIVAL_0_PM
Bits
4:0
Default
0x6
RESERVED5
7:5
0x0
AMD RS690 ASIC Family Register Reference Manual
2-244
Description
Channel A byte 0 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_DQS_ARRIVAL_1_PM
12:8
0x6
RESERVED13
MCA_DQS_ARRIVAL_2_PM
15:13
20:16
0x0
0x6
RESERVED21
23:21
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Channel A byte 1 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
Channel A byte 2 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
AMD RS690 ASIC Family Register Reference Manual
2-245
Graphics Controller Configuration Registers
MCA_DQS_ARRIVAL_3_PM
28:24
0x6
Channel A byte 3 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
RESERVED29
31:29
0x0
Channel A input strobe gating timing in power management mode
MCA_IN_TIMING_DQS_7654_PM - RW - 32 bits - NBMCIND:0xD1
Field Name
MCA_DQS_ARRIVAL_4_PM
Bits
4:0
Default
0x6
RESERVED5
7:5
0x0
AMD RS690 ASIC Family Register Reference Manual
2-246
Description
Channel A byte 4 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_DQS_ARRIVAL_5_PM
12:8
0x6
RESERVED13
MCA_DQS_ARRIVAL_6_PM
15:13
20:16
0x0
0x6
RESERVED21
23:21
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Channel A byte 5 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
Channel A byte 6 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
AMD RS690 ASIC Family Register Reference Manual
2-247
Graphics Controller Configuration Registers
MCA_DQS_ARRIVAL_7_PM
28:24
0x6
RESERVED29
31:29
0x0
Channel A input strobe gating timing in power management mode
Channel A byte 7 input strobe reset removal edge in power
management mode
0=CL
1=CL+0.25
2=CL+0.50
3=CL+0.75
4=CL+1.00
5=CL+1.25
6=CL+1.50
7=CL+1.75
8=CL+2.00
9=CL+2.25
10=CL+2.50
11=CL+2.75
12=CL+3.00
13=CL+3.25
14=CL+3.50
15=CL+3.75
16=CL+4.00
17=CL+4.25
MCA_OUT_TIMING_DQ_PM - RW - 32 bits - NBMCIND:0xD2
Field Name
MCA_OUT_TIMING_DQ_B0_PM
Bits
3:0
Default
0x3
MCA_OUT_TIMING_DQ_B1_PM
7:4
0x3
MCA_OUT_TIMING_DQ_B2_PM
11:8
0x3
AMD RS690 ASIC Family Register Reference Manual
2-248
Description
Channel A byte 0 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 1 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 2 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_OUT_TIMING_DQ_B3_PM
Channel A byte 3 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
MCA_OUT_TIMING_DQ_B4_PM
19:16
0x3
Channel A byte 4 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
MCA_OUT_TIMING_DQ_B5_PM
23:20
0x3
Channel A byte 5 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
MCA_OUT_TIMING_DQ_B6_PM
27:24
0x3
Channel A byte 6 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
MCA_OUT_TIMING_DQ_B7_PM
31:28
0x3
Channel A byte 7 data and mask output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A output data and mask timing in power management mode
© 2007 Advanced Micro Devices, Inc.
Proprietary
15:12
0x3
AMD RS690 ASIC Family Register Reference Manual
2-249
Graphics Controller Configuration Registers
MCA_OUT_TIMING_DQS_PM - RW - 32 bits - NBMCIND:0xD3
Field Name
MCA_OUT_TIMING_DQS_0_PM
Bits
3:0
Default
0x4
MCA_OUT_TIMING_DQS_1_PM
7:4
0x4
MCA_OUT_TIMING_DQS_2_PM
11:8
0x4
MCA_OUT_TIMING_DQS_3_PM
15:12
0x4
MCA_OUT_TIMING_DQS_4_PM
19:16
0x4
AMD RS690 ASIC Family Register Reference Manual
2-250
Description
Channel A byte 0 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 1 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 2 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 3 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 4 strobe output timing in power
management mode
0 = -1 clock delay
1 = -3/4 clock delay
2 = -1/2 clock delay
3 = -1/4 clock delay
4 = 0 clock delay
5 = 1/4 clock delay
6 = 1/2 clock delay
7 = 3/4 clock delay
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_OUT_TIMING_DQS_5_PM
23:20
0x4
MCA_OUT_TIMING_DQS_6_PM
27:24
0x4
MCA_OUT_TIMING_DQS_7_PM
31:28
0x4
Channel A output strobe timing in power management mode
Channel A byte 5 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 6 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
Channel A byte 7 strobe output timing in power
management mode
0= -1 clock delay
1= -3/4 clock delay
2= -1/2 clock delay
3= -1/4 clock delay
4=0 clock delay
5=1/4 clock delay
6=1/2 clock delay
7=3/4 clock delay
MCA_MISCELLANEOUS - RW - 32 bits - NBMCIND:0xD4
Field Name
RESERVED
Channel A miscellaneous
Bits
31:0
Default
0x0
Description
MCA_MISCELLANEOUS_2 - RW - 32 bits - NBMCIND:0xD5
Field Name
RESERVED
Channel A miscellaneous 2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-251
Graphics Controller Configuration Registers
MCA_MX1X2X_DQ - RW - 32 bits - NBMCIND:0xD6
Field Name
MCA_MX1X2X_DQ_B0
Bits
1:0
Default
0x0
MCA_MX1X2X_DQ_B1
3:2
0x0
MCA_MX1X2X_DQ_B0_PM
17:16
0x0
MCA_MX1X2X_DQ_B1_PM
19:18
0x0
Channel A output data/mask phase range
AMD RS690 ASIC Family Register Reference Manual
2-252
Description
Channel A byte 0 output data/mask phase range
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
Channel A byte 1 output data/mask phase range
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
Channel A byte 0 output data/mask phase range in power
management mode
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
Channel A byte 1 output data/mask phase range in power
management mode
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_MX1X2X_DQS - RW - 32 bits - NBMCIND:0xD7
Field Name
MCA_MX1X2X_DQS_0
Bits
1:0
Default
0x0
MCA_MX1X2X_DQS_1
3:2
0x0
MCA_MX1X2X_DQS_0_PM
17:16
0x0
MCA_MX1X2X_DQS_1_PM
19:18
0x0
Channel A output strobe phase range
Description
Channel A byte 0 output strobe phase range
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
Channel A byte 1 output strobe phase range
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
Channel A byte 0 output strobe phase range in power
management mode
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
Channel A byte 1 output strobe phase range in power
management mode
0=Nominal, inverted 1x clock
1=Quarter clock delay, 1x clock sampled with 2x rising
edge clock and resampled with 2x falling edge clock
2=Half clock delay, 1x clock
3=Three quarters clock delay, inverted 1x clock sampled
with 2x rising edge clock and resampled with 2x falling
edge clock
MCA_DLL_MASTER_0 - RW - 32 bits - NBMCIND:0xD8
Field Name
MCA_DLL_ADJ_MSTR_0
Bits
7:0
Default
0x78
MCA_DLL_TSTCTRL_0
MCA_DLL_PWRDN_0
MCA_DLL_RESET_0
MCA_DLL_ADJ_MSTR_0_PM
13:8
14
15
23:16
0x0
0x0
0x0
0x78
RESERVED24
MCA_DLL_RESET_0_PM
Channel A byte 0 DLL master
30:24
31
0x0
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Channel A byte 0 DLL master.
160 (0xA0)
Channel A byte 0 DLL test/control select.
Channel A byte 0 DLL power down.
Channel A byte 0 DLL reset.
Channel A byte 0 DLL master in power management mode.
160 (0xA0)
Channel A byte 0 DLL reset in power management mode.
AMD RS690 ASIC Family Register Reference Manual
2-253
Graphics Controller Configuration Registers
MCA_DLL_MASTER_1 - RW - 32 bits - NBMCIND:0xD9
Field Name
MCA_DLL_ADJ_MSTR_1
Bits
7:0
Default
0x78
MCA_DLL_TSTCTRL_1
MCA_DLL_PWRDN_1
MCA_DLL_RESET_1
MCA_DLL_ADJ_MSTR_1_PM
13:8
14
15
23:16
0x0
0x0
0x0
0x78
RESERVED24
MCA_DLL_RESET_1_PM
Channel A byte 1 DLL master
30:24
31
0x0
0x0
Description
Channel A byte 1 DLL master.
160 (0xA0)
Channel A byte 1 DLL test/control select.
Channel A byte 1 DLL power down.
Channel A byte 1 DLL reset.
Channel A byte 1 DLL master in power management mode.
160 (0xA0)
Channel A byte 1 DLL reset in power management mode.
MCA_DLL_SLAVE_RD_0 - RW - 32 bits - NBMCIND:0xE0
Field Name
MCA_DLL_ADJ_DQSR_0
MCA_DLL_ADJ_DQSR_0_PM
Bits
7:0
Default
0x24
23:16
0x24
Channel A byte 0 input strobe phase
Description
Channel A byte 0 input strobe rising edge phase.
46 (0x2E) , half 2x , quarter 1x
126 (0x7E) , full 2x , half 1x
Channel A byte 0 input strobe rising edge phase in power
management mode.
46 (0x2E) , half 2x , quarter 1x
MCA_DLL_SLAVE_RD_1 - RW - 32 bits - NBMCIND:0xE1
Field Name
MCA_DLL_ADJ_DQSR_1
MCA_DLL_ADJ_DQSR_1_PM
Bits
7:0
Default
0x24
23:16
0x24
Channel A byte 1 input strobe phase
Description
Channel A byte 1 input strobe rising edge phase.
46 (0x2E) , half 2x , quarter 1x
126 (0x7E) , full 2x , half 1x
Channel A byte 1 input strobe rising edge phase in power
management mode.
46 (0x2E) , half 2x , quarter 1x
MCA_DLL_SLAVE_WR_0 - RW - 32 bits - NBMCIND:0xE8
Field Name
MCA_DLL_ADJ_DQ_B0
MCA_DLL_ADJ_DQ_B0_PM
Bits
7:0
Default
0x60
23:16
0x60
Channel A byte 0 output phase
AMD RS690 ASIC Family Register Reference Manual
2-254
Description
Channel A byte 0 data and mask output phase.
46 (0x2E) , half 2x , quarter 1x
126 (0x7E) , full 2x , half 1x
Channel A byte 0 data and mask output phase in power
management mode.
46 (0x2E) , half 2x , quarter 1x
126 (0x7E) , full 2x , half 1x
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_DLL_SLAVE_WR_1 - RW - 32 bits - NBMCIND:0xE9
Field Name
MCA_DLL_ADJ_DQ_B1
MCA_DLL_ADJ_DQ_B1_PM
Bits
7:0
Default
0x60
23:16
0x60
Channel A byte 1 output phase
Description
Channel A byte 1 data and mask output phase.
46 (0x2E) , half 2x , quarter 1x
126 (0x7E) , full 2x , half 1x
Channel A byte 1 data and mask output phase in power
management mode.
46 (0x2E) , half 2x , quarter 1x
126 (0x7E) , full 2x , half 1x
MCA_RESERVED_0 - RW - 32 bits - NBMCIND:0xF0
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_1 - RW - 32 bits - NBMCIND:0xF1
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_2 - RW - 32 bits - NBMCIND:0xF2
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_3 - RW - 32 bits - NBMCIND:0xF3
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_4 - RW - 32 bits - NBMCIND:0xF4
Field Name
RESERVED
Memory controller reserved for future use
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
2-255
Graphics Controller Configuration Registers
MCA_RESERVED_5 - RW - 32 bits - NBMCIND:0xF5
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_6 - RW - 32 bits - NBMCIND:0xF6
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_7 - RW - 32 bits - NBMCIND:0xF7
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_8 - RW - 32 bits - NBMCIND:0xF8
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_9 - RW - 32 bits - NBMCIND:0xF9
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_A - RW - 32 bits - NBMCIND:0xFA
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_B - RW - 32 bits - NBMCIND:0xFB
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-256
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCA_RESERVED_C - RW - 32 bits - NBMCIND:0xFC
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_D - RW - 32 bits - NBMCIND:0xFD
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_E - RW - 32 bits - NBMCIND:0xFE
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCA_RESERVED_F - RW - 32 bits - NBMCIND:0xFF
Field Name
RESERVED
Memory controller reserved for future use
Bits
31:0
Default
0x0
Description
MCCFG_FB_LOCATION - RW - 32 bits - NBMCIND:0x100
Field Name
MC_FB_START
Bits
15:0
Default
0x0
Description
Start of local frame buffer section in the internal address
space.
Note: Bits [5:0] of this field are hardwired to 0.
MC_FB_TOP
31:16
0x3f
Top of local frame buffer section in the internal address
space.
Note: Bits [5:0] of this field are hardwired to 1.
This register defines the base address and the top of memory of the reserved memory area that is allocated to the frame buffer
MCCFG_AGP_LOCATION - RW - 32 bits - NBMCIND:0x101
Field Name
MC_AGP_START
Bits
15:0
Default
0x0
MC_AGP_TOP
31:16
0x3f
Defines the location of AGP in the chip internal address space
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Start location of AGP aperture.
Note: Bits [5:0] of this field are hardwired to 0.
Top location within AGP aperture.
Note: Bits [5:0] of this field are hardwired to 1.
AMD RS690 ASIC Family Register Reference Manual
2-257
Graphics Controller Configuration Registers
MCCFG_AGP_BASE - RW - 32 bits - NBMCIND:0x102
Field Name
AGP_BASE_ADDR
Bits
31:0
Default
0x0
Description
When a request falls in the internal AGP aperture
(MC_AGP_LOCATION), a relative address is formed by
stripping off MC_AGP_START. AGP_BASE_ADDR is
added to the relative address to create the address in the
host system.
Note: Bits [21:0] of this field are hardwired to 0.
Specifies the base location of AGP space in the host system.
MCCFG_AGP_BASE_2 - RW - 32 bits - NBMCIND:0x103
Field Name
AGP_BASE_ADDR_2
Bits
3:0
Default
0x0
Description
Used to represents AGB Base address above 4 GBytes and
up to 32 GBytes.
This is used for handling 32 Gbytes AGP Base Address. The 4 bits field represents the 4 MSBs. It extends the AGP_BASE to 36
bits instead of 32 bits.
MC_INIT_MISC_LAT_TIMER - RW - 32 bits - NBMCIND:0x104
Field Name
MC_CPR_INIT_LAT
Bits
3:0
Default
0x0
Description
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of CPR requests.
MC_VF_INIT_LAT
7:4
0x0
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of VF requests.
MC_DISP0R_INIT_LAT
11:8
0x0
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of DISP0R requests.
MC_DISP1R_INIT_LAT
15:12
0x0
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of DISP0R requests.
MC_FIXED_INIT_LAT
19:16
0x0
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of FIXED requests.
MC_E2R_INIT_LAT
23:20
0x0
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of E2R requests.
SAME_PAGE_PRIO
27:24
0xf
Used by the memory controller efficiency arbitration. It stays
on the same page until the time exceeds the
same_page_priority number. Indicates the consecutive
page hits that are necessary to be able to hide page-misses
to another bank.
MC_GLOBW_INIT_LAT
31:28
0x0
Raises service priority after VALUE * 32 MCLKs to prevent
staleness of Global Write FIFO requests
For read clients such as CP, VF, DISP0, DISP1 and E2, there is a latency timer per client. For the other clients who compete in
the real-time arbiter, there is a single latency timer for the one winner. The latency timer is programmable for each client. When
a request is received, the latency timer starts. If the timer expires before the request wins arbitration, then the request is elevated
to a higher priority. The purpose here is to prevent requests from becoming stale simply because they are not efficient. The
display latency timer is intended to address its high bandwidth requirements for high performance display modes. Since the
display is a periodic requester, the latency timer can be set to a rate slightly above the average rate. The effect will be that the
memory controller will attempt to provide a somewhat regular data flow to the display client. The purpose is to prevent the
display from needing to set its URGENCY flag, which will reduce the overall performance of the memory controller. It is
anticipated that only very-high performance display modes will need this feature, so the register setting will normally be static.
Provisions should be made in SW to re-program this field for high-performance display modes.
AMD RS690 ASIC Family Register Reference Manual
2-258
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_INIT_GFX_LAT_TIMER - RW - 32 bits - NBMCIND:0x105
Field Name
MC_G3D0R_INIT_LAT
Bits
3:0
Default
0x0
Description
Raises the service priority after VALUE * 16 MCLKs to
prevent staleness of G3D0R requests.
MC_G3D1R_INIT_LAT
7:4
0x0
Raises the service priority after VALUE * 16 MCLKs to
prevent staleness of G3D1R requests.
MC_G3D2R_INIT_LAT
11:8
0x0
Raises the service priority after VALUE * 16 MCLKs to
prevent staleness of G3D2R requests.
MC_G3D3R_INIT_LAT
15:12
0x0
Raises the service priority after VALUE * 16 MCLKs to
prevent staleness of G3D3R requests.
MC_TX0R_INIT_LAT
19:16
0x0
Raises the service priority after VALUE * 16 MCLKs to
prevent staleness of TX0R requests.
MC_TX1R_INIT_LAT
23:20
0x0
Raises the service priority after VALUE * 16 MCLKs to
prevent staleness of TX1R requests.
MC_GLOBR_INIT_LAT
27:24
0x0
Raises the service priority after VALUE * 32 MCLKs to
prevent staleness of Global Read FIFO requests.
MC_GLOBW_FULL_LAT
31:28
0xf
Raises the service priority after VALUE * 16 MCLKs to
delay urgency requests for Global Write FIFO requests.
For the graphics 3D clients, there is a latency timer per client. The latency timer period is programmable for each client. When a
request is received, the latency timer starts. If the timer expires before the request wins arbitration, then the request is elevated
to a higher priority. Then intent is to prevent requests from becoming stale simply because they are not efficient.
MC_INIT_WR_LAT_TIMER - RW - 32 bits - NBMCIND:0x106
Field Name
MC_G3D0W_INIT_LAT
Description
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when g3d0w interface fifo full.
MC_G3D1W_INIT_LAT
7:4
0xf
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when g3d1w interface fifo full.
MC_G3D2W_INIT_LAT
11:8
0xf
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when g3d2w interface fifo full.
MC_G3D3W_INIT_LAT
15:12
0xf
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when g3d3w interface fifo full.
MC_IDCTW_INIT_LAT
19:16
0x2
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when idctw interface fifo full.
MC_HDPW_INIT_LAT
23:20
0x2
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when hdpw interface fifo full.
MC_VIPW_INIT_LAT
27:24
0x2
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when vipw interface fifo full.
MC_CPW_INIT_LAT
31:28
0x2
Raises the service priority after VALUE * 16 MCLKS. If
zero, urgent when cpw interface fifo full.
For all the write clients, there is a latency timer per client. The latency timer period is programmable for each client. When the
interface fifo is full, the latency timer starts. If the timer expires before the request wins the first level arbitration, then the request
is elevated to a higher priority. Then intent is to prevent the write requests become urgent all the time because the fifo is full.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
3:0
Default
0xf
AMD RS690 ASIC Family Register Reference Manual
2-259
Graphics Controller Configuration Registers
MC_ARB_CNTL - RW - 32 bits - NBMCIND:0x107
Bits
0
Default
0x0
DISP0R_FIFO_LEVEL
1
0x1
DISP1R_FIFO_LEVEL
2
0x1
OV0R_FIFO_LEVEL
3
0x0
CPR_FIFO_LEVEL
4
0x0
VFR_FIFO_LEVEL
5
0x0
E2R_FIFO_LEVEL
6
0x0
ONE_PAGE
Field Name
AMD RS690 ASIC Family Register Reference Manual
2-260
Description
If 1, then it is One Page mode. In the first level graphics
read arbiter, it uses one page information for efficiency
generation. This is the R300 architecture.
If 0, then it is Four Page mode. It uses four pages instead of
one in order to compute the memory efficiency info, one
page per bank queue. In theory, this mode should improve
memory efficiency and hence the graphics performance.
0=Four Pages mode in First Level GFX Arbiter
1=One Page mode in First Level GFX Arbiter, R300 mode
In R300, it relies on the priority signal from the display unit,
or the timesout counter, to change the display request to a
high priority request. But, once the display unit asserts
priority, it will stay in priority mode for a long time, which will
hurt the memory efficiency. However, using the timesout
counter by itself cannot fulfill the bandwidth requirement
when in 1600x1200 @85Hz mode. This setting is added
which may help to fulfill the display bw requirements without
using priority signal.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
Similar to DISP0R_FIFO_LEVEL.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
All other FIFO_LEVEL settings are added for
completeness.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
All other FIFO_LEVEL settings are added for
completeness.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
All other FIFO_LEVEL settings are added for
completeness.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
All other FIFO_LEVEL settings are added for
completeness.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
IDCTR_FIFO_LEVEL
7
0x0
DIS_DISPACK
8
0x1
Miscellaneous controls for gfx arbiter
All other FIFO_LEVEL settings are added for
completeness.
0=Disable asserting urg request when interface fifo is
almost full
1=Enable asserting urg request when interface fifo is
almost full
0=Enable the Display Ack Protocol, R300 mode
1=Disable the Display Ack Protocol for improving display
BW
MC_DEBUG_CNTL - RW - 32 bits - NBMCIND:0x108
Field Name
MC_DEBUG_1_0
MC_DEBUG_3_2
Bits
1:0
3:2
Default
0x3
0x0
MC_DEBUG_7_4
7:4
0x0
MC_DEBUG_11_8
11:8
0x2
MC_DEBUG_15_12
15:12
MC_DEBUG_19_16
19:16
MC_DEBUG_23_20
23:20
MC_DEBUG_27_24
27:24
MC_DEBUG_31_28
31:28
Debug Register, added for performance tuning
0x0
0x3
0x0
0xf
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
reserved
Bit [0]:
If 0, masking 8 cycles for bank access in write arbiter.
If 1, masking 9 cycles for bank access in write arbiter.
Bit [1]:
If 0, masking 8 cycles for bank access in 2nd level arbiter,
If 1, masking 9 cycles for bank access in 2nd level arbiter.
Reserved for future use.
0=Masking bank access in 1st level wr, 2nd level arbiter
for 8 cycles
1=Masking bank access in 1st level wr for 8 cycles, 2nd
level arb for 9 cycles
2=Masking bank access in 1st level wr for 9 cycles, 2nd
level arb for 8 cycles
3=Masking bank access in 1st level wr, 2nd level arbiter
for 9 cycles
Bit [0]:
Write Flush Mode. In write flush mode, it will force 16 writes
to be issued back to back with no interruption.
0=Disabled
1=Enabled write flush mode
Bit [1]:
Disable Same Page Priority Greater than N mode for write.
In this mode, the write arbitration logic will ignore the
SAME_PAGE_PRIO.
Bit [2]:
Masking the bank for 4 cycles instead of 8/9 in second level
arbiter.
Bit [3]:
Reserved for future use.
Bit [0]:
If 1, enable sideport and UMA first and second arbiter stage
to use fix order arbitration.
If 0, round robbin arbitration is used.
Bit [1]:
If 1, enable sideport and UMA second arbiter stage to use
efficiency based arbitration.
If 0, round robbin arbitration is used.
Reserved
Reserved
Reserved
Reserved
Reserved
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
MC_BIST_CNTL0 - RW - 32 bits - NBMCIND:0x111
Field Name
BIST_DONE (R)
Bits
0
Default
0x0
BIST_MISMATCH_CYCLE (R)
3:1
0x0
BIST_RUN
4
0x0
BIST_RESET_N
5
0x0
7:6
0x0
BIST_MISMATCH_STATUS
Description
Set to 0 when BIST_RUN or BIST_RESET_N is 0.
Set to 1 when the bist read/write is done either normally or
due to mismatch
Records the cycle which caused the mismatch.
3'b000: cycle1 of burst1; 3'b100: cycle1 of burst2;
3'b001: cycle2 of burst1; 3'b1001 cycle2 of burst2;
3'b010: cycle3 of burst1; 3'b110: cycle3 of burst2;
3'b011: cycle4 of burst1; 3'b111: cycle4 of burst2;
0=Disable
1=Enable
0=Resets mcbist, but does not disturb read-only mcbist
values.
1=Active
0=Data (64 bit) mismatch info. Info would be ORed with
subsequent reads
1=Keeps first mismatch data info as sticky
2=Address 32'd0,addr[26:0],5'd0 mismatch info. is
updated at every mismatch
3=Keep first address info sticky
First control register of MCBIST
MC_BIST_CNTL1 - RW - 32 bits - NBMCIND:0x112
Field Name
BIST_MISMATCH_STKY (R)
Bits
0
Default
0x0
BIST_RDWR_EN
2:1
0x0
BIST_SADDR_SEL
4:3
0x0
BIST_CYC
7:5
0x0
BIST_DATA_CMP
8
0x0
BIST_MISMATCH_STOP
9
0x0
BIST_ADDR_BND
10
0x0
AMD RS690 ASIC Family Register Reference Manual
2-262
Description
0=When BIST_RUN is 0
1=Read mismatch
0=No op
1=Activate write client only
2=Activate read client only
3=Activate both read & write clients
0=No op
1=Set start write-address
2=Set start read-address
3=Set both start read and start write addresses
0=No op
1=Run for 2 read (and/or write) bursts
2=Run for 4 read (and/or write) bursts
3=Reserved
4=Reserved
5=Reserved
6=Run for 32 read (and/or write) bursts
7=Run continuously until there is a mismatch-stop, or
end-address stop
0=Read data is compared against expected data
1=Read data is not compared. No question of
mismatch
0=Do not stop if read mismatch
1=Stop if read mismatch
0=Use read address for end-address stop
1=Use write address for end-address stop
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
BIST_ADDR_LOOP
11
0x0
0=Stop based on BIST_CYC
1=Keep looping read (and/or write) operations between
start and end addresses
BIST_WADDR_GEN
14:12
0x0
0=wr_addr[26:0] = wr_addr[26:0] + 1
1=wr_addr[26:0] = wr_addr[26:0] - 1
2=wr_addr[26:0] = wr_addr[26:0] + 4
3=wr_addr[26:0] = wr_addr[26:0] - 4
4=wr_addr[26:13] = wr_addr[26:13] + 1
5=wr_addr[26:13] = wr_addr[26:13] - 1
6=wr_addr[26:19] = wr_addr[26:19] + 1
7=No change in write address
BIST_RADDR_GEN
17:15
0x0
0=rd_addr[26:0] = rd_addr[26:0] + 1
1=rd_addr[26:0] = rd_addr[26:0] - 1
2=rd_addr[26:0] = rd_addr[26:0] + 4
3=rd_addr[26:0] = rd_addr[26:0] - 4
4=rd_addr[26:13] = rd_addr[26:13] + 1
5=rd_addr[26:13] = rd_addr[26:13] - 1
6=rd_addr[26:19] = rd_addr[26:19] + 1
7=No change in read address
BIST_END_ADDR
31:18
0x0
read/write upper address (addr[31:18])
Second control register of MCBIST. The bit field [31:5] of this register is also used as starting address (BIST_START_ADDR).
Refer to bit field BIST_SADDR_SEL for details.
MC_BIST_MISMATCH_L - RW - 32 bits - NBMCIND:0x113
Field Name
Bits
BIST_MISMATCH_L (R)
31:0
Lower 32 bits of the 64 bits mcbist read mismatch info
Default
0x0
Description
Refer to BIST_MISMATCH_STATUS for setting.
MC_BIST_MISMATCH_H - RW - 32 bits - NBMCIND:0x114
Field Name
Bits
BIST_MISMATCH_H (R)
31:0
Upper 32 bits of the 64 bits mcbist read mismatch info
Default
0x0
Description
Refer to BIST_MISMATCH_STATUS for setting.
MC_BIST_PATTERN0L - RW - 32 bits - NBMCIND:0x115
Field Name
Bits
Default
Description
BIST_PATTERN0L
31:0
0x0
32 bit data pattern. Write only.
Lower half of DW0 (double word 0) of data pattern. MCBIST uses 8 user defined DWs to generate two consecutive data bursts each of 4x64 bits.burst_one[255:0] = MC_BIST_PATTERN3H, MC_BIST_PATTERN3L, MC_BIST_PATTERN2H,
MC_BIST_PATTERN2L, MC_BIST_PATTERN1H, MC_BIST_PATTERN1L, MC_BIST_PATTERN0H, MC_BIST_PATTERN0L.
Similarly, burst-two is defined by other 8 registers. These registers are per mcbist engine based.
MC_BIST_PATTERN0H - RW - 32 bits - NBMCIND:0x116
Field Name
BIST_PATTERN0H
Refer to MC_BIST_PATTERN0L
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
AMD RS690 ASIC Family Register Reference Manual
2-263
Graphics Controller Configuration Registers
MC_BIST_PATTERN1L - RW - 32 bits - NBMCIND:0x117
Field Name
BIST_PATTERN1L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN1H - RW - 32 bits - NBMCIND:0x118
Field Name
BIST_PATTERN1H
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN2L - RW - 32 bits - NBMCIND:0x119
Field Name
BIST_PATTERN2L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN2H - RW - 32 bits - NBMCIND:0x11A
Field Name
BIST_PATTERN2H
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN3L - RW - 32 bits - NBMCIND:0x11B
Field Name
BIST_PATTERN3L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN3H - RW - 32 bits - NBMCIND:0x11C
Field Name
BIST_PATTERN3H
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN4L - RW - 32 bits - NBMCIND:0x11D
Field Name
BIST_PATTERN4L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-264
Description
32 bit data pattern. Write only.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_BIST_PATTERN4H - RW - 32 bits - NBMCIND:0x11E
Field Name
BIST_PATTERN4H
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN5L - RW - 32 bits - NBMCIND:0x11F
Field Name
BIST_PATTERN5L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN5H - RW - 32 bits - NBMCIND:0x120
Field Name
BIST_PATTERN5H
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN6L - RW - 32 bits - NBMCIND:0x121
Field Name
BIST_PATTERN6L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN6H - RW - 32 bits - NBMCIND:0x122
Field Name
BIST_PATTERN6H
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN7L - RW - 32 bits - NBMCIND:0x123
Field Name
BIST_PATTERN7L
Refer to MC_BIST_PATTERN0L
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
MC_BIST_PATTERN7H - RW - 32 bits - NBMCIND:0x124
Field Name
BIST_PATTERN7H
Refer to MC_BIST_PATTERN0L
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
32 bit data pattern. Write only.
AMD RS690 ASIC Family Register Reference Manual
2-265
Graphics Controller Configuration Registers
2.9
System GART Control Registers
RCRB_Enhanced_Capability_Header - RW - 32 bits - MMGartReg:0x0
Field Name
PCIE_Extended_CapID (R)
Extended_CapVer (R)
Next_CapOff (R)
RCRB Feature and Capabilities Register
Bits
15:0
19:16
31:20
Default
0xffff
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-266
Description
All Fs indicate the capability list has nothing.
The current Capability version is 3'b1.
All 0s indicate there is no next enhanced capability list.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
2.10 Display Clock Control
Clock control registers
CLOCK_CNTL_INDEX - RW - 32 bits - [IOReg,MMReg:0x8]
PLL_ADDR
PLL_WR_EN
Field Name
PPLL_DIV_SEL
Bits
6:0
7
Default
0x0
0x0
9:8
0x0
Clock generation block register index control.
Description
Register address.
0=Disable writes to CLOCK_CNTL_DATA
1=Enable writing to CLOCK_CNTL_DATA
0=PPLL_DIV0
1=PPLL_DIV1
2=PPLL_DIV2
3=PPLL_DIV3
CLOCK_CNTL_DATA - RW - 32 bits - [IOReg,MMReg:0xC]
Field Name
PLL_DATA
Clock generation block register data
Bits
31:0
Default
0x0
Description
Register value.
PLL_TEST_CNTL - RW - 32 bits - CLKIND:0x21
Field Name
TST_SRC_SEL
TST_REF_SEL
REF_TEST_COUNT
TST_RESET
TEST_COUNT (R)
PLL frequency measurement CNTL.
Bits
3:0
7:4
14:8
15
31:17
Default
0x0
0x0
0x0
0x0
0x0
Description
Source clock to be measured.
Clock used as a frequency reference.
Run TST_REF_SEL by number of cycles.
Reset frequency counter.
Frequency output value.
SPLL_FUNC_CNTL - RW - 32 bits - CLKIND:0x0
Bits
0
Default
0x1
1
0x0
SPLL_REF_DIV
SPLL_FB_DIV
SPLL_PULSEEN
4:2
12:5
13
0x1
0x46
0x0
SPLL_PULSENUM
SPLL_SW_HILEN
SPLL_SW_LOLEN
SPLL_DIVEN
SPLL_BYPASS_EN
15:14
19:16
23:20
24
25
0x0
0x0
0x0
0x1
0x1
SPLL_RESET
Field Name
SPLL_SLEEP
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Run
1=Reset
0=Power Up
1=Power Down
SPLL reference divider value.
SPLL feedback divider value.
0=Don't pulse clock
1=Send the number of pulses indicated by PULSENUM
Number of pulses required by SPLL.
Post divider value for SPLL (high pulse section).
Post divider value for SPLL (low pulse section).
1=Enable PLL CLKOUT divider
1=Enable Bypass Clockout
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SPLL_CHG_STATUS (R)
29
0x0
SPLL_CTLREQ
30
0x0
SPLL_CTLACK (R)
31
0x0
SPLL Control register
1=Previous write/change to SPLL_FUNC_CNTL register
has been completed. SW should not issue another write
to this register until this bit is asserted
1=For debugging purposes. When SW_DIR_CONTROL
is set, asserting this bit will trigger an update of the PLL
clock output mux control. Before writing to this bit,
HILEN/LOLEN/PULSEEN/PULSENUM should already
contain the new set of value
1=For debugging purposes. When SW_DIR_CONTROL
is set, this value replicates the value of the CTLREQ once
the command has been received and it is safe to send
another request
SPLL_BYPASSCLK_SEL - RW - 32 bits - CLKIND:0x1
Field Name
SPLL_CLKOUT_SEL
Bits
5:0
Default
0x6
Description
1=BCLK
2=MCLK
4=DISP CLK
8=AUXSIN
32=INV BCLK
SPLL_CNTL_MODE - RW - 32 bits - CLKIND:0x2
Field Name
SPLL_SW_DIR_CONTROL
Bits
0
Default
0x1
Description
1=SW controls the PLL directly. SW will make sure the
way they program SPLL_FUNC_CNTL register follows
the PLL's requested protocol
SPLL_CLK_SEL - RW - 32 bits - CLKIND:0x3
Field Name
SPLL_REFCLK_SRC_SEL
SPLL_TEST
SPLL_FASTEN
SPLL_ENSAT
Bits
0
Default
0x0
1
2
3
0x0
0x1
0x1
AMD RS690 ASIC Family Register Reference Manual
2-268
Description
0=Ref clock from GPIO
1=Ref clock from XTALIN
1=Enable SPLL test mode
1=Enable SPLL fast lock
1=Enable saturation behavior
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MPLL_FUNC_CNTL - RW - 32 bits - CLKIND:0x4
Bits
0
Default
0x1
1
0x0
MPLL_REF_DIV
MPLL_FB_DIV
MPLL_PULSEEN
4:2
12:5
13
0x1
0x6f
0x0
MPLL_PULSENUM
MPLL_SW_HILEN
MPLL_SW_LOLEN
MPLL_DIVEN
MPLL_BYPASS_EN
MPLL_MCLK_SEL
MPLL_CHG_STATUS (R)
15:14
19:16
23:20
24
25
26
29
0x0
0x0
0x0
0x0
0x1
0x0
0x0
MPLL_CTLREQ
30
0x0
MPLL_CTLACK (R)
31
0x0
MPLL_RESET
Field Name
MPLL_SLEEP
Description
0=Run
1=Reset
0=Power Up
1=Power Down
MPLL reference divider value.
MPLL feedback divider value.
0=Don't pulse clock
1=Send the number of pulses indicated by PULSENUM
Not used.
Not used.
Not used.
1=Enable PLL CLKOUT divider
1=Enable Bypass mode
1=Use MPLL output as mclk
1=Previous write/change to MPLL_FUNC_CNTL register
has been completed. SW should not issue another write
to this register until this bit is asserted
1=For debugging purposes. When SW_DIR_CONTROL
is set, asserting this bit will trigger an update of the PLL
clock output mux control. Before writing to this bit,
HILEN/LOLEN/PULSEEN/PULSENUM should already
contain the new set of value
1=For debugging purposes. When SW_DIR_CONTROL
is set, this value replicates the value of the CTLREQ once
the command has been received and it is safe to send
another request
MPLL Control register
MPLL_BYPASSCLK_SEL - RW - 32 bits - CLKIND:0x5
Field Name
MPLL_CLKOUT_SEL
Bits
5:0
Default
0x6
1=BCLK
2=SCLK
4=DISP CLK
8=TEST YCLK
32=INV BCLK
Description
MPLL_CNTL_MODE - RW - 32 bits - CLKIND:0x6
Field Name
MPLL_SW_DIR_CONTROL
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
1
Default
0x0
Description
1=SW controls the PLL directly. SW will make sure the
way they program MPLL_FUNC_CNTL register follows
the PLL's requested protocol
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
MPLL_CLK_SEL - RW - 32 bits - CLKIND:0x7
Field Name
MPLL_REFCLK_SRC_SEL
MPLL_TEST
MPLL_FASTEN
MPLL_ENSAT
Bits
0
Default
0x0
1
2
3
0x0
0x1
0x1
Description
0=Ref clock from GPIO
1=Ref clock from XTALIN
1=Enable MPLL test mode
1=Enable MPLL fast lock
1=Enable saturation behavior
GENERAL_PWRMGT - RW - 32 bits - CLKIND:0x8
Field Name
GLOBAL_PWRMGT_EN
Bits
0
Default
0x0
MOBILE_SU
2
0x0
SU_SUSTAIN_DISABLE
3
0x0
Description
0=Dynamic power management off
1=Dynamic power management on
0=Regular
1=Optimize power consumption in Suspend mode for
mobile
0=Sustain suspend until PLL lockup
1=Disable
SCLK_PWRMGT_CNTL - RW - 32 bits - CLKIND:0x9
Field Name
SCLK_PWRMGT_OFF
Bits
0
Default
0x0
SCLK_TURNOFF
1
0x0
SPLL_TURNOFF
2
0x0
SPARE
SU_SCLK_USE_BCLK
3
4
0x0
0x0
ACCESS_REGS_IN_SUSPEND
5
0x0
AMD RS690 ASIC Family Register Reference Manual
2-270
Description
0=SCLK power management on
1=SCLK power management off
1=Turn off SCLK, SW direct control, override HW pwrmgt
control
1=Power down SPLL, SW direct control, override HW
pwrmgt control
0=Use slower SCLK under suspend mode
1=Use BCLK as SCLK under suspend mode
0=Disable
1=Force all SCLK branches to allow accessing any
registers in suspend mode
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MCLK_PWRMGT_CNTL - RW - 32 bits - CLKIND:0xA
Field Name
MPLL_PWRMGT_OFF
YCLK_TURNOFF
MPLL_TURNOFF
Bits
0
1
2
Default
0x0
0x0
0x0
SU_MCLK_USE_BCLK
3
0x0
DLL_READY
4
0x0
MC_BUSY (R)
5
0x0
MC_SWITCH
6
0x0
MC_INT_CNTL
7
0x1
MRDCKA_SLEEP
8
0x0
MRDCKB_SLEEP
9
0x0
MRDCKC_SLEEP
10
0x0
MRDCKD_SLEEP
11
0x0
MRDCKA_RESET
12
0x1
MRDCKB_RESET
13
0x1
MRDCKC_RESET
14
0x1
MRDCKD_RESET
15
0x1
DLL_READY_READ (R)
16
0x0
Description
0=M domain clock power management off
0=Turn off YCLK
0=Enable M domain PLL to be turned off at power state
D3
0=Shut down MCLK during suspend mode
1=Use BCLK as SCLK under suspend mode
0=DLL is not ready
1=DLL is ready
0=MC is idle
1=MC is not idle
0=Source of memory clock is not changed
1=Source of memory clock is changed
0=SW overwrite
1=HW control
0=Enable Channel A DLL
1=PowerDown Channel A DLL
0=Enable Channel B DLL
1=PowerDown Channel B DLL
0=Enable Channel C DLL
1=PowerDown Channel C DLL
0=Enable Channel D DLL
1=PowerDown Channel D DLL
0=Enable Channel A DLL
1=Reset Channel A DLL
0=Enable Channel B DLL
1=Reset Channel B DLL
0=Enable Channel C DLL
1=Reset Channel C DLL
0=Enable Channel D DLL
1=Reset Channel D DLL
0=DLL is not ready
1=DLL is ready
DYN_PWRMGT_SCLK_CNTL - RW - 32 bits - CLKIND:0xB
Field Name
ENGINE_DYNCLK_MODE
Bits
0
Default
0x0
SCLK_DYN_START_CNTL
1
0x1
PROG_DELAY_OFFSET
9:2
0x0
PROG_SHUTOFF_REVERT
10
0x0
14:11
19:15
0x5
0x5
20
21
0x0
0x0
DYN_STOP_LAT
ACTIVE_ENABLE_LAT
STATIC_SCREEN_EN
CLIENT_SELECT_POWER_EN
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Treat engine as one single block
1=Provide clock for each engine block separately
0=SCLK starts 4 clocks after BUSY active
1=SCLK starts 1 clock after BUSY active
This field is used to increase latency to turn on clocks/turn
off clocks. The clock turnon/turnoff latency equals to
(PROG_DELAY_OFFSET+1)*<client>_PROG_DELAY_VA
LUE
1=Use revert value of PROG_DELAY_VALUE as shutoff
counter value, only used when the corresponding client's
PROG_SHUTOFF is set
Delay between idle state is detected until sclk is turned off
Delay between clock_enable changes to cg_rbbm_active
changes
1=Enable Static Screen Mode
1=Enable Client Based Power Request
AMD RS690 ASIC Family Register Reference Manual
2-271
Graphics Controller Configuration Registers
LOWER_POWER_STATE (R)
STATIC_SCREEN_STATE (R)
SW_NORMAL_POWER
CLIENT_BUSY_GAP_LAT
22
23
24
29:25
0x0
0x0
0x0
0x8
1=CG is in Lower Power State based on client's request
1=CG is in static screen state
1=Force to go back to normal power state
0=Number of idle cycles allowed during 2 consecutive
busy cycles
Dynamic clock gating control
DYN_PWRMGT_SCLK_LENGTH - RW - 32 bits - CLKIND:0xC
Field Name
NORMAL_POWER_SCLK_HILEN
NORMAL_POWER_SCLK_LOLEN
REDUCED_POWER_SCLK_HILEN
REDUCED_POWER_SCLK_LOLEN
POWER_D1_SCLK_HILEN
POWER_D1_SCLK_LOLEN
STATIC_SCREEN_HILEN
STATIC_SCREEN_LOLEN
Frequency control for different power stage
Bits
3:0
7:4
11:8
15:12
19:16
23:20
27:24
31:28
Default
0x0
0x0
0x1
0x1
0x2
0x2
0x4
0x4
Description
Post divider value for full power mode(high pulse)
Post divider value for full power mode(low pulse)
Post divider value for reduced power mode(high pulse)
Post divider value for reduced power mode(low pulse)
Post divider value for D1 mode(high pulse)
Post divider value for D1 mode(low pulse)
Post divider value for static screen mode(high pulse)
Post divider value for static screen mode(low pulse)
DYN_SCLK_PWMEN_PIPE - RW - 32 bits - CLKIND:0xD
Field Name
PIPE_2D_MASK
PIPE_3D_MASK
PIPE_3D_NOT_AUTO
Bits
3:0
7:4
8
Default
0x1
0xf
0x1
Dynamic clock gating pipe control
Description
Mask the pipe which is used by 2D
Mask the pipe which is used by 3D
0=Auto disable unused pipes' clk
1=Enable pipes' clk based on PIPE_3D_MASK field
DYN_SCLK_VOL_CNTL - RW - 32 bits - CLKIND:0xE
Field Name
IO_CG_VOLTAGE_DROP
Bits
0
Default
0x0
VOLTAGE_DROP_SYNC
2
0x0
VOLTAGE_DELAY_SEL
22:3
0x0
Description
0=Disable dynamic core voltage drop
1=Enable dynamic core voltage drop
0=Disable synchronization of reduced speed SCLK and
core voltage drop
1=Enable synchronization
Delay (in sclk cycle) between voltage goes to normal until
sclk speed goes back to normal.
Static screen mode voltage control
CP_DYN_CNTL - RW - 32 bits - CLKIND:0xF
Field Name
CP_FORCEON
Bits
0
Default
0x1
CP_MAX_DYN_STOP_LAT
1
0x1
CP_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
CP_PROG_SHUTOFF
CP_PROG_DELAY_VALUE
AMD RS690 ASIC Family Register Reference Manual
2-272
Description
0=Dynamic control CP sclk branch
1=Disable dynamic control of CP sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=CP branch is off
1=CP branch is on
1=CP branch shutoff with PROG_DELAY_VALUE delay
Delay CP clock on/off by number of cycles
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CP_LOWER_POWER_IDLE
19:12
0xff
CP_LOWER_POWER_IGNORE
CP_NORMAL_POWER_IGNORE
SPARE
CP_NORMAL_POWER_BUSY
20
21
23:22
31:24
0x1
0x1
0x0
0xf
CP dynamic clock gating control
Cnt CP idle for number of cycles before dropping the power
level. Only used when CP_LOWER_POWER_IGNORE is
set to 0.
1=CP not vote for going to lower power state
1=CP not vote for going back to normal power state
Cnt CP busy for number of cycles before raising the power
level. Only used when CP_NORMAL_POWER_IGNORE is
set to 0.
HDP_DYN_CNTL - RW - 32 bits - CLKIND:0x10
Field Name
HDP_FORCEON
Bits
0
Default
0x1
HDP_MAX_DYN_STOP_LAT
1
0x1
HDP_CLOCK_STATUS (R)
2
0x0
HDP_PROG_SHUTOFF
3
0x0
HDP_PROG_DELAY_VALUE
HDP_LOWER_POWER_IDLE
11:4
19:12
0x1
0xff
HDP_LOWER_POWER_IGNORE
HDP_NORMAL_POWER_IGNORE
SPARE
HDP_NORMAL_POWER_BUSY
20
21
23:22
31:24
0x1
0x1
0x0
0xf
HDP dynamic clock gating control
Description
0=Dynamic control HDP sclk branch
1=Disable dynamic control of HDP sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=HDP branch is off
1=HDP branch is on
1=HDP branch shutoff with PROG_DELAY_VALUE delay
Delay HDP clock on/off by number of cycles
Cnt HDP idle for number of cycles before dropping the
power level. Only used when
HDP_LOWER_POWER_IGNORE is set to 0
1=HDP not vote for going to lower power state
1=HDP not vote for going back to normal power state
Cnt HDP busy for number of cycles before raising the
power level. Only used when
HDP_NORMAL_POWER_IGNORE is set to 0
E2_DYN_CNTL - RW - 32 bits - CLKIND:0x11
Field Name
E2_FORCEON
Bits
0
Default
0x1
E2_MAX_DYN_STOP_LAT
1
0x1
E2_CLOCK_STATUS (R)
2
0x0
E2_PROG_SHUTOFF
E2_PROG_DELAY_VALUE
E2_LOWER_POWER_IDLE
3
11:4
19:12
0x0
0x1
0xff
E2_LOWER_POWER_IGNORE
E2_NORMAL_POWER_IGNORE
SPARE
E2_NORMAL_POWER_BUSY
20
21
23:22
31:24
0x1
0x1
0x0
0xf
E2 dynamic clock gating control
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Dynamic control E2 sclk branch
1=Disable dynamic control of E2 sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=E2 branch is off
1=E2 branch is on
1=E2 branch shutoff with PROG_DELAY_VALUE delay
Delay E2 clock on/off by number of cycles.
Cnt E2 idle for number of cycles before dropping the power
level. Only used when E2_LOWER_POWER_IGNORE is
set to 0
1=E2 not vote for going to lower power state
1=E2 not vote for going back to normal power state
Cnt E2 busy for number of cycles before raising the power
level. Only used when E2_NORMAL_POWER_IGNORE is
set to 0.
AMD RS690 ASIC Family Register Reference Manual
2-273
Graphics Controller Configuration Registers
VIP_DYN_CNTL - RW - 32 bits - CLKIND:0x14
Field Name
VIP_FORCEON
Bits
0
Default
0x1
VIP_MAX_DYN_STOP_LAT
1
0x1
VIP_CLOCK_STATUS (R)
2
0x0
VIP_PROG_SHUTOFF
VIP_PROG_DELAY_VALUE
VIP_LOWER_POWER_IDLE
3
11:4
19:12
0x0
0x1
0xff
VIP_LOWER_POWER_IGNORE
VIP_NORMAL_POWER_IGNORE
SPARE
VIP_NORMAL_POWER_BUSY
20
21
23:22
31:24
0x1
0x1
0x0
0xf
Description
0=Dynamic control VIP sclk branch
1=Disable dynamic control of VIP sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=VIP branch is off
1=VIP branch is on
1=VIP branch shutoff with PROG_DELAY_VALUE delay
Delay VIP clock on/off by number of cycles
Cnt VIP idle for number of cycles before dropping the power
level. Only used when VIP_LOWER_POWER_IGNORE is
set to 0.
1=VIP not vote for going to lower power state
1=VIP not vote for going back to normal power state
Cnt VIP busy for number of cycles before raising the power
level. Only used when VIP_NORMAL_POWER_IGNORE is
set to 0.
VIP dynamic clock gating control
TCL_DYN_CNTL - RW - 32 bits - CLKIND:0x1A
Field Name
TCL_FORCEON
Bits
0
Default
0x1
TCL_MAX_DYN_STOP_LAT
1
0x1
TCL_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
TCL_PROG_SHUTOFF
TCL_PROG_DELAY_VALUE
TCL dynamic clock gating control
Description
0=Dynamic control CP sclk branch
1=Disable dynamic control of CP sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=TCL branch is off
1=TCL branch is on
1=TCL branch shutoff with PROG_DELAY_VALUE delay
Delay TCL clock on/off by number of cycles.
GA_DYN_CNTL - RW - 32 bits - CLKIND:0x1B
Field Name
GA_FORCEON
Bits
0
Default
0x1
GA_MAX_DYN_STOP_LAT
1
0x1
GA_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
GA_PROG_SHUTOFF
GA_PROG_DELAY_VALUE
GA dynamic clock gating control
AMD RS690 ASIC Family Register Reference Manual
2-274
Description
0=Dynamic control GA sclk branch
1=Disable dynamic control of GA sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=GA branch is off
1=GA branch is on
1=GA branch shutoff with PROG_DELAY_VALUE delay
Delay GA clock on/off by number of cycles.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SU_DYN_CNTL - RW - 32 bits - CLKIND:0x15
Field Name
SU_FORCEON
Bits
0
Default
0x1
SU_MAX_DYN_STOP_LAT
1
0x1
SU_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
SU_PROG_SHUTOFF
SU_PROG_DELAY_VALUE
SU dynamic clock gating control
Description
0=Dynamic control SU sclk branch
1=Disable dynamic control of SU sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=SU branch is off
1=SU branch is on
1=SU branch shutoff with PROG_DELAY_VALUE delay
Delay SU clock on/off by number of cycles.
SC_DYN_CNTL - RW - 32 bits - CLKIND:0x18
Field Name
SC_FORCEON
Bits
0
Default
0x1
SC_MAX_DYN_STOP_LAT
1
0x1
SC_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
SC_PROG_SHUTOFF
SC_PROG_DELAY_VALUE
SC dynamic clock gating control
Description
0=Dynamic control SC sclk branch
1=Disable dynamic control of SC sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=SC branch is off
1=SC branch is on
1=SC branch shutoff with PROG_DELAY_VALUE delay
Delay SC clock on/off by number of cycles.
RS_DYN_CNTL - RW - 32 bits - CLKIND:0x19
Field Name
RS_FORCEON
Bits
0
Default
0x1
RS_MAX_DYN_STOP_LAT
1
0x1
RS_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
RS_PROG_SHUTOFF
RS_PROG_DELAY_VALUE
Description
0=Dynamic control RS sclk branch
1=Disable dynamic control of RS sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=RS branch is off
1=RS branch is on
1=RS branch shutoff with PROG_DELAY_VALUE delay
FG_DYN_CNTL - RW - 32 bits - CLKIND:0x17
Field Name
FG_FORCEON
Bits
0
Default
0x1
FG_MAX_DYN_STOP_LAT
1
0x1
FG_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x1
FG_PROG_SHUTOFF
FG_PROG_DELAY_VALUE
FG dynamic clock gating control
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Dynamic control FG sclk branch
1=Disable dynamic control of FG sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=FG branch is off
1=FG branch is on
1=FG branch shutoff with PROG_DELAY_VALUE delay
Delay FG clock on/off by number of cycles.
AMD RS690 ASIC Family Register Reference Manual
2-275
Graphics Controller Configuration Registers
TX_DYN_CNTL - RW - 32 bits - CLKIND:0x27
Field Name
TX_FORCEON
Bits
0
Default
0x1
TX_MAX_DYN_STOP_LAT
1
0x1
TX_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x0
TX_PROG_SHUTOFF
TX_PROG_DELAY_VALUE
TX dynamic clock gating control
Description
0=Dynamic control TX sclk branch
1=Disable dynamic control of TX sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=TX branch is off
1=TX branch is on
1=TX branch shutoff with PROG_DELAY_VALUE delay
Delay TX clock on/off by number of cycles.
US_DYN_CNTL - RW - 32 bits - CLKIND:0x28
Field Name
US_FORCEON
Bits
0
Default
0x1
US_MAX_DYN_STOP_LAT
1
0x1
US_CLOCK_STATUS (R)
2
0x0
3
11:4
0x0
0x0
US_PROG_SHUTOFF
US_PROG_DELAY_VALUE
US dynamic clock gating control
Description
0=Dynamic control US sclk branch
1=Disable dynamic control of US sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=US branch is off
1=US branch is on
1=US branch shutoff with PROG_DELAY_VALUE delay
Delay US clock on/off by number of cycles.
MC_GUI_DYN_CNTL - RW - 32 bits - CLKIND:0x1D
Field Name
MC_GUI_FORCEON
Bits
0
Default
0x1
MC_GUI_MAX_DYN_STOP_LAT
1
0x1
MC_GUI_CLOCK_STATUS (R)
2
0x0
MC_GUI_PROG_SHUTOFF
3
0x0
11:4
0x1
MC_GUI_PROG_DELAY_VALUE
MC_GUI dynamic clock gating control
AMD RS690 ASIC Family Register Reference Manual
2-276
Description
0=Dynamic control MC_GUI sclk branch
1=Disable dynamic control of MC_GUI sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=MC_GUI branch is off
1=MC_GUI branch is on
1=MC_GUI branch shutoff with PROG_DELAY_VALUE
delay
Delay MC_GUI clock on/off by number of cycles.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
MC_HOST_DYN_CNTL - RW - 32 bits - CLKIND:0x1E
Field Name
MC_HOST_FORCEON
Bits
0
Default
0x1
MC_HOST_MAX_DYN_STOP_LAT
1
0x1
MC_HOST_CLOCK_STATUS (R)
2
0x0
MC_HOST_PROG_SHUTOFF
3
0x0
11:4
0x1
MC_HOST_PROG_DELAY_VALUE
MC_HOST dynamic clock gating control
Description
0=Dynamic control MC_HOST sclk branch
1=Disable dynamic control of MC_HOST sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=MC_HOST branch is off
1=MC_HOST branch is on
1=MC_HOST branch shutoff with PROG_DELAY_VALUE
delay
Delay MC_HOST clock on/off by number of cycles.
MC_RBS_DYN_CNTL - RW - 32 bits - CLKIND:0x26
Field Name
MC_RBS_FORCE
Bits
0
Default
0x1
MC_RBS_MAX_DYN_STOP_LAT
1
0x1
MC_RBS_CLOCK_STATUS (R)
2
0x0
MC_RBS_PROG_SHUTOFF
3
0x0
11:4
0x1
MC_RBS_PROG_DELAY_VALUE
MC_RBS dynamic clock gating control
Description
0=Dynamic control CP sclk branch
1=Disable dynamic control of CP sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=MC_RBS branch is off
1=MC_RBS branch is on
1=MC_RBS branch shutoff with PROG_DELAY_VALUE
delay
Delay MC_RBS clock on/off by number of cycles.
CG_MISC_REG - RW - 32 bits - CLKIND:0x1F
Field Name
STARTUP_COUNTER
SYNCHRONIZER_COUNTER
Bits
11:0
15:12
Default
0x28
0x8
DISPCLK_FUNC_SEL
SPARE
Misc control
16
23:17
0x0
0x0
Description
Not used.
For debugging purposes. Number of cycles to be used by
the clock switch logic.
1=Use non functional display clock
CG_DEBUG - RW - 32 bits - CLKIND:0x20
Field Name
TEST_MODE
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
Default
0x0
Description
1=Disable long internal timing to speed up regression
tests
AMD RS690 ASIC Family Register Reference Manual
2-277
Graphics Controller Configuration Registers
MCLK_MISC - RW - 32 bits - CLKIND:0x22
Field Name
SPARE_0
MRDCKA0_SOUTSEL
Bits
1:0
3:2
Default
0x0
0x0
MRDCKA1_SOUTSEL
5:4
0x0
MRDCKB0_SOUTSEL
7:6
0x0
MRDCKB1_SOUTSEL
9:8
0x0
MRDCKC0_SOUTSEL
11:10
0x0
MRDCKC1_SOUTSEL
13:12
0x0
MRDCKD0_SOUTSEL
15:14
0x0
MRDCKD1_SOUTSEL
17:16
0x0
18
0x0
31:19
0x0
MCLK_NONFUNC_SEL
SPARE
Description
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=Select functional mclk source
1=Select non-functional mode mclk source
DLL_CNTL - RW - 32 bits - CLKIND:0x23
Field Name
DLL_RESET_TIME
DLL_LOCK_TIME
DLL control register
Bits
9:0
21:12
Default
0x1f4
0xfa
AMD RS690 ASIC Family Register Reference Manual
2-278
Description
Number of cycles required to hold DLL reset high
Number of cycles required to wait for DLL get locked
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SPLL_TIME - RW - 32 bits - CLKIND:0x24
Field Name
SPLL_LOCK_TIME
SPLL_RESET_TIME
Bits
15:0
31:16
Default
0x2000
0x1f4
Description
MPLL_TIME - RW - 32 bits - CLKIND:0x25
Field Name
MPLL_LOCK_TIME
MPLL_RESET_TIME
Bits
15:0
31:16
Default
0x2000
0x1f4
Description
DYN_BACKBIAS_CNTL - RW - 32 bits - CLKIND:0x29
Field Name
IO_CG_BACKBIAS_EN
BACKBIAS_SYNC
BACKBIAS_DELAY_SEL
Bits
0
Default
0x0
1
0x0
22:3
0x0
Description
0=Disable dynamic back bias switching
1=Enable dynamic back bias switching
0=Disable synchronization of reduced speed SCLK and
back bias switching
1=Enable synchronization
Delay (in sclk cycle) between backbias disabled until sclk
speed goes back to normal.
Static screen mode backbias control
POLARITY_CNTL - RW - 32 bits - CLKIND:0x2A
Field Name
IO_BACKBIAS_POLARITY
IO_VOLTAGE_REGULATOR_POLARITY
Bits
0
Default
0x1
1
0x1
0=Negative
1=Positive
0=Negative
1=Positivie
Description
OVERCLOCK_CNTL - RW - 32 bits - CLKIND:0x2B
Field Name
OVERCLOCK_PROTECTION_SCLK
Bits
0
Default
0x0
OVERCLOCK_PENALTY
13:4
0x10
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Disable
1=Enable
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
ERROR_STATUS - RW - 32 bits - CLKIND:0x2C
Field Name
OVERCLOCK_DETECTION_SCLK (R)
Bits
0
Default
0x0
OVERCLOCK_DETECTION_YCLK (R)
1
0x0
SPLL_UNLOCK (R)
YPLL_UNLOCK (R)
2
3
0x0
0x0
Description
0=No overclock for SCLK
1=SCLK overclock
0=No overclock for YCLK
1=YCLK overclock
CC_FUSE_STRAPS_0 - R - 32 bits - CLKIND:0x2D
Bits
1:0
Default
0x0
OVERCLOCK_DIS
2
0x0
MOBILE_DIS
3
0x0
WS_DIS
4
0x0
MAX_MPS
7:5
0x0
BAD_PIPES
11:8
0x0
MAX_MEM_CHANNELS
13:12
0x0
ROM_DIS
14
0x0
DEBUG_DIS
15
0x0
MAX_PIPES
Field Name
Description
0=4
1=3
2=2
3=1
0=Enable Overclocking
1=Disable Overclocking
0=Enable Mobile
1=Disable Mobile
0=Enable Workstation
1=Disable Workstation
0=8
1=7
2=6
3=5
4=4
5=3
6=2
7=1
Bad Pipe Mask. Each set bit indicates that the
corresponding pipe has been marked as bad.
0=Four channels
1=Reserved
2=Two channels
3=One channel
0=Include ROM straps
1=Ignore ROM straps
0=Include DEBUG straps
1=Ignore DEBUG straps
MAX_SCLK
23:16
0x0
MAX_MCLK
31:24
0x0
Fuse Strap Values. Corresponds to on-die fuses 71-40. See CC_COMBINED_STRAPS_0 register for details.
AMD RS690 ASIC Family Register Reference Manual
2-280
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CC_FUSE_STRAPS_1 - R - 32 bits - CLKIND:0x2E
Field Name
DEVICE_ID
MAJOR_REV_ID
MINOR_REV_ID
ATI_REV_ID
STRAP_MODE
Bits
15:0
19:16
23:20
27:24
29:28
Default
0x0
0x0
0x0
0x0
0x0
Description
0=4 PIPES/4 CHANNELS/8 VAPS
1=2 PIPES/2 CHANNELS/ALL VAPS
2=1 PIPE/2 CHANNELS/ALL VAPS
Fuse Strap Values. Corresponds to on-die fuses 103-72. See CC_COMBINED_STRAPS_1 values for details.
CC_DEBUG_STRAPS_0 - RW - 32 bits - CLKIND:0x2F
Bits
1:0
Default
0x0
OVERCLOCK_DIS
2
0x0
MOBILE_DIS
3
0x0
WS_DIS
4
0x0
7:5
0x0
11:8
13:12
0x0
0x0
ROM_DIS
14
0x0
DEBUG_DIS
15
0x0
MAX_SCLK
MAX_MCLK
23:16
31:24
0x0
0x0
MAX_PIPES
Field Name
MAX_MPS
BAD_PIPES
MAX_MEM_CHANNELS
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=4
1=3
2=2
3=1
0=Enable Overclocking
1=Disable Overclocking
0=Enable Mobile
1=Disable Mobile
0=Enable Workstation
1=Disable Workstation
0=8
1=7
2=6
3=5
4=4
5=3
6=2
7=1
0=Four channels
1=Reserved
2=Two channels
3=One channel
0=Include ROM straps
1=Ignore ROM straps
0=Include DEBUG straps
1=Ignore DEBUG straps
AMD RS690 ASIC Family Register Reference Manual
2-281
Graphics Controller Configuration Registers
CC_DEBUG_STRAPS_1 - RW - 32 bits - CLKIND:0x30
Field Name
DEVICE_ID
MAJOR_REV_ID
MINOR_REV_ID
ATI_REV_ID
STRAP_MODE
Bits
15:0
19:16
23:20
27:24
29:28
Default
0x0
0x0
0x0
0x0
0x0
Description
0=4 PIPES/4 CHANNELS/8 VAPS
1=2 PIPES/2 CHANNELS/ALL VAPS
2=1 PIPE/2 CHANNELS/ALL VAPS
Debug Strap Values. See CC_COMBINED_STRAPS_1 values for details.
CC_IO_STRAPS - R - 32 bits - CLKIND:0x31
Description
0=4
1=3
2=2
3=1
OVERCLOCK_DIS
2
0x0
0=Enable Overclocking
1=Disable Overclocking
MOBILE_DIS
3
0x0
0=Enable Mobile
1=Disable Mobile
WS_DIS
4
0x0
0=Enable Workstation
1=Disable Workstation
DEVICE_ID
9:5
0x0
Device ID 5 LSBs.
MAX_MEM_CHANNELS
11:10
0x0
0=Four channels
1=Reserved
2=Two channels
3=One channel
IO Straps/Substrate Fuses. See CC_COMBINED_STRAPS_# registers for more details.
MAX_PIPES
Field Name
Bits
1:0
Default
0x0
CC_IO_STRAPS_22A - R - 32 bits - CLKIND:0x31
Bits
0
Default
0x0
EXTRA_0
OVERCLOCK_DIS
1
2
0x0
0x0
MOBILE_DIS
3
0x0
WS_DIS
4
0x0
9:5
10
0x0
0x0
MAX_PIPES
Field Name
DEVICE_ID
MAX_MEM_CHANNELS
0=2
1=1
Description
0=Enable Overclocking
1=Disable Overclocking
0=Enable Mobile
1=Disable Mobile
0=Enable Workstation
1=Disable Workstation
Device ID 5 LSBs.
0=Two channels
1=One channel
EXTRA_1
11
0x0
EXTRA_2
12
0x0
EXTRA_3
13
0x0
EXTRA_4
14
0x0
Obsolete. Use CC_IO_STRAPS. IO Straps/Substrate Fuses in CC_STRAP_MODE_22A. See CC_COMBINED_STRAPS_#
registers for more details.
AMD RS690 ASIC Family Register Reference Manual
2-282
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CC_IO_STRAPS_12A - R - 32 bits - CLKIND:0x31
Field Name
EXTRA_0
EXTRA_1
OVERCLOCK_DIS
Bits
0
1
2
Default
0x0
0x0
0x0
MOBILE_DIS
3
0x0
WS_DIS
4
0x0
9:5
10
0x0
0x0
DEVICE_ID
MAX_MEM_CHANNELS
Description
0=Enable Overclocking
1=Disable Overclocking
0=Enable Mobile
1=Disable Mobile
0=Enable Workstation
1=Disable Workstation
Device ID 5 LSBs.
0=Two channels
1=One channel
EXTRA_2
11
0x0
EXTRA_3
12
0x0
EXTRA_4
13
0x0
EXTRA_5
14
0x0
Obsolete. Use CC_IO_STRAPS. IO Straps/Substrate Fuses in CC_STRAP_MODE_12A. See CC_COMBINED_STRAPS_#
registers for more details.
CC_ROM_STRAPS - R - 32 bits - CLKIND:0x32
Bits
15:0
17:16
Default
0x0
0x0
OVERCLOCK_DIS
18
0x0
MOBILE_DIS
19
0x0
WS_DIS
20
0x0
23:22
0x0
DEVICE_ID
MAX_PIPES
Field Name
MAX_MEM_CHANNELS
Description
0=4
1=3
2=2
3=1
0=Enable Overclocking
1=Disable Overclocking
0=Enable Mobile
1=Disable Mobile
0=Enable Workstation
1=Disable Workstation
0=Four channels
1=Reserved
2=Two channels
3=One channel
BAD_PIPES
27:24
0x0
Strap Values from ROM. See CC_COMBINED_STRAPS_# registers for details.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
CC_COMBINED_STRAPS_0 - R - 32 bits - CLKIND:0x33
Description
Maximum Number of Raster Pipes. Default: All 4 raster
pipes (16 pixels) can be enabled by software.
0=4
1=3
2=2
3=1
OVERCLOCK_DIS
2
0x0
Enables a circuit to switch the core clock frequency to the
PCIE reference clock when either the core, or the memory
clock, frequency is detected to be above the value set by
the MAX_SCLK or MAX_MCLK strap settings. Each clock
is monitored independently, but only the core clock is
throttled. Default: No overclock protection.
0=Enable Overclocking
1=Disable Overclocking
MOBILE_DIS
3
0x0
Disables LVDS. Default: LVDS can be enabled by software.
0=Enable Mobile
1=Disable Mobile
WS_DIS
4
0x0
Workstation Disable. Just informational. Default:
Workstation features can be enabled by software.
0=Enable Workstation
1=Disable Workstation
MAX_MPS
7:5
0x0
0=8
1=7
2=6
3=5
4=4
5=3
6=2
7=1
BAD_PIPES
11:8
0x0
Bad Pipe Mask. Each bit position set to 1 indicates that the
corresponding pipe has been marked as bad.
MAX_MEM_CHANNELS
13:12
0x0
Maximum number of memory channels that can be enabled
by software.
0=Four channels
1=Reserved
2=Two channels
3=One channel
ROM_DIS
14
0x0
Disable ROM straps. Ignore the ROM straps when
calculating the combined strap values. Default: ROM straps
can affect strap values.
0=Include ROM straps
1=Ignore ROM straps
DEBUG_DIS
15
0x0
Disable debug strap settings. Setting this bit prevents
software from setting Chip Configuration straps. This bit
should be set for production parts. Default: Software can
write debug strap settings.
0=Include DEBUG straps
1=Ignore DEBUG straps
MAX_SCLK
23:16
0x0
Maximum ratio of core clock to pcie reference clock in 4.4
fixed point. Default: 0 = 16 15/16.
MAX_MCLK
31:24
0x0
Maximum ratio of memory clock to pcie reference clock in
5.3 fixed point. Default: 0 = 32 7/8.
Working Set of Strap Values based on FUSE, IO, ROM and DEBUG Strap values.
MAX_PIPES
Field Name
Bits
1:0
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CC_COMBINED_STRAPS_1 - R - 32 bits - CLKIND:0x34
Field Name
DEVICE_ID
MAJOR_REV_ID
MINOR_REV_ID
ATI_REV_ID
STRAP_MODE
Bits
15:0
19:16
23:20
27:24
29:28
Default
0x0
0x0
0x0
0x0
0x0
Description
PCI Device ID
PCI Major Revision ID
PCI Minor Revision ID
Internal Revision ID
Obsolete. The different strap modes allows the IO straps to
be used for other purposes (in particular, identifying
packages).
For CC_STRAP_MODE_22A, use CC_IO_STRAP_22A to
get the fuse values.
For CC_STRAP_MODE_12A, use CC_IO_STRAP_12A.
0=4 PIPES/4 CHANNELS/8 VAPS
1=2 PIPES/2 CHANNELS/ALL VAPS
2=1 PIPE/2 CHANNELS/ALL VAPS
Working Chip Configuration Strap Values based on Fuse, I/O and ROM Strap values.
CG_CLKPIN_CNTL - RW - 32 bits - CLKIND:0x35
Field Name
Bits
0
Default
0x1
XTL_LOW_GAIN
1
0x1
CG_CLK_TO_OUTPIN
2
0x0
OSC_USE_CORE
3
0x0
OSC_EN
Description
0=Disable Oscillation
1=Enable Oscillation
0=High Gain
1=Low Gain
0=Disabled
1=Send out selected clock for jitter test
0=Pad routing OSC
1=Core routing OSC
VOL_DROP_CNT - RW - 32 bits - CLKIND:0x36
Field Name
VOL_DROP_DELAY
Bits
31:0
Default
0x100
Static screen mode voltage control
Description
Delay (in sclk cycle) between static screen condition is
detected until the voltage is dropped.
BACKBIAS_ENABLE_CNT - RW - 32 bits - CLKIND:0x37
Field Name
BB_ENABLE_DELAY
Bits
31:0
Default
0x100
Description
Delay (in sclk cycle) between static screen condition is
detected until backbias is enabled.
Static screen mode backbias control
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
CG_TC_JTAG_0 - RW - 32 bits - CLKIND:0x38
Field Name
CG_TC_TMS
CG_TC_TDI
CG_TC_MODE
Bits
7:0
15:8
17:16
Default
0x0
0x0
0x0
Description
8 consecutive values for TMS. Bit [0] is sent first.
8 consecutive values for TDI. Bit [0] is sent first.
Indicates what clock should be used for TCK in the jtag
transactions.
0=No Clock
1=PCIE Reference Clock / 4
2=PCIE Reference Clock / 10
3=PCIE Reference Clock / 20
CG_TC_TDO_MASK
31:24
0x0
A mask indicating whether the TDO value should be read
back for a given JTAG cycle. Bit [0] corresponds to the first
TDO sample. This mask can be used to prevent the
readback of unknown values across the bus interface
during simulation. This field can be set to all 1's on real
hardware.
CG Interface to the Test Controller (TC) using IEEE JTAG protocol. This register can be written with 8 consecutive values for the
inputs to the TC's JTAG port. These 8 inputs are sent at consecutive TCK clock edges. The final value is held for indefinitely
many TCK clock edges until the next write to this register. The register can be used to walk through several states of the JTAG
state machine and typically the state machine would be left in a 'paused' state. The TDO values sampled at the 8 edges for
which input was provided is available for readback from the TC_CG_TDO field of the CG_TC_JTAG_1 register.
CG_TC_JTAG_1 - R - 32 bits - CLKIND:0x39
Description
8 consecutive sampled values of TDO. Bit [0] corresponds
to the cycle that the first bit of
CG_TC_JTAG_0.CG_TC_TMS and
CG_TC_JTAG_0.CG_TC_TDI were sampled by the Test
Controller.
TC_CG_DONE
31
0x0
Indicates whether the JTAG sequence has completed.
0=We have completed less than 8 JTAG cycles since the
last write to CG_TC_JTAG_0
1=All 8 JTAG cycles have been completed since the last
write to CG_TC_JTAG_0
TDO readback and status bits for the CG JTAG interface described in more detail in the CG_TC_JTAG_0 register description.
TC_CG_TDO
Field Name
Bits
7:0
Default
0x0
FVTHROT_CNTRL_REG - RW - 32 bits - CLKIND:0x3A
Field Name
DontWaitForFbDivWrap
Minimum_Considered_Idle_Period
Refresh_Rate_Divisor
EnableFV_Throt
EnableFV_Update
TrendSelMode
ForceTrendSel
EnableFV_ThrotIO
Bits
0
24:1
26:25
27
28
29
30
31
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
0=Enable frequency/voltage scaling
0=Enable frequency/voltage updates
0=Determine trend using just last frame or last 4 frames
0=Force up or down trend
0=Enable the OE of the pad used for PWM.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
FVTHROT_TARGET_REG - RW - 32 bits - CLKIND:0x3B
Field Name
TargetIdleCount
Bits
23:0
Default
0x0
Description
FVTHROT_COMPARE_BOUND1 - RW - 32 bits - CLKIND:0x3C
Field Name
Compare1_Boundary
Bits
23:0
Default
0x0
Description
FVTHROT_COMPARE_BOUND2 - RW - 32 bits - CLKIND:0x3D
Field Name
Compare2_Boundary
Bits
23:0
Default
0x0
Description
FVTHROT_COMPARE_BOUND3 - RW - 32 bits - CLKIND:0x3E
Field Name
Compare3_Boundary
Bits
23:0
Default
0x0
Description
FVTHROT_COMPARE_BOUND4 - RW - 32 bits - CLKIND:0x3F
Field Name
Compare4_Boundary
Bits
23:0
Default
0x0
Description
FVTHROT_UPTREND_COEF0 - RW - 32 bits - CLKIND:0x40
Field Name
UpTrendCoefficient0
UpTrendCoefficient1
UpTrendCoefficient2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
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Graphics Controller Configuration Registers
FVTHROT_UPTREND_COEF1 - RW - 32 bits - CLKIND:0x41
Field Name
UpTrendCoefficient3
UpTrendCoefficient4
UpTrendCoefficient5
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_UPTREND_COEF2 - RW - 32 bits - CLKIND:0x42
Field Name
UpTrendCoefficient6
UpTrendCoefficient7
UpTrendCoefficient8
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_UPTREND_COEF3 - RW - 32 bits - CLKIND:0x43
Field Name
UpTrendCoefficient9
UpTrendCoefficient10
UpTrendCoefficient11
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_UPTREND_COEF4 - RW - 32 bits - CLKIND:0x44
Field Name
UpTrendCoefficient12
UpTrendCoefficient13
UpTrendCoefficient14
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_DOWNTREND_COEF0 - RW - 32 bits - CLKIND:0x45
Field Name
DownTrendCoefficient0
DownTrendCoefficient1
DownTrendCoefficient2
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
FVTHROT_DOWNTREND_COEF1 - RW - 32 bits - CLKIND:0x46
Field Name
DownTrendCoefficient3
DownTrendCoefficient4
DownTrendCoefficient5
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_DOWNTREND_COEF2 - RW - 32 bits - CLKIND:0x47
Field Name
DownTrendCoefficient6
DownTrendCoefficient7
DownTrendCoefficient8
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_DOWNTREND_COEF3 - RW - 32 bits - CLKIND:0x48
Field Name
DownTrendCoefficient9
DownTrendCoefficient10
DownTrendCoefficient11
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_DOWNTREND_COEF4 - RW - 32 bits - CLKIND:0x49
Field Name
DownTrendCoefficient12
DownTrendCoefficient13
DownTrendCoefficient14
Bits
9:0
19:10
29:20
Default
0x0
0x0
0x0
Description
FVTHROT_FBDIV_REG0 - RW - 32 bits - CLKIND:0x4A
Field Name
MinFeedbackDiv
MaxFeedbackDiv
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_FBDIV_REG1 - RW - 32 bits - CLKIND:0x4B
Field Name
MaxFeedbackStep
StartingFeedbackDiv
ForceFeedbackDiv
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
11:0
23:12
24
Default
0x0
0x0
0x0
Description
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Graphics Controller Configuration Registers
FVTHROT_FBDIV_REG2 - RW - 32 bits - CLKIND:0x4C
Field Name
ForcedFeedbackDiv
FbDivTimerVal
Bits
11:0
27:12
Default
0x0
0x0
Description
FVTHROT_FB_UPSTEP_REG0 - RW - 32 bits - CLKIND:0x4D
Field Name
FeedbackDivUpStepsize1
FeedbackDivUpStepsize2
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_FB_UPSTEP_REG1 - RW - 32 bits - CLKIND:0x4E
Field Name
FeedbackDivUpStepsize3
FeedbackDivUpStepsize4
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_FB_DOWNSTEP_REG0 - RW - 32 bits - CLKIND:0x4F
Field Name
FeedbackDivDownStepsize1
FeedbackDivDownStepsize2
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_FB_DOWNSTEP_REG1 - RW - 32 bits - CLKIND:0x50
Field Name
FeedbackDivDownStepsize3
FeedbackDivDownStepsize4
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_PWM_CTRL_REG0 - RW - 32 bits - CLKIND:0x51
Field Name
StartingPWM_HighTime
NumberOfCyclesInPeriod
ForceStartingPWM_HighTime
InvertPWM_Waveform
Bits
11:0
23:12
24
25
Default
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
FVTHROT_PWM_CTRL_REG1 - RW - 32 bits - CLKIND:0x52
Field Name
MinimumPWM_HighTime
MaximumPWM_HighTime
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_PWM_UPSTEP_REG0 - RW - 32 bits - CLKIND:0x53
Field Name
PWM_HighTimeUpStepsize1
PWM_HighTimeUpStepsize2
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_PWM_UPSTEP_REG1 - RW - 32 bits - CLKIND:0x54
Field Name
PWM_HighTimeUpStepsize3
PWM_HighTimeUpStepsize4
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_PWM_DOWNSTEP_REG0 - RW - 32 bits - CLKIND:0x55
Field Name
PWM_HighTimeDownStepsize1
PWM_HighTimeDownStepsize2
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_PWM_DOWNSTEP_REG1 - RW - 32 bits - CLKIND:0x56
Field Name
PWM_HighTimeDownStepsize3
PWM_HighTimeDownStepsize4
Bits
11:0
23:12
Default
0x0
0x0
Description
FVTHROT_STATUS_REG0 - R - 32 bits - CLKIND:0x57
Field Name
CurrentFeedbackDiv
REG_CURRENT_PWM_HIGHTIME
REG_COMPARE_RESULT
REG_UpDown
PWM
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
11:0
23:12
27:24
28
29
Default
0x0
0x0
0x0
0x0
0x0
Description
0=Last result of measured vs. target idle time comparison.
0=Current value of the UpDown indicator in the circuit.
0=Current value of the PWM output.
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Graphics Controller Configuration Registers
FVTHROT_STATUS_REG1 - R - 32 bits - CLKIND:0x58
Field Name
REG_LAST_ICOUNT
Bits
23:0
Default
0x0
Description
FVTHROT_STATUS_REG2 - R - 32 bits - CLKIND:0x59
Field Name
REG_LAST_FILTERED_ICOUNT
Bits
23:0
Default
0x0
Description
CG_SPLL_ANALOG_CTRL0 - RW - 32 bits - CLKIND:0x5A
IVCOREF2
IVCOREF1
IVCO
IBIAS
ILF
IPCP
IVCODIV
ISPEC
IACU
ILDRESET
Field Name
Bits
2:0
5:3
13:6
15:14
17:16
21:18
24:22
27:25
30:28
31
Default
0x0
0x0
0x87
0x0
0x0
0x4
0x0
0x0
0x0
0x0
Description
0=VCO Input 2 Voltage Control.
0=VCO Input 1 Voltage Control.
0=VCO Gain/duty cycle adjustment.
0=Bias Generator Adjustment.
0=Loop Filter Adjustment.
0=Charge Pump Adjustment.
0=VCO Output Divider Setting.
0=Lock Detect Static Phase Error Control.
0=Lock Detect Analysis Unlock Control.
0=Lock Detect Manual Reset.
CG_SPLL_ANALOG_CTRL1 - RW - 32 bits - CLKIND:0x5B
IACL
ITMONENVI
ITMONENVC
SPARE_BITS
Field Name
Bits
2:0
3
4
31:5
Default
0x0
0x0
0x0
0x0
Description
0=Lock Detect Analysis Lock Control.
0=VI Access Point Enable.
0=VC Access Points Enable.
CG_INTGFX_MISC - RW - 32 bits - CLKIND:0x5C
Field Name
BIF_SCLK_GATING_EN
BCLK_FREQ_SEL
AZ_SCLK_GATING_EN
AZ_D3D0_RST_EN
CG_IO_DAC_SDA_GPIO_A
CG_IO_DAC_SDA_GPIO_MASK
CG_IO_DAC_SDA_GPIO_EN
CG_IO_DAC_SDA_GPIO_OD
CG_INTGFX_MISC_SPARE
Bits
0
1
2
3
4
5
6
7
31:8
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
0=Enable BIF SCLK Gating
0=0: BCLK is 100MHz, 1: BCLK is SCLK/2
0=Enable Azalia SCLK Gating
0=Enable reset pulse on Azalia exiting D3
0=DAC_SDA GPIO A bit
0=DAC_SDA GPIO Mask bit
0=DAC_SDA GPIO EN bit
0=DAC_SDA GPIO OD bit
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CG_INTGFX_SPARE_RO - R - 32 bits - CLKIND:0x5D
Field Name
INTGFX_SPARE_RO
Bits
31:0
Default
0x0
Description
FVTHROT_PWM_FEEDBACK_DIV_REG1 - RW - 32 bits - CLKIND:0x5E
Field Name
Range0_PWMFeedbackDiv
RangePWMFeedbackDivEn
FVTHROT_PWM_FEEDBACK_DIV_REG
1_SPARE_BITS
Bits
11:0
12
31:13
Default
0x0
0x0
0x0
Description
0=Enable PWM Look Up As Function Of FbDiv
FVTHROT_PWM_FEEDBACK_DIV_REG2 - RW - 32 bits - CLKIND:0x5F
Field Name
Range1_PWMFeedbackDiv
Range2_PWMFeedbackDiv
FVTHROT_PWM_FEEDBACK_DIV_REG
2_SPARE_BITS
Bits
11:0
23:12
31:24
Default
0x0
0x0
0x0
Description
FVTHROT_PWM_FEEDBACK_DIV_REG3 - RW - 32 bits - CLKIND:0x60
Field Name
Range0_PWM
Range1_PWM
FVTHROT_PWM_FEEDBACK_DIV_REG
3_SPARE_BITS
Bits
11:0
23:12
31:24
Default
0x0
0x0
0x0
Description
FVTHROT_PWM_FEEDBACK_DIV_REG4 - RW - 32 bits - CLKIND:0x61
Field Name
Range2_PWM
Range3_PWM
FVTHROT_PWM_FEEDBACK_DIV_REG
4_SPARE_BITS
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
11:0
23:12
31:24
Default
0x0
0x0
0x0
Description
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Graphics Controller Configuration Registers
FVTHROT_SPLL_PARAM_FEEDBACK_DIV_REG1 - RW - 32 bits - CLKIND:0x62
Field Name
Range0_SpllParamFeedbackDiv
RangeSpllParamFeedbackDivEn
FVTHROT_SPLL_PARAM_FEEDBACK_
DIV_REG1_SPARE_BITS
Bits
11:0
12
31:13
Default
0x0
0x0
0x0
Description
0=Enable SPLL Param As Function Of FbDiv
FVTHROT_SPLL_PARAM_FEEDBACK_DIV_REG2 - RW - 32 bits - CLKIND:0x63
Field Name
Range1_SpllParamFeedbackDiv
Range2_SpllParamFeedbackDiv
FVTHROT_SPLL_PARAM_FEEDBACK_
DIV_REG2_SPARE_BITS
Bits
11:0
23:12
31:24
Default
0x0
0x0
0x0
Description
FVTHROT_SPLL_PARAM_FEEDBACK_DIV_REG3 - RW - 32 bits - CLKIND:0x64
Field Name
Range0_SpllParam
Range1_SpllParam
Bits
15:0
31:16
Default
0x0
0x0
Description
FVTHROT_SPLL_PARAM_FEEDBACK_DIV_REG4 - RW - 32 bits - CLKIND:0x65
Field Name
Range2_SpllParam
Range3_SpllParam
Bits
15:0
31:16
Default
0x0
0x0
Description
FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 - RW - 32 bits - CLKIND:0x66
Field Name
Range0_SlowClkFeedbackDiv
RangeSlowClkFeedbackDivEn
FVTHROT_SLOW_CLK_FEEDBACK_DI
V_REG1_SPARE_BITS
Bits
11:0
12
31:13
Default
0x0
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
0=Enable Slow Clk As Function Of FbDiv
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
FVTHROT_SCALE_FEEDBACK_DIV_REG1 - RW - 32 bits - CLKIND:0x67
Field Name
Range0_ScaleFeedbackDiv
Range1_ScaleFeedbackDiv
RangeScaleFeedbackDivEn
Bits
11:0
23:12
24
Default
0x0
0x0
0x0
FVTHROT_SCALE_FEEDBACK_DIV_RE
G1_SPARE_BITS
31:25
0x0
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
0=Enable Feedback and Post Dividers Scaled As
Function Of FVTHROT_FbDiv
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Graphics Controller Configuration Registers
2.11 DAC Control
VGA DAC Registers
DAC_DATA - RW - 8 bits - VGA_IO:0x3C9
Field Name
DAC_DATA
Bits
Default
Description
7:0
0x0
VGA Palette (DAC) Data. Use DAC_R_INDEX and
DAC_W_INDEX to set read or write mode, and entry to
access.
Access order is Red, Green, Blue, and then auto-increment
occurs to next entry.
DAC_8BIT_EN controls whether 6 or 8 bit access.
VGA Palette (DAC) Data.
DAC_MASK - RW - 8 bits - VGA_IO:0x3C6
Field Name
DAC_MASK
Bits
Default
Description
7:0
0x0
Masks off usage of individual palette index bits before pixel
index is looked-up in the palette.
0=Do not use this bit of the index
1=Use this bit of the index
Only has an effect in VGA emulation modes
(CRTC_EXT_DISP_EN=0), not for VESA modes or
extended display modes.
Palette index mask for VGA emulation modes.
DAC_R_INDEX - RW - 8 bits - VGA_IO:0x3C7
Field Name
DAC_R_INDEX
Bits
Default
Description
7:0
0x0
Write: Sets the index for a palette (DAC) read operation.
Index auto-increments after every third read of DAC_DATA.
Read: Indicates if palette in read or write mode.
0=Palette in write mode (DAC_W_INDEX last written).
3=Palette in read mode (DAC_R_INDEX last written).
Also see DAC_W_INDEX.
Palette (DAC) Read Index.
DAC_W_INDEX - RW - 8 bits - VGA_IO:0x3C8
Field Name
DAC_W_INDEX
Bits
Default
Description
7:0
0x0
Sets the index for a palette (DAC) write operation. Index
auto-increments after every third write of DAC_DATA. Also
see DAC_R_INDEX.
Palette (DAC) Write Index.
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
2.12 VGA Control/Status
GENFC_RD - R - 8 bits - VGA_IO:0x3CA
Field Name
VSYNC_SEL_R
Bits
Default
3
0x0
(mirror of GENFC_WT:VSYNC_SEL_W)
Description
Vertical sync select (read).
0=Normal vertical sync
1=Sync is 'vertical sync' ORed with 'vertical display
enable
Feature Control register (Read).
GENFC_WT - W - 8 bits - [VGA_IO:0x3BA] [VGA_IO:0x3DA]
Field Name
VSYNC_SEL_W
Bits
Default
3
0x0
Description
Vertical sync select (write).
0=Normal vertical sync
1=Sync is 'vertical sync' ORed with 'vertical display
enable
Feature Control register (Read).
GENMO_WT - W - 8 bits - VGA_IO:0x3C2
Bits
Default
GENMO_MONO_ADDRESS_B
Field Name
0
0x0
VGA addressing mode.
0=Monochrome emulation, regs at 0x3Bx
1=Color/Graphic emulation, regs at 0x3Dx
VGA_RAM_EN
1
0x0
Enables/Disables CPU access to video RAM at VGA
aperture.
0=Disable
1=Enable
3:2
0x0
Selects pixel clock frequency to use in VGA modes. Used
when CRTC_GEN_CNTL.CRTC_EXT_DISP_EN = 0. See
CLOCK_CNTL_INDEX.PPLL_DIV_SEL for non-VGA mode
pixel clock selection.
0=25.1744MHz (640 Pels)
1=28.3212MHz (720 Pels)
2=Reserved
3=Reserved
5
0x0
This bit is used in odd/even display modes (A/N modes: 0,
1, 2, 3, and 7). This bit is ignored when either bit GRA06[1]
or SEQ4[3] are enabled.
Used to determine if the VGA aperture maps into the lower
(even) or upper (odd) page of memory.
0=Selects odd (high) memory locations
1=Selects even (low) memory locations
VGA_CKSEL
ODD_EVEN_MD_PGSEL
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Proprietary
Description
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Graphics Controller Configuration Registers
VGA_HSYNC_POL
6
0x0
Determines polarity of horizontal sync (HSYNC) for VGA
modes.
0=HSYNC pulse active high
1=HSYNC pulse active low
The convention of VGA is to use active low VSYNC for 400
(and 200) and 480 line modes. Active high is normally used
for 350 line modes.
VGA_VSYNC_POL
7
0x0
Determines polarity of vertical sync (VSYNC) for VGA
modes.
0=VSYNC pulse active high
1=VSYNC pulse active low
The convention of VGA is to use active high VSYNC for 400
(and 200) line modes. Active low is normally used for 350
and 480 line modes.
Miscellaneous Output register (Write).
GENMO_RD - R - 8 bits - VGA_IO:0x3CC
Field Name
GENMO_MONO_ADDRESS_B
Bits
Default
Description
0
0x0
VGA addressing mode.
1
0x0
Enables/Disables CPU access to video RAM at VGA
aperture.
3:2
0x0
Selects pixel clock frequency to use.
5
0x0
This bit is used in odd/even display modes (A/N modes: 0,
1, 2, 3, and 7). This bit is ignored when either bit GRA06[1]
or SEQ4[3] are enabled.
Used to determine if the VGA aperture maps into the lower
(even) or upper (odd) page of memory.
6
0x0
Determines polarity of horizontal sync (HSYNC) for VGA
modes.
0=HSYNC pulse active high
1=HSYNC pulse active low
The convention of VGA is to use active low VSYNC for 400
(and 200) and 480 line modes. Active high is normally used
for 350 line modes.
7
0x0
Determines polarity of vertical sync (VSYNC) for VGA
modes.
0=VSYNC pulse active high
1=VSYNC pulse active low
The convention of VGA is to use active high VSYNC for 400
(and 200) line modes. Active low is normally used for 350
and 480 line modes.
(mirror of
GENMO_WT:GENMO_MONO_ADDRESS_B)
VGA_RAM_EN
(mirror of GENMO_WT:VGA_RAM_EN)
VGA_CKSEL
(mirror of GENMO_WT:VGA_CKSEL)
ODD_EVEN_MD_PGSEL
(mirror of
GENMO_WT:ODD_EVEN_MD_PGSEL)
VGA_HSYNC_POL
(mirror of GENMO_WT:VGA_HSYNC_POL)
VGA_VSYNC_POL
(mirror of GENMO_WT:VGA_VSYNC_POL)
Miscellaneous Output register (Read).
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Graphics Controller Configuration Registers
DAC_CNTL - RW - 32 bits - [IOReg,MMReg:0x58]
Field Name
DAC_VGA_ADR_EN
Bits
13
Default
0x0
Description
Enables access of the palette (DAC) at the VGA I/O DAC
addresses when in extended display modes (non-VGA, or
CRTC_EXT_DISP_EN=1).
General control for the RGB DAC and palette.
GENS0 - R - 8 bits - VGA_IO:0x3C2
Bits
Default
SENSE_SWITCH
Field Name
4
0x0
DAC comparator read back. Used for monitor detection.
Mirror of DAC_CMP_OUTPUT@DAC_CNTL. See
description there.
Description
CRT_INTR
7
0x0
CRT Interrupt:
0=Vertical retrace interrupt is cleared
1=Vertical retrace interrupt is pending
Input Status 0 register.
GENS1 - R - 8 bits - [VGA_IO:0x3BA] [VGA_IO:0x3DA]
Bits
Default
NO_DIPLAY
Field Name
0
0x0
Display enable.
0=Enable
1=Disable
VGA_VSTATUS
3
0x0
Vertical Retrace Status.
0=Vertical retrace not active
1=Vertical retrace active
5:4
0x0
Diagnostic bits 0, 1 respectively.
These two bits are connected to two of the eight colour
outputs (P7:P0) of the attribute controller. Connections are
controlled by ATTR12(5,4) as follows:
0=P2,P0
1=P5,P4
2=P3,P1
3=P7,P6
PIXEL_READ_BACK
Description
Input Status 1 register.
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Graphics Controller Configuration Registers
2.13 VGA Sequencer
SEQ00 - RW - 8 bits - VGASEQIND:0x0
Bits
Default
SEQ_RST0B
Field Name
0
0x1
Synchronous reset bit 0:
0=Follows SEQ_RST1B
1=Sequencer runs unless SEQ_RST1B=0
Description
SEQ_RST1B
1
0x1
Synchronous reset bit 1:
0=Disable character clock, display requests, and H/V
syncs
1=Sequencer runs unless SEQ_RST0B=0
Reset register.
SEQ01 - RW - 8 bits - VGASEQIND:0x1
Bits
Default
Description
SEQ_DOT8
Field Name
0
0x1
8/9 Dot Clocks (Modes 1, 2, 3, and 7 use 9-dot characters.
To change bit 0, GENVS(0) must be logical 0).
0=9 dot char clock. Modes 0, 1, 2, 3 & 7
1=8 dot char clock.
SEQ_SHIFT2
2
0x0
Shift load bits.
0=Load video serializer every clock, if SEQ_SHIFT4=0
1=Load video serializer every other clock, if
SEQ_SHIFT4 = 0
SEQ_PCLKBY2
3
0x0
Dot Clock (typically, 320 and 360 horizontal modes use
divide-by-2 to provide 40 column displays. To change this
bit SEQ00[0:0] must be first set to zero).
0=Dot clock is normal
1=Dot clock is divided by 2
SEQ_SHIFT4
4
0x0
Shift load bits.
0 = SEQ_SHIFT2 determines serializer loading
1 = Load video serializer every fourth clock. Ignore
SEQ_SHIFT2
SEQ_MAXBW
5
0x1
Screen off:
0=Normal. Screen on
1=Screen off and blanked. CPU has uninterrupted
access to frame buffer
Clock Mode register.
SEQ02 - RW - 8 bits - VGASEQIND:0x2
Field Name
Bits
Default
SEQ_MAP0_EN
0
0x0
Enables map 0
0=Disable write to memory map 0
1=Enable write to memory map 0
SEQ_MAP1_EN
1
0x0
Enables map 1
0=Disable write to memory map 1
1=Enable write to memory map 1
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Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SEQ_MAP2_EN
2
0x0
Enables map 2
0=Disable write to memory map 2
1=Enable write to memory map 2
SEQ_MAP3_EN
3
0x0
Enables map 3
0=Disable write to memory map 3
1=Enable write to memory map 3
Map Mask register.
SEQ03 - RW - 8 bits - VGASEQIND:0x3
Bits
Default
SEQ_FONT_B1
Field Name
0
0x0
Character Map Select B Bit 1
Description
SEQ_FONT_B2
1
0x0
Character Map Select B Bit 2
SEQ_FONT_A1
2
0x0
Character Map Select A Bit 1
SEQ_FONT_A2
3
0x0
Character Map Select A Bit 2
SEQ_FONT_B0
4
0x0
Character Map Select B Bit 0
SEQ_FONT_A0
5
0x0
Character Map Select A Bit 0
Character Map Select register.
SEQ04 - RW - 8 bits - VGASEQIND:0x4
Field Name
Bits
Default
Description
SEQ_256K
1
0x0
Extended memory. 1 indicates 256 KB of video memory is
present. It also enables the character map selection in
SEQ03.
0=64KB memory present. Has no effect since 256KB
always available
1=256KB memory present
SEQ_ODDEVEN
2
0x0
Odd/Even
0=Even CPU address (A0=0) accesses maps 0 and 2.
Odd address accesses maps 1 and 3
1=Enables sequential access to maps for odd/even
modes. SEQ02 (Map Mask) selects which maps are used
SEQ_CHAIN
3
0x0
Chain (when logical 1, it takes priority over off/even mode
bits SEQ04[2] and GRA05[4]. Unlike odd/even mode,
SEQ04[2] is the only bit used to enable chain mode (double
odd/even). Chain does not affect CRTC access to video
memory. Odd/even bit SEQ04[2] should be the opposite of
GRA05[4].
0=Enables sequential access to maps. SEQ02 (Map
Mask) selects which maps are used
1=For 256 color modes. Map select by CPU address bits
A1:A0
Memory Mode register.
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Graphics Controller Configuration Registers
SEQ8_IDX - RW - 8 bits - [MMReg,VGA_IO:0x3C4]
SEQ_IDX
Field Name
Bits
2:0
Default
0x0
Description
This index points to one of the sequencer registers (SEQ_)
at I/O port address 0x3C5, for the next SEQ read/write
operation.
SEQ Index Register
SEQ8_DATA - RW - 8 bits - [MMReg,VGA_IO:0x3C5]
Field Name
SEQ_DATA
SEQ Data Register
Bits
7:0
Default
0x0
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Description
SEQ data indirect access.
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Proprietary
Graphics Controller Configuration Registers
2.14 VGA CRT
CRTC8_IDX - RW - 8 bits - [MMReg:0x3B4] [MMReg:0x3D4] [VGA_IO:0x3B4] [VGA_IO:0x3D4]
Field Name
VCRTC_IDX
Bits
5:0
Default
0x0
(mirror bits 0:5 of
CRTC_EXT_CNTL:VCRTC_IDX_MASTER)
Description
This index points to one of the internal registers of the CRT
controller (CRTC) at address 0x3?5, for the next CRTC
read/write operation.
CRT Index Register
CRTC8_DATA - RW - 8 bits - [MMReg:0x3B5] [MMReg:0x3D5] [VGA_IO:0x3B5] [VGA_IO:0x3D5]
Field Name
VCRTC_DATA
CTRC Data Register
Bits
7:0
Default
0x0
Description
CRTC data indirect access
CRT00 - RW - 8 bits - VGACRTIND:0x0
Field Name
H_TOTAL
Bits
Default
Description
7:0
0x0
These bits define the active horizontal display in a scan line,
including the retrace period. The value is five less than the
total number of displayed characters in a scan line.
Horizontal Total register.
CRT01 - RW - 8 bits - VGACRTIND:0x1
Field Name
H_DISP_END
Bits
Default
Description
7:0
0x0
These bits define the active horizontal display in a scan line.
The value is one less than the total number of displayed
characters in a scan line.
Horizontal Display Enable End register.
CRT02 - RW - 8 bits - VGACRTIND:0x2
Field Name
H_BLANK_START
Bits
Default
7:0
0x0
Description
These bits define the horizontal character count that
represents the character count in the active display area,
plus the right border. In other words, the count is from the
start of active display to the start of triggering of the H
blanking pulse.
Start Horizontal Blanking register.
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Graphics Controller Configuration Registers
CRT03 - RW - 8 bits - VGACRTIND:0x3
Bits
Default
Description
H_BLANK_END
Field Name
4:0
0x0
H blanking bits 4-0 respectively. These are the five
low-order bits (of six bits in total) of horizontal character
count for triggering the end of the horizontal blanking pulse.
H_DE_SKEW
6:5
0x0
Display-enable skew:
0=0Skew
1=1Skew
2=2Skew
3=3Skew
7
0x0
Compatibility Read:
0=WrtOnlyToCRT10-11
1=WrtRdToCRT10-11
CR10CR11_R_DIS_B
End Horizontal Blanking register.
CRT04 - RW - 8 bits - VGACRTIND:0x4
Field Name
H_SYNC_START
Bits
Default
7:0
0x0
Description
These bits define the horizontal character count at which
the horizontal retrace pulse becomes active.
Start Horizontal Retrace register.
CRT05 - RW - 8 bits - VGACRTIND:0x5
Field Name
Bits
Default
H_SYNC_END
4:0
0x0
H Retrace Bits (these are the 5-bit result from the sum of
CRT0 plus the width of the horizontal retrace pulse, in
character clock units).
H_SYNC_SKEW
6:5
0x0
H Retrace Delay bits (these two bits skew the horizontal
retrace pulse).
7
0x0
H blocking end bit 5 (this is the bit of the 6-bit character
count for the H blanking end pulse). The other five
low-order bits are CRT03[4:0].
H_BLANK_END_B5
Description
End Horizontal Retrace register.
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Graphics Controller Configuration Registers
CRT06 - RW - 8 bits - VGACRTIND:0x6
Field Name
V_TOTAL
Bits
Default
Description
7:0
0x0
These are the eight low-order bits of the 10-bit vertical total
register. The 2 high-order bits are CRT07[5:0] in the CRTC
overflow register. The value of this register represents the
total number of H raster scans plus vertical retrace (active
display, blanking), minus two scan lines.
Vertical Total register.
CRT07 - RW - 8 bits - VGACRTIND:0x7
Bits
Default
V_TOTAL_B8
Field Name
0
0x0
V Total Bit 8 (CRT06). Bit 8 of 10 bit vertical count for V
Total. For functional description see CRT06 register.
Description
V_DISP_END_B8
1
0x0
End V Display Bit 8 (CRT12). Bit 8 of 10-bit vertical count
for V Display enable. For functional description see CRT12
register.
V_SYNC_START_B8
2
0x0
Start V Retrace Bit 8 (CRT10). Bit 8 of 10-bit vertical count
for V Retrace start. For functional description see CRT10
register.
V_BLANK_START_B8
3
0x0
Start V Blanking Bit 8 (CRT15). Bit 8 of the 10-bit vertical
count for V Blanking start. For functional description see
CRT15 register.
LINE_CMP_B8
4
0x0
Line compare bit 8 (CRT18). Bit 8 of the 10-bit vertical count
for line compare. For functional description see CRT18
register.
V_TOTAL_B9
5
0x0
V Total Bit 9 (CRT06). Bit 9 of 10-bit vertical count for V
Total. For functional description see CRT06 register.
V_DISP_END_B9
6
0x0
End V Display Bit 9 (CRT12). Bit 9 of 10-bit vertical count
for V Display enable end (for functional description see
CRT12 register).
V_SYNC_START_B9
7
0x0
Start V Retrace Bit (CRT10). Bit 9 of 10-bit vertical count for
V Retrace start. For functional description see CRT10
register.
CRTC Overflow register.
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Graphics Controller Configuration Registers
CRT08 - RW - 8 bits - VGACRTIND:0x8
Bits
Default
Description
ROW_SCAN_START
Field Name
4:0
0x0
Preset row scan bit 4:0. This register is used for
software-controlled vertical scrolling in text or graphics
modes. The value specifies the first line to be scanned after
a V retrace (in the next frame). Each H Retrace pulse
increments the counter by 1, up to the maximum scan line
value programmed by CRT09, then the counter is cleared.
BYTE_PAN
6:5
0x0
Byte panning control bits 1 and 0 (respectively). Bits 6 and 5
extend the capability of byte panning (shifting) by up to
three characters (for description H_PEL Panning register
ATTR13).
Preset Row Scan register.
CRT09 - RW - 8 bits - VGACRTIND:0x9
Field Name
Bits
Default
4:0
0x0
Maximum scan line bits. These bits define a value that is
the actual number of scan line per character minus 1.
V_BLANK_START_B9
5
0x0
Start V Blanking bit 9 (CRT15). Bit 9 of 10-bit vertical count
for line compare. For functional description see CRT18
register.
LINE_CMP_B9
6
0x0
Line Compare Bit 9 (CRT18). Bit 9 of 10-bit vertical count
for line compare. For functional description see CRT18
register.
DOUBLE_CHAR_HEIGHT
7
0x0
200/400 line scan. Note: H/V display and blanking timings
etc. (in CRT00-CRT06 registers) are not affected.
0=200LineScan
1=400LineScan
MAX_ROW_SCAN
Description
Maximum Scan Line register.
CRT0A - RW - 8 bits - VGACRTIND:0xA
Field Name
CURSOR_START
CURSOR_DISABLE
Bits
Default
Description
4:0
0x0
Cursor start bits [4:0] (respectively). These bits define a
value that is the starting scan line (on a character row) for
the line cursor. The 5-bit value is equal to the actual number
minus one. This value is used together with the Cursor End
Bits CRT0B[4:0] to determine the height of the cursor. The
cursor height in VGA does not wrap around (as in EGA) and
is actually absent when the 'end' value is less than the 'start'
value. In EGA when the 'end' value is less, the cursor is a
full block cursor the same height as the character cell.
5
0x0
Cursor on/off.
0=On
1=Off
Cursor Start register.
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Graphics Controller Configuration Registers
CRT0B - RW - 8 bits - VGACRTIND:0xB
Bits
Default
Description
CURSOR_END
Field Name
4:0
0x0
Cursor end bits [4:0] (respectively). These bits define the
ending scan row (on a character line) for the line cursor. In
EGA, this 5-bit value is equal to the actual number of lines
plus one. The cursor height in VGA does not wrap around
(as in EGA) and is actually absent when the 'end' value is
less than the 'start' value. In EGA when the 'end' value is
less, the cursor is a full block cursor the same height as the
character cell.
CURSOR_SKEW
6:5
0x0
Cursor skew bits [1:0] (respectively). These bits define the
number of characters the cursor is to be shifted to the right
(skewed) from the character pointed at by the cursor
location (registers CRT0E and CRT0F), in VGA mode.
Skew values, when in EGA mode, are enclosed in brackets.
Cursor End register.
CRT0C - RW - 8 bits - VGACRTIND:0xC
Field Name
DISP_START
Bits
Default
Description
7:0
0x0
SA bits [15:8]. These are the eight high-order bits of the
16-bit display buffer start location. The low order bits are
contained in CRT0D. In split screen mode, CRT0C =
CRT0D point to the starting location of screen A (top half) .
The starting address for screen B is always zero.
Start Address (High Byte) register.
CRT0D - RW - 8 bits - VGACRTIND:0xD
Field Name
DISP_START
Bits
Default
Description
7:0
0x0
SA bits [7:0]. These are the eight low-order bits of the 16-bit
display buffer start location. The high-order bits are
contained in CRT0C. In split screen mode, CRT0C +
CRT0D points to the starting location of screen A (top half.)
The starting address for screen B is always zero.
Start Address (Low Byte) register.
CRT0E - RW - 8 bits - VGACRTIND:0xE
Field Name
CURSOR_LOC_HI
Bits
Default
Description
7:0
0x0
CA bits [15:8]. These are the eight high-order bits of the 16
bit cursor start address. The low-order CA bits are
contained in CRT0F. This address is relative to the start of
the physical display memory address pointed to by CRT0C
+ CRT0D. In other words, if CRT0C + CRT0D is changed,
the cursor still points to the same character as before.
Cursor Location (High Byte) register.
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Graphics Controller Configuration Registers
CRT0F - RW - 8 bits - VGACRTIND:0xF
Field Name
CURSOR_LOC_LO
Bits
Default
Description
7:0
0x0
CA bits [7:0]. These are the eight low-order bits of the 16-bit
cursor start address. The high-order CA bits are contained
in CRT0E. This address is relative to the start of the
physical display memory address pointed to by CRT0C +
CRT0D. In other words, if CRT0C + T0D is changed, the
cursor still points to the same character as before.
Cursor Location (Low Byte) register.
CRT10 - RW - 8 bits - VGACRTIND:0x10
Field Name
V_SYNC_START
Bits
Default
Description
7:0
0x0
Bits CRT10[7:0] are the eight low-order bits of the 10-bit
vertical retrace start count. The two high-order bits are
CRTt07[2:7], located in the CRTC overflow register. These
bits define the horizontal scan count that triggers the V
retrace pulse.
Start Vertical Retrace register.
CRT11 - RW - 8 bits - VGACRTIND:0x11
Field Name
Bits
Default
Description
V_SYNC_END
3:0
0x0
V Retrace End Bits [3:0]. Bits CRT11[0:3] define the
horizontal scan count that triggers the end of the V Retrace
pulse.
V_INTR_CLR
4
0x0
V Retrace Interrupt Set:
0=VRetraceIntCleared
1=Not Cleared
V_INTR_EN
5
0x0
V Retrace Interrupt Disabled:
0=VRetraceIntEna
1=Disable
SEL5_REFRESH_CYC
6
0x0
C0T7_WR_ONLY
7
0x0
0=3 DRAM Refresh/Horz Line
1=5 DRAM Refresh/Horz Line
Write Protect (CRT00-CRT06). All register bits, except
CRTO7[4], are write protected.
0=EnaWrtToCRT00-07
1=C0T7B4WrtOnly
End Vertical Retrace register.
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Graphics Controller Configuration Registers
CRT12 - RW - 8 bits - VGACRTIND:0x12
Field Name
V_DISP_END
Bits
Default
Description
7:0
0x0
These are the eight low-order bits of the 10-bit register
containing the horizontal scan count indicating where the
active display on the screen should end. The high-order bits
are CRT07 [1:6] in the CRT overflow register.
Vertical Display Enable End register.
CRT13 - RW - 8 bits - VGACRTIND:0x13
Field Name
DISP_PITCH
Bits
Default
Description
7:0
0x0
These bits define an offset value, equal to the logical line
width of the screen (from the first character of the current
line to the first character of the next line). Memory
organization is dependent on the video mode. Bit CRT17[6]
selects either byte or word mode. Bit CRT14[6], which
overrides the byte/word mode setting, selects double-word
mode when it is logical one. The first character of the next
line is specified by the start address (CRT0C + CRT0D),
plus the offset. The offset for byte mode is 2x CRT13, for
word mode it is 4x, and for double word mode it is 8x.
Offset register.
CRT14 - RW - 8 bits - VGACRTIND:0x14
Field Name
Bits
Default
Description
4:0
0x0
H Row Scan Bits [4:0]. These bits define the horizontal scan
row, from the top of the characterline, that should be used
for underlining. The 5-bit value is equal to the actual
number, minus one.
ADDR_CNT_BY4
5
0x0
Count-by-4:
0=Char. Clock
1=CountBy4
DOUBLE_WORD
6
0x0
Double-Word Mode:
0=Disable
1=DoubleWordMdEna
UNDRLN_LOC
Underline Location register.
CRT15 - RW - 8 bits - VGACRTIND:0x15
Field Name
V_BLANK_START
Bits
Default
Description
7:0
0x0
These are the eight low-order bits of the 10-bit vertical
blanking start register. Bit [9] is CRT09[5]; and bit [8] is
CRT07[3]. The 10 bits specify the starting location of the
vertical blanking pulse, in units of horizontal scan lines. The
value is equal to the actual number of displayed lines,
minus one.
Start Vertical Blanking register.
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Graphics Controller Configuration Registers
CRT16 - RW - 8 bits - VGACRTIND:0x16
Field Name
V_BLANK_END
Bits
Default
Description
7:0
0x0
These bits define the point at which the end of the vertical
blanking pulse needs to be triggered. The location is
specified in units of horizontal scan lines. The value to be
stored in this register is the seven low-order bits of the sum
of 'pulse width count' plus the content of Start Vertical
Blanking register (CRT15), minus one.
End Vertical Blanking register.
CRT17 - RW - 8 bits - VGACRTIND:0x17
Field Name
RA0_AS_A13B
Bits
Default
0
0x0
Compatibility Mode.
Description
RA1_AS_A14B
1
0x0
Select Row Scan Counter.
VCOUNT_BY2
2
0x0
Vertical_by_2.
Note: When bit [2] is logical one, other vertical register
values should be adjusted as well (CRT06, CRT10, CRT12,
CRT15, and CRT18).
ADDR_CNT_BY2
3
0x0
Count_by_2.
Note: This bit can be written to, and read from, but it has no
effect.
WRAP_A15TOA0
5
0x0
Address Wrap.
Note: This bit can be written to, and read from, but it has no
effect.
BYTE_MODE
6
0x0
Byte/Word Mode.
0=WordMode
1=ByteMode
CRTC_SYNC_EN
7
0x0
H/V Retrace Enable.
0=Disable HVSync
1=EnaHVSync
CRT Mode register.
CRT18 - RW - 8 bits - VGACRTIND:0x18
Field Name
LINE_CMP
Bits
Default
Description
7:0
0x0
These bits are the eight low-order of the 10-bit line compare
register. Bit [8] is CRT07[4], bit [9] is CRT09[6]. The value of
this register is used to disable scrolling on a portion of the
display screen, as when the split screen is active. When the
vertical counter reaches this value, the memory address
and row scan counters are cleared. The screen area above
the line specified by the register is commonly called screen
A. The screen below is screen B. Screen B cannot be
scrolled, but it can be panned only together with screen A,
controlled by the PEL panning compatibility bit ATTR10[5].
(For a description of this control bit see ATTR10[5].)
Line Compare register.
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Graphics Controller Configuration Registers
CRT1E - R - 8 bits - VGACRTIND:0x1E
Field Name
GRPH_DEC_RD1
Bits
Default
1
0x0
Description
This register is used to read back the graphics controller
index decode.
Graphics Controller Index Decode register.
CRT1F - R - 8 bits - VGACRTIND:0x1F
Field Name
GRPH_DEC_RD0
Bits
Default
7:0
0x0
Description
This register is used to read back the graphics controller
index decode.
Graphics Controller Index Decode register.
CRT22 - R - 8 bits - VGACRTIND:0x22
Field Name
GRPH_LATCH_DATA
Bits
Default
Description
7:0
0x0
This register is used to read the data in the Graphics
Controller CPU data latches. The Graphics Controller Read
Map Select register bits 0 and 1 determine which byte is
read back.
RAM Data Latch Readback register.
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Graphics Controller Configuration Registers
2.15 VGA Graphics
GRPH8_IDX - RW - 8 bits - [MMReg,VGA_IO:0x3CE]
Field Name
GRPH_IDX
Bits
3:0
Default
0x0
Description
GRPH8_DATA - RW - 8 bits - [MMReg,VGA_IO:0x3CF]
Field Name
GRPH_DATA
GRPH Data Register
Bits
7:0
Default
0x0
Description
GRPH data indirect access
GRA00 - RW - 8 bits - VGAGRPHIND:0x0
Field Name
Bits
Default
Description
GRPH_SET_RESET0
0
0x0
Set/Reset Map 0.
GRPH_SET_RESET1
1
0x0
Set/Reset Map 1.
GRPH_SET_RESET2
2
0x0
Set/Reset Map 2.
GRPH_SET_RESET3
3
0x0
Set/Reset Map 3.
Set/Reset register.
GRA01 - RW - 8 bits - VGAGRPHIND:0x1
Field Name
Bits
Default
Description
GRPH_SET_RESET_ENA0
0
0x0
Enables Set/Reset Map 0.
GRPH_SET_RESET_ENA1
1
0x0
Enables Set/Reset Map 1.
GRPH_SET_RESET_ENA2
2
0x0
Enables Set/Reset Map 2.
GRPH_SET_RESET_ENA3
3
0x0
Enables Set/Reset Map 3.
Enable Set/Reset register.
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Graphics Controller Configuration Registers
GRA02 - RW - 8 bits - VGAGRPHIND:0x2
Field Name
GRPH_CCOMP
Bits
Default
Description
3:0
0x0
Colour Compare Map bits [3:0]. In Read mode (GRA05[3]
being logical 1), the 4 bits from this register are compared
with the 4-bit PEL value (made up of one bit from each
map), from bit positions 0 through 7. As long as the colour
don't care bits (GRA07[0:3]) for the respective maps are
logical 1's, the compare takes place only on those bits of the
PEL value, and the CPU reads a one for a match in that bit
position. If the Colour Don't Care bit for one map is a logical
zero, the latched data from the map is excluded from the
compare, and only the remaining three bits are compared to
generate bus data.
Colour Compare register.
GRA03 - RW - 8 bits - VGAGRPHIND:0x3
Field Name
Bits
Default
Description
GRPH_ROTATE
2:0
0x0
Rotate Count Bits [2:0]. Specifies the number of bit
positions that the CPU data is to be rotated to the right,
before doing the function selected by bits 3 and 4 above
and subsequency bit mask select and write operations.
Rotation is carried out only in write modes 0 and 3. In these
two modes, the CPU data is rotated first, the operated only
the function bits GRA03[4:3], the updated by the bit mask
register GRA05.
GRPH_FN_SEL
4:3
0x0
Function Select Bits 1 and 2. These functions are
performed on the CPU data before the selected bits are
updated by the bit mask register, and then written to the
display buffers.
0=Replace
1=AND
2=OR
3=XOR
Data Rotate register.
GRA04 - RW - 8 bits - VGAGRPHIND:0x4
Field Name
GRPH_RMAP
Bits
Default
Description
1:0
0x0
Read Mode 0 Only. The GRA controller returns the contents
of one of the four latched buffer bytes to the CPU each time
a CPU read loads these latches. The 2 bits (0 and 1) define
a value that represents the bit map where the CPU is to
read data. This is useful in transferring bit map data
between the maps and the system RAM.
Read Map Select register.
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Graphics Controller Configuration Registers
GRA05 - RW - 8 bits - VGAGRPHIND:0x5
Field Name
Bits
Default
1:0
0x0
Write Mode:
0=Write mode 0
1=Write mode 1
2=Write mode 2
3=Write mode 3
GRPH_READ1
3
0x0
Read Mode:
0=Read mode 0, byte oriented
1=Read mode 1, pixel oriented
CGA_ODDEVEN
4
0x0
Odd/Even Addressing Enable. Used to enable CGA
emulation, this bit enables off/even addressing mode when
it is a logical one. Normally, this bit and memory mode bit
SEQ04[2] are set to agree with each other in enabling
odd/even mode emulation.
0=Disable Odd/Even Addressing
1=Enable Odd/Even Addressing
GRPH_OES
5
0x0
Shift Register Mode. This bit controls how data from
memory is loaded into the shift registers M0D0:M0D7,
M1D0:M1D7; M2D0:M2D7, and M3D0:M3D7 are
representations of this data.
0=Linear shift mode
1=Tiled shift mode
GRPH_PACK
6
0x0
256 Colour Mode. This bit also controls how data from
memory is loaded into the shift registers.
0=Use shift register mode as per GRPH_OES
1=256 color mode, read as packed pixels, ignore
GRPH_OES
GRPH_WRITE_MODE
Description
Graphics Mode register.
GRA06 - RW - 8 bits - VGAGRPHIND:0x6
Bits
Default
GRPH_GRAPHICS
Field Name
0
0x0
Graphics/Alphanumeric Mode
0=Alpha Numeric Mode
1=Graphics Mode
GRPH_ODDEVEN
1
0x0
Chains Odd Maps to Even
0=Normal
1=Chain Odd maps to Even
3:2
0x0
Memory Map Read Bits 1 and 0, respectively.
0=A0000-128K
1=A0000-64K
2=B0000-32K
3=B8000-32K
GRPH_ADRSEL
Description
Graphics Miscellaneous register.
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Graphics Controller Configuration Registers
GRA07 - RW - 8 bits - VGAGRPHIND:0x7
Bits
Default
GRPH_XCARE0
Field Name
0
0x0
Ignore Map 0
0=Ignore map 0
1=Use map 0 for read mode 1
Description
GRPH_XCARE1
1
0x0
Ignore Map 1
0=Ignore map 1
1=Use map 1 for read mode 1
GRPH_XCARE2
2
0x0
Ignore Map 2
0=Ignore map 2
1=Use map 2 for read mode 1
GRPH_XCARE3
3
0x0
Ignore Map 3
0=Ignore map 3
1=Use map 3 for read mode 1
Colour Don't Care register.
GRA08 - RW - 8 bits - VGAGRPHIND:0x8
Field Name
GRPH_BMSK
Bits
Default
7:0
0x0
Description
Bit Mask.
Bit Mask register.
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Graphics Controller Configuration Registers
2.16 VGA Attribute
ATTRX - RW - 8 bits - VGA_IO:0x3C0
Field Name
ATTR_IDX
ATTR_PAL_RW_ENB
Bits
Default
Description
4:0
0x0
ATTR Index. This index points to one of the internal
registers of the attribute controller (ATTR) at addresses
0x3C1/0x3C0, for the next ATTR read/write operation.
Since both the index and data registers are at the same I/O,
a pointer to the registers is necessary. This pointer can be
initialized to point to the index register by a read of GENS1.
5
0x0
Palette Address Source. After loading the colour palette,
this bit should be set to logical 1.
0=Processor to load
1=Memory data to access
Attribute Index register.
ATTRDW - W - 8 bits - VGA_IO:0x3C0
Field Name
ATTR_DATA
Bits
Default
7:0
0x0
Description
Attribute Data Write.
Attribute Data Write register.
ATTRDR - R - 8 bits - VGA_IO:0x3C1
Field Name
ATTR_DATA
Bits
Default
7:0
0x0
Description
Attribute Data Read.
Attribute Data Read register.
ATTR00 - RW - 8 bits - VGAATTRIND:0x0
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 0.
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Graphics Controller Configuration Registers
ATTR01 - RW - 8 bits - VGAATTRIND:0x1
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 1.
ATTR02 - RW - 8 bits - VGAATTRIND:0x2
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 2.
ATTR03 - RW - 8 bits - VGAATTRIND:0x3
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 3.
ATTR04 - RW - 8 bits - VGAATTRIND:0x4
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 4.
ATTR05 - RW - 8 bits - VGAATTRIND:0x5
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 5.
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Graphics Controller Configuration Registers
ATTR06 - RW - 8 bits - VGAATTRIND:0x6
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 6.
ATTR07 - RW - 8 bits - VGAATTRIND:0x7
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 7.
ATTR08 - RW - 8 bits - VGAATTRIND:0x8
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 8.
ATTR09 - RW - 8 bits - VGAATTRIND:0x9
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register 9.
ATTR0A - RW - 8 bits - VGAATTRIND:0xA
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register Ah (10).
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Graphics Controller Configuration Registers
ATTR0B - RW - 8 bits - VGAATTRIND:0xB
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register Bh (11).
ATTR0C - RW - 8 bits - VGAATTRIND:0xC
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register Ch (12).
ATTR0D - RW - 8 bits - VGAATTRIND:0xD
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register Dh (13).
ATTR0E - RW - 8 bits - VGAATTRIND:0xE
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register Eh (14).
ATTR0F - RW - 8 bits - VGAATTRIND:0xF
Field Name
ATTR_PAL
Bits
Default
5:0
0x0
Description
Colour Bits [5:0] map the text attribute or graphics colour
input value to a display colour on the screen. Colour is
disabled for those bits that are set to logical 0, and is
enabled for those bits set to logical 1.
Palette register Fh (15).
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Graphics Controller Configuration Registers
ATTR10 - RW - 8 bits - VGAATTRIND:0x10
Bits
Default
ATTR_GRPH_MODE
Field Name
0
0x0
Graphics/Alphanumeric Mode.
0=Alphanumeric Mode
1=Graphic Mode
Description
ATTR_MONO_EN
1
0x0
Monochrome/Colour Attributes Select:
0=Color Disp
1=MonoChrome Disp
ATTR_LGRPH_EN
2
0x0
Line Graphics Enable. Must be 0 for character fonts that do
not use line graphics character codes for graphics. Zero will
force the 9th dot to the background colour. One will allow
the 8th bit of the line graphics characters to be stretched to
the 9th dot.
0=Disable line graphics 8th dot stretch
1=Enable line graphics 8th dot stretch
ATTR_BLINK_EN
3
0x0
Blink Enable/Background Intensity:
Selects whether bit [7] of the attribute controls intensity or
blinking.
0=Intensity control
1=Blink control
ATTR_PANTOPONLY
5
0x0
PEL Panning Compatibility:
0=Panning both
1=Panning only the top half screen
ATTR_PCLKBY2
6
0x0
PEL Clock Select:
0=Shift register clocked every dot clock
1=For mode 13 (256 colour), 8 bits packed to form a
pixel
ATTR_CSEL_EN
7
0x0
Alternate Colour Source:
0=Select ATTR00-0F bit 5:4 as P5 and P4
1=Select ATTR14 bit 1:0 as P5 and P4
Mode Control register.
ATTR11 - RW - 8 bits - VGAATTRIND:0x11
Field Name
ATTR_OVSC
Bits
Default
7:0
0x0
Description
Overscan Colour.
Overscan Colour register.
ATTR12 - RW - 8 bits - VGAATTRIND:0x12
Field Name
ATTR_MAP_EN
Bits
Default
3:0
0x0
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Description
Enables Colour Map bits.
0=Disables data from respective map from being used
for video output.
1=Enables data from respective map for use in video
output.
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Graphics Controller Configuration Registers
ATTR_VSMUX
5:4
0x0
Video Status Mux bits 1:0. These are control bits for the
multiplexer on colour bits P0-P7. The bit selection is also
indicated at GENS1[5:4]:
00=P2, P0
01=P5, P4
10=P3, P1
11=P7, P6
Colour Map Enable register.
ATTR13 - RW - 8 bits - VGAATTRIND:0x13
Field Name
ATTR_PPAN
Bits
Default
3:0
0x0
Description
Shift Count Bits 3:0. The shift count value (0-8) indicates
how many pixel positions to shift left.
Count
Value
0
1
2
3
4
5
6
7
8
Shift in respective modes
0+,1+,2+,13
All other
3+,7,7+
1
0
2
3
1
4
5
2
6
7
3
8
0
-
0
1
2
3
4
5
6
7
-
Horizontal PEL Panning register.
ATTR14 - RW - 8 bits - VGAATTRIND:0x14
Field Name
Bits
Default
Description
ATTR_CSEL1
1:0
0x0
Colour bits P5 and P4, respectively. These are the colour
output bits (instead of bits 5 and 4 of the internal palette
registers ATTR00-0F) when the alternate colour source, bit
ATTR10[7], is logical 1.
ATTR_CSEL2
3:2
0x0
Colour bits P7 and P6, respectively. These two bits are the
two high-order bits of the 8-bit colour, used for rapid colour
set switching (addressing different parts of the DAC colour
lookup table). The lower order bits are in registers
ATTR00-0F.
Colour Select register.
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Graphics Controller Configuration Registers
2.17 TV Out
SD1_MAIN_CNTL - RW - 32 bits - [MMReg:0x5DFC]
Field Name
SD1_TV_ASYNC_RST
Bits
0
Default
0x1
SD1_RESYNC_ALWAYS
1
0x1
SD1_RESET_SCPHASE_TRIGGER
2
0x0
SD1_FIELD_SYNC_TRIGGER
3
0x0
5:4
0x0
6
0x1
SD1_FIELD_SYNC_CNTL
SD1_ALT_PHASE_EN
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Description
This is an asynchronous reset for the SDTV1 encoder
which gets retimed by TV1_CLK.
0=Normal operation
1=Hold the SDTV1 encoder at initialization state
This bit determines whether the SDTV1 encoder responds
to the secondary display synchronization pulse,
SD1_FRAME_SYNC_PULSE. This pulse synchronizes the
SDTV1 timing to the secondary display by setting the
values listed in SD1_TIMING_H_COUNT_INIT,
SD1_TIMING_V_F_COUNT_INIT, and
SD1_TIMING_INTERNAL_INIT.
The retimed low to high transition of this bit will cause the
SDTV1 sub-carrier sinusoidal to reset to zero, once, at the
next SD1_FRAME_SYNC_PULSE occurrence. The
tolerance of the separation of sub-carrier zero crossing and
horizontal sync falling edge is +/- 40 degrees of sub-carrier.
With pixel 0 marking the horiz. sync falling edge, adjustment
of SD1_TIMING_H_COUNT_INIT.SD1_H_COUNT_INIT
and the equivalent
CRTC1_BACKEND_INIT_CNTL.CRTC1_BACKEND_INIT
_X_START with the application of this trigger will change
the separation. The formula is as follows:
Hsync-SC separation in degrees =
(modulo((SD1_H_COUNT_INIT + 2)/12)/12) * (-360) or
(modulo((SD1_H_COUNT_INIT + 2)/12)/12) * (360) if
modulo is less than 6.
The first occurrence of SD1_FRAME_SYNC_PULSE after
SD1_TV_ASYNC_RST goes low will also reset the
sub-carrier sinusoidal and cause the same action.
If SD1_MAIN_CNTL.SD1_FIELD_SYNC_CNTL = 1, the
retimed low to high or high to low transition of this bit will
cause the current SDTV1 field to repeat once. As an
alternative to the hardware method,
SD1_MAIN_CNTL.SD1_FIELD_SYNC_CNTL = 2 or 3, if
software detects that the SDTV1 encoder is not on the
same odd or even field as the incoming data, the use of the
trigger will force an encoder repeat field and restore field
synchronization
This register controls SDTV1 encoder field manipulation for
the purpose of field synchronization to upstream data in
interlaced modes. Specifically the next encoded field will
have the same polarity as the current one, causing an
odd-odd or even-even sequence forcing a field sync.
This bit, when set, causes the SDTV1 encoder sub-carrier
phase to alternate +/- 45 degrees between lines for the PAL
operation standards.
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Graphics Controller Configuration Registers
SD1_INVERT_ALT_LINE
7
0x0
SD1_MISC_REGS_LOCK
8
0x0
10:9
0x0
SD1_VBI_PASSTHRU_EN
11
0x0
SD1_YPBPR_480I_EN
12
0x0
SD1_YPBPR_480P_EN
13
0x0
SD1_MISC_DOUBLEB_REGS_CNTL
© 2007 Advanced Micro Devices, Inc.
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This bit determines the phase that the sub-carrier gets
assigned at the first occurrence of
SD1_FRAME_SYNC_PULSE after SD1_TV_ASYNC_RST
goes low if
SD1_SDTV0_DEBUG.SD1_SDTV0_DEBUG(16) = 0 or at
every SD1_FRAME_SYNC_PULSE occurrence if
SD1_SDTV0_DEBUG.SD1_SDTV0_DEBUG(16) = 1.
Default of 0 is the normal setting.
This bit allows software to lock out the update of the
buffered version of various registers that could be changed
on the fly during normal operation. This would prevent
undetermined response of the controlled circuits because of
otherwise asynchronous updates. The registers affected by
this lock are: SD1_COL_SC_DENOMIN,
SD1_COL_SC_INC, SD1_COL_SC_INC_CORR,
SD1_SCM_COL_SC_DENOMIN,
SD1_SCM_COL_SC_INC,
SD1_SCM_COL_SC_INC_CORR,
SD1_MAIN_CNTL.SD1_INVERT_ALT_LINE,
SD1_LUMA_COMB_FILT_CNTL1.SD1_COMB_EN, and in
register SD1_SCM_MOD_CNTL fields
SD1_SCM_RST_DTO_ON_BLANK,
SD1_SCM_INVERT_PHASE_EN,
SD1_INVERT_SCM_3LINE, SD1_SCM_3LINE_INIT, and
SD1_SCM_2LINE_EN
Selects at which pixel in the SDTV1 frame the registers
listed under SD1_MISC_REGS_LOCK will be updated to
their buffered versions.
Setting this bit high will allow the SDTV1 encoder to treat
the Y data in the window as defined by registers
SD1_TIMING_H_VBI_PASSTHRU,
SD1_TIMING_V_VBI_PASSTHRU1, and
SD1_TIMING_V_VBI_PASSTHRU2 as Vertical Blank
Interval data services. Other than applying the gain as set
by
SD1_Y_AND_PASSTHRU_GAIN_SETTINGS.SD1_VBI_P
ASSTHRU_GAIN and filtering as set by
SD1_TIMING_H_VBI_PASSTHRU_FILT_WINDOW,
SD1_LUMA_FILT_CNTL.SD1_COMP_PASSTHRU_BLEN
D and SD1_SVID_PASSTHRU_BLEND, no other encoder
function is applied to the data.
Setting this bit high will put the SDTV1 encoder into the
Component 480 Interlaced operational mode. The YUV
input data will be treated as YPbPr and each component
will have the option of running through a simple 9 tap slew
filter or passing straight through to the output, selectable by
SD1_LUMA_FILT_CNTL.SD1_INSIDE_ACTIVE_SLEW_E
N.
Setting this bit high will put the SDTV1 encoder into the
Component 480 Progressive operational mode. The YUV
input data will be treated as YPbPr and each component
will have the option of running through a simple 5 tap slew
filter or passing straight through to the output, selectable by
SD1_LUMA_FILT_CNTL.SD1_INSIDE_ACTIVE_SLEW_E
N.
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_RGB_OUTPUT_EN
14
0x0
SD1_BLANK_ON_RB_SEL
15
0x0
SD1_PATTERN_GEN_EN
16
0x0
SD1_PATTERN_GEN_SEL
19:17
0x0
SD1_PIX_DELAY
25:20
0x2
26
27
0x0
0x0
SD1_ALT_PHASE_RST_ON_SYNC
SD1_PIX_DELAY_SEL
Setting this bit high will allow the SDTV1 encoder to
generate a RGB (with sync on green) version of the NTSC
or PAL standard mode. The U and V data will have the color
burst suppressed as well as pipeline delayed to match Y
data for YUV to RGB conversion. The U and V data has the
standard lowpass filtering, while the Y data filtering is
controlled by
SD1_LUMA_FILT_CNTL.SD1_SVIDY_OUT_BLEND.
Selecting the RGB data for output to the DACs is set
through register SD1_VIDOUT_MUX_CNTL.
This controls the blank level of the Red and Blue outputs if
SDTV1 is generating RGB outputs,
SD1_RGB_OUTPUT_EN = 1. Only the Green output has
the sync and will have the normal luma blank level as
specified in SD1_LUMA_BLANK_SETUP_LEVELS.
Controls the application of the internal pattern generator for
the SDTV1 encoder.
Selects the type of test pattern for the SDTV1 encoder if
SD1_PATTERN_GEN_EN = 1.
Used to align the Luma and Chroma pipelining delays
through the SDTV1 encoder. Either the Luma, Y data, or
modulated Chroma, as selected by SD1_PIX_DELAY_SEL,
is delayed from 0 to 16 TV1_CLK periods as indicated.
Used to select what will be delayed by SD1_PIX_DELAY
TV1_CLK periods.
SD1_Y_1024_DATAIN_EN
29:28
0x0
Controls the manipulation of Y data at the input of the
SDTV1 encoder to accommodate different data ranges.
00=Consider the input Y data range as 512, so multiply Y
data by 2
01=Consider the input Y data range as 1024, so pass Y
data untouched
02=Consider the input Y data range as 512 with -512
offset, so multiply Y data by 2 and add 512
03=Consider the input Y data range as 1024 with a -512
offset, so pass Y data with an addition of 512
SD1_U_1024_DATAIN_EN
30
0x0
Controls the manipulation of U data at the input of the
SDTV1 encoder to accommodate different data ranges.
00=Consider the input U data range based on 512, so
multiply U data by 2
01=Consider the input U data range based on 1024, so
pass U data untouched
SD1_V_1024_DATAIN_EN
31
0x0
Controls the manipulation of V data at the input of the
SDTV1 encoder to accommodate different data ranges.
00=Consider the input V data range based on 512, so
multiply V data by 2
01=Consider the input V data range based on 1024, so
pass V data untouched
This register contains a collection of various control bits for the second Standard Definition TV Encoder known as SDTV1
SD1_TIMING_H_TOTAL - RW - 32 bits - [MMReg:0x5E04]
Field Name
SD1_H_TOTAL
Bits
11:0
Default
0xd4c
Description
Total number of pixels in each SDTV1 scan line =
SD1_H_TOTAL + 1
This register specifies the number of pixels per SDTV1 encoded line
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_TIMING_V_F_TOTAL - RW - 32 bits - [MMReg:0x5E08]
Field Name
SD1_V_TOTAL
Bits
10:0
Default
0x270
Description
Total number of lines in each SDTV1 frame =
SD1_V_TOTAL + 1. A frame is defined as two fields for
interlaced modes.
SD1_F_TOTAL
19:16
0x7
Total number of fields in each SDTV1 sequence =
SD1_F_TOTAL + 1. The sequence is the number of fields
required before the sub-carrier phase repeats, 4 fields in
NTSC, 8 fields in PAL.
This register specifies the number of lines per frame and fields per sequence for SDTV1
SD1_TIMING_H_COUNT - RW - 32 bits - [MMReg:0x5E0C]
Field Name
SD1_H_COUNT (R)
Bits
11:0
Default
0x0
Description
Read only field indicating the current horizontal pixel within
the SDTV1 line being processed.
This register specifies the current SDTV1 horizontal TV1_CLK pixel count
SD1_TIMING_V_F_COUNT - RW - 32 bits - [MMReg:0x5E10]
Field Name
SD1_V_COUNT (R)
Bits
10:0
Default
0x0
SD1_F_COUNT (R)
19:16
0x0
This register specifies the current SDTV1 line and field counts
Description
Read only field indicating the current SDTV1 encoder line
being processed.
Read only field indicating the current SDTV1 encoder field
being processed.
SD1_TIMING_H_COUNT_INIT - RW - 32 bits - [MMReg:0x5E14]
Field Name
SD1_H_COUNT_INIT
Bits
11:0
Default
0xa
This register specifies the initial SDTV1 horizontal pixel count
Description
Indicates the value that the horizontal pixel counter gets set
to during reset, SD1_MAIN_CNTL.SD1_TV_ASYNC_RST
= 1, or at frame synchronization,
SD1_FRAME_SYNC_PULSE = 1.
SD1_TIMING_V_F_COUNT_INIT - RW - 32 bits - [MMReg:0x5E18]
Field Name
SD1_V_COUNT_INIT
Bits
10:0
Default
0x26e
SD1_F_COUNT_INIT
19:16
0x7
This register specifies the initial SDTV1 line and field counts
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Indicates the line counter value set during reset,
SD1_MAIN_CNTL.SD1_TV_ASYNC_RST = 1, or at frame
synchronization, SD1_FRAME_SYNC_PULSE = 1.
Indicates the field counter value set during reset,
SD1_MAIN_CNTL.SD1_TV_ASYNC_RST = 1, or at frame
synchronization, SD1_FRAME_SYNC_PULSE = 1.
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_TIMING_INTERNAL_INIT - RW - 32 bits - [MMReg:0x5E1C]
Field Name
SD1_H_HSYNC_INIT
Bits
0
Default
0x1
Description
Initial value of signal indicating the pixel position of the
horizontal synchronization pulse.
SD1_V_HSYNC_INIT
1
0x1
Initial value of signal indicating the lines that contain
horizontal synchronization pulses.
SD1_H_EQ_PULSE_INIT
2
0x0
Initial value of signal indicating the horizontal pixel positions
of the equalization pulses.
SD1_H_SER_PULSE_INIT
3
0x0
Initial value of signal indicating the horizontal pixel positions
of the seration pulses.
SD1_V_EQ_SER_INIT
4
0x1
Initial value of signal indicating the lines that contain
equalization or seration pulses.
SD1_V_SER_INIT
5
0x0
Initial value of signal indicating the lines that contain
seration pulses.
SD1_H_BURST_INIT
6
0x0
Initial value of signal indicating the horizontal pixel position
of the sub-carrier burst.
SD1_V_BURST_INIT
7
0x0
Initial value of signal indicating the lines that contain
sub-carrier bursts.
SD1_H_SETUP_INIT
8
0x0
Initial value of signal indicating the horizontal pixel position
of data with setup in NTSC or the maximum excursion of
data in other standards.
SD1_V_SETUP_INIT
9
0x1
Initial value of signal indicating the lines that have setup in
NTSC or the maximum possible excursion of lines with
active data in other standards.
SD1_V_ACTIVE_INIT
10
0x1
Initial value of signal indicating the lines that have active
data.
This register specifies the initial values of various internal SDTV1 timing controls. These values are set during reset,
SD1_MAIN_CNTL.SD1_TV_ASYNC_RST = 1, or at frame synchronization, SD1_FRAME_SYNC_PULSE = 1. The particular
field is set active high if the positioning of the initial pixel within the frame, as indicated by SD1_H_COUNT_INIT,
SD1_V_COUNT_INIT, and SD1_F_COUNT_INIT, would mean that the indicated control should be active, ex.
SD1_H_HSYNC_INIT=1 if SD1_H_HSYNC_START < SD1_H_COUNT_INIT <= SD1_H_HSYNC_END and
SD1_V_COUNT_INIT is outside the SD1_TIMING_V_EQUALIZATION lines.
SD1_TIMING_H_HSYNC - RW - 32 bits - [MMReg:0x5E20]
Field Name
SD1_H_HSYNC_START
Bits
11:0
Default
0x0
Description
The first pixel of the horizontal synchronization pulse in
terms of TV1_CLK pixel count is SD1_H_HSYNC_START
+ 1.
SD1_H_HSYNC_END
27:16
0xfa
Indicates the last pixel of the horizontal synchronization
pulse in terms of TV1_CLK pixel count.
This register indicates the timing points of the SDTV1 endcoder horizontal synchronization pulse
SD1_TIMING_H_EQUALIZATION1 - RW - 32 bits - [MMReg:0x5E24]
Field Name
SD1_H_EQ_PULSE_START1
Bits
11:0
Default
0x0
Description
The first pixel of the first equalization pulse in terms of
TV1_CLK pixel count is SD1_H_EQ_PULSE_START1 + 1.
SD1_H_EQ_PULSE_END1
27:16
0x7d
Indicates the last pixel of the first equalization pulse in
terms of TV1_CLK pixel count.
This register indicates the horizontal timing points of the first equalization pulse on the SDTV1 endcoder line.
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Proprietary
Graphics Controller Configuration Registers
SD1_TIMING_H_EQUALIZATION2 - RW - 32 bits - [MMReg:0x5E28]
Field Name
SD1_H_EQ_PULSE_START2
Bits
11:0
Default
0x6a6
Description
The first pixel of the second equalization pulse in terms of
TV1_CLK pixel count is SD1_H_EQ_PULSE_START2 + 1.
SD1_H_EQ_PULSE_END2
27:16
0x723
Indicates the last pixel of the second equalization pulse in
terms of TV1_CLK pixel count.
This register indicates the horizontal timing points of the second equalization pulse on the SDTV1 endcoder line.
SD1_TIMING_H_SERATION1 - RW - 32 bits - [MMReg:0x5E2C]
Field Name
SD1_H_SER_PULSE_START1
Bits
11:0
Default
0x0
Description
The first pixel of the first seration pulse in terms of
TV1_CLK pixel count is SD1_H_SER_PULSE_START1 +
1.
SD1_H_SER_PULSE_END1
27:16
0x5ac
Indicates the last pixel of the first seration pulse in terms of
TV1_CLK pixel count.
This register indicates the horizontal timing points of the first seration pulse on the SDTV1 endcoder line.
SD1_TIMING_H_SERATION2 - RW - 32 bits - [MMReg:0x5E30]
Field Name
SD1_H_SER_PULSE_START2
Bits
11:0
Default
0x6a6
Description
The first pixel of the second seration pulse in terms of
TV1_CLK pixel count is SD1_H_SER_PULSE_START2 +
1.
SD1_H_SER_PULSE_END2
27:16
0xc52
Indicates the last pixel of the second seration pulse in terms
of TV1_CLK pixel count.
This register indicates the horizontal timing points of the second seration pulse on the SDTV1 endcoder line
SD1_TIMING_V_EQUALIZATION1 - RW - 32 bits - [MMReg:0x5E34]
Field Name
SD1_V_EQ_PULSE_START1
Description
SD1_V_EQ_PULSE_START1(10:1) indicates, in terms of
line count, the first line containing an equalization pulse for
the first field. If the LSB is 0, this first line has both
equalization pulses or if 1, then only the second pulse
(starts on second pulse).
SD1_V_EQ_PULSE_DUR1
26:15
0xf
SD1_V_EQ_PULSE_DUR1(4:1) + 1 indicates the number
of lines that contain equalization or seration pulses for the
first field, i.e. last line with a equalization pulse is
SD1_V_EQ_PULSE_START1(10:1) +
SD1_V_EQ_PULSE_DUR1(4:1). If the LSB is 0, this last
line has only the first equalization pulse or if 1, then both
pulses (ends on second pulse).
This register indicates the vertical timing points of the SDTV1 encoder equalization pulses in the first field
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
11:0
Default
0x4dd
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_TIMING_V_EQUALIZATION2 - RW - 32 bits - [MMReg:0x5E38]
Field Name
SD1_V_EQ_PULSE_START2
Bits
11:0
Default
0x26c
Description
SD1_V_EQ_PULSE_START2(10:1) indicates, in terms of
line count, the first line containing an equalization pulse for
the second field. If the LSB is 0, this first line has both
equalization pulses or if 1, then only the second pulse
(starts on second pulse).
SD1_V_EQ_PULSE_DUR2
26:15
0xe
SD1_V_EQ_PULSE_DUR2(4:1) + 1 indicates the number
of lines that contain equalization or seration pulses for the
second field, i.e. last line with a equalization pulse is
SD1_V_EQ_PULSE_START2(10:1) +
SD1_V_EQ_PULSE_DUR2(4:1). If the LSB is 0, this last
line has only the first equalization pulse or if 1, then both
pulses (ends on second pulse).
This register indicates the vertical timing points of the SDTV1 encoder equalization pulses in the second field
SD1_TIMING_V_SERATION1 - RW - 32 bits - [MMReg:0x5E3C]
Field Name
SD1_V_SER_PULSE_START1
Bits
11:0
Default
0x0
Description
SD1_V_SER_PULSE_START1(10:1) indicates, in terms of
line count, the first line containing a seration pulse for the
first field. If the LSB is 0, this first line has both seration
pulses or if 1, then only the second pulse (starts on second
pulse).
SD1_V_SER_PULSE_DUR1
26:15
0x4
SD1_V_SER_PULSE_DUR1(3:1) + 1 indicates the number
of lines that contain seration pulses for the first field, i.e. last
line with a seration pulse is
SD1_V_SER_PULSE_START1(10:1) +
SD1_V_SER_PULSE_DUR1(3:1). If the LSB is 0, this last
line has only the first seration pulse or if 1, then both pulses
(ends on second pulse).
This register indicates the vertical timing points of the SDTV1 encoder seration pulses in the first field
SD1_TIMING_V_SERATION2 - RW - 32 bits - [MMReg:0x5E40]
Field Name
SD1_V_SER_PULSE_START2
Bits
11:0
Default
0x271
Description
SD1_V_SER_PULSE_START2(10:1) indicates, in terms of
line count, the first line containing a seration pulse for the
second field. If the LSB is 0, this first line has both seration
pulses or if 1, then only the second pulse (starts on second
pulse).
SD1_V_SER_PULSE_DUR2
26:15
0x5
SD1_V_SER_PULSE_DUR2(3:1) + 1 indicates the number
of lines that contain seration pulses for the second field, i.e.
last line with a seration pulse is
SD1_V_SER_PULSE_START2(10:1) +
SD1_V_SER_PULSE_DUR2(3:1). If the LSB is 0, this last
line has only the first seration pulse or if 1, then both pulses
(ends on second pulse).
This register indicates the vertical timing points of the SDTV1 encoder seration pulses in the second field
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_TIMING_H_BURST - RW - 32 bits - [MMReg:0x5E44]
Field Name
SD1_H_BURST_START
Bits
11:0
Default
0x12a
Description
The first pixel of the sub-carrier burst in terms of TV1_CLK
pixel count is at SD1_H_BURST_START + 1. Note that for
the SECAM standard, this field indicates the start of an
advanced sub-carrier activation in order to suppress the
initial amplitude spike: SD1_H_BURST_START = Specified
SECAM sub-carrier pixel start - SD1_H_BURST_DUR.
SD1_H_BURST_DUR
23:16
0x78
SD1_H_BURST_DUR + 1 indicates the duration of the
sub-carrier burst in terms of number of TV1_CLK pixels.
The last sub-carrier burst pixel is at
SD1_H_BURST_START + SD1_H_BURST_DUR. Note
that for the SECAM standard, this field indicates the
duration in TV1_CLK pixels of the internal turn-on
sub-carrier spike suppression, see
SD1_H_BURST_START description. Usually set to 30 or
40 in SECAM.
This register indicates the horizontal timing points of the sub-carrier burst on the SDTV1 endcoder line
SD1_TIMING_V_BURST1 - RW - 32 bits - [MMReg:0x5E48]
Field Name
SD1_V_BURST_START1
Bits
10:0
Default
0x6
Description
Indicates the first line containing a sub-carrier burst in the
first field in terms of line count
SD1_V_BURST_END1
26:16
0x134
Indicates the last line containing a sub-carrier burst in the
first field in terms of line count
SD1_ALT_BURST_BLANK_EN
28
0x1
This bit enables a different vertical burst blanking sequence
for the third and fourth fields, as required in PAL systems.
SD1_ALT_V_BURST_START1
29
0x1
Adjusts the third field sub-carrier burst start line, ONLY if
SD1_ALT_BURST_BLANK_EN = 1, usually set to 1.
SD1_ALT_V_BURST_END1
30
0x0
Adjusts the third field sub-carrier burst end line, ONLY if
SD1_ALT_BURST_BLANK_EN = 1, usually set to 0.
This register indicates the vertical timing points of the SDTV1 encoder sub-carrier bursts in the first and third fields
SD1_TIMING_V_BURST2 - RW - 32 bits - [MMReg:0x5E4C]
Field Name
SD1_V_BURST_START2
Description
Indicates the first line containing a sub-carrier burst in the
second field in terms of line count.
SD1_V_BURST_END2
26:16
0x26c
Indicates the last line containing a sub-carrier burst in the
second field in terms of line count.
SD1_ALT_V_BURST_START2
28
0x0
Adjusts the fourth field sub-carrier burst start line, ONLY if
SD1_ALT_BURST_BLANK_EN = 1, usually set to 0.
SD1_ALT_V_BURST_END2
29
0x0
Adjusts the fourth field sub-carrier burst end line, ONLY if
SD1_ALT_BURST_BLANK_EN = 1, usually set to 0.
This register indicates the vertical timing points of the SDTV1 encoder sub-carrier bursts in the second and fourth fields
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
10:0
Default
0x13e
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_TIMING_H_SETUP1 - RW - 32 bits - [MMReg:0x5E50]
Field Name
SD1_H_SETUP_START1
Bits
11:0
Default
0x22f
Description
The first pixel of normal width active data in terms of
TV1_CLK pixel count is SD1_H_SETUP_START1 + 1.
SD1_H_SETUP_END1
27:16
0xcfd
Indicates the last pixel of normal width active data in terms
of TV1_CLK pixel count.
This register indicates the horizontal timing points of the full width active data, with (NTSC) or without a setup level, on the
SDTV1 endcoder line
SD1_TIMING_H_SETUP2 - RW - 32 bits - [MMReg:0x5E54]
Field Name
SD1_H_SETUP_START2
Bits
11:0
Default
0x6a6
Description
The first pixel of partial width active data that starts later
than normal, in terms of TV1_CLK pixel count, is
SD1_H_SETUP_START2 + 1. This data would normally
appear on the first line of the first field in PAL/SECAM and
the first line of the second field in NTSC.
SD1_H_SETUP_END2
27:16
0x656
Indicates the last pixel of partial width active data that ends
earlier than normal, in terms of TV1_CLK pixel count. This
data would normally appear on the last line of the second
field in PAL/SECAM and the last line of the first field in
NTSC.
This register indicates the horizontal timing points of the partial width active data, with (NTSC) or without a setup level, on the
SDTV1 endcoder line
SD1_TIMING_V_SETUP1 - RW - 32 bits - [MMReg:0x5E58]
Field Name
SD1_V_SETUP_START1
Bits
11:0
Default
0x2d
Description
SD1_V_SETUP_START1(10:1) indicates, in terms of line
count, the first line where active data is allowed in the first
field. If the LSB is 0, the active data on this first line has a
horizontal pixel start point as listed in
SD1_TIMING_H_SETUP1.SD1_H_SETUP_START1 or if
1, then it starts as listed in
SD1_TIMING_H_SETUP2.SD1_H_SETUP_START2.
SD1_V_SETUP_END1
26:15
0x26a
SD1_V_SETUP_END1(10:1) indicates, in terms of line
count, the last line where active data is allowed in the first
field. If the LSB is 0, the active data on this last line has a
horizontal pixel end point as listed in
SD1_TIMING_H_SETUP1.SD1_H_SETUP_END1 or if 1,
then it ends as listed in
SD1_TIMING_H_SETUP2.SD1_H_SETUP_END2.
This register indicates the vertical timing points of the SDTV1 endcoder active data, with (NTSC) or without a setup level, in the
first field
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_TIMING_V_SETUP2 - RW - 32 bits - [MMReg:0x5E5C]
Field Name
SD1_V_SETUP_START2
Bits
11:0
Default
0x29e
Description
SD1_V_SETUP_START2(10:1) indicates, in terms of line
count, the first line where active data is allowed in the
second field. If the LSB is 0, the active data on this first line
has a horizontal pixel start point as listed in
SD1_TIMING_H_SETUP1.SD1_H_SETUP_START1 or if
1, then it starts as listed in
SD1_TIMING_H_SETUP2.SD1_H_SETUP_START2.
SD1_V_SETUP_END2
26:15
0x4dd
SD1_V_SETUP_END2(10:1) indicates, in terms of line
count, the last line where active data is allowed in the
second field. If the LSB is 0, the active data on this last line
has a horizontal pixel end point as listed in
SD1_TIMING_H_SETUP1.SD1_H_SETUP_END1 or if 1,
then it ends as listed in
SD1_TIMING_H_SETUP2.SD1_H_SETUP_END2.
This register indicates the vertical timing points of the SDTV1 endcoder active data, with (NTSC) or without a setup level, in the
second field
SD1_TIMING_H_ADV_ACTIVE - RW - 32 bits - [MMReg:0x5E60]
Field Name
SD1_H_ADV_ACTIVE_START1
Description
The advanced active start pulse for normal width active
data appears at pixel SD1_H_ADV_ACTIVE_START1 + 1,
in terms of TV1_CLK pixel count.
SD1_H_ADV_ACTIVE_START2
27:16
0x6a4
The advanced active start pulse for partial width, late arrival
active data appears at pixel
SD1_H_ADV_ACTIVE_START2 + 1, in terms of TV1_CLK
pixel count.
This register controls the generation of an advanced start pulse for every line with active data, as specified in
SD1_TIMING_V_ACTIVE1 and SD1_TIMING_V_ACTIVE2. This start pulse is output from the SDTV1 encoder, but is used
entirely for emulation purposes only
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
11:0
Default
0x22d
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_TIMING_V_ACTIVE1 - RW - 32 bits - [MMReg:0x5E64]
Field Name
SD1_V_ACTIVE_START1
Bits
11:0
Default
0x2c
Description
SD1_V_ACTIVE_START1(10:1) indicates, in terms of line
count, the first line where active data is actually drawn in the
first field. If the LSB is 0, the advanced active start pulse for
this line appears as listed in
SD1_TIMING_H_ADV_ACTIVE.SD1_H_ADV_ACTIVE_ST
ART1 or if 1, then as listed in
SD1_TIMING_H_ADV_ACTIVE.SD1_H_ADV_ACTIVE_ST
ART2.
SD1_V_ACTIVE_END1
26:16
0x135
Indicates the last line where active data is actually drawn in
the first field in terms of line count.
This register indicates the vertically cropped timing points of the SDTV1 endcoder active data in the first field. It represents the
actual vertical limits of active data in the first field, which may be less than or equal to the standard specifications listed in
SD1_TIMING_V_SETUP1. It indicates which lines to allow the advanced active start pulses, as specified by
SD1_TIMING_H_ADV_ACTIVE, which lines to apply the test pattern if SD1_MAIN_CNTL.SD1_PATTERN_GEN_EN = 1, which
lines to apply the active filters, as specified by SD1_TIMING_H_ACTIVE_FILT_WINDOW1 and
SD1_TIMING_H_ACTIVE_FILT_WINDOW2, and which lines to comb if SD1_LUMA_COMB_FILT_CNTL1.SD1_COMB_EN = 1
SD1_TIMING_V_ACTIVE2 - RW - 32 bits - [MMReg:0x5E68]
Field Name
SD1_V_ACTIVE_START2
Bits
11:0
Default
0x29e
Description
SD1_V_ACTIVE_START2(10:1) indicates, in terms of line
count, the first line where active data is actually drawn in the
second field. If the LSB is 0, the advanced active start pulse
for this line appears as listed in
SD1_TIMING_H_ADV_ACTIVE.SD1_H_ADV_ACTIVE_ST
ART1 or if 1, then as listed in
SD1_TIMING_H_ADV_ACTIVE.SD1_H_ADV_ACTIVE_ST
ART2.
SD1_V_ACTIVE_END2
26:16
0x26e
Indicates the last line where active data is actually drawn in
the second field in terms of line count.
This register indicates the vertically cropped timing points of the SDTV1 endcoder active data in the second field. It represents
the actual vertical limits of active data in the second field, which may be less than or equal to the standard specifications listed in
SD1_TIMING_V_SETUP2. It indicates which lines to allow the advanced active start pulses, as specified by
SD1_TIMING_H_ADV_ACTIVE, which lines to apply the test pattern if SD1_MAIN_CNTL.SD1_PATTERN_GEN_EN = 1, which
lines to apply the active filters, as specified by SD1_TIMING_H_ACTIVE_FILT_WINDOW1 and
SD1_TIMING_H_ACTIVE_FILT_WINDOW2, and which lines to comb if SD1_LUMA_COMB_FILT_CNTL1.SD1_COMB_EN = 1
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_TIMING_H_ACTIVE_FILT_WINDOW1 - RW - 32 bits - [MMReg:0x5E8C]
Field Name
SD1_H_ACTIVE_FILT_START1
Bits
11:0
Default
0x22f
Description
The first pixel to use the active data filter in terms of
TV1_CLK pixel count is SD1_H_ACTIVE_FILT_START1 +
1. The setting is related to the pixel start of normal width
data and the filter pipeline delay, so typical values are:
SD1_TIMING_H_SETUP1.SD1_H_SETUP_START1 to
SD1_TIMING_H_SETUP1.SD1_H_SETUP_START1 +
pipeline delay/2(12).
SD1_H_ACTIVE_FILT_END1
27:16
0xd14
Indicates the last pixel to use the active data filter in terms
of TV1_CLK pixel count. The setting is related to the end
pixel of normal width data and the filter pipeline delay, so
typical values are:
SD1_TIMING_H_SETUP1.SD1_H_SETUP_END1 +
pipeline delay/2(12) to
SD1_TIMING_H_SETUP1.SD1_H_SETUP_END1 +
pipeline delay(24).
This register indicates the horizontal timing points that must be applied to filter the full width active data on the SDTV1 endcoder
line. It identifies the pixel window in which the Luminance filter settings, as specified by register SD1_LUMA_FILT_CNTL, apply.
SD1_TIMING_H_ACTIVE_FILT_WINDOW2 - RW - 32 bits - [MMReg:0x5E90]
Field Name
SD1_H_ACTIVE_FILT_START2
Description
The first pixel to use the active data filter on a line where
active data starts later than normal is
SD1_H_ACTIVE_FILT_START2 + 1. The setting is related
to the late pixel start of partial width data and the filter
pipeline delay, so typical values are:
SD1_TIMING_H_SETUP2.SD1_H_SETUP_START2 to
SD1_TIMING_H_SETUP2.SD1_H_SETUP_START2 +
pipeline delay/2(12).
SD1_H_ACTIVE_FILT_END2
27:16
0x66d
Indicates the last pixel to use the active data filter on a line
where active data ends earlier than normal. The setting is
related to the early end pixel of partial width data and the
filter pipeline delay, so typical values are:
SD1_TIMING_H_SETUP2.SD1_H_SETUP_END2 +
pipeline delay/2(12) to
SD1_TIMING_H_SETUP2.SD1_H_SETUP_END2 +
pipeline delay(24).
This register indicates the horizontal timing points that must be applied to filter the partial width active data on the SDTV1
endcoder line. It identifies the pixel window in which the Luminance filter settings, as specified by register
SD1_LUMA_FILT_CNTL, apply.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
11:0
Default
0x6a6
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Graphics Controller Configuration Registers
SD1_TIMING_H_RUNIN_FILT_WINDOW - RW - 32 bits - [MMReg:0x5E94]
Field Name
SD1_H_RUNIN_FILT_START
Bits
11:0
Default
0x1c6
Description
The first pixel to use the clk-runin filter in terms of TV1_CLK
pixel count is SD1_H_RUNIN_FILT_START + 1.
SD1_H_RUNIN_FILT_END
27:16
0x430
Indicates the last pixel to use the clk-runin filter in terms of
TV1_CLK pixel count.
Horizontal timing information for clk-runin filter window of the SDTV1 encoded VBI services CC and EDS. The clk-runin filter just
passes the data untouched.
SD1_Y_BREAK_POINT_SETTING - RW - 32 bits - [MMReg:0x5E98]
Field Name
SD1_Y_GAIN_LIMIT
SD1_Y_BREAK_EN
Bits
10:0
Default
0x2ff
16
0x0
Contrast control register for Luminance portion of the video signal
Description
Gain (contrast) limit constant for the luminanace (Y) portion
of the video signal.
The range of this limiter is between 0 and 0x5FF.
Enables/Disable the Y gain break. When enabled, the Y
component of the video signal will be attenuated by one
half, for the portion that exceeds the SD1_Y_GAIN_LIMIT
value.
0=Disable
1=Enable
SD1_U_V_BREAK_POINT_SETTINGS - RW - 32 bits - [MMReg:0x5E9C]
Field Name
SD1_U_GAIN_LIMIT
Bits
9:0
Default
0x150
Description
Gain (saturation) limit constant for the U portions of the
chrominance video signal.
The range of this limiter is between 0 and 0x17f.
SD1_U_BREAK_EN
12
0x0
Enables/Disable the U gain break. When enabled, the U
components of the video signal will be attenuated by one
half, for the portion that exceeds the SD1_U_GAIN_LIMIT
value.
0=Disable
1=Enable
SD1_V_GAIN_LIMIT
25:16
0x1d7
Gain (saturation) limit constant for the V portions of the
chrominance video signal.
The range of this limiter is between 0 and 0x17f
SD1_V_BREAK_EN
28
0x0
Enables/Disable the V gain break. When enabled, the V
components of the video signal will be attenuated by one
half, for the portion that exceeds the SD1_V_GAIN_LIMIT
value.
0=Disable
1=Enable
Saturation control register for the Chrominance portion of the video signal
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_Y_AND_PASSTHRU_GAIN_SETTINGS - RW - 32 bits - [MMReg:0x5EA0]
SD1_Y_GAIN
Field Name
SD1_VBI_PASSTHRU_GAIN
Bits
8:0
Default
0x100
24:16
0x100
Contains contrast information for luminance video
Description
Unsigned 1.8 bit gain (contrast) value for the luminanace
(Y) portion of the video signal.
The maximum value is 100110011 (gain = 1.20).
Unsigned 1.8 bit gain (contrast) value for the VBI pass
through signal.
The maximum value is 100110011 (gain = 1.20).
SD1_U_AND_V_GAIN_SETTINGS - RW - 32 bits - [MMReg:0x5EA4]
SD1_U_GAIN
Field Name
Bits
8:0
Default
0x100
SD1_V_GAIN
24:16
0x100
Contains saturation information for chrominance video
Description
Unsigned 1.8 bit gain setting for the U portions of the
chrominance video signal.
The maximum value is 100100000 (gain = 1.125). Values
over 1.125 will be limited to 1.125.
Unsigned 1.8 bit gain setting for the V portions of the
chrominance video signal.
The maximum value is 100100000 (gain = 1.125). Values
over 1.125 will be limited to 1.125.
SD1_LUMA_BLANK_SETUP_LEVELS - RW - 32 bits - [MMReg:0x5EA8]
Field Name
SD1_BLANK_LEVEL
Description
Indicates the digital value of the luminance blanking level
and is defined as
SD1_LUMA_SYNC_TIP_LEVELS.SD1_Y_SYNC_TIP_LE
VEL + digital equivalent of blank above sync tip. This blank
above sync tip can be calculated by converting the sync
voltage: (Sync Amplitude/Full Range DAC Amplitude for
given Standard) * 1023(full input range of DAC).
SD1_SETUP_LEVEL
24:16
0xeb
Indicates the digital value of the black level in NTSC and is
defined as SD1_BLANK_LEVEL + digital equivalent of
black above blank level. This black above blank can be
calculated by converting the pedestal IRE: (Setup IRE/Full
White IRE) * Full Digital White = (7.5/92.5) * 512 = 42.
SD1_SETUP_LEVEL = SD1_BLANK_LEVEL for all
standards but NTSC.
Indicates the SDTV1 luminance blank and setup levels for Composite, S-Video, 480i & 480p Component, and RGB with sync on
green outputs
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
8:0
Default
0xeb
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_RGB_OR_PBPR_BLANK_LEVEL - RW - 32 bits - [MMReg:0x5EAC]
Field Name
SD1_RGB_OR_PBPR_BLANK_LEVEL
Bits
8:0
Default
0xeb
Description
Indicates the digital value of the luminance blanking level
for Red and Blue if generating a RGB with sync on Green or
the blank level for Pb & Pr, if set to a Component 480I or
480P mode. The mid range value of 512 is usually used in
the PbPr case.
SDTV1 Blank Level register for RGB with sync on Green if SD1_MAIN_CNTL.SD1_BLANK_ON_RB_SEL = 1 or for Component
Pb and Pr
SD1_LUMA_SYNC_TIP_LEVELS - RW - 32 bits - [MMReg:0x5EB0]
Field Name
SD1_Y_SYNC_TIP_LEVEL
Bits
8:0
Default
0x10
Description
Indicates the digital value of the luminance sync tip or
synchronization level. Usually set at 16 to give a 20 mV
margin above the zero DAC level.
SD1_PBPR_SYNC_TIP_LEVEL
24:16
0x111
Indicates the digital value of the Pb and Pr sync tip level
and is defined as SD1_RGB_OR_PBPR_BLANK_LEVEL digital equivalent of blank above sync tip. See the
SD1_LUMA_BLANK_SETUP_LEVELS.SD1_BLANK_LEV
EL description for the blank above sync tip calculation. If no
synchronizing pulses are required for Pb and Pr, set
SD1_PBPR_SYNC_TIP_LEVEL =
SD1_RGB_OR_PBPR_BLANK_LEVEL.
SDTV1 Sync Tip register for Luminance or for Component Pb and Pr
SD1_LUMA_FILT_CNTL - RW - 32 bits - [MMReg:0x5EB4]
Field Name
SD1_YFLT_EN
SD1_COMPY_OUT_BLEND
Bits
0
11:8
Default
0x1
0x4
AMD RS690 ASIC Family Register Reference Manual
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Description
Enables/Disables the Luminance filter
Controls sharpness blending of luma filters for Composite
output.
Bits [3:2] select the alternate filter:
00=Composite
01=S-video
10=1:1 Slew
11=Raw un-filtered data.
Bits [1:0] controls a 2-bit alpha blend:
00=100% alternate filter
01=75% alternate filter, 25% base filter
10=50% alternate filter, 50% base filter
11=25% alternate filter, 75% base filter
The Composite filter is the base filter for the Composite
output.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_SVIDY_OUT_BLEND
Controls sharpness blending of luma filters for S-Video
output.
Bits [3:2] select the alternate filter:
00=S-Video
01=Composite
10=1:1 Slew
11=Raw un-filtered data
Bits [1:0] controls a 2-bit alpha blend:
00=100% alternate filter
01=75% alternate filter, 25% base filter
10=50% alternate filter, 50% base filter
11=25% alternate filter, 75% base filter
The S-Video filter is the base filter for the S-Video output.
SD1_COMP_PASSTHRU_BLEND
19:16
0x0
Controls sharpness blending of luma filters for Composite
VBI passthrough output.
Bits [3:2] select the alternate filter:
00=Composite
01=S-video
10=1:1 Slew
11=Raw un-filtered data
Bits [1:0] controls a 2-bit alpha blend:
00=100% alternate filter
01=75% alternate filter, 25% base filter
10=50% alternate filter, 50% base filter
11=25% alternate filter, 75% base filter
The Composite filter is the base filter for the Composite VBI
passthrough output.
SD1_SVID_PASSTHRU_BLEND
23:20
0x0
Controls sharpness blending of luma filters for S-Video VBI
passthrough output.
Bits [3:2] select the alternate filter:
00=S-Video,
01=Composite,
10=1:1 Slew,
11=Raw un-filtered data.
Bits [1:0] controls a 2-bit alpha blend:
00=100% alternate filter,
01=75% alternate filter, 25% base filter,
10=50% alternate filter, 50% base filter,
11=5% alternate filter, 75% base filter.
The S-Video filter is the base filter for the S-Video VBI
passthrough output.
SD1_OUTSIDE_ACTIVE_SLEW_EN
24
0x1
Enables/Disables Slewing of the video signal during the
blank region.
If disabled, the blank region of the video signal will be
filtered with the filter settings specified above (_BLEND) for
the active portion of the video signal.
If enabled the blank region of the video signal will be slewed
SD1_INSIDE_ACTIVE_SLEW_EN
25
0x0
Enables/Disables Slewing of the video signal during the
active region.
If disabled, the active portion of the video signal will be
filtered with _BLEND settings specified bove.
If enabled, the active portion of the video signal will be
slewed and no other filter settings will apply
SD1_LUMA_DITHER_SEL
29:28
0x0
Control the addition of dither to Luminance data. Choices
are truncate, round, dither with random number, dither with
previous data
Specifies filter settings and dither settings (first) for Luminance video signal
© 2007 Advanced Micro Devices, Inc.
Proprietary
15:12
0x0
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_LUMA_COMB_FILT_CNTL1 - RW - 32 bits - [MMReg:0x5EB8]
Field Name
SD1_COMB_EN
SD1_DISABLE_FIRST_LAST
Bits
0
1
Default
0x0
0x0
SD1_COMB_LINE_SEL
9:8
0x0
21:16
30:24
0x0
0x0
SD1_P2
SD1_P3
Comb filter register control 1
Description
Enable/Disables the Combing on composite video output
Enable/Disables Combing on the first and last active lines of
the composite video output
Selects between 3 line comb, or 2 line from upper or lower
two pair of lines.
Reference level for AGC. Nominal 0x20.
Gain up value for AGC.
SD1_LUMA_COMB_FILT_CNTL2 - RW - 32 bits - [MMReg:0x5EBC]
Field Name
SD1_P4
SD1_P5
SD1_P6
SD1_P7
Bits
7:0
8
21:16
27:24
Default
0x0
0x0
0x0
0x0
Comb filter register control 2
Description
Lower clip limit or force for AGC multiplier.
Select control curve multiplier inputs.
Sets coring level for nominal signals.
Controls the slope of the coring process to be below the P6
threshold.
SD1_LUMA_COMB_FILT_CNTL3 - RW - 32 bits - [MMReg:0x5EC0]
SD1_P10
Field Name
Bits
5:0
Default
0x0
SD1_P8
16:8
0x0
SD1_P9
Comb filter register control 3
26:20
0x0
Description
Gain of bandpassed centre line to subtract from the Y for
composite. Notch level.
Sets the final gain level for the control signal. Diagonal false
color level.
Upper clip limit or force for final control signal.
SD1_LUMA_COMB_FILT_CNTL4 - RW - 32 bits - [MMReg:0x5EC4]
Field Name
SD1_P11
SD1_FORCE_P9
Comb filter register control 4
Bits
5:0
8
Default
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
Gain of checker board false color to subtract
Forces upper value for P9.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_VIDOUT_MUX_CNTL - RW - 32 bits - [MMReg:0x5EC8]
Field Name
SD1_VIDEO_SELECT_MUX0_EN
Bits
0
Default
0x1
SD1_VIDEO_SELECT_MUX1_EN
1
0x1
SD1_VIDEO_SELECT_MUX2_EN
2
0x1
SD1_VIDEO_SELECT_MUX0
7:4
0x1
SD1_VIDEO_SELECT_MUX1
11:8
0x2
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Enables/Disables the output mux 0.
0=Send data 0
1=Send data as selected by RED_MX
Enables/Disables the output mux 1.
0=Send data 0
1=Send data as selected by GRN_MX
Enables/Disables the output mux 2.
0=Send data 0
1=Send data as selected by BLU_MX
Output Mux selection for first SDTV1 output, which is
normally routed to the triple DAC output DAC4_CHROMA.
0=iSVID_Y
1=iSVID_C
2=iCOMP
3=iGREEN
4=iBLUE
5=iRED
6=iYPBPR_Y
7=iPB
8=iPR
9=irf_FORCE_DAC_DATA
10=iDBG_INPUT_Y
11=iDBG_GAINED_Y
12=iDBG_YFORFILT
13=iDBG_SYNCb
14=iDBG_END_OF_STANDARD_FRAME
15=iDBG_RGB_Y
Output Mux selection for second SDTV1 output, which is
normally routed to the triple DAC output DAC6_COMP.
0=iSVID_Y
1=iSVID_C
2=iCOMP
3=iGREEN
4=iBLUE
5=iRED
6=iYPBPR_Y
7=iPB
8=iPR
9=irf_FORCE_DAC_DATA
10=iDBG_INPUT_Y
11=iDBG_GAINED_Y
12=iDBG_YFORFILT
13=iDBG_SYNCb
14=iDBG_END_OF_STANDARD_FRAME
15=iDBG_RGB_Y
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Graphics Controller Configuration Registers
SD1_VIDEO_SELECT_MUX2
SD1_ENCODER_BYPASS_EN
SD1_VIDEO_OUTPUT_DITHER_SEL
15:12
0x0
28
0x0
31:30
0x0
SDTV1 encoder output selection control register
Output Mux selection for third SDTV1 output, which is
normally routed to the triple DAC output DAC5_LUMA.
0=iSVID_Y
1=iSVID_C
2=iCOMP
3=iGREEN
4=iBLUE
5=iRED
6=iYPBPR_Y
7=iPB
8=iPR
9=irf_FORCE_DAC_DATA
10=iDBG_INPUT_Y
11=iDBG_GAINED_Y
12=iDBG_YFORFILT
13=iDBG_SYNCb
14=iDBG_END_OF_STANDARD_FRAME
15=iDBG_RGB_Y
0=Bypass Encoder with DC offset in U,V
1=Bypass Encoder without any changes
Controls the addition of dither to all the output. Choices are
truncate, round, dither with random number, and dither with
previous data.
SD1_FORCE_DAC_DATA - RW - 32 bits - [MMReg:0x5ECC]
Field Name
SD1_FORCE_DAC_DATA
Bits
9:0
Default
0x0
Description
Specifies a 10 bit value to be routed to those DAC(s) with
the corresponding output selection
mux(SD1_VIDOUT_MUX_CNTL.SD1_VIDEO_SELECT_M
UX1 to .SD1_VIDEO_SELECT_MUX2) set to 9. The
following registers must also be programmed:
DAC_MUX_OUT_CNTL.MUX_CNTL_EN = 0 and
DTO1_VCLK_DENOMIN.DTO1_EN = 0.
This register allows data to be directly applied to the triple DACs
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_CHROMA_MOD_CNTL - RW - 32 bits - [MMReg:0x5EF0]
Field Name
SD1_U_BURST_LEVEL
Bits
8:0
Default
0x1b2
24:16
0x4e
SD1_COL_SC_SECOND_CORR_EN
26
0x0
SD1_CHROMA_PRE_MOD_DELAY_EN
27
0x0
SD1_FORCE_BLACK_WHITE
29
0x0
SD1_FORCE_BURST_ALWAYS
30
0x0
SD1_UVFLT_EN
31
0x1
SD1_V_BURST_LEVEL
Chroma modulation control register
Description
U component burst level. For NTSC: -(20IRE/92.5IRE) *
512 =0x191. For PAL: -(Sin45)*(21.5/100IRE)*512 =
0x1B2.
V component burst level. For NTSC: = 0x0. For PAL:
(cos45)*(21.5IRE/100IRE)*512 = 0x4E.
When set to 1 in NTSC/PAL modes, the Sub-Carrier DTO
Accumulator is incremented by a second correction set by
SD1_SCM_COL_SC_INC_CORR and
SD1_SCM_COL_SC_DENOMIN.
0=Normal Sub-Carrier DTO correction with
SD1_COL_SC_DENOMIN, SD1_COL_SC_INC,
and SD1_COL_SC_INC_CORR
1=Additional Sub-Carrier DTO correction controlled by
SD1_SCM_COL_SC_DENOMIN,
SD1_SCM_COL_SC_INC_CORR
When rf_PIX_DELAY_SEL = 0, it sets the pixel delay
alignment of chrominance signal before or after modulation.
Forces U and V values to be zero
0=Colour ON
1=Colour OFF
Active data will be ignored and Burst will be inserted all of
the way through.
0=Normal Colour Burst production in encoder
1=Colour Burst fills the entire TV frame
If enabled, U and V data gets filtered in U and V filters
respectively, or else no filtering occurs.
0=Bypass U and V filters
1=Enable U and V filters
SD1_COL_SC_DENOMIN - RW - 32 bits - [MMReg:0x5EF4]
Field Name
SD1_COL_SC_DENOMIN
Description
This register value determines when
SD1_COL_SC_INC_CORR register value should be used
as the Increment value for Sub-Carrier DTO Accumulator.
Denominator portion of the correction factor. This field is used in NTSC/PAL mode and during Secam DB component generation
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
24:0
Default
0x2
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_COL_SC_INC - RW - 32 bits - [MMReg:0x5EF8]
Field Name
SD1_COL_SC_INC
Bits
28:0
Default
0x15555
555
Description
This is the increment value the Sub-Carrier DTO need to
increment by every cycle except when the count of
SD1_SCM_COL_SC_DENOMIN is reached.
When the count of SD1_SCM_COL_SC_DENOMIN is
reached, we will increment the accumulator by
SD1_COL_SC_INC_CORR instead of COL_SC_INC.
Note: Use ssdtve.cpp to program this field.
Increment value for Sub-Carrier DTO Accumulator. Used for NTSC/PAL sin/cos generation. In Secam mode, used for DB
component generation
SD1_COL_SC_INC_CORR - RW - 32 bits - [MMReg:0x5EFC]
Field Name
SD1_COL_SC_INC_CORR
Bits
28:0
Default
0x15555
556
Description
SD1_COL_SC_INC register value plus the correction
factor. This total value will be the new Sub-Carrier DTO
Accumulator increment when a count determined by
SD1_SCM_COL_SC_DENOMIN register field is reached.
Increment value for Sub-Carrier DTO Accumulator + Numerator portion of the required correction factor. This field is used in
NTSC/PAL mode and during Secam DB component generation
SD1_SCM_COL_SC_DENOMIN - RW - 32 bits - [MMReg:0x5F00]
Field Name
SD1_SCM_COL_SC_DENOMIN
Bits
24:0
Default
0x0
Description
This register value determines when
SD1_SCM_COL_SC_INC_CORR register value should be
used as the Increment value for Sub-Carrier DTO
Accumulator.
This field is used only for Secam DR component generation. Denominator portion of the correction factor
SD1_SCM_COL_SC_INC - RW - 32 bits - [MMReg:0x5F04]
Field Name
SD1_SCM_COL_SC_INC
Bits
28:0
Default
0x1533a
6ae
Description
This is the increment value the Sub-Carrier DTO need to
increment by every cycle except when the count of
SD1_SCM_COL_SC_DENOMIN is reached. When the
count of SD1_SCM_COL_SC_DENOMIN is reached, we
will increment the accumulator by
SD1_SCM_COL_SC_INC_CORR instead of
SD1_SCM_COL_SC_INC.
This field is used only for Secam DR component generation. Increment value for Sub-Carrier DTO Accumulator.
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_SCM_COL_SC_INC_CORR - RW - 32 bits - [MMReg:0x5F08]
Field Name
SD1_SCM_COL_SC_INC_CORR
Bits
28:0
Default
0x1533a
6ae
Description
SD1_COL_SC_INC register value plus the correction
factor. This total value will be the new Sub-Carrier DTO
Accumulator increment when a count determined by
SD1_SCM_COL_SC_DENOMIN register field is reached.
Increment value for Sub-Carrier DTO Accumulator + Numerator portion of the required correction factor
SD1_SCM_MOD_CNTL - RW - 32 bits - [MMReg:0x5F0C]
Field Name
SD1_SCM_BURST_GAIN
Bits
11:0
Default
0x203
SD1_SCM_NOTCH_TUNER
21:16
0x2c
SD1_SCM_ENABLE
24
0x0
SD1_SCM_RST_DTO_ON_BLANK
25
0x0
26
27
29:28
0x0
0x0
0x0
SD1_SCM_2LINE_EN
30
0x0
SD1_SCM_DTO_LIMIT_EN
31
0x1
SD1_SCM_INVERT_PHASE_EN
SD1_INVERT_SCM_3LINE
SD1_SCM_3LINE_INIT
Secam modulation control register
Description
This register field value determines the amplitude of DR and
DB signals.
Sets the center of Secam high frequency subcarrier
pre-emphasis filter at 4.286MHz frequency. Can be fine
tuned in KHz granularity if required.
Enables Secam mode, thereby generating Secam DR/DB
color components. Setting this field high will disable NTSC
and PAL color modulation.
Qualifier required to reset the Sub-Carrier DTO accumulator
when in Secam mode. In Secam mode, DTO is reset during
blanking period.
Enables phase inversion of the DR and DB subcarriers.
Swaps inversions specific to fields.
This field value is loaded into an internal mod 2 counter.
If loaded by 0, the count values are 0,1,2 corresponding to
phase values of 0,0,180.
If loaded by 1, the count values are 1,2,0 corresponding to
phase values of 0,180,0 and so on.
This field will set the internal counter into a mod 1 mode and
the corresponding phase values are 0 and 180.
When set, the frequency swing of DR/DB components will
be limited to a specific range. The register fields
SD1_SCM_MIN_DTO_SWING and
SD1_SCM_MAX_DTO_SWING will set the range.
If this field is not set, there will be no limit set on the
frequency swing.
SD1_SCM_DB_DR_SCALE_FACTORS - RW - 32 bits - [MMReg:0x5F10]
Field Name
SD1_SCM_DB_SCALE_FACTOR
Description
This field value is multiplied to the 'U' output of the low
frequency pre-emphasis filter to generate the frequency
deviation for the DB component.
SD1_SCM_DR_SCALE_FACTOR
31:16
0x8c99
This field value is multiplied to the 'V' output of the low
frequency pre-emphasis filter to generate the frequency
deviation for the DR component.
Used for generating the required frequency deviation for DR and DB components
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
15:0
Default
0xa5f5
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_SCM_MIN_DTO_SWING - RW - 32 bits - [MMReg:0x5F14]
Field Name
SD1_SCM_MIN_DTO_SWING
Bits
27:0
Default
0x96206
39
Sets the minimum frequency swing for DR/DB components
Description
Sets the minimum frequency swing. Will take effect only
when SD1_SCM_DTO_LIMIT_EN register field is set.
SD1_SCM_MAX_DTO_SWING - RW - 32 bits - [MMReg:0x5F18]
Field Name
SD1_SCM_MAX_DTO_SWING
Bits
27:0
Default
0xb713c
e4
Sets the maximum frequency swing for DR/DB components
Description
Sets the maximum frequency swing. Will take effect only
when SD1_SCM_DTO_LIMIT_EN register field is set.
SD1_CRC_CNTL - RW - 32 bits - [MMReg:0x5F1C]
Description
Enables the CRC signature generation on those output(s)
as selected by SD1_CRC_DATAIN_SEL.
0=Reset/Disable
1=Enable
SD1_CRC_DATAIN_SEL
5:4
0x0
Selects the SDTV1 output(s) on which the CRC generation
is to be performed.
0=V0V1V2
1=V0 only
2=V1 only
3=V2 only
SD1_RST_SC_ON_FSYNC_4CRC
7
0x0
Forces the sub-carrier to be reset at every frame
synchronization pulse to allow CRC generation across
something other than the standard number of fields per
frame(4 for NTSC, 8 for PAL).
0=Normal free running Sub-Carrier
1=Enable reset of Sub-Carrier every Frame Sync
SD1_PROGRESSIVE_MODE_CRC
8
0x0
Selects interlaced of progressive mode CRC generation.
0=CRC generation for interlaced modes
1=CRC generation for progressive modes
Controls the production of CRC signatures from the SDTV1 encoder output(s)
SD1_CRC_EN
Field Name
Bits
0
Default
0x0
SD1_VIDEO_PORT_SIG - RW - 32 bits - [MMReg:0x5F20]
Field Name
SD1_CRC_SIG (R)
Bits
29:0
Default
0x0
Description
SD1_CRC_SIG(9:0)=CRC signature of VIDEO_0 output
SD1_CRC_SIG(19:10)=CRC signature of VIDEO_1 output
SD1_CRC_SIG(29:20)=CRC signature of VIDEO_2 output
Read only register containing the CRC signatures for VIDEO_0, VIDEO_1, and VIDEO_2 outputs of the SDTV1 encoder
AMD RS690 ASIC Family Register Reference Manual
2-344
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
SD1_SDTV0_DEBUG - RW - 32 bits - [MMReg:0x5F28]
Field Name
SD1_SDTV0_DEBUG
Bits
31:0
Default
0xffff
Description
SD1_SDTV0_DEBUG(31:0)=Unassigned
SD1_SDTV0_DEBUG(16)=Enable TVVBI muxing to debug
bus.
The bits in this register can be assigned control functions, if the debugging process yields additional needs
SD1_COL_SC_PHASE_CNTL - RW - 32 bits - [MMReg:0x5FD4]
Field Name
SD1_COL_SC_PHASE_INIT
Phase offset to the Sub-Carrier DTO
Bits
15:0
Default
0x0
Description
Adds phase offset to the Sub-Carrier DTO.
SD1_LUMA_OFFSET_LIMIT - RW - 32 bits - [MMReg:0x5F8C]
Field Name
SD1_LUMA_OFFSET
SD1_LUMA_LIMIT
SD1_YC_OFFSET_LIMIT_BYPASS
Bits
9:0
Default
0x0
21:12
24
0x0
0x0
Luma offset used for color conversion
Description
Luma offset value used in conjunction with SD1_Y_GAIN
for color conversion.
Luma limit used for color conversion
0=Luma and chroma data are both offset. Luma data is
limited.
1=Bypass offset/limiting logic and sign extend luma and
chroma data.
SD1_CHROMA_OFFSET - RW - 32 bits - [MMReg:0x5F90]
Field Name
SD1_CHROMA_OFFSET
Bits
9:0
Default
0x0
Chroma offset used for color conversion
Description
Chroma offset value used in conjunction with SD1_U_GAIN
& SD1_V_GAIN for color conversion.
SD1_UPSAMPLE_MODE - RW - 32 bits - [MMReg:0x5F94]
Field Name
SD1_FOUR_TAP_MODE
SD1_UPSAMP_PICK_NEAR
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
0
4
Default
0x0
0x0
Description
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
SD1_CRTC_HV_START - RW - 32 bits - [MMReg:0x5F98]
Field Name
SD1_CRTC_H_START
SD1_CRTC_V_START
Bits
12:0
28:16
Default
0x0
0x0
CRTC capture pulse start location
Description
CRTC horizontal capture frame pulse start.
CRTC vertical capture frame pulse start. Please note that in
interlace mode, CRTC counts every other line, while
TVOUT counts every line.
SD1_CRTC_TV_FRAMESTART_CNTL - RW - 32 bits - [MMReg:0x5F9C]
Field Name
SD1_CRTC_TV_FRAMESTART_FREQ
Bits
1:0
Default
0x0
Description
0=TV FRAMESTART happens every 2 fields
1=TV FRAMESTART happens every 4 fields, NTSC
standard
2=TV FRAMESTART happens every 8 fields, PAL
standard
3=Reserved
HD_EMBEDDED_SYNC_CNTL - RW - 32 bits - [MMReg:0x5FA0]
Field Name
HD_EMBED_SYNC_EN_Y_G
Bits
0
Default
0x0
HD_EMBED_SYNC_EN_PB_B
1
0x0
HD_EMBED_SYNC_EN_PR_R
2
0x0
HD_TRILEVEL_SYNC_EN
3
0x0
31:16
0x0
HD_DEBUG0
Description
0=Disable embedded sync on Y/G.
1=Enable embedded sync on Y/G.
0=Disable embedded sync on Pb/B.
1=Enable embedded sync on Pb/B.
0=Disable embedded sync on Pr/R.
1=Enable embedded sync on Pr/R.
0=Embedded sync only negative, if enabled.
1=Embedded sync neg. and pos., if enabled.
Reserved
HD_INCR - RW - 32 bits - [MMReg:0x5FA4]
Field Name
HD_INCR_Y_G
HD_INCR_PB_B_PR_R
Bits
9:0
25:16
Default
0x0
0x0
Description
Increment value for Y.
Increment value for PB and PR.
HD_TRILEVEL_DUR - RW - 32 bits - [MMReg:0x5FA8]
Field Name
HD_TRILEVEL_DUR_Y
HD_TRILEVEL_DUR_PBPR
Bits
10:0
26:16
Default
0x0
0x0
AMD RS690 ASIC Family Register Reference Manual
2-346
Description
Negative and positive sync level duration for Y.
Negative and positive sync level duration for PB and PR.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
HD_POS_SYNC_LEVEL - RW - 32 bits - [MMReg:0x5FAC]
Field Name
HD_POS_SYNC_LEVEL_Y_G
HD_POS_SYNC_LEVEL_PB_B_PR_R
Bits
9:0
25:16
Default
0x0
0x0
Description
Positive sync value for Y.
Positive sync value for PB and PR.
HD_BACKPORCH_DUR - RW - 32 bits - [MMReg:0x5FB0]
Field Name
HD_BP_DUR_Y
HD_BP_DUR_PBPR
Bits
10:0
26:16
Default
0x0
0x0
Description
Back porch duration for Y.
Back porch duration for PB and PR.
HD_SERATION_DUR - RW - 32 bits - [MMReg:0x5FB4]
Field Name
HD_SER_DUR_Y
HD_SER_DUR_PBPR
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
10:0
26:16
Default
0x0
0x0
Description
Duration of seration pulse for Y.
Duration of seration pulse for PB and PR.
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
2.18 LVTMA Registers
LVTMA_CRC_CNTL - RW - 32 bits - [MMReg:0x7AB0]
Field Name
LVTMA_CRC_EN
Bits
0
Default
0x0
LVTMA_CRC_CONT_EN
4
0x0
LVTMA_CRC_ONLY_BLANKb
8
0x0
LVTMA_CRC_FIELD
12
0x0
LVTMA_2ND_CRC_EN
16
0x0
LVTMA_2ND_CRC_LINK_SEL
20
0x0
LVTMA_2ND_CRC_DATA_SEL
25:24
0x1
Description
Enable LVTMA CRC calculation.
0=Disable
1=Enable
Select continuous or one-shot mode for primary CRC.
0=CRC is calculated over 1 frame
1=CRC is continuously calculated for every frame
Determines whether primary CRC is calculated for the
whole frame or only during non-blank period.
0=CRC calculated over entire field
1=CRC calculated only during BLANKb
Controls which field polarity starts the LVTMA CRC block
after LVTMA_CRC_EN is set to 1. Used only for interlaced
mode CRCs.
0=Even field begins CRC calculation
1=Odd field begins CRC calculation
Enable LVTMA 2nd CRC calculation.
0=Disable
1=Enable
Select which LVTM link to perform CRC on.
0=Perform CRC on link0
1=Perform CRC on link1
Select whether to perform CRC on all data or a subset of
the video frame.
0=2ND CRC calculated over entire field
1=2ND CRC calculated only during video data enable
(plus preamble and guard band in HDMI mode)
2=2ND CRC calculated over vertical blank region,
including VBI preamble and guard band region, excluding
horizontal blank
3=2ND CRC calculated only during audio data enable
Enable LVTMA CRC Calculation
LVTMA_CRC_SIG_MASK - RW - 32 bits - [MMReg:0x7AB4]
Field Name
LVTMA_CRC_SIG_BLUE_MASK
LVTMA_CRC_SIG_GREEN_MASK
LVTMA_CRC_SIG_RED_MASK
LVTMA_CRC_SIG_CONTROL_MASK
Bits
7:0
15:8
23:16
26:24
Default
0xff
0xff
0xff
0x7
Description
CRC mask bits for LVTMA blue component.
CRC mask bits for LVTMA green component.
CRC mask bits for LVTMA red component.
CRC mask bits for LVTMA control signals 3-bit input value:
Bit 2=Vsync
Bit 1=Hsync
Bit 0=Data Enable
RGB and Control CRC Mask
AMD RS690 ASIC Family Register Reference Manual
2-348
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
LVTMA_CRC_SIG_RGB - RW - 32 bits - [MMReg:0x7AB8]
Field Name
LVTMA_CRC_SIG_BLUE (R)
LVTMA_CRC_SIG_GREEN (R)
LVTMA_CRC_SIG_RED (R)
LVTMA_CRC_SIG_CONTROL (R)
Bits
7:0
15:8
23:16
26:24
Default
0x0
0x0
0x0
0x0
Description
CRC signature value for LVTMA blue component
CRC signature value for LVTMA green component
CRC signature value for LVTMA red component
CRC signature value for LVTMA control signals3-bit input
value:
Bit 2=Vsync
Bit 1=Hsync
Bit 0=Data Enable
RGB and Control CRC Result
LVTMA_2ND_CRC_RESULT - RW - 32 bits - [MMReg:0x7ABC]
Field Name
LVTMA_2ND_CRC_RESULT (R)
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
29:0
Default
0x0
Description
LVTMA 2ND CRC readback
AMD RS690 ASIC Family Register Reference Manual
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Graphics Controller Configuration Registers
2.19 Miscellaneous Detailed Register Reference
AGP_BASE_2 - RW - 32 bits - MCIND:0x103
Field Name
AGP_BASE_ADDR_2
Bits
3:0
Default
0x0
Description
BIF_SLAVE_CNTL - RW - 32 bits - [MMReg:0x180C]
Field Name
DISABLE_FAD_CALC
Bits
0
Default
0x0
DISABLE_NONPOSTED_CHECK
1
0x0
DISABLE_HDP_OWORD_ACCESS
2
0x0
SPARE_BIT_3
SWBF2_DBL_RSYNC_C
SWBF2_DBL_RSYNC_S
SWBRBBM_DBL_RSYNC_C
SWBRBBM_DBL_RSYNC_S
SWBHDP_DBL_RSYNC_B
SWBHDP_DBL_RSYNC_C
SWBCFG_DBL_RSYNC_B
SWBCFG_DBL_RSYNC_C
SRB_DBL_RSYNC_B
SRB_DBL_RSYNC_C
BIF_HDP_fifo_WATERMARK
3
4
5
6
7
8
9
10
11
12
13
15:14
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x3
BIF_SRB_fifo_WATERMARK
17:16
0x3
BIF_RBBM_fifo_WATERMARK
19:18
0x3
HDP_STATUS_DBL_FLOP_EN
DISABLE_ALLSLAVE_AGPBUSY
DISABLE_CFGSLAVE_AGPBUSY
BIF_DEBUGBUS_CYCLE_EN
DISABLE_HOLD_RBBM_READ
BIF_WAIT_FOR_READ
BIF_F2_fifo_WATERMARK
20
21
22
23
24
25
27:26
0x1
0x0
0x0
0x0
0x0
0x0
0x3
BIF_PERF_COUNT_0_CLK_SEL
29:28
0x0
BIF_PERF_COUNT_1_CLK_SEL
31:30
0x0
AMD RS690 ASIC Family Register Reference Manual
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Description
Disables the FAD (non_posted decode) calculation used in
the previous versions of BIF.
When asserted BIF Slave does not wait for non-posted
completion to assert Ack or Commit.
When asserted BIF Slave does not issue OctaWord writes
to HDP.
Reserved.
Double Sync Pointer on CCLK domain.
Double Sync Pointer on SCLK domain.
Double Sync Pointer on CCLK domain.
Double Sync Pointer on SCLK domain.
Double Sync Pointer on BCLK domain.
Double Sync Pointer on CCLK domain.
Double Sync Pointer on BCLK domain.
Double Sync Pointer on CCLK domain.
Double Sync Pointer on BCLK domain.
Double Sync Pointer on CCLK domain.
Values less than 11 will reduce the number of available slots
in FIFO.
Values less than 11 will reduce the number of available slots
in FIFO.
Values less than 11 will reduce the number of available slots
in FIFO.
Double Sync HDP status indicators on CCLK domain.
Removes all slave requests from AGP_BUSY assertion.
Removes CFG slave requests from AGP_BUSY assertion.
Write 1 to cycle through entire BIF Debug BUS.
Write 1 to allow HI to issue multiple reads to RBBM.
Forces HI to wait for SRB completion on a read.
Values less than 11 will reduce the number of available slots
in FIFO.
Clock select for performance counter.
11=MCLK
10=SCLK
01=BCLK
00=CCLK
Clock select for performance counter.
11=MCLK
10=SCLK
01=BCLK
00=CCLK
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
BUS_CNTL - RW - 32 bits - [IOReg,MMReg:0x30]
Field Name
PMI_IO_DISABLE
Bits
0
Default
0x0
PMI_MEM_DISABLE
1
0x0
PMI_BM_DISABLE
2
0x0
PMI_INT_DISABLE
3
0x0
BUS2_IMMEDIATE_PMI_DISABLE
4
0x0
PM_BUSY_ASSERTION
5
0x0
IGNORE_WAIT4COH
6
0x0
IGNORE_RBBM_HIBUSY
BUS2_VGA_REG_COHERENCY_DIS
BUS2_VGA_MEM_COHERENCY_DIS
BUS2_HDP_REG_COHERENCY_DIS
BUS2_GUI_INITIATOR_COHERENCY_D
IS
BUS2_HDP_MEM_COHERENCY_DIS
BUS2_PMI_MULTIFUNC_SEL
7
8
9
10
11
0x0
0x0
0x0
0x0
0x0
12
13
0x0
0x0
BUS_MASTER_DIS
14
0x1
ENABLE_RBBM_HIBUSY_CFG
F0_F1_BM_PMI_SELECT
15
16
0x0
0x0
MST_BUSY (R)
AIC_CNTL_HOLD_RD_fifo
AIC_CNTL_HOLD_RQ_fifo
MSI_REARM
17
18
19
20
0x0
0x0
0x0
0x0
DISABLE_OUTSTANDING_READ
21
0x0
REQ_DBL_RSYNC_C
22
0x1
REQ_DBL_RSYNC_M
23
0x1
CPL_DBL_RSYNC_M
24
0x1
CPL_DBL_RSYNC_C
25
0x1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Description
Power Management for IO cycles. Disabled in D1, D2, and
D3 in ACPI only.
Power Management for MEM cycles. Disabled in D1, D2,
and D3.
Power Management for Bus Mastering. Disabled in D1, D2,
and D3.
Power Management for interrupts. Disabled in D1, D2, and
D3.
0=Address decode using register value
1=Address decode using PM state value
0=Block PM busy assertion
1=Allow Assertion of PM Busy signal to northbridge
Ignores the state of WAIT4COHERENCY after 26 bit
counter assertion
Ignores the state of STAT_RBBM_HIBUSY after 32 cycles.
Disables VGA register coherency checking.
Disables VGA memory coherency checking.
Disables HDP register coherency checking.
Disables GUI register coherency checking.
Disables HDP memory coherency checking.
0=Pick greater of F0 or F1 power state
1=Pick lesser of F0 or F1 power state
1=Disables the GFX master path. Reads abort with FF's
returned
Adds RBBM busy requirements to CFG cycles.
0=Allow busmaster access for F0 and F1 if only one is in
D3
1=Disable busmaster access for F0 and F1 if only one is
in D3
GFX master machine busy status.
Hold master read FIFO.
Hold master request FIFO.
Write a 0, then a 1 to re-arm MSI at the end of the interrupt
routine.
0=Four outstanding reads
1=One outstanding read
0=Single sync flop to CCLK domain for master request
path
1=Double sync flop to CCLK domain for master request
path
0=Single sync flop to MCLK domain for master request
path
1=Double sync flop to MCLK domain for master request
path
0=Single sync flop to MCLK domain for master completion
path
1=Double sync flop to MCLK domain for master
completion path
0=Single sync flop to CCLK domain for master completion
path
1=Double sync flop to CCLK domain for master
completion path
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Graphics Controller Configuration Registers
CPL_DBL_RSYNC_S
26
0x1
BIF_BUS_CNTL_BIT_27
ENABLE_BREAKOUT
27
28
0x1
0x0
BUS2_IMMEDIATE_PMI_ENABLE
29
0x1
BUS2_IMMEDIATE_PMI_ENABLE_REG
30
0x1
BUS2_IMMEDIATE_PMI_DISABLE_REG
31
0x0
0=Single sync flop to SCLK domain for master completion
path
1=Double sync flop to SCLK domain for master
completion path
Reserved.
1=Low coherency lock in BIF to disengage after 26 bit
counter assertion
0=Address decode using register value
1=Address decode using PM state value
0=Register read back value matches PM state
1=Register read back value same as programmed value
0=Register read back value matches PM state
1=Register read back value same as programmed value
BUS_CNTL1 - RW - 32 bits - [IOReg,MMReg:0x34]
Field Name
HDP_READ_DELAY_CNT
HDP_READ_DELAY_CNT_EN
STEREOSYNC_EN
PM_MODE_SEL
Bits
7:0
8
9
10
Default
0x32
0x1
0x0
0x0
GFX_BM_DIS
11
0x0
AZ_BM_DIS
12
0x0
13
14
15
23:16
24
25
26
27
28
29
30
31
0x0
0x0
0x0
0x7
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
GFX_INT_STATUS (R)
AZ_INT_STATUS (R)
BUS_DEBUG_BIT_15
MCLK_GATE_COUNTER
BUS_DEBUG_BIT_24
BUS_DEBUG_BIT_25
BUS_DEBUG_BIT_26
BUS_DEBUG_BIT_27
BUS_DEBUG_BIT_28
BUS_DEBUG_BIT_29
BUS_DEBUG_BIT_30
BUS_DEBUG_BIT_31
Description
Sets the amount of read delay after HDP write.
Delays HDP reads after a write.
1=Enable Stereosync on LVDS_ENA_BL PAD
0=ACPI
1=APM
0=Allow busmastering for GFX client
1=Block GFX busmastering in MC
0=Allow busmastering for AZ client
1=Block AZ busmastering in MC
1=Outstanding GFX interrupt
1=Outstanding AZ interrupt
Reserved.
Number of idle cycles before dynamic MCLK is turned off.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
VGA25_PPLL_POST_DIV_SRC - RW - 32 bits - [MMReg:0x384]
Field Name
VGA25_PPLL_POST_DIV_SRC
Bits
0
Default
0x0
Description
Determines source of lvtmclk, pixclk and dvoclk PPLL
outputs.
0=External source (input of reference divider)
1=Output clock of display PLL
Determines source of pixel clocks when VGA clock speed is 25.175MHz in VGA timing mode
AMD RS690 ASIC Family Register Reference Manual
2-352
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
VGA25_PPLL_POST_DIV - RW - 32 bits - [MMReg:0x388]
Field Name
VGA25_PPLL_POST_DIV
Bits
6:0
Default
0x2e
Description
Post divider value of display PLL.
0x0 - 0x1=Reserved (divide PLL output by 2)
0x2=Divide PLL output by 2
0x3=Divide PLL output by 3
0x4=Divide PLL output by 4
0x5=Divide PLL output by 5
...
0x7f=Divide PLL output by 127
Post divider value of PLL clocks when VGA clock speed is 25.175MHz in VGA timing mode
VGA_MEM_WRITE_PAGE_ADDR - RW - 32 bits - [IOReg,MMReg:0x38]
Field Name
VGA_MEM_WRITE_PAGE0_ADDR
VGA_MEM_WRITE_PAGE1_ADDR
VGA write page register
Bits
9:0
25:16
Default
0x0
0x0
Write page 0 address.
Write page 1 address.
Description
VGA_MEM_READ_PAGE_ADDR - RW - 32 bits - [IOReg,MMReg:0x3C]
Field Name
VGA_MEM_READ_PAGE0_ADDR
VGA_MEM_READ_PAGE1_ADDR
VGA read page register
Bits
9:0
25:16
Default
0x0
0x0
Read page 0 address.
Read page 1 address.
Description
BIOS_0_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x10]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_1_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x14]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_2_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x18]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
AMD RS690 ASIC Family Register Reference Manual
2-353
Graphics Controller Configuration Registers
BIOS_3_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x1C]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_4_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x20]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_5_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x24]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_6_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x28]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_7_SCRATCH - RW - 32 bits - [IOReg,MMReg:0x2C]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
MEDIA_0_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xB0]
Field Name
Bits
MEDIA_0_SCRATCH
31:0
Scratch pad for multimedia driver information
Default
0x0
Description
Scratch pad for multimedia driver information.
MEDIA_1_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xB4]
Field Name
Bits
MEDIA_1_SCRATCH
31:0
Scratch pad for multimedia driver information
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-354
Description
Scratch pad for multimedia driver information.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
BIOS_8_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xC0]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_9_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xC4]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_10_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xC8]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_11_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xCC]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_12_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xD0]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_13_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xD4]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
BIOS_14_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xD8]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
AMD RS690 ASIC Family Register Reference Manual
2-355
Graphics Controller Configuration Registers
BIOS_15_SCRATCH - RW - 32 bits - [IOReg,MMReg:0xDC]
Field Name
BIOS_SCRATCH
Scratch pad for BIOS information
Bits
31:0
Default
0x0
Description
Scratch pad for BIOS information.
CONFIG_XSTRAP - RW - 32 bits - [IOReg,MMReg:0xE4]
Field Name
VGA_DISABLE (R)
Bits
0
Default
0x0
ENINTB (R)
3
0x0
ID_DISABLE (R)
14
0x0
AP_SIZE (R)
18:16
0x0
BUSCFG (R)
26:24
0x0
Description
STRAP VALUE READBACK
0=VGA enabled
1=int gfx will abort VGA requests
STRAP VALUE READBACK
0=Interrupts enabled
1=Interrupts disabled
STRAP VALUE READBACK
0=Normal
1=int gfx disabled
STRAP VALUE READBACK
000=128M
001=256M
010=64M
011=32M
100=512M
101=1G
STRAP VALUE READBACK
0=BondingOption_INT_GFX
1=Reserved
2=ext gfx enable
CONFIG_MEM_BASE_LO - R - 32 bits - [MMReg:0x100]
Field Name
CFG_MEM_BASE_LO
Bits
31:0
Default
0x0
Description
MEM_BASE_LO readback.
Note: Bits [24:0] of this field are hardwired to 0.
CONFIG_MEM_BASE_HI - R - 32 bits - [MMReg:0x104]
Field Name
CFG_MEM_BASE_HI
Bits
31:0
Default
0x0
Description
MEM_BASE_HI readback.
CONFIG_REG_BASE_LO - R - 32 bits - [MMReg:0x10C]
Field Name
CFG_REG_BASE_LO
Bits
31:16
Default
0x0
AMD RS690 ASIC Family Register Reference Manual
2-356
Description
REG_BASE_LO readback.
© 2007 Advanced Micro Devices, Inc.
Proprietary
Graphics Controller Configuration Registers
CONFIG_REG_BASE_HI - R - 32 bits - [MMReg:0x110]
Field Name
CFG_REG_BASE_HI
Bits
31:0
Default
0x0
Description
REG_BASE_HI readback.
HDP_FB_LOCATION - RW - 32 bits - [MMReg:0x134]
Field Name
HDP_FB_START
Bits
15:0
Default
0x0
Description
Defines the location of the frame buffer in the internal
address space. The internal address space has 32 address
bits. It should have the same value as MC_FB_START, and
must be aligned on 256B boundary
Note: Bits [7:0] of this field are hardwired to 0.
Frame Buffer Location
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
2-357
Graphics Controller Configuration Registers
This page intentionally left blank.
AMD RS690 ASIC Family Register Reference Manual
2-358
© 2007 Advanced Micro Devices, Inc.
Proprietary
Appendix A
Cross-Referenced Index
A.1 Quick Cross-Referenced Index
“Index Registers Sorted by Name” on page 2
“All Registers Sorted By Name” on page 3
“All Registers Sorted By Address” on page 29
For users of the PDF version of this document: in the tables below, click on the name of a register to go to the
description of that register found in Chapter 2.
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-1
A.2 Index Registers Sorted by Name
Table 2-1 Index Registers Sorted by Name
Name
Address
ATTRX
VGA_IO\:0x3C0
Secondary
Address
Additional
Address
Page
2-316
CLOCK_CNTL_DATA
IOReg:0xC
MMReg:0xC
2-267
CLOCK_CNTL_INDEX
IOReg:0x8
MMReg:0x8
2-267
CRTC8_DATA
MMReg:0x3B5
MMReg:0x3D5
CRTC8_IDX
MMReg:0x3B4
DAC_DATA
VGA_IO\:0x3C9
MMReg:0x3D4
VGA_IO:0x3B5
VGA_IO:0x3D5:IO 2-303
:0x3D5
VGA_IO:0x3B4
VGA_IO:0x3D4:O:
2-303
0x3D4
2-296
DAC_R_INDEX
VGA_IO\:0x3C7
2-296
DAC_W_INDEX
VGA_IO\:0x3C8
2-296
GRPH8_DATA
MMReg:0x3CF
VGA_IO:0x3CF
2-312
GRPH8_IDX
MMReg:0x3CE
VGA_IO:0x3CE
2-312
HTIU_NB_DATA
nbconfig:0xAC
2-26
HTIU_NB_INDEX
nbconfig:0xA8
2-26
MM_DATA
IOReg:0x4
MMReg:0x4
2-127
MM_INDEX
IOReg:0x0
MMReg:0x0
2-127
NB_MC_DATA
nbconfig\:0xEC
2-25
NB_MC_IND_DATA
nbconfig:0x74
2-33
NB_MC_IND_INDEX
nbconfig:0x70
2-33
NB_MC_INDEX
nbconfig\:0xE8
2-24
NB_MISC_DATA
nbconfig\:0x64
2-7
NB_MISC_INDEX
nbconfig\:0x60
2-7
NB_PCIE_INDX_ADDR
nbconfig\:0xE0
2-24
NB_PCIE_INDX_DATA
nbconfig\:0xE4
2-24
PCIE_PORT_DATA
pcieConfigDev[10:2]\:0xE4
2-89
PCIE_PORT_INDEX
pcieConfigDev[10:2]\:0xE0
2-89
SEQ8_DATA
MMReg:0x3C5
VGA_IO:0x3C5
2-302
SEQ8_IDX
MMReg:0x3C4
VGA_IO:0x3C4
2-302
AMD RS690 ASIC Family Register Reference Manual
A-2
© 2007 Advanced Micro Devices, Inc.
Proprietary
A.3 All Registers Sorted By Name
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
ADAPTER_ID
gcconfig:0x2C
MMReg:0x502C
2-111
ADAPTER_ID_W
gcconfig:0x4C
MMReg:0x504C:R
2-111
AGP_ADDRESS_SPACE_SIZE
NBMCIND\:0x38
2-160
AGP_BASE_2
MCIND:0x103
2-350
AGP_MODE_CONTROL
NBMCIND\:0x39
2-160
AIC_CTRL_SCRATCH
NBMCIND:0x3A
2-160
APC_ADAPTER_ID_W
apcconfig\:0x4C
2-151
APC_AGP_PCI_IO_LIMIT_BASE_HI apcconfig\:0x30
2-149
APC_AGP_PCI_IOBASE_LIMIT
Additional
Address
Page
apcconfig\:0x1C
2-147
APC_AGP_PCI_IRQ_BRIDGE_CTRL apcconfig\:0x3C
2-149
APC_AGP_PCI_MEMORY_LIMIT_B
apcconfig\:0x20
ASE
2-148
APC_AGP_PCI_PREFETCHABLE_B
apcconfig\:0x28
ASE_Upper
2-148
APC_AGP_PCI_PREFETCHABLE_L
apcconfig:0x24
IMIT_BASE
2-148
APC_AGP_PCI_PREFETCHABLE_L
apcconfig\:0x2C
IMIT_Upper
2-148
APC_AGP_PCI_STATUS
apcconfig:0x1E
2-147
APC_BASE_CODE
apcconfig\:0xB
2-146
APC_BIST
apcconfig\:0xF
2-146
APC_CACHE_LINE
apcconfig\:0xC
2-146
APC_CAPABILITIES_PTR
apcconfig:0x34
2-149
APC_COMMAND
apcconfig\:0x4
2-143
APC_DEVICE_ID
apcconfig:0x2
2-143
APC_HEADER
apcconfig\:0xE
2-146
APC_HT_MSI_CAP
apcconfig:0x44
2-151
APC_LATENCY
apcconfig\:0xD
2-146
APC_MISC_DEVICE_CTRL
apcconfig:0x40
2-151
APC_REGPROG_INF
apcconfig\:0x9
2-145
APC_REVISION_ID
apcconfig\:0x8
2-145
APC_SSID
apcconfig\:0xB4
2-152
APC_SSID_CAP_ID
apcconfig\:0xB0
2-152
APC_STATUS
apcconfig:0x6
2-144
APC_SUB_BUS_NUMBER_LATENC
apcconfig\:0x18
Y
2-147
APC_SUB_CLASS
apcconfig\:0xA
2-145
APC_VENDOR_ID
apcconfig\:0x0
2-143
ATTR00
VGAATTRIND\:0x0
2-316
ATTR01
VGAATTRIND\:0x1
2-317
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-3
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
ATTR02
VGAATTRIND\:0x2
2-317
ATTR03
VGAATTRIND\:0x3
2-317
ATTR04
VGAATTRIND\:0x4
2-317
ATTR05
VGAATTRIND\:0x5
2-317
ATTR06
VGAATTRIND\:0x6
2-318
ATTR07
VGAATTRIND\:0x7
2-318
ATTR08
VGAATTRIND\:0x8
2-318
ATTR09
VGAATTRIND\:0x9
2-318
ATTR0A
VGAATTRIND\:0xA
2-318
ATTR0B
VGAATTRIND\:0xB
2-319
ATTR0C
VGAATTRIND\:0xC
2-319
ATTR0D
VGAATTRIND\:0xD
2-319
ATTR0E
VGAATTRIND\:0xE
2-319
ATTR0F
VGAATTRIND\:0xF
2-319
ATTR10
VGAATTRIND\:0x10
2-320
ATTR11
VGAATTRIND\:0x11
2-320
ATTR12
VGAATTRIND\:0x12
2-320
ATTR13
VGAATTRIND\:0x13
2-321
ATTR14
VGAATTRIND\:0x14
2-321
ATTRDR
VGA_IO\:0x3C1
2-316
ATTRDW
VGA_IO\:0x3C0
2-316
ATTRX
VGA_IO\:0x3C0
2-316
BACKBIAS_ENABLE_CNT
CLKIND:0x37
2-285
BASE_CODE
gcconfig:0xB
BIF_SLAVE_CNTL
MMReg:0x180C
BIOS_0_SCRATCH
IOReg:0x10
MMReg:0x10
2-353
BIOS_1_SCRATCH
IOReg:0x14
MMReg:0x14
2-353
BIOS_10_SCRATCH
IOReg:0xC8
MMReg:0xC8
2-355
BIOS_11_SCRATCH
IOReg:0xCC
MMReg:0xCC
2-355
BIOS_12_SCRATCH
IOReg:0xD0
MMReg:0xD0
2-355
BIOS_13_SCRATCH
IOReg:0xD4
MMReg:0xD4
2-355
BIOS_14_SCRATCH
IOReg:0xD8
MMReg:0xD8
2-355
BIOS_15_SCRATCH
IOReg:0xDC
MMReg:0xDC
2-356
BIOS_2_SCRATCH
IOReg:0x18
MMReg:0x18
2-353
BIOS_3_SCRATCH
IOReg:0x1C
MMReg:0x1C
2-354
BIOS_4_SCRATCH
IOReg:0x20
MMReg:0x20
2-354
BIOS_5_SCRATCH
IOReg:0x24
MMReg:0x24
2-354
BIOS_6_SCRATCH
IOReg:0x28
MMReg:0x28
2-354
BIOS_7_SCRATCH
IOReg:0x2C
MMReg:0x2C
2-354
BIOS_8_SCRATCH
IOReg:0xC0
MMReg:0xC0
2-355
BIOS_9_SCRATCH
IOReg:0xC4
MMReg:0xC4
2-355
AMD RS690 ASIC Family Register Reference Manual
A-4
MMReg:0x500B
Page
2-111
2-350
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
BIST
gcconfig:0xF
MMReg:0x500F
2-112
BUS_CNTL
IOReg:0x30
MMReg:0x30
2-351
BUS_CNTL1
IOReg:0x34
MMReg:0x34
2-352
CACHE_LINE
gcconfig:0xC
MMReg:0x500C:R
CAP_PTR
pcieConfigDev[10:2]\:0x34
CAPABILITIES_PTR
gcconfig:0x34
CC_COMBINED_STRAPS_0
CLKIND:0x33
Page
2-114
2-78
MMReg:0x5034
2-112
2-284
CC_COMBINED_STRAPS_1
CLKIND:0x34
2-285
CC_DEBUG_STRAPS_0
CLKIND:0x2F
2-281
CC_DEBUG_STRAPS_1
CLKIND:0x30
2-282
CC_FUSE_STRAPS_0
CLKIND:0x2D
2-280
CC_FUSE_STRAPS_1
CLKIND:0x2E
2-281
CC_IO_STRAPS
CLKIND:0x31
2-282
CC_IO_STRAPS_12A
CLKIND:0x31
2-283
CC_IO_STRAPS_22A
CLKIND:0x31
2-282
CC_ROM_STRAPS
CLKIND:0x32
2-283
CFG_CT_CLKGATE_HTIU
clkconfig:0xF8
2-138
CG_CLKPIN_CNTL
CLKIND:0x35
2-285
CG_DEBUG
CLKIND:0x20
2-277
CG_INTGFX_MISC
CLKIND:0x5C
2-292
CG_INTGFX_SPARE_RO
CLKIND:0x5D
2-293
CG_MISC_REG
CLKIND:0x1F
2-277
CG_SPLL_ANALOG_CTRL0
CLKIND:0x5A
2-292
CG_SPLL_ANALOG_CTRL1
CLKIND:0x5B
2-292
CG_TC_JTAG_0
CLKIND:0x38
2-286
CG_TC_JTAG_1
CLKIND:0x39
2-286
CLK_CFG_HTPLL_CNTL
clkconfig\:0xD4
2-136
CLK_TOP_PERF_CNTL
clkconfig:0xAC
2-135
clk_top_pwm1_ctrl
clkconfig:0xB0
2-141
clk_top_pwm2_ctrl
clkconfig:0xB4
2-141
clk_top_pwm3_ctrl
clkconfig:0xCC
2-142
CLK_TOP_PWM4_CTRL
clkconfig:0x4C
2-138
CLK_TOP_PWM5_CTRL
clkconfig:0x50
2-139
CLK_TOP_SPARE_A
clkconfig:0xE0
2-136
CLK_TOP_SPARE_B
clkconfig:0xE4
2-137
CLK_TOP_SPARE_C
clkconfig:0xE8
2-137
CLK_TOP_SPARE_D
clkconfig:0xEC
2-137
clk_top_spare_pll
clkconfig:0xD0
2-142
clk_top_test_ctrl
clkconfig:0xB8
2-141
CLK_TOP_THERMAL_ALERT_INTR
clkconfig:0xC0
_EN
2-141
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-5
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
Page
CLK_TOP_THERMAL_ALERT_STAT
clkconfig:0xC4
US
2-141
CLK_TOP_THERMAL_ALERT_WAIT
clkconfig:0xC8
_WINDOW
2-142
CLKGATE_DISABLE
clkconfig:0x94
2-132
CLKGATE_DISABLE2
clkconfig:0x8C
2-132
CLOCK_CNTL_DATA
IOReg:0xC
MMReg:0xC
2-267
CLOCK_CNTL_INDEX
IOReg:0x8
MMReg:0x8
2-267
COMMAND
gcconfig:0x4
MMReg:0x5004:R
2-110
CONFIG_APER_SIZE
MMReg\:0x108
CONFIG_CNTL
IOReg\:0xE0
CONFIG_MEM_BASE_HI
MMReg:0x104
CONFIG_MEM_BASE_LO
MMReg:0x100
CONFIG_MEMSIZE
IOReg\:0xF8
CONFIG_REG_APER_SIZE
MMReg:0x114
2-113
CONFIG_REG_BASE_HI
MMReg:0x110
2-357
CONFIG_REG_BASE_LO
MMReg:0x10C
CONFIG_XSTRAP
IOReg:0xE4
CP_DYN_CNTL
CLKIND:0xF
2-272
CPLL_CONTROL
clkconfig:0x44
2-138
CPLL_CONTROL2
clkconfig:0x98
2-140
CPLL_CONTROL3
clkconfig:0x70
2-140
CRS_TIMER
pcieConfigDev[10:2]\:0x90
2-87
CRT00
VGACRTIND\:0x0
2-303
CRT01
VGACRTIND\:0x1
2-303
CRT02
VGACRTIND\:0x2
2-303
CRT03
VGACRTIND\:0x3
2-304
CRT04
VGACRTIND\:0x4
2-304
CRT05
VGACRTIND\:0x5
2-304
CRT06
VGACRTIND\:0x6
2-305
CRT07
VGACRTIND\:0x7
2-305
CRT08
VGACRTIND\:0x8
2-306
CRT09
VGACRTIND\:0x9
2-306
CRT0A
VGACRTIND\:0xA
2-306
CRT0B
VGACRTIND\:0xB
2-307
CRT0C
VGACRTIND\:0xC
2-307
CRT0D
VGACRTIND\:0xD
2-307
CRT0E
VGACRTIND\:0xE
2-307
CRT0F
VGACRTIND\:0xF
2-308
CRT10
VGACRTIND\:0x10
2-308
CRT11
VGACRTIND\:0x11
2-308
CRT12
VGACRTIND\:0x12
2-309
AMD RS690 ASIC Family Register Reference Manual
A-6
2-112
MMReg\:0xE0
2-112
2-356
2-356
MMReg\:0xF8
2-112
2-356
MMReg:0xE4
2-356
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
CRT13
VGACRTIND\:0x13
2-309
CRT14
VGACRTIND\:0x14
2-309
CRT15
VGACRTIND\:0x15
2-309
CRT16
VGACRTIND\:0x16
2-310
CRT17
VGACRTIND\:0x17
2-310
CRT18
VGACRTIND\:0x18
2-310
CRT1E
VGACRTIND\:0x1E
2-311
CRT1F
VGACRTIND\:0x1F
2-311
CRT22
VGACRTIND\:0x22
2-311
CRTC8_DATA
MMReg:0x3B5
MMReg:0x3D5
MMReg:0x3D4
VGA_IO:0x3B5
VGA_IO:0x3D5:I 2-303
O:0x3D5
VGA_IO:0x3B4
VGA_IO:0x3D4: 2-303
O:0x3D4
CRTC8_IDX
MMReg:0x3B4
CT_DISABLE_BIU
clkconfig:0x68
DAC_CNTL
IOReg:0x58
DAC_DATA
VGA_IO\:0x3C9
2-296
DAC_MASK
VGA_IO\:0x3C6
2-296
DAC_R_INDEX
VGA_IO\:0x3C7
2-296
2-139
MMReg:0x58
2-299
DAC_W_INDEX
VGA_IO\:0x3C8
2-296
DELAY_SET_IOC_CCLK
clkconfig:0x5C
2-139
DEVICE_CAP
pcieConfigDev[10:2]\:0x5C
2-80
DEVICE_CNTL
pcieConfigDev[10:2]\:0x60
2-81
DEVICE_ID
gcconfig:0x2
DEVICE_STATUS
pcieConfigDev[10:2]\:0x62
MMReg:0x5002
2-82
2-110
DFT_CNTL0
NBMISCIND:0x5
2-27
DFT_CNTL1
NBMISCIND:0x6
2-27
DFT_CNTL2
NBMISCIND:0x10
2-28
DFT_SPARE
NBMISCIND:0x7F
2-43
DFT_VIP_IO_GPIO
NBMISCIND:0x44
2-32
DFT_VIP_IO_GPIO_OR
NBMISCIND:0x45
2-33
DLL_CNTL
CLKIND:0x23
2-278
DYN_BACKBIAS_CNTL
CLKIND:0x29
2-279
DYN_PWRMGT_SCLK_CNTL
CLKIND:0xB
2-271
DYN_PWRMGT_SCLK_LENGTH
CLKIND:0xC
2-272
DYN_SCLK_PWMEN_PIPE
CLKIND:0xD
2-272
DYN_SCLK_VOL_CNTL
CLKIND:0xE
2-272
E2_DYN_CNTL
CLKIND:0x11
2-273
ERROR_STATUS
CLKIND:0x2C
2-280
F1_ADAPTER_ID
gcconfig:0x12C
© 2007 Advanced Micro Devices, Inc.
Proprietary
MMReg:0x512C
2-118
AMD RS690 ASIC Family Register Reference Manual
A-7
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
F1_ADAPTER_ID_W
gcconfig:0x14C
MMReg:0x514C:R
2-120
F1_BASE_CODE
gcconfig:0x10B
MMReg:0x510B
2-117
F1_BIST
gcconfig:0x10F
MMReg:0x510F
2-117
F1_CACHE_LINE
gcconfig:0x10C
MMReg:0x510C:R
2-117
F1_CAPABILITIES_PTR
gcconfig:0x134
MMReg:0x5134
2-118
F1_COMMAND
gcconfig:0x104
MMReg:0x5104:R
2-116
F1_DEVICE_ID
gcconfig:0x102
MMReg:0x5102
2-116
F1_HEADER
gcconfig:0x10E
MMReg:0x510E
2-117
F1_INTERRUPT_LINE
gcconfig:0x13C
MMReg:0x513C:R
2-118
F1_INTERRUPT_PIN
gcconfig:0x13D
MMReg:0x513D
2-118
F1_LATENCY
gcconfig:0x10D
MMReg:0x510D:R
2-117
F1_MAX_LATENCY
gcconfig:0x13F
MMReg:0x513F
2-119
F1_MIN_GRANT
gcconfig:0x13E
MMReg:0x513E
2-119
F1_PMI_CAP_ID
gcconfig:0x150
MMReg:0x5150
2-119
F1_PMI_DATA
gcconfig:0x157
MMReg:0x5157
2-119
F1_PMI_NXT_CAP_PTR
gcconfig:0x151
MMReg:0x5151
2-119
F1_PMI_PMC_REG
gcconfig:0x152
MMReg:0x5152
2-119
F1_PMI_STATUS
gcconfig:0x154
MMReg:0x5154:R
2-120
F1_REG_BASE_HI
gcconfig:0x114
MMReg:0x511C:R
2-118
F1_REG_BASE_LO
gcconfig:0x110
MMReg:0x5114:R
2-118
F1_REGPROG_INF
gcconfig:0x109
MMReg:0x5109
2-116
F1_REVISION_ID
gcconfig:0x108
MMReg:0x5108
2-116
F1_STATUS
gcconfig:0x106
MMReg:0x5106
2-116
F1_SUB_CLASS
gcconfig:0x10A
MMReg:0x510A
2-117
F1_VENDOR_ID
gcconfig:0x100
MMReg:0x5100
2-116
F2_ADAPTER_ID
gcconfig:0x22C
MMReg:0x522C
2-123
F2_ADAPTER_ID_W
gcconfig:0x24C
MMReg:0x524C:R
2-124
F2_BASE_CODE
gcconfig:0x20B
MMReg:0x520B
2-122
F2_BIST
gcconfig:0x20F
MMReg:0x520F
2-122
F2_CACHE_LINE
gcconfig:0x20C
MMReg:0x520C:R
2-122
F2_CAPABILITIES_PTR
gcconfig:0x234
MMReg:0x5234
2-123
F2_COMMAND
gcconfig:0x204
MMReg:0x5204:R
2-121
F2_DEVICE_ID
gcconfig:0x202
MMReg:0x5202
2-120
F2_HEADER
gcconfig:0x20E
MMReg:0x520E
2-122
F2_INTERRUPT_LINE
gcconfig:0x23C
MMReg:0x523C:R
2-123
F2_INTERRUPT_PIN
gcconfig:0x23D
MMReg:0x523D
2-123
F2_LATENCY
gcconfig:0x20D
MMReg:0x520D:R
2-122
F2_MAX_LATENCY
gcconfig:0x23F
MMReg:0x523F
2-124
F2_MIN_GRANT
gcconfig:0x23E
MMReg:0x523E
2-123
F2_MSI_CAP_ID
gcconfig:0x260
MMReg:0x5260
2-125
F2_MSI_MSG_ADDR_HI
gcconfig:0x268
MMReg:0x5268:R
2-126
AMD RS690 ASIC Family Register Reference Manual
A-8
Page
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
F2_MSI_MSG_ADDR_LO
gcconfig:0x264
MMReg:0x5264:R
2-126
F2_MSI_MSG_CNTL
gcconfig:0x262
MMReg:0x5262:R
2-126
F2_MSI_MSG_DATA
gcconfig:0x26C
MMReg:0x526C:R
2-126
Page
F2_MSI_NXT_CAP_PTR
gcconfig:0x261
MMReg:0x5261
2-125
F2_PMI_CAP_ID
gcconfig:0x250
MMReg:0x5250
2-124
F2_PMI_DATA
gcconfig:0x257
MMReg:0x5257
2-125
F2_PMI_NXT_CAP_PTR
gcconfig:0x251
MMReg:0x5251
2-124
F2_PMI_PMC_REG
gcconfig:0x252
MMReg:0x5252
2-124
F2_PMI_STATUS
gcconfig:0x254
MMReg:0x5254:R
2-125
F2_REG_BASE_HI
gcconfig:0x214
MMReg:0x5214:R
2-123
F2_REG_BASE_LO
gcconfig:0x210
MMReg:0x5210:R
2-122
F2_REGPROG_INF
gcconfig:0x209
MMReg:0x5209
2-121
F2_REVISION_ID
gcconfig:0x208
MMReg:0x5208
2-121
F2_STATUS
gcconfig:0x206
MMReg:0x5206
2-121
F2_SUB_CLASS
gcconfig:0x20A
MMReg:0x520A
2-121
F2_VENDOR_ID
gcconfig:0x200
MMReg:0x5200
FG_DYN_CNTL
CLKIND:0x17
2-275
FVTHROT_CNTRL_REG
CLKIND:0x3A
2-286
FVTHROT_COMPARE_BOUND1
CLKIND:0x3C
2-287
FVTHROT_COMPARE_BOUND2
CLKIND:0x3D
2-287
FVTHROT_COMPARE_BOUND3
CLKIND:0x3E
2-287
FVTHROT_COMPARE_BOUND4
CLKIND:0x3F
2-287
FVTHROT_DOWNTREND_COEF0
CLKIND:0x45
2-288
FVTHROT_DOWNTREND_COEF1
CLKIND:0x46
2-289
FVTHROT_DOWNTREND_COEF2
CLKIND:0x47
2-289
FVTHROT_DOWNTREND_COEF3
CLKIND:0x48
2-289
FVTHROT_DOWNTREND_COEF4
CLKIND:0x49
2-289
FVTHROT_FB_DOWNSTEP_REG0
CLKIND:0x4F
2-290
FVTHROT_FB_DOWNSTEP_REG1
CLKIND:0x50
2-290
FVTHROT_FB_UPSTEP_REG0
CLKIND:0x4D
2-290
FVTHROT_FB_UPSTEP_REG1
CLKIND:0x4E
2-290
FVTHROT_FBDIV_REG0
CLKIND:0x4A
2-289
FVTHROT_FBDIV_REG1
CLKIND:0x4B
2-289
FVTHROT_FBDIV_REG2
CLKIND:0x4C
2-290
FVTHROT_PWM_CTRL_REG0
CLKIND:0x51
2-290
FVTHROT_PWM_CTRL_REG1
CLKIND:0x52
2-291
FVTHROT_PWM_DOWNSTEP_REG
CLKIND:0x55
0
2-291
FVTHROT_PWM_DOWNSTEP_REG
CLKIND:0x56
1
2-291
FVTHROT_PWM_FEEDBACK_DIV_
CLKIND:0x5E
REG1
2-293
© 2007 Advanced Micro Devices, Inc.
Proprietary
2-120
AMD RS690 ASIC Family Register Reference Manual
A-9
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
Page
FVTHROT_PWM_FEEDBACK_DIV_
CLKIND:0x5F
REG2
2-293
FVTHROT_PWM_FEEDBACK_DIV_
CLKIND:0x60
REG3
2-293
FVTHROT_PWM_FEEDBACK_DIV_
CLKIND:0x61
REG4
2-293
FVTHROT_PWM_UPSTEP_REG0
CLKIND:0x53
2-291
FVTHROT_PWM_UPSTEP_REG1
CLKIND:0x54
2-291
FVTHROT_SCALE_FEEDBACK_DIV
CLKIND:0x67
_REG1
2-295
FVTHROT_SLOW_CLK_FEEDBACK
CLKIND:0x66
_DIV_REG1
2-294
FVTHROT_SPLL_PARAM_FEEDBA
CK_DIV_REG1
CLKIND:0x62
2-294
FVTHROT_SPLL_PARAM_FEEDBA
CK_DIV_REG2
CLKIND:0x63
2-294
FVTHROT_SPLL_PARAM_FEEDBA
CK_DIV_REG3
CLKIND:0x64
2-294
FVTHROT_SPLL_PARAM_FEEDBA
CK_DIV_REG4
CLKIND:0x65
2-294
FVTHROT_STATUS_REG0
CLKIND:0x57
2-291
FVTHROT_STATUS_REG1
CLKIND:0x58
2-292
FVTHROT_STATUS_REG2
CLKIND:0x59
2-292
FVTHROT_TARGET_REG
CLKIND:0x3B
2-287
FVTHROT_UPTREND_COEF0
CLKIND:0x40
2-287
FVTHROT_UPTREND_COEF1
CLKIND:0x41
2-288
FVTHROT_UPTREND_COEF2
CLKIND:0x42
2-288
FVTHROT_UPTREND_COEF3
CLKIND:0x43
2-288
FVTHROT_UPTREND_COEF4
CLKIND:0x44
2-288
GA_DYN_CNTL
CLKIND:0x1B
2-274
GART_BASE
NBMCIND\:0x2C
2-157
GART_CACHE_CNTRL
NBMCIND:0x2E
2-157
GART_CACHE_ENTRY_CNTRL
NBMCIND\:0x2F
2-157
GART_CACHE_SZBASE
NBMCIND\:0x2D
2-157
GART_ERROR_0
NBMCIND\:0x30
2-158
GART_ERROR_1
NBMCIND\:0x31
2-158
GART_ERROR_2
NBMCIND\:0x32
2-158
GART_ERROR_3
NBMCIND\:0x33
2-158
GART_ERROR_4
NBMCIND\:0x34
2-159
GART_ERROR_5
NBMCIND\:0x35
2-159
GART_ERROR_6
NBMCIND\:0x36
2-159
GART_ERROR_7
NBMCIND\:0x37
2-159
GART_FEATURE_ID
NBMCIND:0x2B
2-155
AMD RS690 ASIC Family Register Reference Manual
A-10
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
GC_CLK_CNTRL
clkconfig:0x74
2-131
GENENB
VGA_IO\:0x3C3
2-127
GENERAL_PWRMGT
CLKIND:0x8
2-270
GENFC_RD
VGA_IO\:0x3CA
GENFC_WT
VGA_IO\:0x3BA
VGA_IO\:0x3DA
2-297
2-297
GENMO_RD
MMReg:0x3CC
VGA_IO:0x3CC
2-128
GENMO_RD
VGA_IO\:0x3CC
GENMO_WT
MMReg:0x3C2
GENMO_WT
VGA_IO\:0x3C2
2-297
GENS0
VGA_IO\:0x3C2
2-299
GENS1
VGA_IO\:0x3BA
GPIO_PAD
NBMISCIND:0x40
2-31
GPIO_PAD_CNTL_PU_PD
NBMISCIND:0x41
2-31
GPIO_PAD_SCHMEM_OE
NBMISCIND:0x42
2-32
GPIO_PAD_SP_SN
NBMISCIND:0x43
2-32
GRA00
VGAGRPHIND\:0x0
2-312
GRA01
VGAGRPHIND\:0x1
2-312
GRA02
VGAGRPHIND\:0x2
2-313
GRA03
VGAGRPHIND\:0x3
2-313
GRA04
VGAGRPHIND\:0x4
2-313
GRA05
VGAGRPHIND\:0x5
2-314
GRA06
VGAGRPHIND\:0x6
2-314
GRA07
VGAGRPHIND\:0x7
2-315
2-298
VGA_IO:0x3C2
VGA_IO\:0x3DA
2-127
2-299
GRA08
VGAGRPHIND\:0x8
GRPH8_DATA
MMReg:0x3CF
VGA_IO:0x3CF
2-315
2-312
GRPH8_IDX
MMReg:0x3CE
VGA_IO:0x3CE
2-312
HD_BACKPORCH_DUR
MMReg:0x5FB0
2-347
HD_EMBEDDED_SYNC_CNTL
MMReg:0x5FA0
2-346
HD_INCR
MMReg:0x5FA4
2-346
HD_POS_SYNC_LEVEL
MMReg:0x5FAC
2-347
HD_SERATION_DUR
MMReg:0x5FB4
2-347
HD_TRILEVEL_DUR
MMReg:0x5FA8
2-346
HDP_DYN_CNTL
CLKIND:0x10
2-273
HDP_FB_LOCATION
MMReg:0x134
2-357
HEADER
gcconfig:0xE
HTIU_CNTL_1
HTIUNBIND:0x0
2-43
HTIU_CNTL_2
HTIUNBIND:0x1
2-43
HTIU_DEBUG
HTIUNBIND:0x5
2-46
HTIU_DOWNSTREAM_CONFIG
HTIUNBIND:0x6
2-46
HTIU_NB_DATA
nbconfig:0xAC
2-26
HTIU_NB_INDEX
nbconfig:0xA8
2-26
© 2007 Advanced Micro Devices, Inc.
Proprietary
MMReg:0x500E
2-113
AMD RS690 ASIC Family Register Reference Manual
A-11
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
Page
HTIU_PERF_CNTL
HTIUNBIND:0x2
2-43
HTIU_PERF_COUNT_0
HTIUNBIND:0x3
2-45
HTIU_PERF_COUNT_1
HTIUNBIND:0x4
2-45
HTIU_UPSTREAM_CONFIG_0
HTIUNBIND:0x7
2-47
HTIU_UPSTREAM_CONFIG_1
HTIUNBIND:0x8
2-48
HTIU_UPSTREAM_CONFIG_10
HTIUNBIND:0x11
2-52
HTIU_UPSTREAM_CONFIG_11
HTIUNBIND:0x12
2-52
HTIU_UPSTREAM_CONFIG_12
HTIUNBIND:0x13
2-52
HTIU_UPSTREAM_CONFIG_13
HTIUNBIND:0x14
2-53
HTIU_UPSTREAM_CONFIG_14
HTIUNBIND:0x15
2-53
HTIU_UPSTREAM_CONFIG_15
HTIUNBIND:0x16
2-54
HTIU_UPSTREAM_CONFIG_16
HTIUNBIND:0x17
2-54
HTIU_UPSTREAM_CONFIG_17
HTIUNBIND:0x18
2-54
HTIU_UPSTREAM_CONFIG_18
HTIUNBIND:0x19
2-55
HTIU_UPSTREAM_CONFIG_19
HTIUNBIND:0x1A
2-55
HTIU_UPSTREAM_CONFIG_2
HTIUNBIND:0x9
2-48
HTIU_UPSTREAM_CONFIG_20
HTIUNBIND:0x1B
2-56
HTIU_UPSTREAM_CONFIG_21
HTIUNBIND:0x1C
2-56
HTIU_UPSTREAM_CONFIG_22
HTIUNBIND:0x1D
2-56
HTIU_UPSTREAM_CONFIG_23
HTIUNBIND:0x1E
2-56
HTIU_UPSTREAM_CONFIG_24
HTIUNBIND:0x1F
2-56
HTIU_UPSTREAM_CONFIG_3
HTIUNBIND:0xA
2-49
HTIU_UPSTREAM_CONFIG_4
HTIUNBIND:0xB
2-49
HTIU_UPSTREAM_CONFIG_5
HTIUNBIND:0xC
2-50
HTIU_UPSTREAM_CONFIG_6
HTIUNBIND:0xD
2-50
HTIU_UPSTREAM_CONFIG_7
HTIUNBIND:0xE
2-51
HTIU_UPSTREAM_CONFIG_8
HTIUNBIND:0xF
2-51
HTIU_UPSTREAM_CONFIG_9
HTIUNBIND:0x10
2-51
INTERRUPT_LINE
gcconfig:0x3C
MMReg:0x503C:R
2-113
INTERRUPT_PIN
gcconfig:0x3D
MMReg:0x503D
2-113
IO_BASE
gcconfig:0x20
MMReg:0x5020:R
2-111
IO_BASE_LIMIT
pcieConfigDev[10:2]\:0x1C
2-76
IO_BASE_LIMIT_HI
pcieConfigDev[10:2]\:0x30
2-77
IOC_CNTL
pcieConfigDev[10:2]\:0x94
2-88
IOC_DMA_ARBITER
NBMISCIND\:0x9
2-10
IOC_LAT_PERF_CNTR_CNTL
NBMISCIND:0x30
2-29
IOC_LAT_PERF_CNTR_OUT
NBMISCIND:0x31
2-29
IOC_P2P_CNTL
NBMISCIND:0xC
2-11
IOC_PCIE_CNTL
NBMISCIND:0xB
2-10
IOC_PCIE_CSR_Count
NBMISCIND\:0xA
2-10
IOC_PCIE_D2_CNTL
NBMISCIND:0x51
2-34
AMD RS690 ASIC Family Register Reference Manual
A-12
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
IOC_PCIE_D2_CSR_Count
NBMISCIND:0x50
2-34
IOC_PCIE_D3_CNTL
NBMISCIND:0x53
2-35
IOC_PCIE_D3_CSR_Count
NBMISCIND:0x52
2-34
IOC_PCIE_D4_CNTL
NBMISCIND:0x55
2-35
IOC_PCIE_D4_CSR_Count
NBMISCIND:0x54
2-35
IOC_PCIE_D5_CNTL
NBMISCIND:0x57
2-36
IOC_PCIE_D5_CSR_Count
NBMISCIND:0x56
2-35
IOC_PCIE_D6_CNTL
NBMISCIND:0x59
2-36
IOC_PCIE_D6_CSR_Count
NBMISCIND:0x58
2-36
IOC_PCIE_D7_CNTL
NBMISCIND:0x5B
2-37
IOC_PCIE_D7_CSR_Count
NBMISCIND:0x5A
2-37
IOCIsocMapAddr_HI
NBMISCIND:0xF
2-28
IOCIsocMapAddr_LO
NBMISCIND:0xE
2-27
IRQ_BRIDGE_CNTL
pcieConfigDev[10:2]\:0x3E
2-78
K8_DRAM_BANK_ADDR_MAPPING NBMCIND\:0x73
2-167
K8_DRAM_CS0_BASE
NBMCIND:0x63
2-162
K8_DRAM_CS0_MASK
NBMCIND:0x6B
2-165
K8_DRAM_CS1_BASE
NBMCIND:0x64
2-163
K8_DRAM_CS1_MASK
NBMCIND:0x6C
2-165
K8_DRAM_CS2_BASE
NBMCIND:0x65
2-163
K8_DRAM_CS2_MASK
NBMCIND:0x6D
2-165
K8_DRAM_CS3_BASE
NBMCIND:0x66
2-163
K8_DRAM_CS3_MASK
NBMCIND:0x6E
2-166
K8_DRAM_CS4_BASE
NBMCIND:0x67
2-164
K8_DRAM_CS4_MASK
NBMCIND:0x6F
2-166
K8_DRAM_CS5_BASE
NBMCIND:0x68
2-164
K8_DRAM_CS5_MASK
NBMCIND:0x70
2-166
K8_DRAM_CS6_BASE
NBMCIND:0x69
2-164
K8_DRAM_CS6_MASK
NBMCIND\:0x71
2-166
K8_DRAM_CS7_BASE
NBMCIND:0x6A
2-165
K8_DRAM_CS7_MASK
NBMCIND\:0x72
2-167
K8_FB_LOCATION
NBMCIND\:0x1E
LATENCY
gcconfig:0xD
LINK_CAP
pcieConfigDev[10:2]\:0x64
2-82
LINK_CNTL
pcieConfigDev[10:2]\:0x68
2-83
LINK_STATUS
pcieConfigDev[10:2]\:0x6A
2-83
LVTMA_2ND_CRC_RESULT
MMReg:0x7ABC
2-349
LVTMA_CRC_CNTL
MMReg:0x7AB0
2-348
LVTMA_CRC_SIG_MASK
MMReg:0x7AB4
2-348
LVTMA_CRC_SIG_RGB
MMReg:0x7AB8
2-349
MAX_LATENCY
gcconfig:0x3F
© 2007 Advanced Micro Devices, Inc.
Proprietary
2-154
MMReg:0x500D:R
MMReg:0x503F
2-113
2-113
AMD RS690 ASIC Family Register Reference Manual
A-13
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
MC_ARB_CNTL
NBMCIND:0x107
2-260
MC_AZ_DEFAULT_ADDR
NBMCIND:0x99
2-195
MC_BIST_CNTL0
NBMCIND:0x111
2-262
MC_BIST_CNTL1
NBMCIND:0x112
2-262
MC_BIST_MISMATCH_H
NBMCIND:0x114
2-263
MC_BIST_MISMATCH_L
NBMCIND:0x113
2-263
MC_BIST_PATTERN0H
NBMCIND:0x116
2-263
MC_BIST_PATTERN0L
NBMCIND:0x115
2-263
MC_BIST_PATTERN1H
NBMCIND:0x118
2-264
MC_BIST_PATTERN1L
NBMCIND:0x117
2-264
MC_BIST_PATTERN2H
NBMCIND:0x11A
2-264
MC_BIST_PATTERN2L
NBMCIND:0x119
2-264
MC_BIST_PATTERN3H
NBMCIND:0x11C
2-264
MC_BIST_PATTERN3L
NBMCIND:0x11B
2-264
MC_BIST_PATTERN4H
NBMCIND:0x11E
2-265
MC_BIST_PATTERN4L
NBMCIND:0x11D
2-264
MC_BIST_PATTERN5H
NBMCIND:0x120
2-265
MC_BIST_PATTERN5L
NBMCIND:0x11F
2-265
MC_BIST_PATTERN6H
NBMCIND:0x122
2-265
MC_BIST_PATTERN6L
NBMCIND:0x121
2-265
MC_BIST_PATTERN7H
NBMCIND:0x124
2-265
MC_BIST_PATTERN7L
NBMCIND:0x123
2-265
MC_DEBUG_CNTL
NBMCIND:0x108
2-261
MC_GART_ERROR_ADDRESS
NBMCIND\:0x3B
2-161
MC_GART_ERROR_ADDRESS_HI
NBMCIND\:0x3C
2-161
MC_GENERAL_PURPOSE
NBMCIND:0x0
2-153
MC_GUI_DYN_CNTL
CLKIND:0x1D
2-276
MC_HOST_DYN_CNTL
CLKIND:0x1E
2-277
MC_INIT_GFX_LAT_TIMER
NBMCIND:0x105
2-259
MC_INIT_MISC_LAT_TIMER
NBMCIND:0x104
2-258
MC_INIT_WR_LAT_TIMER
NBMCIND:0x106
2-259
MC_INTFC_GENERAL_PURPOSE
NBMCIND:0x91
2-192
MC_INTFC_IMP_CTRL_CNTL
NBMCIND:0x92
2-193
MC_INTFC_IMP_CTRL_REF
NBMCIND:0x93
2-193
MC_LATENCY_COUNT_CNTL
NBMCIND:0x94
2-194
MC_LATENCY_COUNT_EVENT
NBMCIND:0x95
2-194
MC_MCLK_CONTROL
NBMCIND:0x7A
2-172
MC_MISC_CNTL
NBMCIND:0x18
2-153
MC_MISC_CNTL2
NBMCIND:0x4E
2-161
MC_MISC_CNTL3
NBMCIND:0x4F
2-182
MC_MISC_UMA_CNTL
NBMCIND:0x5F
2-162
AMD RS690 ASIC Family Register Reference Manual
A-14
Page
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
MC_MISC_UMA_CNTL2
NBMCIND\:0x7E
2-173
MC_MPLL_CONTROL
NBMCIND:0x74
2-169
MC_MPLL_CONTROL2
NBMCIND:0x75
2-169
MC_MPLL_CONTROL3
NBMCIND:0x76
2-170
MC_MPLL_DIV_CONTROL
NBMCIND:0x79
2-171
MC_MPLL_FREQ_CONTROL
NBMCIND:0x77
2-170
MC_MPLL_SEQ_CONTROL
NBMCIND:0x78
2-171
MC_PM_CNTL
NBMCIND\:0x26
2-154
MC_RBS_DYN_CNTL
CLKIND:0x26
2-277
MC_SYSTEM_STATUS
NBMCIND:0x90
2-191
MC_UMA_AGP_GRP_CNTL
NBMCIND:0x85
2-179
MC_UMA_AGP_GRP_CNTL
NBMCIND:0x85
2-189
MC_UMA_DUALCH_CNTL
NBMCIND:0x86
2-180
MC_UMA_DUALCH_CNTL
NBMCIND:0x86
2-190
MC_UMA_GRP_CNTL
NBMCIND\:0x7C
2-172
MC_UMA_GRP_TMR
NBMCIND\:0x7D
2-173
MC_UMA_HDR_LAT_INIT
NBMCIND\:0x7B
2-172
MC_UMA_RW_G3DR_GRP_CNTL
NBMCIND:0x83
2-176
MC_UMA_RW_G3DR_GRP_CNTL
NBMCIND:0x83
2-185
MC_UMA_RW_GRP_TMR
NBMCIND:0x82
2-176
MC_UMA_RW_GRP_TMR
NBMCIND:0x82
2-184
MC_UMA_RW_TXR_E2R_GRP_CNT
NBMCIND:0x84
L
2-178
MC_UMA_RW_TXR_E2R_GRP_CNT
NBMCIND:0x84
L
2-187
MC_UMA_WC_GRP_CNTL
NBMCIND:0x81
2-175
MC_UMA_WC_GRP_CNTL
NBMCIND:0x81
2-183
MC_UMA_WC_GRP_TMR
NBMCIND:0x80
2-174
MC_UMA_WC_GRP_TMR
NBMCIND:0x80
2-182
MCA_CKE_MUX_SELECT
NBMCIND:0xAD
2-206
MCA_DLL_MASTER_0
NBMCIND:0xD8
2-253
MCA_DLL_MASTER_1
NBMCIND:0xD9
2-254
MCA_DLL_SLAVE_RD_0
NBMCIND:0xE0
2-254
MCA_DLL_SLAVE_RD_1
NBMCIND:0xE1
2-254
MCA_DLL_SLAVE_WR_0
NBMCIND:0xE8
2-254
MCA_DLL_SLAVE_WR_1
NBMCIND:0xE9
2-255
MCA_DQ_DQS_READ_BACK
NBMCIND:0xC6
2-235
MCA_DQS_CLK_READ_BACK
NBMCIND:0xC7
2-235
MCA_DRIVING
NBMCIND:0xB4
2-216
MCA_GENERAL_PURPOSE
NBMCIND:0xC3
2-233
MCA_GENERAL_PURPOSE_2
NBMCIND:0xC4
2-234
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-15
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
MCA_IN_TIMING_DQS_3210
NBMCIND:0xB2
2-212
MCA_IN_TIMING_DQS_3210_PM
NBMCIND:0xD0
2-244
MCA_IN_TIMING_DQS_7654
NBMCIND:0xB3
2-214
MCA_IN_TIMING_DQS_7654_PM
NBMCIND:0xD1
2-246
MCA_MEMORY_INIT_EMRS
NBMCIND:0xA1
2-196
MCA_MEMORY_INIT_EMRS_PM
NBMCIND:0xC9
2-237
MCA_MEMORY_INIT_EMRS2
NBMCIND:0xA2
2-196
MCA_MEMORY_INIT_EMRS2_PM
NBMCIND:0xCA
2-238
MCA_MEMORY_INIT_EMRS3
NBMCIND:0xA3
2-197
MCA_MEMORY_INIT_EMRS3_PM
NBMCIND:0xCB
2-239
MCA_MEMORY_INIT_MRS
NBMCIND:0xA0
2-195
MCA_MEMORY_INIT_MRS_PM
NBMCIND:0xC8
2-237
MCA_MEMORY_INIT_SEQUENCE_
NBMCIND:0xA4
1
2-198
MCA_MEMORY_INIT_SEQUENCE_
NBMCIND:0xA5
2
2-199
MCA_MEMORY_INIT_SEQUENCE_
NBMCIND:0xA6
3
2-200
MCA_MEMORY_INIT_SEQUENCE_
NBMCIND:0xA7
4
2-201
MCA_MEMORY_TYPE
NBMCIND:0xAC
2-206
MCA_MISCELLANEOUS
NBMCIND:0xD4
2-251
MCA_MISCELLANEOUS_2
NBMCIND:0xD5
2-251
MCA_MX1X2X_DQ
NBMCIND:0xD6
2-252
MCA_MX1X2X_DQS
NBMCIND:0xD7
2-253
MCA_OCD_CONTROL
NBMCIND:0xC5
2-234
MCA_ODT_MUX_SELECT
NBMCIND:0xAE
2-207
MCA_OUT_TIMING
NBMCIND:0xB5
2-217
MCA_OUT_TIMING_DQ
NBMCIND:0xB6
2-219
MCA_OUT_TIMING_DQ_PM
NBMCIND:0xD2
2-248
MCA_OUT_TIMING_DQS
NBMCIND:0xB7
2-221
MCA_OUT_TIMING_DQS_PM
NBMCIND:0xD3
2-250
MCA_PREAMP
NBMCIND:0xBD
2-226
MCA_PREAMP_N
NBMCIND:0xBE
2-229
MCA_PREAMP_P
NBMCIND:0xBF
2-230
MCA_PREAMP_STEP
NBMCIND:0xC0
2-230
MCA_PREBUF_SLEW_N
NBMCIND:0xC1
2-232
MCA_PREBUF_SLEW_P
NBMCIND:0xC2
2-233
MCA_RECEIVING
NBMCIND:0xB1
2-211
MCA_RESERVED_0
NBMCIND:0xF0
2-255
MCA_RESERVED_1
NBMCIND:0xF1
2-255
MCA_RESERVED_2
NBMCIND:0xF2
2-255
AMD RS690 ASIC Family Register Reference Manual
A-16
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
MCA_RESERVED_3
NBMCIND:0xF3
2-255
MCA_RESERVED_4
NBMCIND:0xF4
2-255
MCA_RESERVED_5
NBMCIND:0xF5
2-256
MCA_RESERVED_6
NBMCIND:0xF6
2-256
MCA_RESERVED_7
NBMCIND:0xF7
2-256
MCA_RESERVED_8
NBMCIND:0xF8
2-256
MCA_RESERVED_9
NBMCIND:0xF9
2-256
MCA_RESERVED_A
NBMCIND:0xFA
2-256
MCA_RESERVED_B
NBMCIND:0xFB
2-256
MCA_RESERVED_C
NBMCIND:0xFC
2-257
MCA_RESERVED_D
NBMCIND:0xFD
2-257
MCA_RESERVED_E
NBMCIND:0xFE
2-257
MCA_RESERVED_F
NBMCIND:0xFF
2-257
MCA_SEQ_CONTROL
NBMCIND:0xB0
2-209
MCA_SEQ_PERF_CNTL
NBMCIND:0xAF
2-208
MCA_STRENGTH_N
NBMCIND:0xB8
2-222
MCA_STRENGTH_P
NBMCIND:0xB9
2-223
MCA_STRENGTH_READ_BACK_N
NBMCIND:0xBB
2-225
MCA_STRENGTH_READ_BACK_P
NBMCIND:0xBC
2-226
MCA_STRENGTH_STEP
NBMCIND:0xBA
2-223
MCA_TIMING_PARAMETERS_1
NBMCIND:0xA8
2-202
MCA_TIMING_PARAMETERS_1_P
M
NBMCIND:0xCC
2-239
MCA_TIMING_PARAMETERS_2
NBMCIND:0xA9
2-203
MCA_TIMING_PARAMETERS_2_P
M
NBMCIND:0xCD
2-241
MCA_TIMING_PARAMETERS_3
NBMCIND:0xAA
2-204
MCA_TIMING_PARAMETERS_3_P
M
NBMCIND:0xCE
2-242
MCA_TIMING_PARAMETERS_4
NBMCIND:0xAB
2-205
MCA_TIMING_PARAMETERS_4_P
M
NBMCIND:0xCF
2-243
MCCFG_AGP_BASE
NBMCIND:0x102
2-258
MCCFG_AGP_BASE_2
NBMCIND:0x103
2-258
MCCFG_AGP_LOCATION
NBMCIND:0x101
2-257
MCCFG_FB_LOCATION
NBMCIND:0x100
2-257
MCLK_MISC
CLKIND:0x22
2-278
MCLK_PWRMGT_CNTL
CLKIND:0xA
2-271
MCS_PERF_CNTL
NBMCIND:0x98
2-195
MCS_PERF_COUNT0
NBMCIND:0x96
2-194
MCS_PERF_COUNT1
NBMCIND:0x97
MEDIA_0_SCRATCH
IOReg:0xB0
© 2007 Advanced Micro Devices, Inc.
Proprietary
2-194
MMReg:0xB0
2-354
AMD RS690 ASIC Family Register Reference Manual
A-17
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
MEDIA_1_SCRATCH
IOReg:0xB4
MMReg:0xB4
2-354
MEM_BASE_HI
gcconfig:0x14
MMReg:0x5014:R
2-114
MEM_BASE_LIMIT
pcieConfigDev[10:2]\:0x20
MEM_BASE_LO
gcconfig:0x10
Page
2-77
MMReg:0x5010:R
2-114
MIN_GRANT
gcconfig:0x3E
MMReg:0x503E
2-114
MM_DATA
IOReg:0x4
MMReg:0x4
2-127
MM_INDEX
IOReg:0x0
MMReg:0x0
2-127
MPLL_BYPASSCLK_SEL
CLKIND:0x5
2-269
MPLL_CLK_SEL
CLKIND:0x7
2-270
MPLL_CNTL_MODE
CLKIND:0x6
2-269
MPLL_FUNC_CNTL
CLKIND:0x4
2-269
MPLL_TIME
CLKIND:0x25
2-279
MSI_CAP_ID
gcconfig:0x80
MSI_CAP_LIST
pcieConfigDev[10:2]\:0x80
MMReg:0x5080
2-86
2-115
MSI_CAP_LIST
pcieConfigDev[10:2]\:0x80
2-107
MSI_MAP
pcieConfigDev[10:2]\:0xB8
2-88
MSI_MSG_ADDR_HI
gcconfig:0x88
MMReg:0x5088:R
2-115
MSI_MSG_ADDR_LO
gcconfig:0x84
MMReg:0x5084:R
2-115
MSI_MSG_CNTL
gcconfig:0x82
MMReg:0x5082:R
2-115
MSI_MSG_DATA
gcconfig:0x8C
MMReg:0x508C:R
2-116
MSI_NXT_CAP_PTR
gcconfig:0x81
MMReg:0x5081
2-115
NB_ADAPTER_ID
nbconfig:0x2C
2-5
NB_ADAPTER_ID_W
nbconfig\:0x50
2-7
NB_AGP_ADDRESS_SPACE_SIZE
nbconfig\:0xF8
2-23
NB_AGP_MODE_CONTROL
nbconfig\:0xFC
2-24
NB_APIC_P2P_CNTL
NBMISCIND:0x3D
2-30
NB_APIC_P2P_RANGE_0
NBMISCIND:0x3E
2-30
NB_APIC_P2P_RANGE_1
NBMISCIND:0x3F
2-30
NB_BAR1_RCRB
nbconfig:0x14
2-26
NB_BAR2_PM2
nbconfig:0x18
2-4
NB_BAR3_PCIEXP_MMCFG
nbconfig:0x1C
2-5
NB_BAR3_UPPER_PCIEXP_MMCF
G
nbconfig\:0x20
2-5
NB_BASE_CODE
nbconfig\:0xB
2-3
NB_BIST
nbconfig\:0xF
2-4
NB_BROADCAST_BASE_HI
NBMISCIND:0x3B
2-29
NB_BROADCAST_BASE_LO
NBMISCIND:0x3A
2-29
NB_BROADCAST_CNTL
NBMISCIND:0x3C
2-30
NB_CACHE_LINE
nbconfig:0xC
2-3
NB_CAPABILITIES_PTR
nbconfig:0x34
2-5
NB_CFG_Q_F1000_800
nbconfig:0x9C
2-25
AMD RS690 ASIC Family Register Reference Manual
A-18
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
NB_CNTL
NBMISCIND\:0x0
2-8
NB_COMMAND
nbconfig:0x4
2-1
NB_DEVICE_ID
nbconfig:0x2
2-1
NB_ECC_CTRL
nbconfig:0x48
2-26
NB_EXSMRAM
nbconfig:0x6A
2-15
NB_FDHC
nbconfig\:0x68
2-14
NB_GC_STRAPS
nbconfig:0x8C
2-22
NB_HEADER
nbconfig:0xE
2-4
NB_HT_CLK_CNTL_RECEIVER_CO
nbconfig:0x80
MP_CNTL
2-17
NB_HT_LINK_COMMAND
nbconfig:0xC4
2-18
NB_HT_LINK_CONF_CNTL
nbconfig:0xC8
2-18
NB_HT_LINK_END
nbconfig:0xCC
2-19
NB_HT_LINK_FREQ_CAP_A
nbconfig:0xD0
2-19
NB_HT_LINK_FREQ_CAP_B
nbconfig:0xD4
2-20
NB_HT_MEMORY_BASE_UPPER
nbconfig:0xDC
2-20
NB_HT_TRANS_COMP_CNTL
nbconfig:0x94
2-17
NB_HTIU_CFG
HTIUNBIND:0x32
2-57
NB_INTERRUPT_PIN
NBMISCIND:0x1F
2-28
NB_IOC_CFG_CNTL
nbconfig:0x7C
2-34
NB_IOC_DEBUG
NBMISCIND:0x1
2-27
NB_LATENCY
nbconfig\:0xD
2-4
NB_LOWER_TOP_OF_DRAM2
HTIUNBIND:0x30
2-57
NB_MC_DATA
nbconfig\:0xEC
2-25
NB_MC_DEBUG
NBMCIND:0x1F
2-154
NB_MC_IND_DATA
nbconfig:0x74
2-33
NB_MC_IND_INDEX
nbconfig:0x70
2-33
NB_MC_INDEX
nbconfig\:0xE8
2-24
NB_MEM_CH_CNTL0
NBMCIND:0x1C
2-181
NB_MEM_CH_CNTL1
NBMCIND:0x1D
2-182
NB_MEM_CH_CNTL2
NBMCIND:0x1B
2-181
NB_MISC_DATA
nbconfig\:0x64
2-7
NB_MISC_INDEX
nbconfig\:0x60
2-7
NB_MMIOBASE
NBMISCIND:0x17
2-28
NB_MMIOLIMIT
NBMISCIND:0x18
2-28
NB_PCI_ARB
nbconfig:0x84
2-20
NB_PCI_CTRL
nbconfig:0x4C
2-6
NB_PCIE_INDX_ADDR
nbconfig\:0xE0
2-24
NB_PCIE_INDX_DATA
nbconfig\:0xE4
2-24
NB_PMCR
nbconfig\:0x6B
2-15
NB_PROG_DEVICE_REMAP_0
NBMISCIND:0x20
2-29
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-19
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
NB_REGPROG_INF
nbconfig\:0x9
2-3
NB_REVISION_ID
nbconfig:0x8
2-3
NB_SMRAM
nbconfig:0x69
2-14
NB_SPARE1
NBMISCIND\:0x2
2-8
NB_STATUS
nbconfig:0x6
2-2
NB_STRAP_READ_BACK
nbconfig:0x6C
2-15
NB_STRAPS_READBACK_DATA
NBMISCIND\:0x4
2-9
NB_STRAPS_READBACK_MUX
NBMISCIND\:0x3
2-9
NB_SUB_CLASS
nbconfig\:0xA
2-3
NB_TOM_PCI
NBMISCIND:0x16
2-28
NB_TOP_OF_DRAM_SLOT1
nbconfig:0x90
2-22
NB_UPPER_TOP_OF_DRAM2
HTIUNBIND:0x31
2-57
NB_VENDOR_ID
nbconfig\:0x0
2-1
OSC_CONTROL
clkconfig:0x40
2-130
OVERCLOCK_CNTL
CLKIND:0x2B
2-279
PCIE_ADV_ERR_CAP_CNTL
pcieConfigDev[10:2]\:0x158
2-91
PCIE_B_P90_CNTL
PCIEIND:0xF9
2-103
PCIE_BASE_CODE
pcieConfigDev[10:2]\:0xB
2-74
PCIE_BIST
pcieConfigDev[10:2]\:0xF
2-75
PCIE_BUS_CNTL
PCIEIND\:0x21
2-59
PCIE_CACHE_LINE
pcieConfigDev[10:2]\:0xC
2-74
PCIE_CAP
pcieConfigDev[10:2]\:0x5A
2-80
PCIE_CAP_LIST
pcieConfigDev[10:2]\:0x58
2-80
PCIE_CFG_SCRATCH
pcieConfigDev[10:2]\:0xC0
2-107
PCIE_CI_CNTL
PCIEIND:0x20
2-59
PCIE_CNTL
PCIEIND:0x10
2-58
PCIE_COMMAND
pcieConfigDev[10:2]\:0x4
2-73
PCIE_CONFIG_CNTL
PCIEIND\:0x11
2-58
PCIE_CORR_ERR_MASK
pcieConfigDev[10:2]\:0x154
2-91
PCIE_CORR_ERR_STATUS
pcieConfigDev[10:2]\:0x150
2-90
PCIE_DEBUG_CNTL
PCIEIND:0x12
2-94
PCIE_DEVICE_ID
pcieConfigDev[10:2]\:0x2
2-73
PCIE_ENH_ADV_ERR_RPT_CAP_H
pcieConfigDev[10:2]\:0x140
DR
2-89
PCIE_ERR_CNTL
PCIEIND_P\:0x6A
2-68
PCIE_ERR_SRC_ID
pcieConfigDev[10:2]\:0x174
2-93
PCIE_FC_CPL
PCIEIND_P\:0x62
2-68
PCIE_FC_NP
PCIEIND_P\:0x61
2-68
PCIE_FC_P
PCIEIND_P\:0x60
2-68
PCIE_HDR_LOG0
pcieConfigDev[10:2]\:0x15C
2-91
PCIE_HDR_LOG1
pcieConfigDev[10:2]\:0x160
2-91
AMD RS690 ASIC Family Register Reference Manual
A-20
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
PCIE_HDR_LOG2
pcieConfigDev[10:2]\:0x164
2-92
PCIE_HDR_LOG3
pcieConfigDev[10:2]\:0x168
2-92
PCIE_HEADER
pcieConfigDev[10:2]\:0xE
2-75
PCIE_INTERRUPT_LINE
pcieConfigDev[10:2]\:0x3C
2-78
PCIE_INTERRUPT_PIN
pcieConfigDev[10:2]\:0x3D
2-78
PCIE_LATENCY
pcieConfigDev[10:2]\:0xD
2-75
PCIE_LC_CNTL
PCIEIND_P:0xA0
2-69
PCIE_LC_LINK_WIDTH_CNTL
PCIEIND_P\:0xA2
2-72
PCIE_LC_N_FTS_CNTL
PCIEIND_P:0xA3
2-72
PCIE_LC_N_FTS_CNTL
PCIEIND_P:0xA3
2-106
PCIE_LC_STATE0
PCIEIND_P\:0xA5
2-71
PCIE_LC_STATE1
PCIEIND_P\:0xA6
2-71
PCIE_LC_STATE2
PCIEIND_P\:0xA7
2-71
PCIE_LC_STATE3
PCIEIND_P\:0xA8
2-71
PCIE_LC_STATE4
PCIEIND_P\:0xA9
2-71
PCIE_LC_STATE5
PCIEIND_P\:0xAA
2-71
PCIE_LC_TRAINING_CNTL
PCIEIND_P:0xA1
2-72
PCIE_LINK_CFG
NBMISCIND:0x8
2-9
PCIE_MSI_MSG_ADDR_HI
pcieConfigDev[10:2]\:0x88
2-87
PCIE_MSI_MSG_ADDR_LO
pcieConfigDev[10:2]\:0x84
2-87
PCIE_MSI_MSG_CNTL
pcieConfigDev[10:2]\:0x82
2-86
PCIE_MSI_MSG_DATA
pcieConfigDev[10:2]\:0x88
2-87
PCIE_MSI_MSG_DATA_64
pcieConfigDev[10:2]\:0x8C
2-87
PCIE_NBCFG_REG0
NBMISCIND:0x32
2-11
PCIE_NBCFG_REG3
NBMISCIND:0x33
2-12
PCIE_NBCFG_REG4
NBMISCIND:0x34
2-12
PCIE_NBCFG_REG5
NBMISCIND:0x35
2-13
PCIE_NBCFG_REG6
NBMISCIND:0x36
2-13
PCIE_NBCFG_REG7
NBMISCIND:0x37
2-13
PCIE_NBCFG_REG8
NBMISCIND:0x38
2-14
PCIE_P_BUF_STATUS
PCIEIND\:0x41
2-61
PCIE_P_CNTL
PCIEIND:0x40
2-60
PCIE_P_DECODER_STATUS
PCIEIND\:0x42
2-62
PCIE_P_IMP_CNTL_STRENGTH
PCIEIND\:0x60
2-63
PCIE_P_IMP_CNTL_UPDATE
PCIEIND\:0x61
2-64
PCIE_P_PAD_FORCE_DIS
PCIEIND\:0x65
2-65
PCIE_P_PAD_FORCE_EN
PCIEIND\:0x64
2-64
PCIE_P_PAD_MISC_CNTL
PCIEIND\:0x63
2-64
PCIE_P_PLL_CNTL
PCIEIND\:0x44
2-63
PCIE_P_PORT_LANE_STATUS
PCIEIND_P\:0x50
2-68
PCIE_P_STR_CNTL_UPDATE
PCIEIND\:0x62
2-64
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-21
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
Page
PCIE_P90_BRX_PRBS_ER
PCIEIND:0xF7
2-103
PCIE_P90RX_PRBS_CLR
PCIEIND:0xF6
2-102
PCIE_P90TX_PRBS_EN
PCIEIND:0xF8
2-103
PCIE_PDNB_CNTL
NBMISCIND:0x7
2-25
PCIE_PERF_LATENCY_CNTL
PCIEIND:0x70
2-95
PCIE_PERF_LATENCY_COUNTER0 PCIEIND:0x77
2-97
PCIE_PERF_LATENCY_COUNTER1 PCIEIND:0x78
2-97
PCIE_PERF_LATENCY_MAX
2-96
PCIEIND:0x74
PCIE_PERF_LATENCY_REQ_ID
PCIEIND:0x71
2-96
PCIE_PERF_LATENCY_TAG
PCIEIND:0x72
2-96
PCIE_PERF_LATENCY_THRESHOL
PCIEIND:0x73
D
2-96
PCIE_PERF_LATENCY_TIMER_HI
PCIEIND:0x76
2-97
PCIE_PERF_LATENCY_TIMER_LO
PCIEIND:0x75
2-96
PCIE_PORT_DATA
pcieConfigDev[10:2]\:0xE4
2-89
PCIE_PORT_INDEX
pcieConfigDev[10:2]\:0xE0
2-89
PCIE_PORT_VC_CAP_REG1
pcieConfigDev[10:2]\:0x104
2-108
PCIE_PORT_VC_CAP_REG2
pcieConfigDev[10:2]\:0x108
2-108
PCIE_PORT_VC_CNTL
pcieConfigDev[10:2]\:0x10C
2-108
PCIE_PORT_VC_STATUS
pcieConfigDev[10:2]\:0x10E
2-109
PCIE_PRBS23_BITCNT_0
PCIEIND:0xD0
2-97
PCIE_PRBS23_BITCNT_1
PCIEIND:0xD1
2-97
PCIE_PRBS23_BITCNT_10
PCIEIND:0xDA
2-98
PCIE_PRBS23_BITCNT_11
PCIEIND:0xDB
2-99
PCIE_PRBS23_BITCNT_12
PCIEIND:0xDC
2-99
PCIE_PRBS23_BITCNT_13
PCIEIND:0xDD
2-99
PCIE_PRBS23_BITCNT_14
PCIEIND:0xDE
2-99
PCIE_PRBS23_BITCNT_15
PCIEIND:0xDF
2-99
PCIE_PRBS23_BITCNT_2
PCIEIND:0xD2
2-97
PCIE_PRBS23_BITCNT_3
PCIEIND:0xD3
2-97
PCIE_PRBS23_BITCNT_4
PCIEIND:0xD4
2-98
PCIE_PRBS23_BITCNT_5
PCIEIND:0xD5
2-98
PCIE_PRBS23_BITCNT_6
PCIEIND:0xD6
2-98
PCIE_PRBS23_BITCNT_7
PCIEIND:0xD7
2-98
PCIE_PRBS23_BITCNT_8
PCIEIND:0xD8
2-98
PCIE_PRBS23_BITCNT_9
PCIEIND:0xD9
2-98
PCIE_PRBS23_CLR
PCIEIND:0xF0
2-102
PCIE_PRBS23_EN
PCIEIND:0xF5
2-102
PCIE_PRBS23_ERRCNT_0
PCIEIND:0xE0
2-99
PCIE_PRBS23_ERRCNT_1
PCIEIND:0xE1
2-99
PCIE_PRBS23_ERRCNT_10
PCIEIND:0xEA
2-101
AMD RS690 ASIC Family Register Reference Manual
A-22
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
PCIE_PRBS23_ERRCNT_11
PCIEIND:0xEB
2-101
PCIE_PRBS23_ERRCNT_12
PCIEIND:0xEC
2-101
PCIE_PRBS23_ERRCNT_13
PCIEIND:0xED
2-101
PCIE_PRBS23_ERRCNT_14
PCIEIND:0xEE
2-101
PCIE_PRBS23_ERRCNT_15
PCIEIND:0xEF
2-101
PCIE_PRBS23_ERRCNT_2
PCIEIND:0xE2
2-100
PCIE_PRBS23_ERRCNT_3
PCIEIND:0xE3
2-100
PCIE_PRBS23_ERRCNT_4
PCIEIND:0xE4
2-100
PCIE_PRBS23_ERRCNT_5
PCIEIND:0xE5
2-100
PCIE_PRBS23_ERRCNT_6
PCIEIND:0xE6
2-100
PCIE_PRBS23_ERRCNT_7
PCIEIND:0xE7
2-100
PCIE_PRBS23_ERRCNT_8
PCIEIND:0xE8
2-100
PCIE_PRBS23_ERRCNT_9
PCIEIND:0xE9
2-101
PCIE_PRBS23_ERRSTAT
PCIEIND:0xF1
2-102
PCIE_PRBS23_FREERUN
PCIEIND:0xF3
2-102
PCIE_PRBS23_LOCK_CNT
PCIEIND:0xF4
2-102
PCIE_PRBS23_LOCKED
PCIEIND:0xF2
2-102
PCIE_REGPROG_INF
pcieConfigDev[10:2]\:0x9
2-74
PCIE_RESERVED
PCIEIND\:0x0
2-58
PCIE_REVISION_ID
pcieConfigDev[10:2]\:0x8
2-74
PCIE_ROOT_ERR_CMD
pcieConfigDev[10:2]\:0x16C
2-92
PCIE_ROOT_ERR_STATUS
pcieConfigDev[10:2]\:0x170
2-92
PCIE_RX_CNTL
PCIEIND_P:0x70
2-69
PCIE_RX_CREDITS_ALLOCATED_
CPL
PCIEIND_P:0x82
2-105
PCIE_RX_CREDITS_ALLOCATED_
NP
PCIEIND_P:0x81
2-105
PCIE_RX_CREDITS_ALLOCATED_
P
PCIEIND_P:0x80
2-105
PCIE_RX_CREDITS_RECEIVED_CP
PCIEIND_P:0x85
L
2-106
PCIE_RX_CREDITS_RECEIVED_NP PCIEIND_P:0x84
2-106
PCIE_RX_CREDITS_RECEIVED_P
PCIEIND_P:0x83
2-106
PCIE_RX_LASTACK_SEQNUM
PCIEIND_P\:0x84
2-69
PCIE_RX_VENDOR_SPECIFIC
PCIEIND_P:0x72
2-105
PCIE_SCRATCH
PCIEIND\:0x1
2-58
PCIE_STATUS
pcieConfigDev[10:2]\:0x6
2-73
PCIE_STRAP_REG2
NBMISCIND:0x39
2-14
PCIE_STRAP_REG2
NBMISCIND:0x39
2-29
PCIE_SUB_CLASS
pcieConfigDev[10:2]\:0xA
2-74
PCIE_TX_ACK_LATENCY_LIMIT
PCIEIND_P:0x26
2-67
PCIE_TX_ACK_LATENCY_LIMIT
PCIEIND_P:0x26
2-103
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-23
Table 2-2 All Registers Sorted By Name
Name
Address
PCIE_TX_CNTL
PCIEIND_P:0x20
Secondary
Address
Additional
Address
Page
2-66
PCIE_TX_CREDITS_CONSUMED_C
PCIEIND_P:0x32
PL
2-104
PCIE_TX_CREDITS_CONSUMED_N
PCIEIND_P:0x31
P
2-104
PCIE_TX_CREDITS_CONSUMED_P PCIEIND_P:0x30
2-103
PCIE_TX_CREDITS_LIMIT_CPL
PCIEIND_P:0x35
2-105
PCIE_TX_CREDITS_LIMIT_NP
PCIEIND_P:0x34
2-104
PCIE_TX_CREDITS_LIMIT_P
PCIEIND_P:0x33
2-104
PCIE_TX_REPLAY
PCIEIND_P:0x25
2-67
PCIE_TX_REQUEST_NUM_CNTL
PCIEIND_P:0x23
2-67
PCIE_TX_REQUESTER_ID
PCIEIND_P:0x21
2-66
PCIE_TX_SEQ
PCIEIND_P:0x24
2-67
PCIE_TX_VENDOR_SPECIFIC
PCIEIND_P:0x22
2-67
PCIE_TX_VENDOR_SPECIFIC
PCIEIND_P:0x22
2-103
PCIE_UNCORR_ERR_MASK
pcieConfigDev[10:2]\:0x148
2-90
PCIE_UNCORR_ERR_SEVERITY
pcieConfigDev[10:2]\:0x14C
2-90
PCIE_UNCORR_ERR_STATUS
pcieConfigDev[10:2]\:0x144
2-89
PCIE_VC_ENH_CAP_HDR
pcieConfigDev[10:2]\:0x100
2-108
PCIE_VC0_RESOURCE_CAP
pcieConfigDev[10:2]\:0x110
2-93
PCIE_VC0_RESOURCE_CNTL
pcieConfigDev[10:2]\:0x114
2-94
PCIE_VC0_RESOURCE_STATUS
pcieConfigDev[10:2]\:0x11A
2-94
PCIE_VC1_RESOURCE_CAP
pcieConfigDev[10:2]\:0x11C
2-109
PCIE_VC1_RESOURCE_CNTL
pcieConfigDev[10:2]\:0x120
2-109
PCIE_VC1_RESOURCE_STATUS
pcieConfigDev[10:2]\:0x124
2-109
PCIE_VENDOR_ID
pcieConfigDev[10:2]\:0x0
2-72
PCIE_WPR_CNTL
PCIEIND:0x30
2-95
PCIEP_PORT_CNTL
PCIEIND_P:0x10
2-65
PCIEP_RESERVED
PCIEIND_P\:0x0
2-65
PCIEP_SCRATCH
PCIEIND_P\:0x1
2-65
PLL_TEST_CNTL
CLKIND:0x21
2-267
PMI_CAP
pcieConfigDev[10:2]\:0x52
2-79
PMI_CAP_ID
gcconfig:0x50
PMI_CAP_LIST
pcieConfigDev[10:2]\:0x50
PMI_DATA
gcconfig:0x57
MMReg:0x5057
2-129
PMI_NXT_CAP_PTR
gcconfig:0x51
MMReg:0x5051
2-129
PMI_PMC_REG
gcconfig:0x52
MMReg:0x5052
2-129
PMI_STATUS
gcconfig:0x54
MMReg:0x5054:R
2-120
PMI_STATUS_CNTL
pcieConfigDev[10:2]\:0x54
2-79
POLARITY_CNTL
CLKIND:0x2A
2-279
PREF_BASE_LIMIT
pcieConfigDev[10:2]\:0x24
2-77
PREF_BASE_UPPER
pcieConfigDev[10:2]\:0x28
2-77
AMD RS690 ASIC Family Register Reference Manual
A-24
MMReg:0x5050
2-129
2-79
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
PREF_LIMIT_UPPER
pcieConfigDev[10:2]\:0x2C
2-77
RCRB_Enhanced_Capability_Header
MMGartReg:0x0
2-266
REG_BASE_HI
gcconfig:0x1C
MMReg:0x501C:R
2-115
REG_BASE_LO
gcconfig:0x18
MMReg:0x5018:R
2-114
REGPROG_INF
gcconfig:0x9
MMReg:0x5009
2-114
REVISION_ID
gcconfig:0x8
MMReg:0x5008
2-111
ROOT_CAP
pcieConfigDev[10:2]\:0x76
2-107
ROOT_CNTL
pcieConfigDev[10:2]\:0x74
2-85
ROOT_CNTL
pcieConfigDev[10:2]\:0x74
2-107
ROOT_STATUS
pcieConfigDev[10:2]\:0x78
2-86
RS_DYN_CNTL
CLKIND:0x19
2-275
SC_DYN_CNTL
CLKIND:0x18
2-275
SCLK_PWRMGT_CNTL
CLKIND:0x9
2-270
scratch_0
NBMISCIND:0x70
2-41
scratch_1
NBMISCIND:0x71
2-41
SCRATCH_1_CLKCFG
clkconfig\:0x78
2-131
SCRATCH_1_NBCFG
nbconfig\:0x54
2-16
scratch_2
NBMISCIND:0x72
2-41
SCRATCH_2_CLKCFG
clkconfig\:0x7C
2-131
SCRATCH_2_NBCFG
nbconfig\:0x98
2-17
scratch_3
NBMISCIND:0x73
2-41
SCRATCH_4
NBMISCIND:0x74
2-41
SCRATCH_5
NBMISCIND:0x75
2-42
SCRATCH_6
NBMISCIND:0x76
2-42
SCRATCH_7
NBMISCIND:0x77
2-42
SCRATCH_8
NBMISCIND:0x78
2-42
SCRATCH_9
NBMISCIND:0x79
2-42
SCRATCH_A
NBMISCIND:0x7A
2-42
SCRATCH_CLKCFG
clkconfig\:0x84
2-132
SCRATCH_NBCFG
nbconfig\:0x78
2-16
SD1_CHROMA_MOD_CNTL
MMReg:0x5EF0
2-341
SD1_CHROMA_OFFSET
MMReg:0x5F90
2-345
SD1_COL_SC_DENOMIN
MMReg:0x5EF4
2-341
SD1_COL_SC_INC
MMReg:0x5EF8
2-342
SD1_COL_SC_INC_CORR
MMReg:0x5EFC
2-342
SD1_COL_SC_PHASE_CNTL
MMReg:0x5FD4
2-345
SD1_CRC_CNTL
MMReg:0x5F1C
2-344
SD1_CRTC_HV_START
MMReg:0x5F98
2-346
SD1_CRTC_TV_FRAMESTART_CNT
MMReg:0x5F9C
L
2-346
SD1_FORCE_DAC_DATA
2-340
© 2007 Advanced Micro Devices, Inc.
Proprietary
MMReg:0x5ECC
Page
AMD RS690 ASIC Family Register Reference Manual
A-25
Table 2-2 All Registers Sorted By Name
Name
Address
Secondary
Address
Additional
Address
Page
SD1_LUMA_BLANK_SETUP_LEVEL
MMReg:0x5EA8
S
2-335
SD1_LUMA_COMB_FILT_CNTL1
MMReg:0x5EB8
2-338
SD1_LUMA_COMB_FILT_CNTL2
MMReg:0x5EBC
2-338
SD1_LUMA_COMB_FILT_CNTL3
MMReg:0x5EC0
2-338
SD1_LUMA_COMB_FILT_CNTL4
MMReg:0x5EC4
2-338
SD1_LUMA_FILT_CNTL
MMReg:0x5EB4
2-336
SD1_LUMA_OFFSET_LIMIT
MMReg:0x5F8C
2-345
SD1_LUMA_SYNC_TIP_LEVELS
MMReg:0x5EB0
2-336
SD1_MAIN_CNTL
MMReg:0x5DFC
2-322
SD1_RGB_OR_PBPR_BLANK_LEVE
MMReg:0x5EAC
L
2-336
SD1_SCM_COL_SC_DENOMIN
MMReg:0x5F00
2-342
SD1_SCM_COL_SC_INC
MMReg:0x5F04
2-342
SD1_SCM_COL_SC_INC_CORR
MMReg:0x5F08
2-343
SD1_SCM_DB_DR_SCALE_FACTOR
MMReg:0x5F10
S
2-343
SD1_SCM_MAX_DTO_SWING
MMReg:0x5F18
2-344
SD1_SCM_MIN_DTO_SWING
MMReg:0x5F14
2-344
SD1_SCM_MOD_CNTL
MMReg:0x5F0C
2-343
SD1_SDTV0_DEBUG
MMReg:0x5F28
2-345
SD1_TIMING_H_ACTIVE_FILT_WI
NDOW1
MMReg:0x5E8C
2-333
SD1_TIMING_H_ACTIVE_FILT_WI
NDOW2
MMReg:0x5E90
2-333
SD1_TIMING_H_ADV_ACTIVE
MMReg:0x5E60
2-331
SD1_TIMING_H_BURST
MMReg:0x5E44
2-329
SD1_TIMING_H_COUNT
MMReg:0x5E0C
2-325
SD1_TIMING_H_COUNT_INIT
MMReg:0x5E14
2-325
SD1_TIMING_H_EQUALIZATION1
MMReg:0x5E24
2-326
SD1_TIMING_H_EQUALIZATION2
MMReg:0x5E28
2-327
SD1_TIMING_H_HSYNC
MMReg:0x5E20
2-326
SD1_TIMING_H_RUNIN_FILT_WIN
MMReg:0x5E94
DOW
2-334
SD1_TIMING_H_SERATION1
MMReg:0x5E2C
2-327
SD1_TIMING_H_SERATION2
MMReg:0x5E30
2-327
SD1_TIMING_H_SETUP1
MMReg:0x5E50
2-330
SD1_TIMING_H_SETUP2
MMReg:0x5E54
2-330
SD1_TIMING_H_TOTAL
MMReg:0x5E04
2-324
SD1_TIMING_INTERNAL_INIT
MMReg:0x5E1C
2-326
SD1_TIMING_V_ACTIVE1
MMReg:0x5E64
2-332
SD1_TIMING_V_ACTIVE2
MMReg:0x5E68
2-332
SD1_TIMING_V_BURST1
MMReg:0x5E48
2-329
AMD RS690 ASIC Family Register Reference Manual
A-26
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
SD1_TIMING_V_BURST2
MMReg:0x5E4C
2-329
SD1_TIMING_V_EQUALIZATION1
MMReg:0x5E34
2-327
SD1_TIMING_V_EQUALIZATION2
MMReg:0x5E38
2-328
SD1_TIMING_V_F_COUNT
MMReg:0x5E10
2-325
SD1_TIMING_V_F_COUNT_INIT
MMReg:0x5E18
2-325
SD1_TIMING_V_F_TOTAL
MMReg:0x5E08
2-325
SD1_TIMING_V_SERATION1
MMReg:0x5E3C
2-328
SD1_TIMING_V_SERATION2
MMReg:0x5E40
2-328
SD1_TIMING_V_SETUP1
MMReg:0x5E58
2-330
SD1_TIMING_V_SETUP2
MMReg:0x5E5C
2-331
SD1_U_AND_V_GAIN_SETTINGS
MMReg:0x5EA4
2-335
SD1_U_V_BREAK_POINT_SETTING
MMReg:0x5E9C
S
2-334
SD1_UPSAMPLE_MODE
MMReg:0x5F94
2-345
SD1_VIDEO_PORT_SIG
MMReg:0x5F20
2-344
SD1_VIDOUT_MUX_CNTL
MMReg:0x5EC8
2-339
SD1_Y_AND_PASSTHRU_GAIN_SET
MMReg:0x5EA0
TINGS
2-335
SD1_Y_BREAK_POINT_SETTING
MMReg:0x5E98
2-334
SECONDARY_STATUS
pcieConfigDev[10:2]\:0x1E
2-76
SEQ00
VGASEQIND\:0x0
2-300
SEQ01
VGASEQIND\:0x1
2-300
SEQ02
VGASEQIND\:0x2
2-300
SEQ03
VGASEQIND\:0x3
2-301
SEQ04
VGASEQIND\:0x4
2-301
SEQ8_DATA
MMReg:0x3C5
VGA_IO:0x3C5
2-302
SEQ8_IDX
MMReg:0x3C4
VGA_IO:0x3C4
2-302
SLOT_CAP
pcieConfigDev[10:2]\:0x6C
2-84
SLOT_CNTL
pcieConfigDev[10:2]\:0x70
2-84
SLOT_STATUS
pcieConfigDev[10:2]\:0x72
2-85
SPLL_BYPASSCLK_SEL
CLKIND:0x1
2-268
SPLL_CLK_SEL
CLKIND:0x3
2-268
SPLL_CNTL_MODE
CLKIND:0x2
2-268
SPLL_FUNC_CNTL
CLKIND:0x0
2-267
SPLL_TIME
CLKIND:0x24
2-279
SSID_CAP_LIST
pcieConfigDev[10:2]\:0xB0
2-88
SSID_ID
pcieConfigDev[10:2]\:0xB4
2-88
STATUS
gcconfig:0x6
StrapsOutputMux_0
NBMISCIND:0x60
2-37
StrapsOutputMux_1
NBMISCIND:0x61
2-37
StrapsOutputMux_2
NBMISCIND:0x62
2-37
© 2007 Advanced Micro Devices, Inc.
Proprietary
MMReg:0x5006:R
2-110
AMD RS690 ASIC Family Register Reference Manual
A-27
Table 2-2 All Registers Sorted By Name
Secondary
Address
Additional
Address
Name
Address
Page
StrapsOutputMux_3
NBMISCIND:0x63
2-38
StrapsOutputMux_4
NBMISCIND:0x64
2-38
StrapsOutputMux_5
NBMISCIND:0x65
2-38
StrapsOutputMux_6
NBMISCIND:0x66
2-38
StrapsOutputMux_7
NBMISCIND:0x67
2-39
StrapsOutputMux_8
NBMISCIND:0x68
2-39
StrapsOutputMux_9
NBMISCIND:0x69
2-40
StrapsOutputMux_A
NBMISCIND:0x6A
2-40
StrapsOutputMux_B
NBMISCIND:0x6B
2-40
StrapsOutputMux_C
NBMISCIND:0x6C
2-40
StrapsOutputMux_D
NBMISCIND:0x6D
2-40
StrapsOutputMux_E
NBMISCIND:0x6E
2-41
StrapsOutputMux_F
NBMISCIND:0x6F
2-41
SU_DYN_CNTL
CLKIND:0x15
2-275
SUB_BUS_NUMBER_LATENCY
pcieConfigDev[10:2]\:0x18
2-75
SUB_CLASS
gcconfig:0xA
TCL_DYN_CNTL
CLKIND:0x1A
2-274
TX_DYN_CNTL
CLKIND:0x27
2-276
US_DYN_CNTL
CLKIND:0x28
2-276
VENDOR_ID
gcconfig:0x0
MMReg:0x500A
2-112
MMReg:0x5000
2-110
VGA_MEM_READ_PAGE_ADDR
IOReg:0x3C
MMReg:0x3C
2-353
VGA_MEM_WRITE_PAGE_ADDR
IOReg:0x38
MMReg:0x38
2-353
VGA25_PPLL_POST_DIV
MMReg:0x388
2-353
VGA25_PPLL_POST_DIV_SRC
MMReg:0x384
2-352
VIP_DYN_CNTL
CLKIND:0x14
2-274
VOL_DROP_CNT
CLKIND:0x36
2-285
AMD RS690 ASIC Family Register Reference Manual
A-28
© 2007 Advanced Micro Devices, Inc.
Proprietary
A.4 All Registers Sorted By Address
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
apcconfig:0x1E
APC_AGP_PCI_STATUS
2-147
apcconfig:0x2
APC_DEVICE_ID
2-143
apcconfig:0x24
APC_AGP_PCI_PREFETCHABLE_LIMI
T_BASE
2-148
apcconfig:0x34
APC_CAPABILITIES_PTR
2-149
apcconfig:0x40
APC_MISC_DEVICE_CTRL
2-151
apcconfig:0x44
APC_HT_MSI_CAP
2-151
apcconfig:0x6
APC_STATUS
2-144
apcconfig\:0x0
APC_VENDOR_ID
2-143
apcconfig\:0x18
APC_SUB_BUS_NUMBER_LATENCY
2-147
apcconfig\:0x1C
APC_AGP_PCI_IOBASE_LIMIT
2-147
apcconfig\:0x20
APC_AGP_PCI_MEMORY_LIMIT_BASE
2-148
apcconfig\:0x28
APC_AGP_PCI_PREFETCHABLE_BASE
_Upper
2-148
apcconfig\:0x2C
APC_AGP_PCI_PREFETCHABLE_LIMI
T_Upper
2-148
apcconfig\:0x30
APC_AGP_PCI_IO_LIMIT_BASE_HI
2-149
apcconfig\:0x3C
APC_AGP_PCI_IRQ_BRIDGE_CTRL
2-149
apcconfig\:0x4
APC_COMMAND
2-143
apcconfig\:0x4C
APC_ADAPTER_ID_W
2-151
apcconfig\:0x8
APC_REVISION_ID
2-145
apcconfig\:0x9
APC_REGPROG_INF
2-145
apcconfig\:0xA
APC_SUB_CLASS
2-145
apcconfig\:0xB
APC_BASE_CODE
2-146
apcconfig\:0xB0
APC_SSID_CAP_ID
2-152
apcconfig\:0xB4
APC_SSID
2-152
apcconfig\:0xC
APC_CACHE_LINE
2-146
apcconfig\:0xD
APC_LATENCY
2-146
apcconfig\:0xE
APC_HEADER
2-146
apcconfig\:0xF
APC_BIST
2-146
clkconfig:0x40
OSC_CONTROL
2-130
clkconfig:0x44
CPLL_CONTROL
2-138
clkconfig:0x4C
CLK_TOP_PWM4_CTRL
2-138
clkconfig:0x50
CLK_TOP_PWM5_CTRL
2-139
clkconfig:0x5C
DELAY_SET_IOC_CCLK
2-139
clkconfig:0x68
CT_DISABLE_BIU
2-139
clkconfig:0x70
CPLL_CONTROL3
2-140
clkconfig:0x74
GC_CLK_CNTRL
2-131
clkconfig:0x8C
CLKGATE_DISABLE2
2-132
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-29
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
clkconfig:0x94
CLKGATE_DISABLE
2-132
clkconfig:0x98
CPLL_CONTROL2
2-140
clkconfig:0xAC
CLK_TOP_PERF_CNTL
2-135
clkconfig:0xB0
clk_top_pwm1_ctrl
2-141
clkconfig:0xB4
clk_top_pwm2_ctrl
2-141
clkconfig:0xB8
clk_top_test_ctrl
2-141
clkconfig:0xC0
CLK_TOP_THERMAL_ALERT_INTR_EN
2-141
clkconfig:0xC4
CLK_TOP_THERMAL_ALERT_STATUS
2-141
clkconfig:0xC8
CLK_TOP_THERMAL_ALERT_WAIT_WI
NDOW
2-142
clkconfig:0xCC
clk_top_pwm3_ctrl
2-142
clkconfig:0xD0
clk_top_spare_pll
2-142
clkconfig:0xE0
CLK_TOP_SPARE_A
2-136
clkconfig:0xE4
CLK_TOP_SPARE_B
2-137
clkconfig:0xE8
CLK_TOP_SPARE_C
2-137
clkconfig:0xEC
CLK_TOP_SPARE_D
2-137
clkconfig:0xF8
CFG_CT_CLKGATE_HTIU
2-138
clkconfig\:0x78
SCRATCH_1_CLKCFG
2-131
clkconfig\:0x7C
SCRATCH_2_CLKCFG
2-131
clkconfig\:0x84
SCRATCH_CLKCFG
2-132
clkconfig\:0xD4
CLK_CFG_HTPLL_CNTL
2-136
CLKIND:0x0
SPLL_FUNC_CNTL
2-267
CLKIND:0x1
SPLL_BYPASSCLK_SEL
2-268
CLKIND:0x10
HDP_DYN_CNTL
2-273
CLKIND:0x11
E2_DYN_CNTL
2-273
CLKIND:0x14
VIP_DYN_CNTL
2-274
CLKIND:0x15
SU_DYN_CNTL
2-275
CLKIND:0x17
FG_DYN_CNTL
2-275
CLKIND:0x18
SC_DYN_CNTL
2-275
CLKIND:0x19
RS_DYN_CNTL
2-275
CLKIND:0x1A
TCL_DYN_CNTL
2-274
CLKIND:0x1B
GA_DYN_CNTL
2-274
CLKIND:0x1D
MC_GUI_DYN_CNTL
2-276
CLKIND:0x1E
MC_HOST_DYN_CNTL
2-277
CLKIND:0x1F
CG_MISC_REG
2-277
CLKIND:0x2
SPLL_CNTL_MODE
2-268
CLKIND:0x20
CG_DEBUG
2-277
CLKIND:0x21
PLL_TEST_CNTL
2-267
CLKIND:0x22
MCLK_MISC
2-278
CLKIND:0x23
DLL_CNTL
2-278
CLKIND:0x24
SPLL_TIME
2-279
AMD RS690 ASIC Family Register Reference Manual
A-30
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
CLKIND:0x25
MPLL_TIME
2-279
CLKIND:0x26
MC_RBS_DYN_CNTL
2-277
CLKIND:0x27
TX_DYN_CNTL
2-276
CLKIND:0x28
US_DYN_CNTL
2-276
CLKIND:0x29
DYN_BACKBIAS_CNTL
2-279
CLKIND:0x2A
POLARITY_CNTL
2-279
CLKIND:0x2B
OVERCLOCK_CNTL
2-279
CLKIND:0x2C
ERROR_STATUS
2-280
CLKIND:0x2D
CC_FUSE_STRAPS_0
2-280
CLKIND:0x2E
CC_FUSE_STRAPS_1
2-281
CLKIND:0x2F
CC_DEBUG_STRAPS_0
2-281
CLKIND:0x3
SPLL_CLK_SEL
2-268
CLKIND:0x30
CC_DEBUG_STRAPS_1
2-282
CLKIND:0x31
CC_IO_STRAPS
2-282
CLKIND:0x31
CC_IO_STRAPS_12A
2-283
CLKIND:0x31
CC_IO_STRAPS_22A
2-282
CLKIND:0x32
CC_ROM_STRAPS
2-283
CLKIND:0x33
CC_COMBINED_STRAPS_0
2-284
CLKIND:0x34
CC_COMBINED_STRAPS_1
2-285
CLKIND:0x35
CG_CLKPIN_CNTL
2-285
CLKIND:0x36
VOL_DROP_CNT
2-285
CLKIND:0x37
BACKBIAS_ENABLE_CNT
2-285
CLKIND:0x38
CG_TC_JTAG_0
2-286
CLKIND:0x39
CG_TC_JTAG_1
2-286
CLKIND:0x3A
FVTHROT_CNTRL_REG
2-286
CLKIND:0x3B
FVTHROT_TARGET_REG
2-287
CLKIND:0x3C
FVTHROT_COMPARE_BOUND1
2-287
CLKIND:0x3D
FVTHROT_COMPARE_BOUND2
2-287
CLKIND:0x3E
FVTHROT_COMPARE_BOUND3
2-287
CLKIND:0x3F
FVTHROT_COMPARE_BOUND4
2-287
CLKIND:0x4
MPLL_FUNC_CNTL
2-269
CLKIND:0x40
FVTHROT_UPTREND_COEF0
2-287
CLKIND:0x41
FVTHROT_UPTREND_COEF1
2-288
CLKIND:0x42
FVTHROT_UPTREND_COEF2
2-288
CLKIND:0x43
FVTHROT_UPTREND_COEF3
2-288
CLKIND:0x44
FVTHROT_UPTREND_COEF4
2-288
CLKIND:0x45
FVTHROT_DOWNTREND_COEF0
2-288
CLKIND:0x46
FVTHROT_DOWNTREND_COEF1
2-289
CLKIND:0x47
FVTHROT_DOWNTREND_COEF2
2-289
CLKIND:0x48
FVTHROT_DOWNTREND_COEF3
2-289
CLKIND:0x49
FVTHROT_DOWNTREND_COEF4
2-289
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-31
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
CLKIND:0x4A
FVTHROT_FBDIV_REG0
2-289
CLKIND:0x4B
FVTHROT_FBDIV_REG1
2-289
CLKIND:0x4C
FVTHROT_FBDIV_REG2
2-290
CLKIND:0x4D
FVTHROT_FB_UPSTEP_REG0
2-290
CLKIND:0x4E
FVTHROT_FB_UPSTEP_REG1
2-290
CLKIND:0x4F
FVTHROT_FB_DOWNSTEP_REG0
2-290
CLKIND:0x5
MPLL_BYPASSCLK_SEL
2-269
CLKIND:0x50
FVTHROT_FB_DOWNSTEP_REG1
2-290
CLKIND:0x51
FVTHROT_PWM_CTRL_REG0
2-290
CLKIND:0x52
FVTHROT_PWM_CTRL_REG1
2-291
CLKIND:0x53
FVTHROT_PWM_UPSTEP_REG0
2-291
CLKIND:0x54
FVTHROT_PWM_UPSTEP_REG1
2-291
CLKIND:0x55
FVTHROT_PWM_DOWNSTEP_REG0
2-291
CLKIND:0x56
FVTHROT_PWM_DOWNSTEP_REG1
2-291
CLKIND:0x57
FVTHROT_STATUS_REG0
2-291
CLKIND:0x58
FVTHROT_STATUS_REG1
2-292
CLKIND:0x59
FVTHROT_STATUS_REG2
2-292
CLKIND:0x5A
CG_SPLL_ANALOG_CTRL0
2-292
CLKIND:0x5B
CG_SPLL_ANALOG_CTRL1
2-292
CLKIND:0x5C
CG_INTGFX_MISC
2-292
CLKIND:0x5D
CG_INTGFX_SPARE_RO
2-293
CLKIND:0x5E
FVTHROT_PWM_FEEDBACK_DIV_REG
1
2-293
CLKIND:0x5F
FVTHROT_PWM_FEEDBACK_DIV_REG
2
2-293
CLKIND:0x6
MPLL_CNTL_MODE
2-269
CLKIND:0x60
FVTHROT_PWM_FEEDBACK_DIV_REG
3
2-293
CLKIND:0x61
FVTHROT_PWM_FEEDBACK_DIV_REG
4
2-293
CLKIND:0x62
FVTHROT_SPLL_PARAM_FEEDBACK_
DIV_REG1
2-294
CLKIND:0x63
FVTHROT_SPLL_PARAM_FEEDBACK_
DIV_REG2
2-294
CLKIND:0x64
FVTHROT_SPLL_PARAM_FEEDBACK_
DIV_REG3
2-294
CLKIND:0x65
FVTHROT_SPLL_PARAM_FEEDBACK_
DIV_REG4
2-294
CLKIND:0x66
FVTHROT_SLOW_CLK_FEEDBACK_DI
V_REG1
2-294
CLKIND:0x67
FVTHROT_SCALE_FEEDBACK_DIV_RE
G1
2-295
CLKIND:0x7
MPLL_CLK_SEL
2-270
CLKIND:0x8
GENERAL_PWRMGT
2-270
AMD RS690 ASIC Family Register Reference Manual
A-32
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
CLKIND:0x9
SCLK_PWRMGT_CNTL
2-270
CLKIND:0xA
MCLK_PWRMGT_CNTL
2-271
CLKIND:0xB
DYN_PWRMGT_SCLK_CNTL
2-271
CLKIND:0xC
DYN_PWRMGT_SCLK_LENGTH
2-272
CLKIND:0xD
DYN_SCLK_PWMEN_PIPE
2-272
CLKIND:0xE
DYN_SCLK_VOL_CNTL
2-272
CLKIND:0xF
CP_DYN_CNTL
2-272
gcconfig:0x0
VENDOR_ID
MMReg:0x5000
2-110
gcconfig:0x10
MEM_BASE_LO
MMReg:0x5010:R
2-114
gcconfig:0x100
F1_VENDOR_ID
MMReg:0x5100
2-116
gcconfig:0x102
F1_DEVICE_ID
MMReg:0x5102
2-116
gcconfig:0x104
F1_COMMAND
MMReg:0x5104:R
2-116
gcconfig:0x106
F1_STATUS
MMReg:0x5106
2-116
gcconfig:0x108
F1_REVISION_ID
MMReg:0x5108
2-116
gcconfig:0x109
F1_REGPROG_INF
MMReg:0x5109
2-116
gcconfig:0x10A
F1_SUB_CLASS
MMReg:0x510A
2-117
gcconfig:0x10B
F1_BASE_CODE
MMReg:0x510B
2-117
gcconfig:0x10C
F1_CACHE_LINE
MMReg:0x510C:R
2-117
gcconfig:0x10D
F1_LATENCY
MMReg:0x510D:R
2-117
gcconfig:0x10E
F1_HEADER
MMReg:0x510E
2-117
gcconfig:0x10F
F1_BIST
MMReg:0x510F
2-117
gcconfig:0x110
F1_REG_BASE_LO
MMReg:0x5114:R
2-118
gcconfig:0x114
F1_REG_BASE_HI
MMReg:0x511C:R
2-118
gcconfig:0x12C
F1_ADAPTER_ID
MMReg:0x512C
2-118
gcconfig:0x134
F1_CAPABILITIES_PTR
MMReg:0x5134
2-118
gcconfig:0x13C
F1_INTERRUPT_LINE
MMReg:0x513C:R
2-118
gcconfig:0x13D
F1_INTERRUPT_PIN
MMReg:0x513D
2-118
gcconfig:0x13E
F1_MIN_GRANT
MMReg:0x513E
2-119
gcconfig:0x13F
F1_MAX_LATENCY
MMReg:0x513F
2-119
gcconfig:0x14
MEM_BASE_HI
MMReg:0x5014:R
2-114
gcconfig:0x14C
F1_ADAPTER_ID_W
MMReg:0x514C:R
2-120
gcconfig:0x150
F1_PMI_CAP_ID
MMReg:0x5150
2-119
gcconfig:0x151
F1_PMI_NXT_CAP_PTR
MMReg:0x5151
2-119
gcconfig:0x152
F1_PMI_PMC_REG
MMReg:0x5152
2-119
gcconfig:0x154
F1_PMI_STATUS
MMReg:0x5154:R
2-120
gcconfig:0x157
F1_PMI_DATA
MMReg:0x5157
2-119
gcconfig:0x18
REG_BASE_LO
MMReg:0x5018:R
2-114
gcconfig:0x1C
REG_BASE_HI
MMReg:0x501C:R
2-115
gcconfig:0x2
DEVICE_ID
MMReg:0x5002
2-110
gcconfig:0x20
IO_BASE
MMReg:0x5020:R
2-111
gcconfig:0x200
F2_VENDOR_ID
MMReg:0x5200
2-120
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-33
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
gcconfig:0x202
F2_DEVICE_ID
MMReg:0x5202
2-120
gcconfig:0x204
F2_COMMAND
MMReg:0x5204:R
2-121
gcconfig:0x206
F2_STATUS
MMReg:0x5206
2-121
gcconfig:0x208
F2_REVISION_ID
MMReg:0x5208
2-121
gcconfig:0x209
F2_REGPROG_INF
MMReg:0x5209
2-121
gcconfig:0x20A
F2_SUB_CLASS
MMReg:0x520A
2-121
gcconfig:0x20B
F2_BASE_CODE
MMReg:0x520B
2-122
gcconfig:0x20C
F2_CACHE_LINE
MMReg:0x520C:R
2-122
gcconfig:0x20D
F2_LATENCY
MMReg:0x520D:R
2-122
gcconfig:0x20E
F2_HEADER
MMReg:0x520E
2-122
gcconfig:0x20F
F2_BIST
MMReg:0x520F
2-122
gcconfig:0x210
F2_REG_BASE_LO
MMReg:0x5210:R
2-122
gcconfig:0x214
F2_REG_BASE_HI
MMReg:0x5214:R
2-123
gcconfig:0x22C
F2_ADAPTER_ID
MMReg:0x522C
2-123
gcconfig:0x234
F2_CAPABILITIES_PTR
MMReg:0x5234
2-123
gcconfig:0x23C
F2_INTERRUPT_LINE
MMReg:0x523C:R
2-123
gcconfig:0x23D
F2_INTERRUPT_PIN
MMReg:0x523D
2-123
gcconfig:0x23E
F2_MIN_GRANT
MMReg:0x523E
2-123
gcconfig:0x23F
F2_MAX_LATENCY
MMReg:0x523F
2-124
gcconfig:0x24C
F2_ADAPTER_ID_W
MMReg:0x524C:R
2-124
gcconfig:0x250
F2_PMI_CAP_ID
MMReg:0x5250
2-124
gcconfig:0x251
F2_PMI_NXT_CAP_PTR
MMReg:0x5251
2-124
gcconfig:0x252
F2_PMI_PMC_REG
MMReg:0x5252
2-124
gcconfig:0x254
F2_PMI_STATUS
MMReg:0x5254:R
2-125
gcconfig:0x257
F2_PMI_DATA
MMReg:0x5257
2-125
gcconfig:0x260
F2_MSI_CAP_ID
MMReg:0x5260
2-125
gcconfig:0x261
F2_MSI_NXT_CAP_PTR
MMReg:0x5261
2-125
gcconfig:0x262
F2_MSI_MSG_CNTL
MMReg:0x5262:R
2-126
gcconfig:0x264
F2_MSI_MSG_ADDR_LO
MMReg:0x5264:R
2-126
gcconfig:0x268
F2_MSI_MSG_ADDR_HI
MMReg:0x5268:R
2-126
gcconfig:0x26C
F2_MSI_MSG_DATA
MMReg:0x526C:R
2-126
gcconfig:0x2C
ADAPTER_ID
MMReg:0x502C
2-111
gcconfig:0x34
CAPABILITIES_PTR
MMReg:0x5034
2-112
gcconfig:0x3C
INTERRUPT_LINE
MMReg:0x503C:R
2-113
gcconfig:0x3D
INTERRUPT_PIN
MMReg:0x503D
2-113
gcconfig:0x3E
MIN_GRANT
MMReg:0x503E
2-114
gcconfig:0x3F
MAX_LATENCY
MMReg:0x503F
2-113
gcconfig:0x4
COMMAND
MMReg:0x5004:R
2-110
gcconfig:0x4C
ADAPTER_ID_W
MMReg:0x504C:R
2-111
gcconfig:0x50
PMI_CAP_ID
MMReg:0x5050
2-129
gcconfig:0x51
PMI_NXT_CAP_PTR
MMReg:0x5051
2-129
AMD RS690 ASIC Family Register Reference Manual
A-34
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
gcconfig:0x52
PMI_PMC_REG
MMReg:0x5052
2-129
gcconfig:0x54
PMI_STATUS
MMReg:0x5054:R
2-120
gcconfig:0x57
PMI_DATA
MMReg:0x5057
2-129
Page
gcconfig:0x6
STATUS
MMReg:0x5006:R
2-110
gcconfig:0x8
REVISION_ID
MMReg:0x5008
2-111
gcconfig:0x80
MSI_CAP_ID
MMReg:0x5080
2-115
gcconfig:0x81
MSI_NXT_CAP_PTR
MMReg:0x5081
2-115
gcconfig:0x82
MSI_MSG_CNTL
MMReg:0x5082:R
2-115
gcconfig:0x84
MSI_MSG_ADDR_LO
MMReg:0x5084:R
2-115
gcconfig:0x88
MSI_MSG_ADDR_HI
MMReg:0x5088:R
2-115
gcconfig:0x8C
MSI_MSG_DATA
MMReg:0x508C:R
2-116
gcconfig:0x9
REGPROG_INF
MMReg:0x5009
2-114
gcconfig:0xA
SUB_CLASS
MMReg:0x500A
2-112
gcconfig:0xB
BASE_CODE
MMReg:0x500B
2-111
gcconfig:0xC
CACHE_LINE
MMReg:0x500C:R
2-114
gcconfig:0xD
LATENCY
MMReg:0x500D:R
2-113
gcconfig:0xE
HEADER
MMReg:0x500E
2-113
gcconfig:0xF
BIST
MMReg:0x500F
2-112
HTIUNBIND:0x0
HTIU_CNTL_1
2-43
HTIUNBIND:0x1
HTIU_CNTL_2
2-43
HTIUNBIND:0x10
HTIU_UPSTREAM_CONFIG_9
2-51
HTIUNBIND:0x11
HTIU_UPSTREAM_CONFIG_10
2-52
HTIUNBIND:0x12
HTIU_UPSTREAM_CONFIG_11
2-52
HTIUNBIND:0x13
HTIU_UPSTREAM_CONFIG_12
2-52
HTIUNBIND:0x14
HTIU_UPSTREAM_CONFIG_13
2-53
HTIUNBIND:0x15
HTIU_UPSTREAM_CONFIG_14
2-53
HTIUNBIND:0x16
HTIU_UPSTREAM_CONFIG_15
2-54
HTIUNBIND:0x17
HTIU_UPSTREAM_CONFIG_16
2-54
HTIUNBIND:0x18
HTIU_UPSTREAM_CONFIG_17
2-54
HTIUNBIND:0x19
HTIU_UPSTREAM_CONFIG_18
2-55
HTIUNBIND:0x1A
HTIU_UPSTREAM_CONFIG_19
2-55
HTIUNBIND:0x1B
HTIU_UPSTREAM_CONFIG_20
2-56
HTIUNBIND:0x1C
HTIU_UPSTREAM_CONFIG_21
2-56
HTIUNBIND:0x1D
HTIU_UPSTREAM_CONFIG_22
2-56
HTIUNBIND:0x1E
HTIU_UPSTREAM_CONFIG_23
2-56
HTIUNBIND:0x1F
HTIU_UPSTREAM_CONFIG_24
2-56
HTIUNBIND:0x2
HTIU_PERF_CNTL
2-43
HTIUNBIND:0x3
HTIU_PERF_COUNT_0
2-45
HTIUNBIND:0x30
NB_LOWER_TOP_OF_DRAM2
2-57
HTIUNBIND:0x31
NB_UPPER_TOP_OF_DRAM2
2-57
HTIUNBIND:0x32
NB_HTIU_CFG
2-57
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-35
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
HTIUNBIND:0x4
HTIU_PERF_COUNT_1
2-45
HTIUNBIND:0x5
HTIU_DEBUG
2-46
HTIUNBIND:0x6
HTIU_DOWNSTREAM_CONFIG
2-46
HTIUNBIND:0x7
HTIU_UPSTREAM_CONFIG_0
2-47
HTIUNBIND:0x8
HTIU_UPSTREAM_CONFIG_1
2-48
HTIUNBIND:0x9
HTIU_UPSTREAM_CONFIG_2
2-48
HTIUNBIND:0xA
HTIU_UPSTREAM_CONFIG_3
2-49
HTIUNBIND:0xB
HTIU_UPSTREAM_CONFIG_4
2-49
HTIUNBIND:0xC
HTIU_UPSTREAM_CONFIG_5
2-50
HTIUNBIND:0xD
HTIU_UPSTREAM_CONFIG_6
2-50
HTIUNBIND:0xE
HTIU_UPSTREAM_CONFIG_7
2-51
HTIUNBIND:0xF
HTIU_UPSTREAM_CONFIG_8
2-51
IOReg:0x0
MM_INDEX
MMReg:0x0
2-127
IOReg:0x10
BIOS_0_SCRATCH
MMReg:0x10
2-353
IOReg:0x14
BIOS_1_SCRATCH
MMReg:0x14
2-353
IOReg:0x18
BIOS_2_SCRATCH
MMReg:0x18
2-353
IOReg:0x1C
BIOS_3_SCRATCH
MMReg:0x1C
2-354
IOReg:0x20
BIOS_4_SCRATCH
MMReg:0x20
2-354
IOReg:0x24
BIOS_5_SCRATCH
MMReg:0x24
2-354
IOReg:0x28
BIOS_6_SCRATCH
MMReg:0x28
2-354
IOReg:0x2C
BIOS_7_SCRATCH
MMReg:0x2C
2-354
IOReg:0x30
BUS_CNTL
MMReg:0x30
2-351
IOReg:0x34
BUS_CNTL1
MMReg:0x34
2-352
IOReg:0x38
VGA_MEM_WRITE_PAGE_ADDR
MMReg:0x38
2-353
IOReg:0x3C
VGA_MEM_READ_PAGE_ADDR
MMReg:0x3C
2-353
IOReg:0x4
MM_DATA
MMReg:0x4
2-127
IOReg:0x58
DAC_CNTL
MMReg:0x58
2-299
IOReg:0x8
CLOCK_CNTL_INDEX
MMReg:0x8
2-267
IOReg:0xB0
MEDIA_0_SCRATCH
MMReg:0xB0
2-354
IOReg:0xB4
MEDIA_1_SCRATCH
MMReg:0xB4
2-354
IOReg:0xC
CLOCK_CNTL_DATA
MMReg:0xC
2-267
IOReg:0xC0
BIOS_8_SCRATCH
MMReg:0xC0
2-355
IOReg:0xC4
BIOS_9_SCRATCH
MMReg:0xC4
2-355
IOReg:0xC8
BIOS_10_SCRATCH
MMReg:0xC8
2-355
IOReg:0xCC
BIOS_11_SCRATCH
MMReg:0xCC
2-355
IOReg:0xD0
BIOS_12_SCRATCH
MMReg:0xD0
2-355
IOReg:0xD4
BIOS_13_SCRATCH
MMReg:0xD4
2-355
IOReg:0xD8
BIOS_14_SCRATCH
MMReg:0xD8
2-355
IOReg:0xDC
BIOS_15_SCRATCH
MMReg:0xDC
2-356
IOReg:0xE4
CONFIG_XSTRAP
MMReg:0xE4
2-356
IOReg\:0xE0
CONFIG_CNTL
MMReg\:0xE0
2-112
AMD RS690 ASIC Family Register Reference Manual
A-36
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
IOReg\:0xF8
CONFIG_MEMSIZE
MMReg\:0xF8
MCIND:0x103
AGP_BASE_2
2-350
MMGartReg:0x0
RCRB_Enhanced_Capability_Header
2-266
Page
2-112
MMReg:0x100
CONFIG_MEM_BASE_LO
2-356
MMReg:0x104
CONFIG_MEM_BASE_HI
2-356
MMReg:0x10C
CONFIG_REG_BASE_LO
2-356
MMReg:0x110
CONFIG_REG_BASE_HI
2-357
MMReg:0x114
CONFIG_REG_APER_SIZE
2-113
MMReg:0x134
HDP_FB_LOCATION
2-357
MMReg:0x180C
BIF_SLAVE_CNTL
2-350
MMReg:0x384
VGA25_PPLL_POST_DIV_SRC
2-352
MMReg:0x388
VGA25_PPLL_POST_DIV
2-353
VGA_IO:0x3B4
VGA_IO:0x3D4:
O:0x3D4
MMReg:0x3B4
CRTC8_IDX
MMReg:0x3D4
2-303
MMReg:0x3B5
CRTC8_DATA
MMReg:0x3D5
VGA_IO:0x3B5
VGA_IO:0x3D5:I 2-303
O:0x3D5
MMReg:0x3C2
GENMO_WT
VGA_IO:0x3C2
2-127
MMReg:0x3C4
SEQ8_IDX
VGA_IO:0x3C4
2-302
MMReg:0x3C5
SEQ8_DATA
VGA_IO:0x3C5
2-302
MMReg:0x3CC
GENMO_RD
VGA_IO:0x3CC
2-128
MMReg:0x3CE
GRPH8_IDX
VGA_IO:0x3CE
2-312
MMReg:0x3CF
GRPH8_DATA
VGA_IO:0x3CF
2-312
MMReg:0x5DFC
SD1_MAIN_CNTL
2-322
MMReg:0x5E04
SD1_TIMING_H_TOTAL
2-324
MMReg:0x5E08
SD1_TIMING_V_F_TOTAL
2-325
MMReg:0x5E0C
SD1_TIMING_H_COUNT
2-325
MMReg:0x5E10
SD1_TIMING_V_F_COUNT
2-325
MMReg:0x5E14
SD1_TIMING_H_COUNT_INIT
2-325
MMReg:0x5E18
SD1_TIMING_V_F_COUNT_INIT
2-325
MMReg:0x5E1C
SD1_TIMING_INTERNAL_INIT
2-326
MMReg:0x5E20
SD1_TIMING_H_HSYNC
2-326
MMReg:0x5E24
SD1_TIMING_H_EQUALIZATION1
2-326
MMReg:0x5E28
SD1_TIMING_H_EQUALIZATION2
2-327
MMReg:0x5E2C
SD1_TIMING_H_SERATION1
2-327
MMReg:0x5E30
SD1_TIMING_H_SERATION2
2-327
MMReg:0x5E34
SD1_TIMING_V_EQUALIZATION1
2-327
MMReg:0x5E38
SD1_TIMING_V_EQUALIZATION2
2-328
MMReg:0x5E3C
SD1_TIMING_V_SERATION1
2-328
MMReg:0x5E40
SD1_TIMING_V_SERATION2
2-328
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-37
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
MMReg:0x5E44
SD1_TIMING_H_BURST
2-329
MMReg:0x5E48
SD1_TIMING_V_BURST1
2-329
MMReg:0x5E4C
SD1_TIMING_V_BURST2
2-329
MMReg:0x5E50
SD1_TIMING_H_SETUP1
2-330
MMReg:0x5E54
SD1_TIMING_H_SETUP2
2-330
MMReg:0x5E58
SD1_TIMING_V_SETUP1
2-330
MMReg:0x5E5C
SD1_TIMING_V_SETUP2
2-331
MMReg:0x5E60
SD1_TIMING_H_ADV_ACTIVE
2-331
MMReg:0x5E64
SD1_TIMING_V_ACTIVE1
2-332
MMReg:0x5E68
SD1_TIMING_V_ACTIVE2
2-332
MMReg:0x5E8C
SD1_TIMING_H_ACTIVE_FILT_WINDO
W1
2-333
MMReg:0x5E90
SD1_TIMING_H_ACTIVE_FILT_WINDO
W2
2-333
MMReg:0x5E94
SD1_TIMING_H_RUNIN_FILT_WINDO
W
2-334
MMReg:0x5E98
SD1_Y_BREAK_POINT_SETTING
2-334
MMReg:0x5E9C
SD1_U_V_BREAK_POINT_SETTINGS
2-334
MMReg:0x5EA0
SD1_Y_AND_PASSTHRU_GAIN_SETTIN
GS
2-335
MMReg:0x5EA4
SD1_U_AND_V_GAIN_SETTINGS
2-335
MMReg:0x5EA8
SD1_LUMA_BLANK_SETUP_LEVELS
2-335
MMReg:0x5EAC
SD1_RGB_OR_PBPR_BLANK_LEVEL
2-336
MMReg:0x5EB0
SD1_LUMA_SYNC_TIP_LEVELS
2-336
MMReg:0x5EB4
SD1_LUMA_FILT_CNTL
2-336
MMReg:0x5EB8
SD1_LUMA_COMB_FILT_CNTL1
2-338
MMReg:0x5EBC
SD1_LUMA_COMB_FILT_CNTL2
2-338
MMReg:0x5EC0
SD1_LUMA_COMB_FILT_CNTL3
2-338
MMReg:0x5EC4
SD1_LUMA_COMB_FILT_CNTL4
2-338
MMReg:0x5EC8
SD1_VIDOUT_MUX_CNTL
2-339
MMReg:0x5ECC
SD1_FORCE_DAC_DATA
2-340
MMReg:0x5EF0
SD1_CHROMA_MOD_CNTL
2-341
MMReg:0x5EF4
SD1_COL_SC_DENOMIN
2-341
MMReg:0x5EF8
SD1_COL_SC_INC
2-342
MMReg:0x5EFC
SD1_COL_SC_INC_CORR
2-342
MMReg:0x5F00
SD1_SCM_COL_SC_DENOMIN
2-342
MMReg:0x5F04
SD1_SCM_COL_SC_INC
2-342
MMReg:0x5F08
SD1_SCM_COL_SC_INC_CORR
2-343
MMReg:0x5F0C
SD1_SCM_MOD_CNTL
2-343
MMReg:0x5F10
SD1_SCM_DB_DR_SCALE_FACTORS
2-343
MMReg:0x5F14
SD1_SCM_MIN_DTO_SWING
2-344
MMReg:0x5F18
SD1_SCM_MAX_DTO_SWING
2-344
AMD RS690 ASIC Family Register Reference Manual
A-38
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
MMReg:0x5F1C
SD1_CRC_CNTL
2-344
MMReg:0x5F20
SD1_VIDEO_PORT_SIG
2-344
MMReg:0x5F28
SD1_SDTV0_DEBUG
2-345
MMReg:0x5F8C
SD1_LUMA_OFFSET_LIMIT
2-345
MMReg:0x5F90
SD1_CHROMA_OFFSET
2-345
MMReg:0x5F94
SD1_UPSAMPLE_MODE
2-345
MMReg:0x5F98
SD1_CRTC_HV_START
2-346
MMReg:0x5F9C
SD1_CRTC_TV_FRAMESTART_CNTL
2-346
MMReg:0x5FA0
HD_EMBEDDED_SYNC_CNTL
2-346
MMReg:0x5FA4
HD_INCR
2-346
MMReg:0x5FA8
HD_TRILEVEL_DUR
2-346
MMReg:0x5FAC
HD_POS_SYNC_LEVEL
2-347
MMReg:0x5FB0
HD_BACKPORCH_DUR
2-347
MMReg:0x5FB4
HD_SERATION_DUR
2-347
MMReg:0x5FD4
SD1_COL_SC_PHASE_CNTL
2-345
MMReg:0x7AB0
LVTMA_CRC_CNTL
2-348
MMReg:0x7AB4
LVTMA_CRC_SIG_MASK
2-348
MMReg:0x7AB8
LVTMA_CRC_SIG_RGB
2-349
MMReg:0x7ABC
LVTMA_2ND_CRC_RESULT
2-349
MMReg\:0x108
CONFIG_APER_SIZE
2-112
nbconfig:0x14
NB_BAR1_RCRB
2-26
nbconfig:0x18
NB_BAR2_PM2
2-4
nbconfig:0x1C
NB_BAR3_PCIEXP_MMCFG
2-5
nbconfig:0x2
NB_DEVICE_ID
2-1
nbconfig:0x2C
NB_ADAPTER_ID
2-5
nbconfig:0x34
NB_CAPABILITIES_PTR
2-5
nbconfig:0x4
NB_COMMAND
2-1
nbconfig:0x48
NB_ECC_CTRL
2-26
nbconfig:0x4C
NB_PCI_CTRL
2-6
nbconfig:0x6
NB_STATUS
2-2
nbconfig:0x69
NB_SMRAM
2-14
nbconfig:0x6A
NB_EXSMRAM
2-15
nbconfig:0x6C
NB_STRAP_READ_BACK
2-15
nbconfig:0x70
NB_MC_IND_INDEX
2-33
nbconfig:0x74
NB_MC_IND_DATA
2-33
nbconfig:0x7C
NB_IOC_CFG_CNTL
2-34
nbconfig:0x8
NB_REVISION_ID
2-3
nbconfig:0x80
NB_HT_CLK_CNTL_RECEIVER_COMP_
CNTL
2-17
nbconfig:0x84
NB_PCI_ARB
2-20
nbconfig:0x8C
NB_GC_STRAPS
2-22
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-39
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
nbconfig:0x90
NB_TOP_OF_DRAM_SLOT1
2-22
nbconfig:0x94
NB_HT_TRANS_COMP_CNTL
2-17
nbconfig:0x9C
NB_CFG_Q_F1000_800
2-25
nbconfig:0xA8
HTIU_NB_INDEX
2-26
nbconfig:0xAC
HTIU_NB_DATA
2-26
nbconfig:0xC
NB_CACHE_LINE
2-3
nbconfig:0xC4
NB_HT_LINK_COMMAND
2-18
nbconfig:0xC8
NB_HT_LINK_CONF_CNTL
2-18
nbconfig:0xCC
NB_HT_LINK_END
2-19
nbconfig:0xD0
NB_HT_LINK_FREQ_CAP_A
2-19
nbconfig:0xD4
NB_HT_LINK_FREQ_CAP_B
2-20
nbconfig:0xDC
NB_HT_MEMORY_BASE_UPPER
2-20
nbconfig:0xE
NB_HEADER
2-4
nbconfig\:0x0
NB_VENDOR_ID
2-1
nbconfig\:0x20
NB_BAR3_UPPER_PCIEXP_MMCFG
2-5
nbconfig\:0x50
NB_ADAPTER_ID_W
2-7
nbconfig\:0x54
SCRATCH_1_NBCFG
2-16
nbconfig\:0x60
NB_MISC_INDEX
2-7
nbconfig\:0x64
NB_MISC_DATA
2-7
nbconfig\:0x68
NB_FDHC
2-14
nbconfig\:0x6B
NB_PMCR
2-15
nbconfig\:0x78
SCRATCH_NBCFG
2-16
nbconfig\:0x9
NB_REGPROG_INF
2-3
nbconfig\:0x98
SCRATCH_2_NBCFG
2-17
nbconfig\:0xA
NB_SUB_CLASS
2-3
nbconfig\:0xB
NB_BASE_CODE
2-3
nbconfig\:0xD
NB_LATENCY
2-4
nbconfig\:0xE0
NB_PCIE_INDX_ADDR
2-24
nbconfig\:0xE4
NB_PCIE_INDX_DATA
2-24
nbconfig\:0xE8
NB_MC_INDEX
2-24
nbconfig\:0xEC
NB_MC_DATA
2-25
nbconfig\:0xF
NB_BIST
2-4
nbconfig\:0xF8
NB_AGP_ADDRESS_SPACE_SIZE
2-23
nbconfig\:0xFC
NB_AGP_MODE_CONTROL
2-24
NBMCIND:0x0
MC_GENERAL_PURPOSE
2-153
NBMCIND:0x100
MCCFG_FB_LOCATION
2-257
NBMCIND:0x101
MCCFG_AGP_LOCATION
2-257
NBMCIND:0x102
MCCFG_AGP_BASE
2-258
NBMCIND:0x103
MCCFG_AGP_BASE_2
2-258
NBMCIND:0x104
MC_INIT_MISC_LAT_TIMER
2-258
NBMCIND:0x105
MC_INIT_GFX_LAT_TIMER
2-259
AMD RS690 ASIC Family Register Reference Manual
A-40
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
NBMCIND:0x106
MC_INIT_WR_LAT_TIMER
2-259
NBMCIND:0x107
MC_ARB_CNTL
2-260
NBMCIND:0x108
MC_DEBUG_CNTL
2-261
NBMCIND:0x111
MC_BIST_CNTL0
2-262
NBMCIND:0x112
MC_BIST_CNTL1
2-262
NBMCIND:0x113
MC_BIST_MISMATCH_L
2-263
NBMCIND:0x114
MC_BIST_MISMATCH_H
2-263
NBMCIND:0x115
MC_BIST_PATTERN0L
2-263
NBMCIND:0x116
MC_BIST_PATTERN0H
2-263
NBMCIND:0x117
MC_BIST_PATTERN1L
2-264
NBMCIND:0x118
MC_BIST_PATTERN1H
2-264
NBMCIND:0x119
MC_BIST_PATTERN2L
2-264
NBMCIND:0x11A
MC_BIST_PATTERN2H
2-264
NBMCIND:0x11B
MC_BIST_PATTERN3L
2-264
NBMCIND:0x11C
MC_BIST_PATTERN3H
2-264
NBMCIND:0x11D
MC_BIST_PATTERN4L
2-264
NBMCIND:0x11E
MC_BIST_PATTERN4H
2-265
NBMCIND:0x11F
MC_BIST_PATTERN5L
2-265
NBMCIND:0x120
MC_BIST_PATTERN5H
2-265
NBMCIND:0x121
MC_BIST_PATTERN6L
2-265
NBMCIND:0x122
MC_BIST_PATTERN6H
2-265
NBMCIND:0x123
MC_BIST_PATTERN7L
2-265
NBMCIND:0x124
MC_BIST_PATTERN7H
2-265
NBMCIND:0x18
MC_MISC_CNTL
2-153
NBMCIND:0x1B
NB_MEM_CH_CNTL2
2-181
NBMCIND:0x1C
NB_MEM_CH_CNTL0
2-181
NBMCIND:0x1D
NB_MEM_CH_CNTL1
2-182
NBMCIND:0x1F
NB_MC_DEBUG
2-154
NBMCIND:0x2B
GART_FEATURE_ID
2-155
NBMCIND:0x2E
GART_CACHE_CNTRL
2-157
NBMCIND:0x3A
AIC_CTRL_SCRATCH
2-160
NBMCIND:0x4E
MC_MISC_CNTL2
2-161
NBMCIND:0x4F
MC_MISC_CNTL3
2-182
NBMCIND:0x5F
MC_MISC_UMA_CNTL
2-162
NBMCIND:0x63
K8_DRAM_CS0_BASE
2-162
NBMCIND:0x64
K8_DRAM_CS1_BASE
2-163
NBMCIND:0x65
K8_DRAM_CS2_BASE
2-163
NBMCIND:0x66
K8_DRAM_CS3_BASE
2-163
NBMCIND:0x67
K8_DRAM_CS4_BASE
2-164
NBMCIND:0x68
K8_DRAM_CS5_BASE
2-164
NBMCIND:0x69
K8_DRAM_CS6_BASE
2-164
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-41
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
NBMCIND:0x6A
K8_DRAM_CS7_BASE
2-165
NBMCIND:0x6B
K8_DRAM_CS0_MASK
2-165
NBMCIND:0x6C
K8_DRAM_CS1_MASK
2-165
NBMCIND:0x6D
K8_DRAM_CS2_MASK
2-165
NBMCIND:0x6E
K8_DRAM_CS3_MASK
2-166
NBMCIND:0x6F
K8_DRAM_CS4_MASK
2-166
NBMCIND:0x70
K8_DRAM_CS5_MASK
2-166
NBMCIND:0x74
MC_MPLL_CONTROL
2-169
NBMCIND:0x75
MC_MPLL_CONTROL2
2-169
NBMCIND:0x76
MC_MPLL_CONTROL3
2-170
NBMCIND:0x77
MC_MPLL_FREQ_CONTROL
2-170
NBMCIND:0x78
MC_MPLL_SEQ_CONTROL
2-171
NBMCIND:0x79
MC_MPLL_DIV_CONTROL
2-171
NBMCIND:0x7A
MC_MCLK_CONTROL
2-172
NBMCIND:0x80
MC_UMA_WC_GRP_TMR
2-174
NBMCIND:0x80
MC_UMA_WC_GRP_TMR
2-182
NBMCIND:0x81
MC_UMA_WC_GRP_CNTL
2-175
NBMCIND:0x81
MC_UMA_WC_GRP_CNTL
2-183
NBMCIND:0x82
MC_UMA_RW_GRP_TMR
2-176
NBMCIND:0x82
MC_UMA_RW_GRP_TMR
2-184
NBMCIND:0x83
MC_UMA_RW_G3DR_GRP_CNTL
2-176
NBMCIND:0x83
MC_UMA_RW_G3DR_GRP_CNTL
2-185
NBMCIND:0x84
MC_UMA_RW_TXR_E2R_GRP_CNTL
2-178
NBMCIND:0x84
MC_UMA_RW_TXR_E2R_GRP_CNTL
2-187
NBMCIND:0x85
MC_UMA_AGP_GRP_CNTL
2-179
NBMCIND:0x85
MC_UMA_AGP_GRP_CNTL
2-189
NBMCIND:0x86
MC_UMA_DUALCH_CNTL
2-180
NBMCIND:0x86
MC_UMA_DUALCH_CNTL
2-190
NBMCIND:0x90
MC_SYSTEM_STATUS
2-191
NBMCIND:0x91
MC_INTFC_GENERAL_PURPOSE
2-192
NBMCIND:0x92
MC_INTFC_IMP_CTRL_CNTL
2-193
NBMCIND:0x93
MC_INTFC_IMP_CTRL_REF
2-193
NBMCIND:0x94
MC_LATENCY_COUNT_CNTL
2-194
NBMCIND:0x95
MC_LATENCY_COUNT_EVENT
2-194
NBMCIND:0x96
MCS_PERF_COUNT0
2-194
NBMCIND:0x97
MCS_PERF_COUNT1
2-194
NBMCIND:0x98
MCS_PERF_CNTL
2-195
NBMCIND:0x99
MC_AZ_DEFAULT_ADDR
2-195
NBMCIND:0xA0
MCA_MEMORY_INIT_MRS
2-195
NBMCIND:0xA1
MCA_MEMORY_INIT_EMRS
2-196
NBMCIND:0xA2
MCA_MEMORY_INIT_EMRS2
2-196
AMD RS690 ASIC Family Register Reference Manual
A-42
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
NBMCIND:0xA3
MCA_MEMORY_INIT_EMRS3
2-197
NBMCIND:0xA4
MCA_MEMORY_INIT_SEQUENCE_1
2-198
NBMCIND:0xA5
MCA_MEMORY_INIT_SEQUENCE_2
2-199
NBMCIND:0xA6
MCA_MEMORY_INIT_SEQUENCE_3
2-200
NBMCIND:0xA7
MCA_MEMORY_INIT_SEQUENCE_4
2-201
NBMCIND:0xA8
MCA_TIMING_PARAMETERS_1
2-202
NBMCIND:0xA9
MCA_TIMING_PARAMETERS_2
2-203
NBMCIND:0xAA
MCA_TIMING_PARAMETERS_3
2-204
NBMCIND:0xAB
MCA_TIMING_PARAMETERS_4
2-205
NBMCIND:0xAC
MCA_MEMORY_TYPE
2-206
NBMCIND:0xAD
MCA_CKE_MUX_SELECT
2-206
NBMCIND:0xAE
MCA_ODT_MUX_SELECT
2-207
NBMCIND:0xAF
MCA_SEQ_PERF_CNTL
2-208
NBMCIND:0xB0
MCA_SEQ_CONTROL
2-209
NBMCIND:0xB1
MCA_RECEIVING
2-211
NBMCIND:0xB2
MCA_IN_TIMING_DQS_3210
2-212
NBMCIND:0xB3
MCA_IN_TIMING_DQS_7654
2-214
NBMCIND:0xB4
MCA_DRIVING
2-216
NBMCIND:0xB5
MCA_OUT_TIMING
2-217
NBMCIND:0xB6
MCA_OUT_TIMING_DQ
2-219
NBMCIND:0xB7
MCA_OUT_TIMING_DQS
2-221
NBMCIND:0xB8
MCA_STRENGTH_N
2-222
NBMCIND:0xB9
MCA_STRENGTH_P
2-223
NBMCIND:0xBA
MCA_STRENGTH_STEP
2-223
NBMCIND:0xBB
MCA_STRENGTH_READ_BACK_N
2-225
NBMCIND:0xBC
MCA_STRENGTH_READ_BACK_P
2-226
NBMCIND:0xBD
MCA_PREAMP
2-226
NBMCIND:0xBE
MCA_PREAMP_N
2-229
NBMCIND:0xBF
MCA_PREAMP_P
2-230
NBMCIND:0xC0
MCA_PREAMP_STEP
2-230
NBMCIND:0xC1
MCA_PREBUF_SLEW_N
2-232
NBMCIND:0xC2
MCA_PREBUF_SLEW_P
2-233
NBMCIND:0xC3
MCA_GENERAL_PURPOSE
2-233
NBMCIND:0xC4
MCA_GENERAL_PURPOSE_2
2-234
NBMCIND:0xC5
MCA_OCD_CONTROL
2-234
NBMCIND:0xC6
MCA_DQ_DQS_READ_BACK
2-235
NBMCIND:0xC7
MCA_DQS_CLK_READ_BACK
2-235
NBMCIND:0xC8
MCA_MEMORY_INIT_MRS_PM
2-237
NBMCIND:0xC9
MCA_MEMORY_INIT_EMRS_PM
2-237
NBMCIND:0xCA
MCA_MEMORY_INIT_EMRS2_PM
2-238
NBMCIND:0xCB
MCA_MEMORY_INIT_EMRS3_PM
2-239
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-43
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
NBMCIND:0xCC
MCA_TIMING_PARAMETERS_1_PM
2-239
NBMCIND:0xCD
MCA_TIMING_PARAMETERS_2_PM
2-241
NBMCIND:0xCE
MCA_TIMING_PARAMETERS_3_PM
2-242
NBMCIND:0xCF
MCA_TIMING_PARAMETERS_4_PM
2-243
NBMCIND:0xD0
MCA_IN_TIMING_DQS_3210_PM
2-244
NBMCIND:0xD1
MCA_IN_TIMING_DQS_7654_PM
2-246
NBMCIND:0xD2
MCA_OUT_TIMING_DQ_PM
2-248
NBMCIND:0xD3
MCA_OUT_TIMING_DQS_PM
2-250
NBMCIND:0xD4
MCA_MISCELLANEOUS
2-251
NBMCIND:0xD5
MCA_MISCELLANEOUS_2
2-251
NBMCIND:0xD6
MCA_MX1X2X_DQ
2-252
NBMCIND:0xD7
MCA_MX1X2X_DQS
2-253
NBMCIND:0xD8
MCA_DLL_MASTER_0
2-253
NBMCIND:0xD9
MCA_DLL_MASTER_1
2-254
NBMCIND:0xE0
MCA_DLL_SLAVE_RD_0
2-254
NBMCIND:0xE1
MCA_DLL_SLAVE_RD_1
2-254
NBMCIND:0xE8
MCA_DLL_SLAVE_WR_0
2-254
NBMCIND:0xE9
MCA_DLL_SLAVE_WR_1
2-255
NBMCIND:0xF0
MCA_RESERVED_0
2-255
NBMCIND:0xF1
MCA_RESERVED_1
2-255
NBMCIND:0xF2
MCA_RESERVED_2
2-255
NBMCIND:0xF3
MCA_RESERVED_3
2-255
NBMCIND:0xF4
MCA_RESERVED_4
2-255
NBMCIND:0xF5
MCA_RESERVED_5
2-256
NBMCIND:0xF6
MCA_RESERVED_6
2-256
NBMCIND:0xF7
MCA_RESERVED_7
2-256
NBMCIND:0xF8
MCA_RESERVED_8
2-256
NBMCIND:0xF9
MCA_RESERVED_9
2-256
NBMCIND:0xFA
MCA_RESERVED_A
2-256
NBMCIND:0xFB
MCA_RESERVED_B
2-256
NBMCIND:0xFC
MCA_RESERVED_C
2-257
NBMCIND:0xFD
MCA_RESERVED_D
2-257
NBMCIND:0xFE
MCA_RESERVED_E
2-257
NBMCIND:0xFF
MCA_RESERVED_F
2-257
NBMCIND\:0x1E
K8_FB_LOCATION
2-154
NBMCIND\:0x26
MC_PM_CNTL
2-154
NBMCIND\:0x2C
GART_BASE
2-157
NBMCIND\:0x2D
GART_CACHE_SZBASE
2-157
NBMCIND\:0x2F
GART_CACHE_ENTRY_CNTRL
2-157
NBMCIND\:0x30
GART_ERROR_0
2-158
NBMCIND\:0x31
GART_ERROR_1
2-158
AMD RS690 ASIC Family Register Reference Manual
A-44
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
NBMCIND\:0x32
GART_ERROR_2
2-158
NBMCIND\:0x33
GART_ERROR_3
2-158
NBMCIND\:0x34
GART_ERROR_4
2-159
NBMCIND\:0x35
GART_ERROR_5
2-159
NBMCIND\:0x36
GART_ERROR_6
2-159
NBMCIND\:0x37
GART_ERROR_7
2-159
NBMCIND\:0x38
AGP_ADDRESS_SPACE_SIZE
2-160
NBMCIND\:0x39
AGP_MODE_CONTROL
2-160
NBMCIND\:0x3B
MC_GART_ERROR_ADDRESS
2-161
NBMCIND\:0x3C
MC_GART_ERROR_ADDRESS_HI
2-161
NBMCIND\:0x71
K8_DRAM_CS6_MASK
2-166
NBMCIND\:0x72
K8_DRAM_CS7_MASK
2-167
NBMCIND\:0x73
K8_DRAM_BANK_ADDR_MAPPING
2-167
NBMCIND\:0x7B
MC_UMA_HDR_LAT_INIT
2-172
NBMCIND\:0x7C
MC_UMA_GRP_CNTL
2-172
NBMCIND\:0x7D
MC_UMA_GRP_TMR
2-173
NBMCIND\:0x7E
MC_MISC_UMA_CNTL2
2-173
NBMISCIND:0x1
NB_IOC_DEBUG
2-27
NBMISCIND:0x10
DFT_CNTL2
2-28
NBMISCIND:0x16
NB_TOM_PCI
2-28
NBMISCIND:0x17
NB_MMIOBASE
2-28
NBMISCIND:0x18
NB_MMIOLIMIT
2-28
NBMISCIND:0x1F
NB_INTERRUPT_PIN
2-28
NBMISCIND:0x20
NB_PROG_DEVICE_REMAP_0
2-29
NBMISCIND:0x30
IOC_LAT_PERF_CNTR_CNTL
2-29
NBMISCIND:0x31
IOC_LAT_PERF_CNTR_OUT
2-29
NBMISCIND:0x32
PCIE_NBCFG_REG0
2-11
NBMISCIND:0x33
PCIE_NBCFG_REG3
2-12
NBMISCIND:0x34
PCIE_NBCFG_REG4
2-12
NBMISCIND:0x35
PCIE_NBCFG_REG5
2-13
NBMISCIND:0x36
PCIE_NBCFG_REG6
2-13
NBMISCIND:0x37
PCIE_NBCFG_REG7
2-13
NBMISCIND:0x38
PCIE_NBCFG_REG8
2-14
NBMISCIND:0x39
PCIE_STRAP_REG2
2-14
NBMISCIND:0x39
PCIE_STRAP_REG2
2-29
NBMISCIND:0x3A
NB_BROADCAST_BASE_LO
2-29
NBMISCIND:0x3B
NB_BROADCAST_BASE_HI
2-29
NBMISCIND:0x3C
NB_BROADCAST_CNTL
2-30
NBMISCIND:0x3D
NB_APIC_P2P_CNTL
2-30
NBMISCIND:0x3E
NB_APIC_P2P_RANGE_0
2-30
NBMISCIND:0x3F
NB_APIC_P2P_RANGE_1
2-30
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-45
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
NBMISCIND:0x40
GPIO_PAD
2-31
NBMISCIND:0x41
GPIO_PAD_CNTL_PU_PD
2-31
NBMISCIND:0x42
GPIO_PAD_SCHMEM_OE
2-32
NBMISCIND:0x43
GPIO_PAD_SP_SN
2-32
NBMISCIND:0x44
DFT_VIP_IO_GPIO
2-32
NBMISCIND:0x45
DFT_VIP_IO_GPIO_OR
2-33
NBMISCIND:0x5
DFT_CNTL0
2-27
NBMISCIND:0x50
IOC_PCIE_D2_CSR_Count
2-34
NBMISCIND:0x51
IOC_PCIE_D2_CNTL
2-34
NBMISCIND:0x52
IOC_PCIE_D3_CSR_Count
2-34
NBMISCIND:0x53
IOC_PCIE_D3_CNTL
2-35
NBMISCIND:0x54
IOC_PCIE_D4_CSR_Count
2-35
NBMISCIND:0x55
IOC_PCIE_D4_CNTL
2-35
NBMISCIND:0x56
IOC_PCIE_D5_CSR_Count
2-35
NBMISCIND:0x57
IOC_PCIE_D5_CNTL
2-36
NBMISCIND:0x58
IOC_PCIE_D6_CSR_Count
2-36
NBMISCIND:0x59
IOC_PCIE_D6_CNTL
2-36
NBMISCIND:0x5A
IOC_PCIE_D7_CSR_Count
2-37
NBMISCIND:0x5B
IOC_PCIE_D7_CNTL
2-37
NBMISCIND:0x6
DFT_CNTL1
2-27
NBMISCIND:0x60
StrapsOutputMux_0
2-37
NBMISCIND:0x61
StrapsOutputMux_1
2-37
NBMISCIND:0x62
StrapsOutputMux_2
2-37
NBMISCIND:0x63
StrapsOutputMux_3
2-38
NBMISCIND:0x64
StrapsOutputMux_4
2-38
NBMISCIND:0x65
StrapsOutputMux_5
2-38
NBMISCIND:0x66
StrapsOutputMux_6
2-38
NBMISCIND:0x67
StrapsOutputMux_7
2-39
NBMISCIND:0x68
StrapsOutputMux_8
2-39
NBMISCIND:0x69
StrapsOutputMux_9
2-40
NBMISCIND:0x6A
StrapsOutputMux_A
2-40
NBMISCIND:0x6B
StrapsOutputMux_B
2-40
NBMISCIND:0x6C
StrapsOutputMux_C
2-40
NBMISCIND:0x6D
StrapsOutputMux_D
2-40
NBMISCIND:0x6E
StrapsOutputMux_E
2-41
NBMISCIND:0x6F
StrapsOutputMux_F
2-41
NBMISCIND:0x7
PCIE_PDNB_CNTL
2-25
NBMISCIND:0x70
scratch_0
2-41
NBMISCIND:0x71
scratch_1
2-41
NBMISCIND:0x72
scratch_2
2-41
NBMISCIND:0x73
scratch_3
2-41
AMD RS690 ASIC Family Register Reference Manual
A-46
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
NBMISCIND:0x74
SCRATCH_4
2-41
NBMISCIND:0x75
SCRATCH_5
2-42
NBMISCIND:0x76
SCRATCH_6
2-42
NBMISCIND:0x77
SCRATCH_7
2-42
NBMISCIND:0x78
SCRATCH_8
2-42
NBMISCIND:0x79
SCRATCH_9
2-42
NBMISCIND:0x7A
SCRATCH_A
2-42
NBMISCIND:0x7F
DFT_SPARE
2-43
NBMISCIND:0x8
PCIE_LINK_CFG
2-9
NBMISCIND:0xB
IOC_PCIE_CNTL
2-10
NBMISCIND:0xC
IOC_P2P_CNTL
2-11
NBMISCIND:0xE
IOCIsocMapAddr_LO
2-27
NBMISCIND:0xF
IOCIsocMapAddr_HI
2-28
NBMISCIND\:0x0
NB_CNTL
2-8
NBMISCIND\:0x2
NB_SPARE1
2-8
NBMISCIND\:0x3
NB_STRAPS_READBACK_MUX
2-9
NBMISCIND\:0x4
NB_STRAPS_READBACK_DATA
2-9
NBMISCIND\:0x9
IOC_DMA_ARBITER
2-10
NBMISCIND\:0xA
IOC_PCIE_CSR_Count
2-10
pcieConfigDev[10:2]\:0x
PCIE_VENDOR_ID
0
2-72
pcieConfigDev[10:2]\:0x
PCIE_VC_ENH_CAP_HDR
100
2-108
pcieConfigDev[10:2]\:0x
PCIE_PORT_VC_CAP_REG1
104
2-108
pcieConfigDev[10:2]\:0x
PCIE_PORT_VC_CAP_REG2
108
2-108
pcieConfigDev[10:2]\:0x
PCIE_PORT_VC_CNTL
10C
2-108
pcieConfigDev[10:2]\:0x
PCIE_PORT_VC_STATUS
10E
2-109
pcieConfigDev[10:2]\:0x
PCIE_VC0_RESOURCE_CAP
110
2-93
pcieConfigDev[10:2]\:0x
PCIE_VC0_RESOURCE_CNTL
114
2-94
pcieConfigDev[10:2]\:0x
PCIE_VC0_RESOURCE_STATUS
11A
2-94
pcieConfigDev[10:2]\:0x
PCIE_VC1_RESOURCE_CAP
11C
2-109
pcieConfigDev[10:2]\:0x
PCIE_VC1_RESOURCE_CNTL
120
2-109
pcieConfigDev[10:2]\:0x
PCIE_VC1_RESOURCE_STATUS
124
2-109
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-47
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
pcieConfigDev[10:2]\:0x
PCIE_ENH_ADV_ERR_RPT_CAP_HDR
140
2-89
pcieConfigDev[10:2]\:0x
PCIE_UNCORR_ERR_STATUS
144
2-89
pcieConfigDev[10:2]\:0x
PCIE_UNCORR_ERR_MASK
148
2-90
pcieConfigDev[10:2]\:0x
PCIE_UNCORR_ERR_SEVERITY
14C
2-90
pcieConfigDev[10:2]\:0x
PCIE_CORR_ERR_STATUS
150
2-90
pcieConfigDev[10:2]\:0x
PCIE_CORR_ERR_MASK
154
2-91
pcieConfigDev[10:2]\:0x
PCIE_ADV_ERR_CAP_CNTL
158
2-91
pcieConfigDev[10:2]\:0x
PCIE_HDR_LOG0
15C
2-91
pcieConfigDev[10:2]\:0x
PCIE_HDR_LOG1
160
2-91
pcieConfigDev[10:2]\:0x
PCIE_HDR_LOG2
164
2-92
pcieConfigDev[10:2]\:0x
PCIE_HDR_LOG3
168
2-92
pcieConfigDev[10:2]\:0x
PCIE_ROOT_ERR_CMD
16C
2-92
pcieConfigDev[10:2]\:0x
PCIE_ROOT_ERR_STATUS
170
2-92
pcieConfigDev[10:2]\:0x
PCIE_ERR_SRC_ID
174
2-93
pcieConfigDev[10:2]\:0x
SUB_BUS_NUMBER_LATENCY
18
2-75
pcieConfigDev[10:2]\:0x
IO_BASE_LIMIT
1C
2-76
pcieConfigDev[10:2]\:0x
SECONDARY_STATUS
1E
2-76
pcieConfigDev[10:2]\:0x
PCIE_DEVICE_ID
2
2-73
pcieConfigDev[10:2]\:0x
MEM_BASE_LIMIT
20
2-77
pcieConfigDev[10:2]\:0x
PREF_BASE_LIMIT
24
2-77
pcieConfigDev[10:2]\:0x
PREF_BASE_UPPER
28
2-77
pcieConfigDev[10:2]\:0x
PREF_LIMIT_UPPER
2C
2-77
pcieConfigDev[10:2]\:0x
IO_BASE_LIMIT_HI
30
2-77
AMD RS690 ASIC Family Register Reference Manual
A-48
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
pcieConfigDev[10:2]\:0x
CAP_PTR
34
2-78
pcieConfigDev[10:2]\:0x
PCIE_INTERRUPT_LINE
3C
2-78
pcieConfigDev[10:2]\:0x
PCIE_INTERRUPT_PIN
3D
2-78
pcieConfigDev[10:2]\:0x
IRQ_BRIDGE_CNTL
3E
2-78
pcieConfigDev[10:2]\:0x
PCIE_COMMAND
4
2-73
pcieConfigDev[10:2]\:0x
PMI_CAP_LIST
50
2-79
pcieConfigDev[10:2]\:0x
PMI_CAP
52
2-79
pcieConfigDev[10:2]\:0x
PMI_STATUS_CNTL
54
2-79
pcieConfigDev[10:2]\:0x
PCIE_CAP_LIST
58
2-80
pcieConfigDev[10:2]\:0x
PCIE_CAP
5A
2-80
pcieConfigDev[10:2]\:0x
DEVICE_CAP
5C
2-80
pcieConfigDev[10:2]\:0x
PCIE_STATUS
6
2-73
pcieConfigDev[10:2]\:0x
DEVICE_CNTL
60
2-81
pcieConfigDev[10:2]\:0x
DEVICE_STATUS
62
2-82
pcieConfigDev[10:2]\:0x
LINK_CAP
64
2-82
pcieConfigDev[10:2]\:0x
LINK_CNTL
68
2-83
pcieConfigDev[10:2]\:0x
LINK_STATUS
6A
2-83
pcieConfigDev[10:2]\:0x
SLOT_CAP
6C
2-84
pcieConfigDev[10:2]\:0x
SLOT_CNTL
70
2-84
pcieConfigDev[10:2]\:0x
SLOT_STATUS
72
2-85
pcieConfigDev[10:2]\:0x
ROOT_CNTL
74
2-85
pcieConfigDev[10:2]\:0x
ROOT_CNTL
74
2-107
pcieConfigDev[10:2]\:0x
ROOT_CAP
76
2-107
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-49
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
pcieConfigDev[10:2]\:0x
ROOT_STATUS
78
2-86
pcieConfigDev[10:2]\:0x
PCIE_REVISION_ID
8
2-74
pcieConfigDev[10:2]\:0x
MSI_CAP_LIST
80
2-86
pcieConfigDev[10:2]\:0x
MSI_CAP_LIST
80
2-107
pcieConfigDev[10:2]\:0x
PCIE_MSI_MSG_CNTL
82
2-86
pcieConfigDev[10:2]\:0x
PCIE_MSI_MSG_ADDR_LO
84
2-87
pcieConfigDev[10:2]\:0x
PCIE_MSI_MSG_ADDR_HI
88
2-87
pcieConfigDev[10:2]\:0x
PCIE_MSI_MSG_DATA
88
2-87
pcieConfigDev[10:2]\:0x
PCIE_MSI_MSG_DATA_64
8C
2-87
pcieConfigDev[10:2]\:0x
PCIE_REGPROG_INF
9
2-74
pcieConfigDev[10:2]\:0x
CRS_TIMER
90
2-87
pcieConfigDev[10:2]\:0x
IOC_CNTL
94
2-88
pcieConfigDev[10:2]\:0x
PCIE_SUB_CLASS
A
2-74
pcieConfigDev[10:2]\:0x
PCIE_BASE_CODE
B
2-74
pcieConfigDev[10:2]\:0x
SSID_CAP_LIST
B0
2-88
pcieConfigDev[10:2]\:0x
SSID_ID
B4
2-88
pcieConfigDev[10:2]\:0x
MSI_MAP
B8
2-88
pcieConfigDev[10:2]\:0x
PCIE_CACHE_LINE
C
2-74
pcieConfigDev[10:2]\:0x
PCIE_CFG_SCRATCH
C0
2-107
pcieConfigDev[10:2]\:0x
PCIE_LATENCY
D
2-75
pcieConfigDev[10:2]\:0x
PCIE_HEADER
E
2-75
pcieConfigDev[10:2]\:0x
PCIE_PORT_INDEX
E0
2-89
pcieConfigDev[10:2]\:0x
PCIE_PORT_DATA
E4
2-89
AMD RS690 ASIC Family Register Reference Manual
A-50
© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Address
Secondary
Address
Name
Additional
Address
Page
pcieConfigDev[10:2]\:0x
PCIE_BIST
F
2-75
PCIEIND:0x10
PCIE_CNTL
2-58
PCIEIND:0x12
PCIE_DEBUG_CNTL
2-94
PCIEIND:0x20
PCIE_CI_CNTL
2-59
PCIEIND:0x30
PCIE_WPR_CNTL
2-95
PCIEIND:0x40
PCIE_P_CNTL
2-60
PCIEIND:0x70
PCIE_PERF_LATENCY_CNTL
2-95
PCIEIND:0x71
PCIE_PERF_LATENCY_REQ_ID
2-96
PCIEIND:0x72
PCIE_PERF_LATENCY_TAG
2-96
PCIEIND:0x73
PCIE_PERF_LATENCY_THRESHOLD
2-96
PCIEIND:0x74
PCIE_PERF_LATENCY_MAX
2-96
PCIEIND:0x75
PCIE_PERF_LATENCY_TIMER_LO
2-96
PCIEIND:0x76
PCIE_PERF_LATENCY_TIMER_HI
2-97
PCIEIND:0x77
PCIE_PERF_LATENCY_COUNTER0
2-97
PCIEIND:0x78
PCIE_PERF_LATENCY_COUNTER1
2-97
PCIEIND:0xD0
PCIE_PRBS23_BITCNT_0
2-97
PCIEIND:0xD1
PCIE_PRBS23_BITCNT_1
2-97
PCIEIND:0xD2
PCIE_PRBS23_BITCNT_2
2-97
PCIEIND:0xD3
PCIE_PRBS23_BITCNT_3
2-97
PCIEIND:0xD4
PCIE_PRBS23_BITCNT_4
2-98
PCIEIND:0xD5
PCIE_PRBS23_BITCNT_5
2-98
PCIEIND:0xD6
PCIE_PRBS23_BITCNT_6
2-98
PCIEIND:0xD7
PCIE_PRBS23_BITCNT_7
2-98
PCIEIND:0xD8
PCIE_PRBS23_BITCNT_8
2-98
PCIEIND:0xD9
PCIE_PRBS23_BITCNT_9
2-98
PCIEIND:0xDA
PCIE_PRBS23_BITCNT_10
2-98
PCIEIND:0xDB
PCIE_PRBS23_BITCNT_11
2-99
PCIEIND:0xDC
PCIE_PRBS23_BITCNT_12
2-99
PCIEIND:0xDD
PCIE_PRBS23_BITCNT_13
2-99
PCIEIND:0xDE
PCIE_PRBS23_BITCNT_14
2-99
PCIEIND:0xDF
PCIE_PRBS23_BITCNT_15
2-99
PCIEIND:0xE0
PCIE_PRBS23_ERRCNT_0
2-99
PCIEIND:0xE1
PCIE_PRBS23_ERRCNT_1
2-99
PCIEIND:0xE2
PCIE_PRBS23_ERRCNT_2
2-100
PCIEIND:0xE3
PCIE_PRBS23_ERRCNT_3
2-100
PCIEIND:0xE4
PCIE_PRBS23_ERRCNT_4
2-100
PCIEIND:0xE5
PCIE_PRBS23_ERRCNT_5
2-100
PCIEIND:0xE6
PCIE_PRBS23_ERRCNT_6
2-100
PCIEIND:0xE7
PCIE_PRBS23_ERRCNT_7
2-100
PCIEIND:0xE8
PCIE_PRBS23_ERRCNT_8
2-100
© 2007 Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
A-51
Table 2-3 All Registers Sorted By Address
Address
Name
Secondary
Address
Additional
Address
Page
PCIEIND:0xE9
PCIE_PRBS23_ERRCNT_9
2-101
PCIEIND:0xEA
PCIE_PRBS23_ERRCNT_10
2-101
PCIEIND:0xEB
PCIE_PRBS23_ERRCNT_11
2-101
PCIEIND:0xEC
PCIE_PRBS23_ERRCNT_12
2-101
PCIEIND:0xED
PCIE_PRBS23_ERRCNT_13
2-101
PCIEIND:0xEE
PCIE_PRBS23_ERRCNT_14
2-101
PCIEIND:0xEF
PCIE_PRBS23_ERRCNT_15
2-101
PCIEIND:0xF0
PCIE_PRBS23_CLR
2-102
PCIEIND:0xF1
PCIE_PRBS23_ERRSTAT
2-102
PCIEIND:0xF2
PCIE_PRBS23_LOCKED
2-102
PCIEIND:0xF3
PCIE_PRBS23_FREERUN
2-102
PCIEIND:0xF4
PCIE_PRBS23_LOCK_CNT
2-102
PCIEIND:0xF5
PCIE_PRBS23_EN
2-102
PCIEIND:0xF6
PCIE_P90RX_PRBS_CLR
2-102
PCIEIND:0xF7
PCIE_P90_BRX_PRBS_ER
2-103
PCIEIND:0xF8
PCIE_P90TX_PRBS_EN
2-103
PCIEIND:0xF9
PCIE_B_P90_CNTL
2-103
PCIEIND\:0x0
PCIE_RESERVED
2-58
PCIEIND\:0x1
PCIE_SCRATCH
2-58
PCIEIND\:0x11
PCIE_CONFIG_CNTL
2-58
PCIEIND\:0x21
PCIE_BUS_CNTL
2-59
PCIEIND\:0x41
PCIE_P_BUF_STATUS
2-61
PCIEIND\:0x42
PCIE_P_DECODER_STATUS
2-62
PCIEIND\:0x44
PCIE_P_PLL_CNTL
2-63
PCIEIND\:0x60
PCIE_P_IMP_CNTL_STRENGTH
2-63
PCIEIND\:0x61
PCIE_P_IMP_CNTL_UPDATE
2-64
PCIEIND\:0x62
PCIE_P_STR_CNTL_UPDATE
2-64
PCIEIND\:0x63
PCIE_P_PAD_MISC_CNTL
2-64
PCIEIND\:0x64
PCIE_P_PAD_FORCE_EN
2-64
PCIEIND\:0x65
PCIE_P_PAD_FORCE_DIS
2-65
PCIEIND_P:0x10
PCIEP_PORT_CNTL
2-65
PCIEIND_P:0x20
PCIE_TX_CNTL
2-66
PCIEIND_P:0x21
PCIE_TX_REQUESTER_ID
2-66
PCIEIND_P:0x22
PCIE_TX_VENDOR_SPECIFIC
2-67
PCIEIND_P:0x22
PCIE_TX_VENDOR_SPECIFIC
2-103
PCIEIND_P:0x23
PCIE_TX_REQUEST_NUM_CNTL
2-67
PCIEIND_P:0x24
PCIE_TX_SEQ
2-67
PCIEIND_P:0x25
PCIE_TX_REPLAY
2-67
PCIEIND_P:0x26
PCIE_TX_ACK_LATENCY_LIMIT
2-67
PCIEIND_P:0x26
PCIE_TX_ACK_LATENCY_LIMIT
2-103
PCIEIND_P:0x30
PCIE_TX_CREDITS_CONSUMED_P
2-103
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
PCIEIND_P:0x31
PCIE_TX_CREDITS_CONSUMED_NP
2-104
PCIEIND_P:0x32
PCIE_TX_CREDITS_CONSUMED_CPL
2-104
PCIEIND_P:0x33
PCIE_TX_CREDITS_LIMIT_P
2-104
PCIEIND_P:0x34
PCIE_TX_CREDITS_LIMIT_NP
2-104
PCIEIND_P:0x35
PCIE_TX_CREDITS_LIMIT_CPL
2-105
PCIEIND_P:0x70
PCIE_RX_CNTL
2-69
PCIEIND_P:0x72
PCIE_RX_VENDOR_SPECIFIC
2-105
PCIEIND_P:0x80
PCIE_RX_CREDITS_ALLOCATED_P
2-105
PCIEIND_P:0x81
PCIE_RX_CREDITS_ALLOCATED_NP
2-105
PCIEIND_P:0x82
PCIE_RX_CREDITS_ALLOCATED_CPL
2-105
PCIEIND_P:0x83
PCIE_RX_CREDITS_RECEIVED_P
2-106
PCIEIND_P:0x84
PCIE_RX_CREDITS_RECEIVED_NP
2-106
PCIEIND_P:0x85
PCIE_RX_CREDITS_RECEIVED_CPL
2-106
PCIEIND_P:0xA0
PCIE_LC_CNTL
2-69
PCIEIND_P:0xA1
PCIE_LC_TRAINING_CNTL
2-72
PCIEIND_P:0xA3
PCIE_LC_N_FTS_CNTL
2-72
PCIEIND_P:0xA3
PCIE_LC_N_FTS_CNTL
2-106
PCIEIND_P\:0x0
PCIEP_RESERVED
2-65
PCIEIND_P\:0x1
PCIEP_SCRATCH
2-65
PCIEIND_P\:0x50
PCIE_P_PORT_LANE_STATUS
2-68
PCIEIND_P\:0x60
PCIE_FC_P
2-68
PCIEIND_P\:0x61
PCIE_FC_NP
2-68
PCIEIND_P\:0x62
PCIE_FC_CPL
2-68
PCIEIND_P\:0x6A
PCIE_ERR_CNTL
2-68
PCIEIND_P\:0x84
PCIE_RX_LASTACK_SEQNUM
2-69
PCIEIND_P\:0xA2
PCIE_LC_LINK_WIDTH_CNTL
2-72
PCIEIND_P\:0xA5
PCIE_LC_STATE0
2-71
PCIEIND_P\:0xA6
PCIE_LC_STATE1
2-71
PCIEIND_P\:0xA7
PCIE_LC_STATE2
2-71
PCIEIND_P\:0xA8
PCIE_LC_STATE3
2-71
PCIEIND_P\:0xA9
PCIE_LC_STATE4
2-71
PCIEIND_P\:0xAA
PCIE_LC_STATE5
VGA_IO\:0x3BA
GENFC_WT
VGA_IO\:0x3DA
2-297
VGA_IO\:0x3BA
GENS1
VGA_IO\:0x3DA
2-299
VGA_IO\:0x3C0
ATTRDW
2-316
VGA_IO\:0x3C0
ATTRX
2-316
VGA_IO\:0x3C1
ATTRDR
2-316
VGA_IO\:0x3C2
GENMO_WT
2-297
VGA_IO\:0x3C2
GENS0
2-299
VGA_IO\:0x3C3
GENENB
2-127
VGA_IO\:0x3C6
DAC_MASK
2-296
© 2007 Advanced Micro Devices, Inc.
Proprietary
2-71
AMD RS690 ASIC Family Register Reference Manual
A-53
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
Page
VGA_IO\:0x3C7
DAC_R_INDEX
2-296
VGA_IO\:0x3C8
DAC_W_INDEX
2-296
VGA_IO\:0x3C9
DAC_DATA
2-296
VGA_IO\:0x3CA
GENFC_RD
2-297
VGA_IO\:0x3CC
GENMO_RD
2-298
VGAATTRIND\:0x0
ATTR00
2-316
VGAATTRIND\:0x1
ATTR01
2-317
VGAATTRIND\:0x10
ATTR10
2-320
VGAATTRIND\:0x11
ATTR11
2-320
VGAATTRIND\:0x12
ATTR12
2-320
VGAATTRIND\:0x13
ATTR13
2-321
VGAATTRIND\:0x14
ATTR14
2-321
VGAATTRIND\:0x2
ATTR02
2-317
VGAATTRIND\:0x3
ATTR03
2-317
VGAATTRIND\:0x4
ATTR04
2-317
VGAATTRIND\:0x5
ATTR05
2-317
VGAATTRIND\:0x6
ATTR06
2-318
VGAATTRIND\:0x7
ATTR07
2-318
VGAATTRIND\:0x8
ATTR08
2-318
VGAATTRIND\:0x9
ATTR09
2-318
VGAATTRIND\:0xA
ATTR0A
2-318
VGAATTRIND\:0xB
ATTR0B
2-319
VGAATTRIND\:0xC
ATTR0C
2-319
VGAATTRIND\:0xD
ATTR0D
2-319
VGAATTRIND\:0xE
ATTR0E
2-319
VGAATTRIND\:0xF
ATTR0F
2-319
VGACRTIND\:0x0
CRT00
2-303
VGACRTIND\:0x1
CRT01
2-303
VGACRTIND\:0x10
CRT10
2-308
VGACRTIND\:0x11
CRT11
2-308
VGACRTIND\:0x12
CRT12
2-309
VGACRTIND\:0x13
CRT13
2-309
VGACRTIND\:0x14
CRT14
2-309
VGACRTIND\:0x15
CRT15
2-309
VGACRTIND\:0x16
CRT16
2-310
VGACRTIND\:0x17
CRT17
2-310
VGACRTIND\:0x18
CRT18
2-310
VGACRTIND\:0x1E
CRT1E
2-311
VGACRTIND\:0x1F
CRT1F
2-311
VGACRTIND\:0x2
CRT02
2-303
VGACRTIND\:0x22
CRT22
2-311
AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Table 2-3 All Registers Sorted By Address
Secondary
Address
Additional
Address
Address
Name
VGACRTIND\:0x3
CRT03
2-304
VGACRTIND\:0x4
CRT04
2-304
VGACRTIND\:0x5
CRT05
2-304
VGACRTIND\:0x6
CRT06
2-305
VGACRTIND\:0x7
CRT07
2-305
VGACRTIND\:0x8
CRT08
2-306
VGACRTIND\:0x9
CRT09
2-306
VGACRTIND\:0xA
CRT0A
2-306
VGACRTIND\:0xB
CRT0B
2-307
VGACRTIND\:0xC
CRT0C
2-307
VGACRTIND\:0xD
CRT0D
2-307
VGACRTIND\:0xE
CRT0E
2-307
VGACRTIND\:0xF
CRT0F
2-308
VGAGRPHIND\:0x0
GRA00
2-312
VGAGRPHIND\:0x1
GRA01
2-312
VGAGRPHIND\:0x2
GRA02
2-313
VGAGRPHIND\:0x3
GRA03
2-313
VGAGRPHIND\:0x4
GRA04
2-313
VGAGRPHIND\:0x5
GRA05
2-314
VGAGRPHIND\:0x6
GRA06
2-314
VGAGRPHIND\:0x7
GRA07
2-315
VGAGRPHIND\:0x8
GRA08
2-315
VGASEQIND\:0x0
SEQ00
2-300
VGASEQIND\:0x1
SEQ01
2-300
VGASEQIND\:0x2
SEQ02
2-300
VGASEQIND\:0x3
SEQ03
2-301
VGASEQIND\:0x4
SEQ04
2-301
© 2007 Advanced Micro Devices, Inc.
Proprietary
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AMD RS690 ASIC Family Register Reference Manual
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AMD RS690 ASIC Family Register Reference Manual
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© 2007 Advanced Micro Devices, Inc.
Proprietary
Appendix B
Revision History
Rev 3.00o (December 2007)
•
Open source release.
Advanced Micro Devices, Inc.
Proprietary
AMD RS690 ASIC Family Register Reference Manual
B-1
AMD RS690 ASIC Family Register Reference Manual
B-2
Advanced Micro Devices, Inc.
Proprietary