AS5SS256K36

SSRAM
AS5SS256K36
256K x 36 SSRAM
PIN ASSIGNMENT
(Top View)
Flow-Through, Synchronous
Burst SRAM
100-pin TQFP (DQ)
FEATURES












OPTIONS

MARKING
Timing
7.5ns/8.5ns/117MHz
8.5ns/10ns/100MHz
10ns/15ns/66MHz
-7.5
-8.5
-10
Packages
TQFP
DQ
Operating Temperature Ranges
Military (-55oC to +125oC)
Enhanced (-40oC to +105oC)
Industrial (-40oC to +85oC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
SA
SA
SA
SA
SA
SA
SA
SA
NF
VDD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE

DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
Vss
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Organized 256K x 36
Fast Clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (VDD)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
Low capacitive bus loading
100-lead TQFP package for high density, high speed
RoHs compliant options available
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
VDD
CE2\
BWa\
BWb\
BWc\
BWd\
CE2
CE\
SA
SA

No. 1001
/XT
/ET
/IT
For more products and information
please visit our web site at
www.micross.com
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x 36
SRAM core with advanced synchronous peripheral circuitry and a
2-bit burst counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data inputs, active
LOW chip enable (CE\), two additional chip enables for easy depth
expansion (CE2\, CE2), burst control inputs (ADSC\, ADSP\, ADV\),
byte write enables (BWx\) and global write (GW\).
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
1
SSRAM
AS5SS256K36
GENERAL DESCRIPTION (continued)
simplify WRITE cycles. This allows self-timed WRITE cycles.
Individual byte enables allow individual bytes to be written.
During WRITE cycles on the x18 device, BWa\ controls DQa’s
and DQPa; BWb\ controls DQb’s and DQPb; BWc\ controls
DQc’s and DQPc; BWd\ controls DQd’s and DQPd. GW\ LOW
causes all bytes to be written. Parity bits are also featured on
this device.
This 8Mb Synchronous Burst SRAM operates from a
+3.3V VDD power supply, and all inputs and outputs are TTLcompatible. The device is ideally suited for 486, Pentium©,
680x0 and PowerPCTM systems and those systems that benefit
from a wide synchronous data bus.
Asynchronous inputs include the output enable (OE\),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved and
linear burst modes. The data-out (Q), enabled by OE\, is also
asynchronous. WRITE cycles can be from one to four bytes
wide as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP\) or address status controller (ADSC\)
inputs. Subsequent burst addresses can be internally generated
as controlled by the burst advance input (ADV\).
Address and write control are registered on-chip to
FUNCTIONAL BLOCK DIAGRAM
18
SA0, SA1, SAs
MODE
ADV\
CLK
18
ADDRESS
REGISTER
16
18
SA0-SA1
Q1
BINARY
COUNTER
AND LOGIC
CL
SA1'
Q0
SA0'
ADSC\
ADSP\
BWd\
BYTE "d"
WRITE REGISTER
BYTE "d"
WRITE DRIVER
BWc\
BYTE "c"
WRITE REGISTER
BYTE "c"
WRITE DRIVER
BWb\
BYTE "b"
WRITE REGISTER
BYTE "b"
WRITE DRIVER
BWa\
BWE\
GW\
BYTE "a"
WRITE REGISTER
BYTE "a"
WRITE DRIVER
CE\
CE2
CE2\
OE\
256K x 9 x 4
(x36)
MEMORY
ARRAY
DQs
SENSE
AMPS
OUTPUT
BUFFERS
DQPb
DQPc
DQPd
INPUT
REGISTERS
ENABLE
REGISTER
4
NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions
for detailed information.
AS5SS256K36
Rev. 4.4 10/13
DQPa
and time diagrams
Micross Components reserves the right to change products or specifications without notice.
2
SSRAM
AS5SS256K36
PIN DESCRIPTION
Pin Number
37
36
32-35, 44-50,
81, 82, 99,
100
43
SYMBOL
SA0
SA1
SA
TYPE
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet
Input the setup and hold times around the rising edge of CLK. Two different
pinouts are available for the TQFP packages.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold times
around the rising edge of CLK. A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;
Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;
Bwd\ controls DQd pins and DQPd. Parity bits are featured on this
device.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold items around the rising
edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur
independent of the BWE\ and BWx\ lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: CLK registers address, data, chip enable, byte write enables and
burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the
device and conditions the internal use of ADSP\. CE\ is sampled only
when a new external address is loaded.
93
94
95
96
BWa\
BWb\
BWc\
BWd\
Input
87
BWE\
Input
88
GW\
Input
89
CLK
Input
98
CE\
Input
92
CE2\
Input
Synchronous Chip Enable: This active LOW input is used to enable the
device and is sampled only when a new external address is loaded.
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable the
device and is sampled only when a new external address is loaded.
86
OE\
83
ADV\
85
ADSC\
AS5SS256K36
Rev. 4.4 10/13
Output Enable: This active LOW, asynchronous input enables the data
I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
Input
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV\ must be HIGH at the rising edge of
the first clock after an ADSP\ cycle is initiated.
Synchronous Address Status Controller: This active LOW input interrupts
any ongoing burst, causing a new external address to be registered. A
Input READ or WRITE is performed using the new address if CE\ is LOW.
ADSC\ is also used to place the chip into power-down state when CE\ is
HIGH.
Input
Micross Components reserves the right to change products or specifications without notice.
3
SSRAM
AS5SS256K36
PIN DESCRIPTION (continued)
Pin Number
SYMBOL
84
ASDP\
31
MODE
64
ZZ
(a) 52, 53, 56-59,
62, 63
(b) 68, 69, 72-75,
78, 79
(c) 2, 3, 6-9, 12,
13
(d) 18, 19, 22-25,
28, 29
51
80
1
30
DQa
DQb
DQc
DQd
TYPE
DESCRIPTION
Synchronous Address Status Processor: This active LOW inputs
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address, independent of
Input
the byte write enables and ADSC\, but dependent upon CE\, CE2 and
CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if
CE2 is LOW or CE2\ is HIGH.
MODE: This inputs selects the burst sequence. A LOW on this pin select
Input "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not
alter input state while device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the device
Input to enter a low-power standby mode in which all data in the memory array
is retained. When ZZ is active, all other inputs are ignored.
SRAM Data I/O's: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is
Input/
DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold
Output
times around the rising edge of CLK.
NC/DQPa
Parity Data I/Os: Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte
NC/DQPb
NC/ I/O
"c" parity is DQPc; Byte "d" parity is DQPd.
NC/DQPc
NC/DQPd
Power Supply: See DC Electrical Characteristics and Operating
VDD
15, 41, 65, 91
Supply
Conditions for range.
4, 11, 20, 27, 54,
Isolated Output Buffer Supply: See DC Electrical Characteristics and
VDDQ
Supply
61, 70, 77
Operating Conditions for range.
5, 10, 14, 17, 21,
26, 40, 55, 60, 67,
Vss
Supply Ground: GND
71, 76, 90
Do Not Use: These signals may either be unconnected or wired to GND
38, 39
DNU
--to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
16, 66
NC
--connected to GND to improve package heat dissipation.
No Function: These pins are internally connected to the die and have the
capacitance of an input pin. It is allowable to leave these pins
42
NF
--unconnected or driven by signals. Pin 42 is reserved as an address
upgrade pin for the 16Mb Synchronous Burst.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
4
SSRAM
AS5SS256K36
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS
FUNCTION
READ
READ
WRITE Byte "a"
WRITE All Bytes
WRITE All Bytes
AS5SS256K36
Rev. 4.4 10/13
GW\
H
H
H
H
L
BWE\
H
L
L
L
X
BWa\
X
H
L
L
X
BWb\
X
H
H
L
X
BWc\
X
H
H
L
X
BWd\
X
H
H
L
X
Micross Components reserves the right to change products or specifications without notice.
5
SSRAM
AS5SS256K36
TRUTH TABLE
OPERATION
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADDRESS
CE\ CE2\ CE2
USED
None
H
X
X
None
L
X
L
None
L
H
X
None
L
X
L
None
L
H
X
None
X
X
X
External
L
L
H
External
L
L
H
External
L
L
H
External
L
L
H
External
L
L
H
Next
X
X
X
Next
X
X
X
Next
H
X
X
Next
H
X
X
Next
X
X
X
Next
H
X
X
Current
X
X
X
Current
X
X
X
Current
H
X
X
Current
H
X
X
Current
X
X
X
Current
H
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP\ ADSC\
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV\
WRITE\
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE\ CLK
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “Don’t Care.” \ means active LOW. H Means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\, BWc\, or BWd\) and BWE\ are LOW or
GW\ is LOW. WRITE\ = H for all BWx\, BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQa pins, DQPa. BWb\ enables WRITEs to DQb pins, DQPb. BWc\ enables WRITEs to DQc
pins, DQPc. BWd\ enables WRITEs to DQd pins, DQPd.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
6
SSRAM
AS5SS256K36
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature (Plastics) ...........................-55C to +150C
Storage Temperature (Ceramics) .........................-55C to +125C
Short Circuit Output Current (per I/O)…............................100mA
Voltage on any Pin Relative to Vss........................-0.5V to +4.6 V
Max Junction Temperature**..............................................+150C
VIN (DQx) .........................................................-0.5V to VDDQ +0.5V
VIN (inputs) ................................................... ....-0.5V to VDD +0.5V
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operation section of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
** Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow,
and humidity.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(-55oC to +125oC, -40oC to +105oC or -40oC to +85oC; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
PARAMETER
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
CONDITION
OV < VIN < Vcc
Output(s) disabled, OV < VOUT < Vcc
IOH = -4.0 mA
IOL = 8.0 mA
Isolated Output Buffer Supply
SYMBOL
VIH
VIL
ILI
ILO
VOH
VOL
VDD
VDDQ
MIN
2.2
-0.3
-5
-5
2.4
--3.135
3.135
MAX
VCC +0.3
0.8
5
5
-0.4
3.6
3.6
UNITS
V
V
P$
P$
V
V
V
V
NOTES
1, 2
1, 2
3
1, 4
1, 4
1
1, 5
THERMAL RESISTANCE
Parameter
Ĭ JA
Ĭ JC
Description
TestConditions
Thermal Resistance (Junction to
Ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
Thermal Resistance (Junction to Case) impedance, per EIA/JESD51
DQ
DQC
Package Package
Unit
29.41
30.2
o
6.31
6.5
o
C/W
C/W
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: VIH < +4.6V for t<tKC/2 for I < 20mA
Undershoot: VIL > -0.7V for t<tKC/2 for I < 20mA
Power-up: VIH < +3.6V and VDD < 3.135V for t < 200ms
3. MODE and ZZ pins have internal pull-up resistors, and input leakage = +10A
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the stated DC values.
AC I/O curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.
6. This parameter is sampled.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
7
SSRAM
AS5SS256K36
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(-55oC to +125oC or -40oC to +85oC)
SYM
-7.5
MAX
-8.5
-10
IDD
250
225
200
mA
1, 2, 3
Device selected; VDD = MAX;
ADSC\, ADSP\, ADV\, GW\, BWx\
>VIH; All inputs < Vss+ 0.2 or > VDD -0.2;
Cycle time < tKC MIN; Outputs open
IDD1
160
150
140
mA
1, 2, 3
CMOS Standby
Device deselected; VDD = MAX;
All inputs < Vss +0.2 or > VDD -0.2;
All inputs static; CLK frequency = 0
ISB2
90
90
90
mA
2, 3
TTL Standby
Device deselected; VDD = MAX;
All inputs < VIL or > VIH;
All inputs static; CLK frequency = 0
ISB3
130
130
130
mA
2, 3
DESCRIPTION
CONDITIONS
Device selected; all inputs < VIL
Power Supply
Current: Operating
Power Supply
Current: Idle
KC
or > VIH; Cycle time > t MIN;
VDD = MAX; Outputs open
UNITS NOTES
CAPACITANCE
DESCRIPTION
Input Capacitance
Input/Output Capacitance
CONDITIONS
TA = 25oC; f = 1MHz;
VDD = 3.3V
SYM
CI
MAX
6
UNITS
pF
NOTES
4
CO
8
pF
4
NOTES:
1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device
is active (not in power-down mode).
3. A typical value is measured at 3.3V, 25oC and 15ns cycle time.
4. This parameter is sampled.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
8
SSRAM
AS5SS256K36
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (-55oC to +125oC or -40oC to +85oC)
DESCRIPTION
SYMBOL
-75
MIN
-8.5
MAX
MIN
-10
MAX
MIN
MAX
UNITS
NOTES
CLOCK
Clock cycle time
tKC
Clock frequency
tKF
Clock HIGH time
tKH
2.5
3.0
4.0
ns
2
Clock LOW time
OUTPUT TIMES
Clock to output valid
tKL
2.5
3.0
4.0
ns
2
tKQ
7.5
Clock to output invalid
tKQX
2.5
2.5
2.5
ns
3
Clock to output in Low-Z
tKQLZ
2.5
2.5
2.5
ns
3, 4, 5, 6,
3, 4, 5, 6,
8.5
10.0
117
15.0
100
ns
66
8.5
10.0
MHz
ns
Clock to output in High-Z
tKQHZ
4.0
5.0
5.0
ns
OE\ to output valid
tOEQ
3.4
4.4
5.0
ns
7
OE\ to output in Low-Z
tOELZ
ns
3, 4, 5, 6,
OE\ to output in High-Z
SETUP TIMES
Address
tOEHZ
ns
3, 4, 5, 6,
tAS
1.5
1.8
2.0
ns
8, 9
Address status (ADSC\, ADSP\)
tADSS
1.5
1.8
2.0
ns
8, 9
Address advance (ADV\)
tAAS
1.5
1.8
2.0
ns
8, 9
Byte write enables (BWa\ - BWd\, GW\, BWE\)
tWS
1.5
1.8
2.0
ns
8, 9
Data-in
tDS
1.5
1.8
2.0
ns
8, 9
Chip enable (CE\)
HOLD TIMES
Address
tCES
1.5
1.8
2.0
ns
8, 9
tAH
0.5
0.5
0.5
ns
8, 9
Address status (ADSC\, ADSP\)
tADSH
0.5
0.5
0.5
ns
8, 9
Address advance (ADV\)
tAAH
0.5
0.5
0.5
ns
8, 9
Byte write enables (BWa\ - BWd\, GW\, BWE\)
tWH
0.5
0.5
0.5
ns
8, 9
Data-in
tDH
0.5
0.5
0.5
ns
8, 9
Chip enable (CE\)
tCEH
0.5
0.5
0.5
ns
8, 9
0
0
3.5
0
4.4
5.0
NOTE:
1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
4. This parameter is sampled.
5. Transition is measured +500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters.
7. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by at
least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or ADSC\ is
LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when
the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to remain enabled.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
9
SSRAM
AS5SS256K36
AC TEST CONDITIONS
Input Pulse Levels..................................0V to 3.0V
Input rise and fall times...................................1.5ns
Input timing reference levels............................1.5V
Output reference levels....................................1.5V
Output load...............................See Figures 1 and 2
OUTPUT LOADS
+3.3v
317
DQ
DQ
Z0=50
351
50
5 pF
Vt = 1.5V
Fig. 1 3.3V I/O OUTPUT LOAD EQUIVALENT
Fig. 2 3.3V I/O OUTPUT LOAD EQUIVALENT
NOTE: SRAM timing is dependent upon the capacitive loading on the outputs.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
10
SSRAM
AS5SS256K36
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode
in which the device is deselected and current is reduced to
ZZ is an asynchronous, active HIGH input that causes the
device to enter SNOOZE MODE. When ZZ becomes a logic
ISB2Z. The duration of SNOOZE MODE is dictated by the
length of time ZZ is in a HIGH state. After the device enters
SNOOZE MODE, all inputs except ZZ become gated inputs
and are ignored.
HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any
READ or WRITE operation pending when the device enters
SNOOZE MODE is not guaranteed to complete successfully.
Therefore, SNOOZE MODE must not be initiated until valid
pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
MAX
UNITS
ISB2Z
80
mA
ZZ active to input ignored
tZZ
2tcyc
ns
1
ZZ inactive to input sampled
tRZZ
ns
1
ZZ active to snooze current
tZZI
ns
1
ZZ inactive to exit snooze current
tRZZI
ns
1
Current during SNOOZE MODE
CONDITIONS
SYM
ZZ > VIH
MIN
2tcyc
2tcyc
0
NOTES
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t
t
ZZ
RZZ
ZZ
t
ZZI
ISUPPLY
t
SB2
t
RZZI
ALL INPUTS*
*Except ZZ
Don’t Care
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
11
SSRAM
AS5SS256K36
t
READ TIMING3
KC
t
KL
CLK
t
t
ADSS
KH
ADSP\
t
ADSH
t
ADSS
ADSC\
t
ADSH
t
AS
A2
A1
ADDRESS
Deselect Cycle
(note 4)
t
AH
BWE\, GW\,
BWa\ - BWd\
t
t
t
CES
WH
WS
CE\
(Note 2)
t
tAAS
CEH
ADV\
ADV\ suspends burst.
tAAH
OE\
t
t
Q
OEQ
KQLZ
High-Z
t KQ
t OEHZ
Q(A1)
tOELZ
t KQ
tKQX
Q(A2)
tKQHZ
Q(A2+1)
Q(A2+2)
Q(A2+3)
(Note 1)
SINGLE READ
Q(A2)
Q(A2+1)
Q(A2+2)
Burst wraps around to
its initial state
BURST READ
Don’t Care
Undefined
NOTE:
1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is
HIGH, CE2\ is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
4. Outputs are disabled tKQHZ after deselect.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
12
SSRAM
AS5SS256K36
t
KC
t
WRITE TIMING
KL
CLK
t
t
ADSS
KH
ADSP\
t
ADSS
t
ADSH
ADSC\ extends burst.
t
ADSS
ADSC\
t
ADSH
tAS
A2
A1
ADDRESS
t
ADSH
t
AH
A3
BYTE WRITE signals are
ignored when ADSP\ is LOW.
t WS
BWE\
BWa\ - BWd\
t WH
t WS
GW\
(Note 5)
t CES
t WH
CE\
(See Note)
t
t AAS
CEH
ADV\
(Note 4)
ADV\ suspends burst.
t
AAH
(Note 3)
OE\
tDS tDH
D
High-Z
D(A1)
t OEHZ
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
(Note 1)
Q
BURST READ
Single WRITE
Don’t Care
NOTE:
Extended BURST WRITE
BURST WRITE
Undefined
1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable
inputs being sampled.
4. ADV\ must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
13
SSRAM
AS5SS256K36
t
KC
t
READ/WRITE TIMING3
KL
CLK
tKH
tADSS
ADSP\
tADSH
ADSC\
t
AS
ADDRESS
A1
A2
A5
A4
A3
t
AH
t
t
WS WH
t
t
DH
A6
WEH\, WEL\,
BWE\, GW\
t
CES
CE\
(See
Note)
t
CEH
ADV\
OE\
D
Q
High-Z
t
OEHZ
Q(A1)
1.
2.
3.
4.
5.
D(A3)
t
OELZ
D(A5)
t
KQ
Q(A2)
Back-to-Back
READs
(Note 5)
NOTE:
DS
(Note 1)
Q(A4)
SINGLE WRITE
D(A6)
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
Don’t Care
Back-to-Back
WRITEs
Undefined
Q(A4) refers to output from address A. Q(A4+1) refers to output from the next internal burst address following A4.
CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
The data bus (Q) remains in High-A following a WRITE cycle unless an ADSP\, ADSC\ or ADV\ cycle is performed.
GW\ is HIGH.
Back-to-back READs may be controlled by either ADSP\ or ADSC\.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
14
SSRAM
AS5SS256K36
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQ)
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
15
SSRAM
AS5SS256K36
ORDERING INFORMATION
TQFP
EXAMPLE: AS5SS256K36DQ-10/IT
Package
Device Number
Speed ns Process
Type
AS5SS256K36
DQ
-8.5
/*
AS5SS256K36
DQ
-10
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
ET = Enhanced Temperature Range
XT = Military Temperature Range
AS5SS256K36
Rev. 4.4 10/13
-40oC to +85oC
-40oC to +105oC
-55oC to +125oC
Micross Components reserves the right to change products or specifications without notice.
16
SSRAM
AS5SS256K36
DOCUMENT TITLE
256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
REVISION HISTORY
Rev #
4.0
History
Removed “A” Version
Release Date
November 2009
Status
Release
4.1
Updated Micross Information
January 2010
Release
4.2
Added copper lead frame and RoHS
May 2011
compliant options. Added -7.5 speed
option and enhanced temp range.
Updated thermal resistance:
From
To
ΘJA 40
29.41 oC/W
ΘJC 9
6.31 oC/W
Updated input/output capacitance and
AC test conditions, CI from 4pF to 6pF
and CO from 5pF to 8pF. Updated
ISB2Z from 10mA to 80mA, and tZZ, tKC
and tZZZ from tKC to 2tKC. Increased min/max
Input and output leakage to ± 5μA.
Changed:
From
To
tKQXmin
3.0ns
2.5ns
tKQLZmin
3.0ns
2.5ns
tOEQ & tOEHZmax
5.0ns
4.4ns
IDDmax (-8.5)
325mA
225mA
(-10)
250mA
200mA
IDD1max (-8.5)
85mA
150mA
(-10)
65mA
140mA
ISB2max
15mA
90mA
ISB3max
30mA
130mA
Deleted ISB4 Specification
Release
4.3
Added DQC package on the Thermal
Resistance table, page 7.
September 2011
Release
4.4
Removed Cu-lead frame option
October 2013
Release
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
17