TMT T35L6464A

tm
TE
CH
T35L6464A
SYNCHRONOUS
BURST SRAM
64K x 64 SRAM
3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
BURST COUNTER
• Fast Access times: 5, 6, 7, and 8ns
• Fast clock speed: 100, 83, 66, and 50 MHz
• Provide high performance 3-1-1-1 access rate
• Fast OE access times: 5 and 6ns
• Single 3.3V +10% / -5V power supply
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL
WRITE control
• Five chip enables for depth expansion and
address pipelining
• Address, control, input, and output pipelined
registers
• Internally self -timed WRITE cycle
• WRITE pass-through capability
• Burst control pins ( interleaved or linear burst
sequence)
• High density, high speed packages
• Low capacitive bus loading
• High 30pF output drive capability at rated access
time
• SNOOZE MODE for reduced power standby
• Single cycle disable ( PentiumT M BSRAM
compatible )
OPTIONS
VCCQ
CE3
CE2
CE3
CE2
VSS
VCC
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
VSS
VCC
BW2
BW1
ADSC
ADSP
ADV
VSSQ
PIN ASSIGNMENT (Top View)
128127126125 124 123122 121 120 119 118117 116115114113112111110109108107106105104103
VSSQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
VCCQ
VSSQ
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
VCCQ
VSSQ
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128-pin QFP
or
128-pin LQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCCQ
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
VSSQ
VCCQ
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
VSSQ
VCCQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
VSSQ
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VSSQ
NC
MODE
A15
A14
A13
VCC
VSS
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VCC
VSS
A2
A1
A0
ZZ
VCCQ
FEATURES
GENERAL DESCRIPTION
TIMING
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
Package
128-pin QFP
128-pin LQFP
MARKING
-5
-6
-7
-8
Q
L
Part Number Examples
PART NO.
T35L6464A -5Q
Pkg.
Q
T35L6464A -5L
L
BURST SEQUENCE
Interleaved
(MODE=NC or VCC)
Linear (MODE=GND)
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6464A SRAM integrates 65536 x 64
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW
chip enable (CE , CE2 and CE3 ), two additional
chip enables (CE2 and CE3) , burst control inputs
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
GENERAL
DESCRIPTION
(continued)
as controlled by the write control inputs.
Individual byte write allows individual byte to be
BW2
written. BW1 controls DQ1-DQ8.
controls DQ9-DQ16. BW3 controls DQ17-DQ24.
BW4 controls DQ25-DQ32. BW5 controls
BW6
DQ33-DQ40.
controls DQ41-DQ48.
BW7 controls DQ49-DQ56. BW8 controls
DQ57-DQ64. BW1 , BW2 , BW3 , BW4 , BW5 ,
BW6 , BW7 and BW8 can be active only with
BWE being LOW. GW being LOW causes all
bytes to be written.
WRITE pass-through
capability allows written data available at the output
for the immediately next READ cycle. This
device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system
performance.
( ADSC , ADSP ,and ADV ), write enables ( BW1 ,
BW2 , BW3 , BW4 , BW5 , BW6 , BW7 ,
BW8 and BWE ), and global write ( GW ).
Asynchronous inputs include the output enable
( OE ) , Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by OE ,
are also asynchronous.
Addresses and chip enables are registered with
either address status processor ( ADSP ) or address
status controller (ADSC ) input pins. Subsequent
burst addresses can be internally generated as
controlled by the burst advance pin ( ADV ).
Address, data inputs, and write controls are
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to eight bytes
wide
FUNCTIONAL BLOCK DIAGRAM
16
16
ADDRESS
REGISTER
A0-A15
A0
14
16
A1
MODE
ADV
CLK
A1'
DO D1 Q1
BINARY
COUNTER
& LOGIC
LOAD
CLR
ADSC
Q0
A0'
ADSP
8
BWE
BYTE 8
WRITE DRIVER
BYTE 8
WRITE REGISTER
8
BW8
8
BYTE 7
WRITE DRIVER
BYTE 7
WRITE REGISTER
8
BW7
8
BYTE 6
WRITE DRIVER
BYTE 6
WRITE REGISTER
8
BW6
8
BYTE 5
WRITE DRIVER
BYTE 5
WRITE REGISTER
8
64K x 8 x 8
MEMORY
ARRAY
BW5
8
BYTE 4
WRITE REGISTER
SENSE
AMPS
8
BYTE 4
WRITE DRIVER
BW4
8
BYTE 3
WRITE REGISTER
8
BYTE 3
WRITE DRIVER
64
BW3
8
BYTE 2
WRITE REGISTER
64
OUTPUT
REGISTERS
OUTPUT
BUFFERS
64
8
BYTE 2
WRITE DRIVER
DQ1
.
.
.
DQ64
BW2
8
BYTE 1
WRITE REGISTER
8
BYTE 1
WRITE DRIVER
BW1
INPUT
REGISTERS
GW
CE
CE2
CE3
CE2
CE3
OE
Chip
Enable
ENABLE
REGISTER
PIPELINED
ENABLE
8
Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
Taiwan Memory Technology, Inc. reserves the right P. 2
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
PIN DESCRIPTIONS
QFP PINS
42-44, 47-51,
53-57, 60-62
107, 108, 111,
112,117-120
114
113
115
121
124
126
125
127
116
SYM.
TYPE
DESCRIPTION
A0InputAddresses: These inputs are registered and must meet the setup and
A15 Synchronous hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1,during burst
cycle and wait cycle.
BW1 InputByte Write: A byte write is LOW for a WRITE cyle and HIGH for
BW8 Synchronous a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32.
BW5 controls DQ33-DQ40. BW6 controls DQ41-DQ48. BW7
controls DQ49-DQ56. BW8 controls DQ57-DQ64. Data I/O are
high impedance if either of these inputs are LOW ,conditioned by
BWE being LOW.
BWE
InputWrite Enable: This active LOW input gates byte write operations
Synchronous and must meet the setup and hold times around the rising edge of
CLK.
GW
InputGlobal Write: This active LOW input allows a full 64-bit WRITE
Synchronous to occur independent of the BWE and BWn lines and must meet
the setup and hold times around the rising edge of CLK.
CLK
InputClock: This signal registers the addresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.
CE
InputSynchronous Chip Enable: This active LOW input is used to enable
Synchronous the device and conditions internal use of ADSP . This input is
sampled only when a new external address is loaded.
CE2
InputSynchronous Chip Enable: This active LOW input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
CE2
InputSynchronous Chip Enable: This active HIGH input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
CE3
InputSynchronous Chip Enable: This active LOW input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
CE3
InputSynchronous Chip Enable: This active HIGH input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
OE
Input
Output enable: This active LOW asynchronous input enables the
data output drivers.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
PIN DESCRIPTIONS (continued)
QFP PINS
104
SYM.
105
ADSP
106
ADSC
41
MODE
63
ZZ
2-12,15-24,
27-37,66-76,
79-88,91-101
DQ1DQ64
45,58,109,122
46,59,110,123
13,25,38,64,
77,89,102,128
1,14,26,39,65,
78,90,103
40,52
VCC
VSS
VCCQ
ADV
VSSQ
NC
TYPE
DESCRIPTION
InputAddress Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
InputAddress Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
InputAddress Status Controller:This active LOW input causes device to
Synchronous be de- selected or selected along with new external address to be
registered. A READ or WRITE cycle is initiated depending upon
write control inputs.
InputMode: This input selects the burst sequence. A LOW on this pin
Static
selects LINEAR BURST. A NC or HIGH on this pin selects
INTERLEAVED BURST. Do not alter input state while device is
operating.
Input
Snooze Enable: This active HIGH asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained.
Input/
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9Output
DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25- DQ32.
Fifth Byte is DQ33- DQ40. Sixth Byte is DQ41- DQ48. Seventh
Byte is DQ49- DQ56. Eighth Byte is DQ57- DQ64. Input data
must meet setup and hold times around the rising edge of CLK.
Supply
Power Supply: 3.3V +10%/-5%.
Ground
Ground: GND
I/O Supply Isolated Output Buffer Supply: 3.3V +10%/-5%.
I/O Ground Output Buffer Ground: GND
-
No Connect: These signals are not internally conntected.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
INTERLEAVED BURST ADDRESS TABLE (MODE = NC/Vcc)
First Address
(external)
A...A00
A...A01
A...A10
A...A11
Second Address
(internal)
A...A01
A...A00
A...A11
A...A10
Third Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth Address
(internal)
A...A11
A...A10
A...A01
A...A00
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address
(external)
A...A00
A...A01
A...A10
A...A11
Second Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth Address
(internal)
A...A11
A...A00
A...A01
A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function
BW1
X
H
L
H
H
H
H
H
H
H
L
X
BW2
X
H
H
L
H
H
H
H
H
H
L
X
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 5
READ
READ
WRITE byte 1
WRITE byte 2
WRITE byte 3
WRITE byte 4
WRITE byte 5
WRITE byte 6
WRITE byte 7
WRITE byte 8
WRITE all byte
WRITE all byte
GW
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
X
BW3
X
H
H
H
L
H
H
H
H
H
L
X
BW4
BW5
BW6
BW7
BW8
X
H
H
H
H
L
H
H
H
H
L
X
X
H
H
H
H
H
L
H
H
H
L
X
X
H
H
H
H
H
H
L
H
H
L
X
X
H
H
H
H
H
H
H
L
H
L
X
X
H
H
H
H
H
H
H
H
L
L
X
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
TRUTH TABLE
OPERATION
ADDRESS CE CE2 CE2 CE3 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
USED
Deselected Cycle, Power Down
None
H
X
X
X
X
L
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
X
X
L
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
X
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
X
X
L
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
X
H
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
X
X
L
H
L
X
X
X
L-H
High-Z
Snooze Cycle, Power Down
None
X
X
X
X
X
H
X
X
X
X
X
X
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
X
X
L
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
X
L
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
X
X
L
H
H
L
L
X
L-H
D
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
X
L
X
H
L
L
X
L-H
READ Cycle, Suspend Burst
Current
X
X
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
X
X
L
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
X
L
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
X
L
X
H
H
L
X
L-H
D
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one
or more byte write enable signals ( BW1 , BW2 , BW3 , BW4 , BW5 , BW6 , BW7 or BW8 )
and BWE are LOW, or GW equals LOW. WRITE = H means all byte write signal are HIGH.
2. BW1 = enables write to DQ1-DQ8. BW2 = enables write to DQ9-DQ16. BW3 = enables write
to DQ17-DQ24. BW4 =enables write to DQ25-DQ32. BW5 = enables write to DQ33-DQ40.
BW6 = enables write to DQ41-DQ48. BW7 = enables write to DQ49-DQ56. BW8 = enables
write to DQ57-DQ64.
3. All inputs except OE must meet setup and hold times around the rising edge ( LOW to HIGH)
of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation. OE must be HIGH before the input data
required setup time plus High-Z time for OE and staying HIGH throughout the input data hold
time.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7. ADSP = LOW along with chip being selected always initiates an internal READ cycle at the L-H
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge
of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss..
………... -0.5V to +4.6V
I/O Supply Voltage VccQ .........……..-0.5V to Vcc
VIN (inputs) ............................ -0.5V to Vcc +0.5V
Storage Temperature (plastic)...... -55°C to +150°C
Junction Temperature ...........…................ +150°C
Power Dissipation .........................................1.6W
Short Circuit Output Current...................... 100mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ T A ≤ 70°C; Vcc = + 3.3V +10%/-5%; unless otherwise noted)
DESCRIPTION
Input High (Logic) voltage
Input Low (Logic) voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
CONDITIONS
0V ≤ VIN ≤ VCC
Output(s) disabled, 0V
≤ VOUT≤ VCC
IOH = -4.0 mA
IOL = 8.0 mA
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
SYM. MIN
VIH
2
VIL
-0.3
ILI
-2
ILO
-2
VOH
VOL
Vcc
P. 7
MAX
VccQ + 0.3
0.8
2
2
UNITS
V
V
µA
µA
NOTES
1, 2
1, 2
14
0.4
3.6
V
V
V
1,11
1,11
1
2.4
3.1
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ T A ≤ 70°C; Vcc = + 3.3V +10%/-5% unless otherwise noted)
MA X
DESCRIPTION
Power Supply
Current:
Operating
Power Supply
Current: Idle
CMOS Standby
TTL Standby
Clock Running
CONDITIONS
Device selected; all inputs
≤VIL or ≥ VIH; cycle time
≥tKC MIN; VCC = MAX;
outputs open
Device selected; ADSC ,
ADSP , ADV , GW , BWE
≥ VIH; all other inputs ≤ VIL
or ≥VIH; VCC = MAX; cycle
time ≥tKC MIN: outputs open
Device deselected; VCC =
MAX; all inputs ≤ VSS + 0.2
or ≥ VCC - 0.2; all inputs
static; CLK frequency = 0
Device deselected; all inputs
≤ VIL or ≥ VIH; all inputs
static; VCC = MAX;
CLK frequency = 0
Device deselected; all inputs ≤
VIL or ≥ VIH; VCC = MAX;
CLK cycle time ≥ tKCMIN
SYM. TYP
Icc 200
-5
300
-6
260
-7
240
-8 UNITS NOTES
210
mA
3, 12, 13
ISB1
30
60
55
50
45
mA
12, 13
ISB2
2
10
10
10
10
mA
12, 13
ISB3
15
40
40
40
40
mA
12, 13
ISB4
30
81
76
66
51
mA
12, 13
CAPACITANCE
DESCRIPTION
Input Capacitance
Input/ Output
Capacitance(DQ)
CONDITIONS
TA = 25°C; f = 1 MHz
VCC = 3.3V
SYM.
CI
CO
TYP
3
6
MAX
4
7
UNITS
pF
pF
NOTES
4
4
THERMAL CONSIDERATION
DESCRIPTION
Thermal Resistance - Junction to
Ambient
Thermal Resistance - Junction to
Case
CONDITIONS
Still air, soldered on
4.25x
1.125 inch 4-layer PCB
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 8
SYM. QFP TYP UNITS
ΘJA
20
°C/W
ΘJB
1
NOTES
°C/W
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0°C ≤ TA ≤ 70°C; Vcc = + 3.3V +10%/-5%)
DESCRIPTION
Clock
Clock cycle time
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
-5
-6
-7
-8
SYM. MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tKC
tKH
10
4
12
4.5
15
5
20
6
ns
ns
tKL
4
4.5
5
6
ns
tKQ
tKQX
Clock to output invalid
Clock to output in Low-Z tKQLZ
Clock to output in High-Z tKQHZ
tOEQ
OE to output valid
tOELZ
OE to output in Low-Z
tOEHZ
OE to output in High-Z
Setup Times
tAS
Address
tADSS
Address Status
( ADSC , ADSP )
Address Advance ( ADV ) tAAS
tWS
Byte Write Enables
( BW1~ BW8 , BWE , GW )
tDS
Data-in
tCES
Chip Enables ( CE ,
CE2 ,CE2, CE3 ,CE3)
Hold Times
tAH
Address
tADSH
Address Status
( ADSC , ADSP )
Address Advance ( ADV )
Byte Write Enables
( BW1~ BW8 , BWE , GW )
Data-in
Chip Enables ( CE ,
CE2 ,CE2, CE3 ,CE3)
5
2
4
6
2
5
5
5
0
7
2
5
5
5
0
4
ns
6
6
ns
ns
ns
ns
ns
ns
6,7
6,7
9
6,7
6,7
2
5
6
5
0
5
8
0
6
6
3
3
3
3
3
3
3
3
ns
ns
8,10
8,10
3
3
3
3
3
3
3
3
ns
ns
8,10
8,10
3
3
3
3
3
3
3
3
ns
ns
8,10
8,10
0.5
0.5
0.5
0.5
ns
8,10
0.5
0.5
0.5
0.5
ns
8,10
tAAH
tWH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8,10
8,10
tDH
tCEH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8,10
8,10
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to change products or specifications without notice.
P. 9
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
AC TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input timing reference
levels
Output reference levels
Output load
0V to 3.0V
1.5ns
1.5V
1.5V
See Figures 1 and 2
Notes:
1. All voltages referenced to Vss (GND).
2. Overshoot: VIH ≤ +3.6 V for t ≤ tKC/2
Undershoot: VIL ≥ -1.0 V for t ≤ tKC/2
3. Icc is given with no output current. Icc increases
with greater output loading and faster cycle
times.
4. This parameter is sampled.
5. Test conditions as specified with the output
loading as shown in Fig. 1 unless otherwise
noted.
6. Output loading is specified with CL=5 pF as in
Fig.2.
7. At any given temperature and voltage condition,
tKQHZ is less than t KQLZ and tOEHZ is less
than tOELZ.
8. A Write cycle is defined by at least one byte
write enable LOW and ADSP HIGH for the
required setup and hold times. A Read cycle
is defined by all byte write enables HIGH and
( ADSC or ADV LOW) or ADSP LOW for
the required setup and hold times.
9. OE is a "don't care" when a byte write enable is
sampled LOW.
10.This is a synchronous device. All synchronous
inputs must meet the setup and hold times,
except for “don‘t care” as defined in the truth
table.
11.AC I/O curves are available upon request.
12."Device Deselected means the device is in
POWER-DOWN mode as defined in the truth
table. "Device Selected" means the device is
active.(not in POWER-DOWN mode).
13.Typical values are measured at 3.3V 25°C and
20ns cycle time.
14.MODE pin has an internal pull-up and exhibits
an input leakage current of ± 10µA.
OUTPUT LOADS
DQ
30 pF
50
Z 0 = 50
Vt =1.5V
Fig.1 OUTPUT LOAD EQUIVALENT
3.3V
317
DQ
5 pF
351
Fig.2 OUTPUT LOAD EQUIVALENT
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
SNOOZE MODE
SNOOZE MODE is a low current, “power
down” mode in which the device is deselected and
the current is reduced to IZ Z. The duration of
SNOOZE MODE is dictated by the length of time
the ZZ pin is in a HIGH state. After entering
SNOOZE MODE, the clock and all other inputs
are ignored.
The ZZ pin (pin 63) is an asynchronous ,
active HIGH input that causes the device to enter
SNOOZE MODE. When the ZZ pin becomes a
logic HIGH, IZ Z is guaranteed after the setup time
t
ZZ is met. Any access pending when entering
SNOOZE MODE is not guaranteed to successfully
complete. Therefore, SNOOZE MODE must not
be initiated until valid pending operations are
completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during
SNOOZE MODE
ZZ HIGH to
SNOOZE MODE time
SNOOZE MODE
Operation Recovery Time
CONDITIONS
SYMBOL
ZZ ≥ VIH
IZZ
tZZ
tRZZ
MIN
MAX
UNITS
10
mA
2(tKC)
2(tKC)
NOTES
ns
3
ns
3
SNOOZE MODE WAVEFORM
CLK
CE
tRZ Z
Z Z
t ZZ
I
S UPP LY
I S U PP L Y
I ZZ
DON'T CARE
Note:
1. The CE signal shown above refers to a TRUE state on all chip selects for the device.
2. All other inputs held to static CMOS levels (VIN ≤ Vss + 0.2 V or ≥ Vcc -0.2 V).
3. This parameter is sampled.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 11
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
READ TIMING
t KC
CLK
t K H t KL
t A D SS t A DS H
ADS P
t A DS S t A DS H
A DSC
t AS t A H
AD DR ES S
A1
A2
A3
B urs t c on tinue d w ith
new ba s e ad d re ss .
t WS t WH
G W, B WE ,
B W 1 -B W 8
Des elec t c yc le.
t C E S t CE H
CE
(N O T E 2 )
(NO T E 4)
t A A S t AA H
ADV
A DV s us p en d s b u rs t.
O E
t O EQ
(NOT E 3)
t K QLZ
Q
Hig h -Z
t OE HZ
Q (A 1)
t KQ
tO ELZ
t KQ
t KQX
Q (A 2)
t K Q HZ
Q (A2 +1)
Q(A 2+2 )
(NOT E 1)
Q (A2 +3)
Q (A 2)
Q (A 2+1)
Bu rs t wr ap s ar ou nd
to its inita l s ta te .
S in g le RE A D
B UR ST RE A D
D ON 'T CAR E
U ND EFIN ED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 , CE2, CE3 and CE3 have timing identical to CE . On this diagram, when CE is LOW,
CE2 , CE3 is LOW and CE2 , CE3 is HIGH. When CE is HIGH, CE2 , CE3 is HIGH and
CE2 , CE3 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE
does not cause Q to be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 12
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
WRITE TIMING
tKC
CLK
t KH
tK L
t A D S S t A D SH
ADS P
A DS C exte nd s b ur s t.
t A D SS t A D SH
t A D S S t A D SH
A DSC
t AS t AH
A DDRES S
A1
A2
A3
B Y T E W RIT E s ig na ls ar e
ig no red f or fir s t c yc le wh en
A D S P initia ltes b u r s t.
t WS t WH
B W E,
B W 1 -B W 8
t WS t WH
(NOT E 5)
G W
t C E S t CE H
CE
(N O T E 2 )
t AA S t AAH
ADV
(NO TE 4)
A DV s u s p nd s b u rs t.
O E
(NO TE 3)
t DS
D
H ig h-Z
t DH
D(A 1)
tOE HZ
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
(NOT E 1)
Q
B U RS T R E A D
S in g le WRIT E
B U RS T WR IT E
Exte nd e d B U RS T WRIT E
DON 'T CAR E
UND EF IN ED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address
following A2.
2. CE2 , CE2, CE3 and CE3 have timing identical to CE . On this diagram, when CE is LOW, CE2 ,
CE3 is LOW and CE2, CE3 is HIGH. When CE is HIGH, CE2 , CE3 is HIGH and CE2, CE3 is
LOW.
3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time. This prevents
input/output data contention for the time period to the byte write enable inputs being sampled.
4. ADV must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1 - BW8 LOW.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 13
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
READ/WRITE TIMING
t KC
C LK
t KH
t KL
t A DS S t A DS H
A DSP
ADS C
t AS t AH
A DDRE SS
A1
A2
A3
A4
A5
A6
D (A5)
D (A6)
t WS t WH
B W 1 -B W 8
t C ES t C EH
CE
(N O T E 2 )
ADV
O E
t DS
t KQ
D
Hig h-Z
Hig h-Z
tO ELZ
D (A3)
t K Q LZ
Q
t DH
Q (A1 )
B ac k-to-B ac k RE A Ds
tO E HZ
tK Q
(NO TE 1)
Q (A2 )
Q (A3 )
Si ng le WR IT E
P as s -throu gh
RE A D
Q (A 4)
Q(A 4+1
)
Q (A4 +2)
B U RS T RE A D
Q(A 4+3 )
B ac k-to-B ac k
WRIT E s
DO N' T C ARE
UN DEF INED
Note: 1. Q (A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2. CE2 , CE2, CE3 and CE3 have timing identical to CE . On this diagram, when CE is LOW,
CE2 , CE3 is LOW and CE2, CE3 is HIGH. When CE is HIGH, CE2 , CE3 is HIGH and CE2,
CE3 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or
ADV cycle is performed.
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC .
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 14
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
PACKAGE DIMENSIONS
128-LEAD QFP SSRAM (14 x 20 mm)
Seating Plane
SYMBOL
A
A1
A2
b
D
E
e
HD'
HE'
L'
L1'
t
y
θ
y
DIMENSIONS IN INCHES
0.134(MAX)
0.107+0.007-0.009
0.010(MIN)
0.008+0.003-0.001
0.551
0.787
0.020
0.677
0.913
0.035±0.006
0.063 ±0.006
0.006+0.003-0.002
0.003
0°~7°
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P.15
DIMENTION IN MM
3.400(MAX)
2.720+0.180-0.220
0.250(MIN)
0.200+0.070-0.030
14.000
20.000
0.500
17.200
23.200
0.880±0.150
1.600 ±0.150
0.150+0.080-0.040
0.080
0°~7°
Publication Date: AUG. 1998
Revision: E
tm
TE
CH
T35L6464A
PACKAGE DIMENSIONS
128-LEAD LQFP SSRAM (14 x 20 mm)
Seating Plane
SYMBOL
A
A1
A2
b
D
E
e
HD'
HE'
L'
L1'
t
y
θ
y
DIMENSIONS IN INCHES
0.063(MAX)
0.055±0.002
0.002(MIN)
0.008+0.003-0.001
0.551
0.787
0.020
0.630
0.866
0.024±0.006
0.039
0.004(MIN),0.008(MAX)
0.003
0°~7°
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P.16
DIMENTION IN MM
1.600(MAX)
1.400±0.050
0.050(MIN)
0.200+0.070-0.030
14.000
20.000
0.500
16.000
22.000
0.600±0.150
1.000
0.090(MIN),0.200(MAX)
0.080
0°~7°
Publication Date: AUG. 1998
Revision: E