English

BL1524
IC card interface
General Description
The BL1524 is a complete and cost-efficient analog interface for asynchronous 3 or 5 V smart
cards. It can be placed between the card and the microcontroller to perform all supply, protection
and control functions. Very few external components are required.
Features
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IC card interface
3 or 5 V supply for the IC (VDD and GND)
Three specifically protected half-duplex bidirectional buffered I/O lines to card contacts C4,
C7 and C8
DC/DC converter for VCC generation separately powered from a 5 V ± 20% supply (VDDP and
PGND)
3 or 5 V ± 5% regulated card supply voltage (VCC) with appropriate decoupling has the
following capabilities:
- ICC < 80 mA at VDDP = 4 to 6.5 V
- Handles current spikes of 40 nAs up to 20 MHz
- Controls rise and fall times
- Filtered overload detection at approximately 120 mA
Thermal and short-circuit protection on all card contacts
Automatic activation and deactivation sequences; initiated by software or by hardware in the
event of a short-circuit, card take-off, overheating, VDD or VDDP drop-out
Enhanced ESD protection on card side (>6 kV)
26 MHz integrated crystal oscillator
Clock generation for cards up to 20 MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and
CLKDIV2 signals) with synchronous frequency changes
Non-inverted control of RST via pin RSTIN
ISO 7816, GSM11.11 and EMV (payment systems) compatibility
Supply supervisor for spike-killing during power-on and power-off and Power-on reset
(threshold fixed internally or externally by a resistor bridge)
Built-in debounce on card presence contacts
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One multiplexed status signal OFF
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Package:SOP28
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Applications
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IC card readers for banking
Electronic payment
Identification
Pay TV
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BL1524
Pin Configuration
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Pin Function
SYMBOL
PIN
TYPE
CLKDIV1
1
I
CLK frequency selection input 1
CLKDIV2
2
I
CLK frequency selection input 2
5V/3V
3
I
card supply voltage selection input; VCC = 5 V (HIGH) or VCC = 3 V (LOW)
PGND
4
S
S2
5
I/O
DC/DC converter power supply ground
DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
VDDP
6
S
S1
7
I/O
VUP
8
I/O
PRES
9
I
PRES
10
I
I/O
11
I/O
data line to/from card reader contact C7; integrated 11 kΩ pull-up resistor to VCC
AUX2
12
I/O
data line to/from card reader contact C8; integrated 11 kΩ pull-up resistor to VCC
AUX1
13
I/O
data line to/from card reader contact C4; integrated 11 kΩ pull-up resistor to VCC
CGND
14
S
CLK
15
I/O
RST
16
O
VCC
17
S
PORADJ
18
I
CMDVCC
19
I
input from the host to start activation sequence (active LOW)
RSTIN
20
I
card reset input from the host
VDD
21
S
supply voltage
GND
22
S
ground
OFF
23
O
XTAL1
24
I
XTAL2
25
O
I/OUC
26
I/O
crystal connection (leave open-circuit if external clock source is used)
host data I/O line; integrated 11 kΩ pull-up resistor to VDD
AUX1UC
27
I/O
auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
AUX2UC
28
I/O
auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
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DESCRIPTION
DC/DC converter power supply voltage
DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
DC/DC converter output decoupling capacitor connection; C = 100 nF with
ESR < 100 mW must be connected between VUP and PGND
card presence contact input (active LOW); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
card signal ground
card clock to/from card reader contact C3
card reset output from card reader contact C2
card supply voltage to card reader contact C1; decoupled to CGND via 2
or 100 + 220 nF capacitors with ESR < 100 mΩ ; note 1
100 nF
Power-on reset threshold adjustment input for changing the reset threshold with
an external resistor bridge; doubles the width of the POR pulse when used.
NMOS interrupt output to the host (active LOW); 20 kΩ integrated pull-up
resistor to VDD
crystal connection or input for external clock
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Block Diagram
Figure 1
Functional Description
Throughout this document it is assumed that the reader is familiar with ISO7816 terminology.
Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals
interfacing with the system controller are referred to VDD, therefore VDD should also supply the
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system controller. All card reader contacts remain inactive during power-on or power-off.
The internal circuits are maintained in the reset state until VDD reaches Vth2 + Vhys2 and for the
duration of the internal Power-on reset pulse, tW (see Figure 2). When VDD falls below Vth2, an
automatic deactivation of the contacts is performed.
A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The DC/DC
converter should be supplied separately by VDDP and PGND. Due to the possibility of large
transient currents, the two 100 nF capacitors of the DC/DC converter should be located as near as
possible to the IC and have an ESR less than 100 mΩ.
The DC/DC converter functions as a voltage doubler or a voltage follower according to the
respective values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV).
The DC/DC converter function changes as follows:
VCC = 5 V and VDDP > 5.8 V; voltage follower
VCC = 5 V and VDDP < 5.7 V; voltage doubler
VCC = 3 V and VDDP > 4.1 V; voltage follower
VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Supply voltages VDD and VDDP may be applied to the IC in any sequence.
After powering the device, OFF remains LOW until CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the falling threshold voltage.
Voltage supervisor
 WITHOUT EXTERNAL DIVIDER ON PIN PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms (tW) is
used internally to keep the IC inactive during power-on or power-off of the VDD supply (see Figure
2).
As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the
command lines. This state also lasts for the duration of tW after VDD has reached a level higher than
Vth2 + Vhys2.
When VDD falls below Vth2, a deactivation sequence of the contacts is performed.
 WITH AN EXTERNAL DIVIDER ON PIN PORADJ
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If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure1), then the
following occurs:
The internal threshold voltage Vth2 is overridden by the external voltage and by the hysteresis,
therefore:
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
The reset pulse width tW is doubled to approximately 16 ms.
Input PORADJ is biased internally with a pull-down current source of 4μA which is removed
when the voltage on pin PORADJ exceeds 1 V. This ensures that after detection of the external
bridge by the IC during power-on, the input current on pin PORADJ does not cause inaccuracy of
the bridge voltage.
The minimum threshold voltage should be higher than 2 V.
The maximum threshold voltage may be up to VDD.
APPLICATION EXAMPLES
The voltage supervisor is used as Power-on reset and as supply dropout detection during a card
session.
Supply dropout detection is to ensure that a proper deactivation sequence is followed before the
voltage is too low.
For the internal voltage supervisor to function, the system microcontroller should operate down to
2.35 V to ensure a proper deactivation sequence. If this is not possible, external resistor values
can be chosen to overcome the problem.
 Microcontroller requiring a 3.3 V±20% supply
For a microcontroller supplied by 3.3 V with a±5% regulator and with resistors R1, R2 having
a±1% tolerance, the minimum supply voltage is 3.135 V.
VPROADJ＝k×VDD，where k＝s1/(s1+s2) with S1 and S2 the actual values of nominal resistors R1
and R2.
This can be shown as 0.99×R1 < S1 < 1.01×R1 and 0.99×R2 < S2 < 1.01×R2
Transposed, this becomes
If V1 = Vth(ext)(rise)(max) and V2 = Vth(ext)(fall)(min), activation will always be possible if VPORADJ > V1 and
deactivation will always be done for VPORADJ < V2.
Activation is always possible for VDD> V1/k and deactivation is always possible for VDD< V2/k.
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Deactivation will be effective at V2×(1 + 1.02×1.365) = 2.847 V in any case.
If the microcontroller continues to function down to 2.80 V, the slew rate on VDD should be less
than 2 V/ms to ensure that clock CLK is correctly delivered to the card until time t12 (see Figure 6).
 Microcontroller requiring a 3.3 V ±10% supply
For a microcontroller supplied by a 3.3 V with a ±1% regulator and with resistors R1, R2 having a
±0.1% tolerance, the minimum supply voltage is 3.267 V.
Deactivation will be effective at V2×(1 + 1.002×1.491) = 2.967 V in any case.
If the microcontroller continues to function down to 2.97 V, the slew rate on VDD should be less
than 0.20 V/ms to ensure that clock CLK is correctly delivered to the card until time t12 (see Figure
6)
Clock circuitry
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a crystal
operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL, 1/2×fXTAL, 1/4×fXTAL or 1/8×fXTAL. Frequency selection is made via
inputs CLKDIV1 and CLKDIV2 (see Table 1).
Table 1. Clock frequency selection（note 1）
Note 1.
The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns
minimum between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is shorter than
45% of the smallest period, and that the first and last clock pulses about the instant of change
have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of XTAL1
after the command.
The duty factor of fXTAL depends on the signal present at pin XTAL1.
In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1 should have a
duty factor of 48 to 52% and transition times of less than 5% of the input signal period.
If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit layout
and on the crystal characteristics and frequency.
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In other cases, the duty factor on pin CLK is guaranteed between 45 and 55% of the clock period.
The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used, or if the
clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as shown in the
activation sequences shown in Figure 4 and 5.
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will be
applied to the card when it is sent by the system microcontroller (after completion of the activation
sequence).
I/O transceivers
The three data lines I/O, AUX1 and AUX2 are identical.
The idle state is realized by both I/O and I/OUC lines being pulled HIGH via a 11 kΩ resistor (I/O to
VCC and I/OUC to VDD).
Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus allowing operation when VCC is not equal
to VDD.
The first side of the transceiver to receive a falling edge becomes the master. An anti-latch circuit
disables the detection of falling edges on the line of the other side, which then becomes a slave.
After a time delay td(edge), an N transistor on the slave side is turned on, thus transmitting the logic 0
present on the master side.
When the master side returns to logic 1, a P transistor on the slave side is turned on during the
time delay tpu and then both sides return to their idle states.
This active pull-up feature ensures fast LOW-to-HIGH transitions; as shown in Fig.3, it is able to
deliver more than 1 mA at an output voltage of up to 0.9VCC into an 80 pF load. At the end of the
active pull-up pulse, the output voltage depends only on the internal pull-up resistor and the load
current.
The current to and from the card I/O lines is limited internally to 15 mA and the maximum
frequency on these lines is 1 MHz.
(1) Current
(2) Voltage
Figure 3. I/O,AUX1 and AUX2 output voltage and current as functions of time during a
LOW-to-HIGH transition.
Inactive mode
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After a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits are
active while waiting for the microcontroller to start a session:
 All card contacts are inactive (approximately 200Ω to GND)
 Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 kΩ pull-up resistor to
VDD)
 Voltage generators are stopped
 XTAL oscillator is running
 Voltage supervisor is active
 The internal oscillator is running at its low frequency.
Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can check the
presence of a card using the signals OFF and CMDVCC as shown in Table 2.
Table 2, Card presence indication
If the card is in the reader (this is the case if PRES or PRES is active), the system
microcontroller can start a card session by pulling CMDVCC LOW. The following sequence
then occurs (see Figure 3):
1) CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0).
2）The voltage doubler is started (between t0 and t1).
3）VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5×T) where T is 64 times the
period of the internal oscillator (approximately 25 μs).
4）I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (these were pulled LOW until this moment).
5）CLK is applied to the C3 contact of the card reader (t4).
6）RST is enabled (t5 = t1 + 7T).
The clock may be applied to the card using the following sequence:
1）Set RSTIN HIGH.
2）Set CMDVCC LOW.
3）Reset RSTIN LOW between t3 and t5; CLK will start at this moment.
4）RST remains LOW until t5, when RST is enabled to be the copy of RSTIN.
5）After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses before
toggling RST.
If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this
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case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t5,RSTIN may be
set HIGH in order to obtain an Answer To Request (ATR) from the card.
Activation should not be performed with RSTIN held permanently HIGH.
Figure 4 .Activation sequence using RSTIN and CMDVCC
Figure 5.Activation sequence at t3
Active mode
When the activation sequence is completed, the BL1524 will be in its active mode. Data is
exchanged between the card and the microcontroller via the I/O lines. The BL1524 is designed for
cards without VPP (the voltage required to program or erase the internal non-volatile memory).
Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and finishing
in the inactive mode (see Figure 6):
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Figure 6. Deactivation sequence
1) RST goes LOW (t10).
2) CLK is held LOW (t12 = t10 + 0.5×T) where T is 64 times the period of the internal oscillator
(approximately 25 μs).
3) I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).
4) VCC starts to fall towards zero (t14 = t10 + 1.5×T).
5) The deactivation sequence is complete at tde, when VCC reaches its inactive state.
6) VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND; I/OUC,
AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 kΩ resistor).
7) The internal oscillator returns to its lower frequency.
VCC generator
The VCC generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at 3 V.
An internal overload detector operates at approximately 120 mA. Current samples to the detector
are internally filtered, allowing spurious current pulses up to 200 mA with a duration in the order of
ms to be drawn by the card without causing deactivation. The average current must stay below the
specified maximum current value.
For reasons of VCC voltage accuracy, a 100nF capacitor with an ESR < 100mΩ should be tied to
CGND near to pin VCC, and a 100 or 220nF capacitor (220nF is the best choice) with the same
ESR should be tied to CGND near card reader contact C1.
Fault detection
The following fault conditions are monitored:
 Short-circuit or high current on VCC
 Removal of a card during a transaction
 VDD dropping
 DC/DC converter operating out of the specified values (VDDP too low or current from VUP too
high)
 Overheating.
There are two different cases (see Figure 7):
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Figure 7. Behaviour of OFF , CMDVCC ,PRES and Vcc
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CMDVCC HIGH outside a card session. Output OFF is LOW if a card is not in the card
reader, and HIGH if a card is in the reader. A voltage drop on the VDD supply is detected by
the supply supervisor, this generates an internal Power-on reset pulse but does not act upon
OFF . No short-circuit or overheating is detected because the card is not powered-up.
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CMDVCC LOW within a card session. Output OFF goes LOW when a fault condition is
detected. As soon as this occurs, an emergency deactivation is performed automatically (see
Figure 8). When the system controller resets CMDVCC to HIGH it may sense the OFF
level again after completing the deactivation sequence. This distinguishes between a
hardware problem or a card extraction ( OFF goes HIGH again if a card is present).
Figure 8. Emergency deactivation sequence(card extraction)
Depending on the type of card-present switch within the connector (normally-closed or
normally-open) and on the mechanical characteristics of the switch, bouncing may occur on the
PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms typical duration (see Figure 7). When a
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card is inserted, output OFF goes HIGH only at the end of the debounce time.
When the card is extracted, an automatic deactivation sequence of the card is performed on the
first true/false transition on PRES or PRES and output OFF goes LOW.
Absolute Maximum Ratings
Notes
1. All card contacts are protected against any short-circuit with any other card contact.
2. Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2
for the remaining. Method 3015 (HBM; 1500Ω and 100 pF) 3 pulses positive and 3 pulses negative
on each pin referenced to ground
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CHARACTERISTICS
VDD = 3.3 V; VDDP = 5 V; Tamb = 25℃; fXTAL = 10 MHz; all currents flowing into the IC are positive;
see note 1; unless otherwise specified.
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Notes
1. All parameters remain within limits but are tested only statistically for the temperature range.
When a parameter is specified as a function of VDD or VCC it means their actual value at the
moment of measurement.
2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18
to ground.
3. To meet these specifications, pin VCC should be decoupled to CGND using two ceramic
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multilayer capacitors of low ESR both with values of 100 nF, or one 100 nF and one 220 nF (see
Figure 10).
4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330 nF.
5. Transition time and duty factor definitions are shown in Fig.12; δ=t1/(t1+t2)
Figure 9. Definition of output and input transition times
6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2
functions see Table 1.
7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25 μA current
source to GND (PRES to VDD); the card is considered present if at least one of the inputs PRES
or PRES is active.
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Application Circuits
Fig.10 Application diagram
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Package Dimension
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