INTEGRATED CIRCUITS DATA SHEET TDA8024 IC card interface Product specification Supersedes data of 2003 Aug 19 2004 July 12 Philips Semiconductors Product specification IC card interface TDA8024 CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.2.1 Power supply Voltage supervisor Without external divider on pin PORADJ (or with TDA8024AT) With an external divider on pin PORADJ (not for the TDA8024AT) Application examples Clock circuitry I/O transceivers Inactive mode Activation sequence Active mode Deactivation sequence VCC generator Fault detection 8.2.2 8.2.3 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 2004 July 12 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINES 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 15.2 15.3 15.4 15.5 2 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS Philips Semiconductors Product specification IC card interface 1 TDA8024 2 FEATURES APPLICATIONS • IC card interface • IC card readers for banking • 3 or 5 V supply for the IC (VDD and GND) • Electronic payment • Three specifically protected half-duplex bidirectional buffered I/O lines to card contacts C4, C7 and C8 • Identification • Pay TV. • DC/DC converter for VCC generation separately powered from a 5 V ± 20% supply (VDDP and PGND) 3 • 3 or 5 V ± 5% regulated card supply voltage (VCC) with appropriate decoupling has the following capabilities: GENERAL DESCRIPTION The TDA8024 is a complete and cost-efficient analog interface for asynchronous 3 or 5 V smart cards. It can be placed between the card and the microcontroller to perform all supply, protection and control functions. Very few external components are required. The TDA8024AT is a direct replacement for the TDA8004AT. – ICC < 80 mA at VDDP = 4 to 6.5 V – Handles current spikes of 40 nAs up to 20 MHz – Controls rise and fall times – Filtered overload detection at approximately 120 mA More information can be obtained from the Philips Internet site (http://www.semiconductors.philips.com) and from “Application note AN10141”. • Thermal and short-circuit protection on all card contacts • Automatic activation and deactivation sequences; initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, VDD or VDDP drop-out • Enhanced ESD protection on card side (>6 kV) • 26 MHz integrated crystal oscillator • Clock generation for cards up to 20 MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals) with synchronous frequency changes • Non-inverted control of RST via pin RSTIN • ISO 7816, GSM11.11 and EMV (payment systems) compatibility • Supply supervisor for spike-killing during power-on and power-off and Power-on reset (threshold fixed internally or externally by a resistor bridge); not for TDA8024AT • Built-in debounce on card presence contacts • One multiplexed status signal OFF. 4 ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA8024T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 TDA8024AT SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 TDA8024TT TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 2004 July 12 3 Philips Semiconductors Product specification IC card interface 5 TDA8024 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Power supplies supply voltage VDDP DC/DC converter supply voltage VCC = 5 V; ICC < 80 mA 4.0 5.0 6.5 V VCC = 5 V; ICC < 20 mA 3.0 − 6.5 V supply current VDD = 3.3 V; fXTAL = 10 MHz card inactive − − 1.2 mA card active; fCLK = fXTAL; CL = 30 pF − − 1.5 mA inactive mode − − 0.1 mA active mode; fCLK = fXTAL; CL = 30 pF; ICC = 0 − − 10 mA 4.75 5.0 5.25 V 4.65 5.0 5.25 V card active; ICC < 65 mA DC 2.85 3.0 3.15 V card active; current pulses Ip = 40 nAs 2.76 3.0 3.20 V IDD IDDP DC/DC converter supply current 2.7 − VDD 6.5 V VDDP = 5 V; fXTAL = 10 MHz Card supply VCC card supply voltage (including 5 V card ripple voltage) card active; ICC < 80 mA DC card active; current pulses Ip = 40 nAs 3 V card VCC(ripple)(p-p) ripple voltage on VCC (peak-to-peak value) fripple = 20 kHz to 200 MHz − − 350 mV ICC card supply current VCC = 0 to 5 V − − 80 mA VCC = 0 to 3 V − − 65 mA 50 80 100 µs − − 0.56 W −25 − +85 °C General tde deactivation time Ptot total power dissipation Tamb ambient temperature 2004 July 12 continuous operation; Tamb = −25 to +85 °C 4 Philips Semiconductors Product specification IC card interface 6 TDA8024 BLOCK DIAGRAM 100 nF 100 nF VDD VDDP 6 S1 7 S2 5 SUPPLY 4 PGND DC/DC CONVERTER INTERNAL REFERENCE R1 (1) VDD 21 100 nF Vref PORADJ 18 INTERNAL OSCILLATOR 2.5 MHz VOLTAGE SENSE R2 POWER_ON 100 nF 8 VUP EN1 CLKUP ALARM OFF RSTIN CMDVCC 5V/3V EN2 23 20 PVCC CLKDIV2 17 VCC GENERATOR 19 100 nF 100 nF 14 CGND 3 EN5 SEQUENCER CLKDIV1 VCC HORSEQ 1 RST BUFFER EN4 CLOCK BUFFER 2 16 15 10 CLOCK CIRCUITRY 9 RST CLK PRES PRES CLK XTAL1 XTAL2 AUX1UC EN3 24 25 THERMAL PROTECTION OSCILLATOR I/O TRANSCEIVER 13 28 I/O TRANSCEIVER 12 26 I/O TRANSCEIVER 11 27 AUX1 TDA8024 AUX2UC I/OUC AUX2 I/O 22 GND mdb051 (1) Optional external resistor bridge. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2. Pin 18 is not connected in the TDA8024AT. Fig.1 Block diagram. 2004 July 12 5 Philips Semiconductors Product specification IC card interface 7 TDA8024 PINNING SYMBOL PIN TYPE DESCRIPTION CLKDIV1 1 I CLK frequency selection input 1 CLKDIV2 2 I CLK frequency selection input 2 5V/3V 3 I card supply voltage selection input; VCC = 5 V (HIGH) or VCC = 3 V (LOW) PGND 4 S DC/DC converter power supply ground S2 5 I/O VDDP 6 S S1 7 I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with ESR < 100 mΩ VUP 8 I/O DC/DC converter output decoupling capacitor connection; C = 100 nF with ESR < 100 mW must be connected between VUP and PGND PRES 9 I card presence contact input (active LOW); if PRES or PRES is active, the card is considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated PRES 10 I card presence contact input (active HIGH); if PRES or PRES is active, the card is considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated I/O 11 I/O data line to/from card reader contact C7; integrated 11 kΩ pull-up resistor to VCC AUX2 12 I/O data line to/from card reader contact C8; integrated 11 kΩ pull-up resistor to VCC AUX1 13 I/O CGND 14 S CLK 15 I/O card clock to/from card reader contact C3 RST 16 O card reset output from card reader contact C2 VCC 17 S card supply voltage to card reader contact C1; decoupled to CGND via 2 × 100 nF or 100 + 220 nF capacitors with ESR < 100 mΩ; note 1 PORADJ 18 I Power-on reset threshold adjustment input for changing the reset threshold with an external resistor bridge; doubles the width of the POR pulse when used; this pin is not connected for the TDA8024AT DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with ESR < 100 mΩ DC/DC converter power supply voltage data line to/from card reader contact C4; integrated 11 kΩ pull-up resistor to VCC card signal ground CMDVCC 19 I input from the host to start activation sequence (active LOW) RSTIN 20 I card reset input from the host VDD 21 S supply voltage GND 22 S ground OFF 23 O NMOS interrupt output to the host (active LOW); 20 kΩ integrated pull-up resistor to VDD XTAL1 24 I crystal connection or input for external clock XTAL2 25 O crystal connection (leave open-circuit if external clock source is used) I/OUC 26 I/O host data I/O line; integrated 11 kΩ pull-up resistor to VDD AUX1UC 27 I/O auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD AUX2UC 28 I/O auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD Note 1. The noise margin on VCC will be higher with the 220 nF capacitor. 2004 July 12 6 Philips Semiconductors Product specification IC card interface TDA8024 CLKDIV1 1 28 AUX2UC CLKDIV1 1 28 AUX2UC CLKDIV2 2 27 AUX1UC CLKDIV2 2 27 AUX1UC 5V/3V 3 26 I/OUC 5V/3V 3 26 I/OUC PGND 4 25 XTAL2 PGND 4 25 XTAL2 S2 5 24 XTAL1 S2 5 24 XTAL1 VDDP 6 23 OFF VDDP 6 23 OFF S1 7 22 GND S1 7 VUP 8 VUP 8 PRES 9 20 RSTIN PRES 9 19 CMDVCC PRES 10 TDA8024T PRES 10 21 VDD 18 PORADJ I/O 11 TDA8024TT 22 GND 21 VDD 20 RSTIN 19 CMDVCC 18 PORADJ I/O 11 AUX2 12 17 VCC AUX2 12 17 VCC AUX1 13 16 RST AUX1 13 16 RST CGND 14 15 CLK CGND 14 15 CLK 001aab430 001aab431 Fig.2 Pin configuration TDA8024T. CLKDIV1 1 28 AUX2UC CLKDIV2 2 27 AUX1UC 5V/3V 3 26 I/OUC PGND 4 25 XTAL2 S2 5 24 XTAL1 VDDP 6 23 OFF S1 7 VUP 8 PRES 9 TDA8024AT Fig.3 Pin configuration TDA8024TT. 22 GND 21 VDD 20 RSTIN PRES 10 19 CMDVCC I/O 11 18 n.c. AUX2 12 17 VCC AUX1 13 16 RST CGND 14 15 CLK 001aab382 Fig.4 Pin configuration TDA8024AT. 2004 July 12 7 Philips Semiconductors Product specification IC card interface 8 TDA8024 The DC/DC converter function changes as follows: FUNCTIONAL DESCRIPTION • VCC = 5 V and VDDP > 5.8 V; voltage follower Throughout this document it is assumed that the reader is familiar with ISO7816 terminology. 8.1 • VCC = 5 V and VDDP < 5.7 V; voltage doubler • VCC = 3 V and VDDP > 4.1 V; voltage follower Power supply • VCC = 3 V and VDDP < 4.0 V; voltage doubler. The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals interfacing with the system controller are referred to VDD, therefore VDD should also supply the system controller. All card reader contacts remain inactive during power-on or power-off. Supply voltages VDD and VDDP may be applied to the IC in any sequence. After powering the device, OFF remains LOW until CMDVCC is set HIGH. The internal circuits are maintained in the reset state until VDD reaches Vth2 + Vhys2 and for the duration of the internal Power-on reset pulse, tW (see Fig.5). When VDD falls below Vth2, an automatic deactivation of the contacts is performed. During power off, OFF falls LOW when VDD is below the falling threshold voltage. 8.2 8.2.1 A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The DC/DC converter should be supplied separately by VDDP and PGND. Due to the possibility of large transient currents, the two 100 nF capacitors of the DC/DC converter should be located as near as possible to the IC and have an ESR less than 100 mΩ. Voltage supervisor WITHOUT EXTERNAL DIVIDER ON PIN PORADJ (OR WITH TDA8024AT) The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms (tW) is used internally to keep the IC inactive during power-on or power-off of the VDD supply (see Fig.5). As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the command lines. This state also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys2. The DC/DC converter functions as a voltage doubler or a voltage follower according to the respective values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV). When VDD falls below Vth2, a deactivation sequence of the contacts is performed. handbook, full pagewidth Vth2 + Vhys2 Vth2 VDD ALARM (internal signal) tw tw power-on supply dropout power-off MDB053 Fig.5 Voltage supervisor. 2004 July 12 8 Philips Semiconductors Product specification IC card interface 8.2.2 TDA8024 Transposed, this becomes WITH AN EXTERNAL DIVIDER ON PIN PORADJ (NOT TDA8024AT) FOR THE R1 0.99 R1 1 1 + 0.98 × ------- = 1 + ----------- × -------- < -- 1.01 R2 k R2 If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Fig.1), then the following occurs: 1 1.01 R1 R1 --- < 1 + ----------- × ------- = 1 + 1.02 × ------- k 0.99 R2 R2 • The internal threshold voltage Vth2 is overridden by the external voltage and by the hysteresis, therefore: If V1 = Vth(ext)(rise)(max) and V2 = Vth(ext)(fall)(min) V hys(ext) R1 V th2(ext)(rise) = 1 + ------- × V bridge + ------------------ R2 2 activation will always be possible if VPORADJ > V1 and deactivation will always be done for VPORADJ < V2. V hys(ext) R1 V th2(ext)(fall) = 1 + ------- × V bridge – ------------------ R2 2 V1 Activation is always possible for V DD > ------k where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ. • The reset pulse width tW is doubled to approximately 16 ms. V2 and deactivation is always possible for V DD < ------- . k Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed when the voltage on pin PORADJ exceeds 1 V. This ensures that after detection of the external bridge by the IC during power-on, the input current on pin PORADJ does not cause inaccuracy of the bridge voltage. That is V1 = 1.31 V and V2 = 1.19 V R1 3.135 and ------- < --------------- – 1 × 0.98 = 1.365 R2 1.31 Suppose R1 + R2 = 100 kΩ, then 100 kΩ R2 = ------------------- = 42.3 kΩ and R1 = 57.7 kΩ. 2.365 The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage may be up to VDD. 8.2.3 Deactivation will be effective at V2 × (1 + 1.02 × 1.365) = 2.847 V in any case. APPLICATION EXAMPLES If the microcontroller continues to function down to 2.80 V, the slew rate on VDD should be less than 2 V/ms to ensure that clock CLK is correctly delivered to the card until time t12 (see Fig.9). The voltage supervisor is used as Power-on reset and as supply dropout detection during a card session. Supply dropout detection is to ensure that a proper deactivation sequence is followed before the voltage is too low. 8.2.3.2 For a microcontroller supplied by a 3.3 V with a ±1% regulator and with resistors R1, R2 having a ±0.1% tolerance, the minimum supply voltage is 3.267 V. For the internal voltage supervisor to function, the system microcontroller should operate down to 2.35 V to ensure a proper deactivation sequence. If this is not possible, external resistor values can be chosen to overcome the problem. 8.2.3.1 The same calculations as in Section 8.2.3.1 conclude: R1 3.267 ------- < --------------- – 1 × 0.998 = 1.491 R2 1.310 Microcontroller requiring a 3.3 V ±20% supply For a microcontroller supplied by 3.3 V with a ±5% regulator and with resistors R1, R2 having a ±1% tolerance, the minimum supply voltage is 3.135 V. 100 kΩ Therefore R2 = ------------------- = 40.14 kΩ and R1 = 59.86 kΩ. 2.49 Deactivation will be effective at V2 × (1 + 1.002 × 1.491) = 2.967 V in any case. S1 VPORADJ = k × VDD, where k = --------------------- with S1 and S2 S1 + S2 the actual values of nominal resistors R1 and R2. If the microcontroller continues to function down to 2.97 V, the slew rate on VDD should be less than 0.20 V/ms to ensure that clock CLK is correctly delivered to the card until time t12 (see Fig.9). This can be shown as 0.99 × R1 < S1 < 1.01 × R1 and 0.99 × R2 < S2 < 1.01 × R2 2004 July 12 Microcontroller requiring a 3.3 V ±10% supply 9 Philips Semiconductors Product specification IC card interface 8.3 TDA8024 The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used, or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as shown in the activation sequences shown in Figs 7 and 8. Clock circuitry The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2. The clock frequency can be fXTAL, 1/2 × fXTAL, 1/4 × fXTAL or 1/8 × fXTAL. Frequency selection is made via inputs CLKDIV1 and CLKDIV2 (see Table 1). Table 1 If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will be applied to the card when it is sent by the system microcontroller (after completion of the activation sequence). Clock frequency selection; note 1 CLKDIV1 CLKDIV2 fCLK 0 0 f XTAL ------------8 0 1 f XTAL ------------4 1 1 f XTAL ------------2 1 0 fXTAL 8.4 The three data lines I/O, AUX1 and AUX2 are identical. The idle state is realized by both I/O and I/OUC lines being pulled HIGH via a 11 kΩ resistor (I/O to VCC and I/OUC to VDD). Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus allowing operation when VCC is not equal to VDD. The first side of the transceiver to receive a falling edge becomes the master. An anti-latch circuit disables the detection of falling edges on the line of the other side, which then becomes a slave. Note 1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1. After a time delay td(edge), an N transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. When the master side returns to logic 1, a P transistor on the slave side is turned on during the time delay tpu and then both sides return to their idle states. The frequency change is synchronous, which means that during transition no pulse is shorter than 45% of the smallest period, and that the first and last clock pulses about the instant of change have the correct width. This active pull-up feature ensures fast LOW-to-HIGH transitions; as shown in Fig.6, it is able to deliver more than 1 mA at an output voltage of up to 0.9VCC into an 80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the internal pull-up resistor and the load current. When changing the frequency dynamically, the change is effective for only eight periods of XTAL1 after the command. The duty factor of fXTAL depends on the signal present at pin XTAL1. The current to and from the card I/O lines is limited internally to 15 mA and the maximum frequency on these lines is 1 MHz. In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1 should have a duty factor of 48 to 52% and transition times of less than 5% of the input signal period. If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin CLK is guaranteed between 45 and 55% of the clock period. 2004 July 12 I/O transceivers 10 Philips Semiconductors Product specification IC card interface TDA8024 Table 2 FCE661 6 12 Io Vo Card presence indication OFF CMDVCC INDICATION HIGH HIGH card present LOW HIGH card not present (mA) (V) (1) If the card is in the reader (this is the case if PRES or PRES is active), the system microcontroller can start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Fig.6): (2) 4 8 2 4 1. CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0). 2. The voltage doubler is started (between t0 and t1). 0 20 0 40 t (ns) 3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5 × T) where T is 64 times the period of the internal oscillator (approximately 25 µs). 0 60 4. I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (these were pulled LOW until this moment). (1) Current. (2) Voltage. 5. CLK is applied to the C3 contact of the card reader (t4). Fig.6 The clock may be applied to the card using the following sequence: 6. RST is enabled (t5 = t1 + 7T). I/O, AUX1 and AUX2 output voltage and current as functions of time during a LOW-to-HIGH transition. 1. Set RSTIN HIGH. 2. Set CMDVCC LOW. 8.5 3. Reset RSTIN LOW between t3 and t5; CLK will start at this moment. Inactive mode After a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits are active while waiting for the microcontroller to start a session: 4. RST remains LOW until t5, when RST is enabled to be the copy of RSTIN. 5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses before toggling RST. • All card contacts are inactive (approximately 200 Ω to GND) • Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 kΩ pull-up resistor to VDD) If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t5, RSTIN may be set HIGH in order to obtain an Answer To Request (ATR) from the card. • Voltage generators are stopped • XTAL oscillator is running • Voltage supervisor is active Activation should not be performed with RSTIN held permanently HIGH. • The internal oscillator is running at its low frequency. 8.6 Activation sequence After power-on and after the internal pulse width delay, the system microcontroller can check the presence of a card using the signals OFF and CMDVCC as shown in Table 2. 2004 July 12 11 Philips Semiconductors Product specification IC card interface TDA8024 handbook, full pagewidth CMDVCC VUP VCC ATR I/O CLK RSTIN RST I/OUC t0 t2 t4 t5 = tact t3 MDB054 t1 Fig.7 Activation sequence using RSTIN and CMDVCC. handbook, full pagewidth CMDVCC VUP VCC I/O ATR CLK 200 ns RSTIN RST I/OUC t0 t1 t2 t5 = tact t3 t4 MDB055 Fig.8 Activation sequence at t3. 2004 July 12 12 Philips Semiconductors Product specification IC card interface 8.7 TDA8024 Active mode 1. RST goes LOW (t10). 2. CLK is held LOW (t12 = t10 + 0.5 × T) where T is 64 times the period of the internal oscillator (approximately 25 µs). When the activation sequence is completed, the TDA8024 will be in its active mode. Data is exchanged between the card and the microcontroller via the I/O lines. The TDA8024 is designed for cards without VPP (the voltage required to program or erase the internal non-volatile memory). 8.8 3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T). 4. VCC starts to fall towards zero (t14 = t10 + 1.5 × T). 5. The deactivation sequence is complete at tde, when VCC reaches its inactive state. Deactivation sequence 6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 kΩ resistor). When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit then executes an automatic deactivation sequence by counting the sequencer back and finishing in the inactive mode (see Fig.9): 7. The internal oscillator returns to its lower frequency. handbook, full pagewidth CMDVCC RST CLK I/O VCC VUP t10 t12 t13 tde t14 MDB056 t15 Fig.9 Deactivation sequence. 2004 July 12 13 Philips Semiconductors Product specification IC card interface 8.9 TDA8024 VCC generator There are two different cases (see Fig.10): • CMDVCC HIGH outside a card session. Output OFF is LOW if a card is not in the card reader, and HIGH if a card is in the reader. A voltage drop on the VDD supply is detected by the supply supervisor, this generates an internal Power-on reset pulse but does not act upon OFF. No short-circuit or overheating is detected because the card is not powered-up. The VCC generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at 3 V. An internal overload detector operates at approximately 120 mA. Current samples to the detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration in the order of µs to be drawn by the card without causing deactivation. The average current must stay below the specified maximum current value. • CMDVCC LOW within a card session. Output OFF goes LOW when a fault condition is detected. As soon as this occurs, an emergency deactivation is performed automatically (see Fig.11). When the system controller resets CMDVCC to HIGH it may sense the OFF level again after completing the deactivation sequence. This distinguishes between a hardware problem or a card extraction (OFF goes HIGH again if a card is present). For reasons of VCC voltage accuracy, a 100 nF capacitor with an ESR < 100 mΩ should be tied to CGND near to pin VCC, and a 100 or 220 nF capacitor (220 nF is the best choice) with the same ESR should be tied to CGND near card reader contact C1. 8.10 Fault detection Depending on the type of card-present switch within the connector (normally-closed or normally-open) and on the mechanical characteristics of the switch, bouncing may occur on the PRES signals at card insertion or withdrawal. The following fault conditions are monitored: • Short-circuit or high current on VCC • Removal of a card during a transaction There is a debounce feature in the device with an 8 ms typical duration (see Fig.10). When a card is inserted, output OFF goes HIGH only at the end of the debounce time. • VDD dropping • DC/DC converter operating out of the specified values (VDDP too low or current from VUP too high) • Overheating. handbook, full pagewidth When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on PRES or PRES and output OFF goes LOW. PRES OFF CMDVCC debounce debounce VCC deactivation caused by cards withdrawal deactivation caused by short-circuit See “Application note AN10141” for software decision algorithm on OFF signal. Fig.10 Behaviour of OFF, CMDVCC, PRES and VCC. 2004 July 12 14 MDB059 Philips Semiconductors Product specification IC card interface TDA8024 handbook, full pagewidth OFF PREST RST CLK I/O VCC VUP t12 t10 t13 t14 MDB057 tde t15 Fig.11 Emergency deactivation sequence (card extraction). 2004 July 12 15 Philips Semiconductors Product specification IC card interface 9 TDA8024 LIMITING VALUES SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage −0.3 +6.5 V VDDP DC/DC converter supply voltage −0.3 +6.5 V VI, VO voltage on input and output pins pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX1UC, AUX2UC, I/OUC, CLKDIV1, CLKDIV2, CMDVCC, OFF and PORADJ −0.3 +6.5 V Vcard voltage on card pins pins PRES, PRES, I/O, RST, AUX1, AUX2 and CLK −0.3 +6.5 V Vn voltage on other pins pins VUP, S1 and S2 −0.3 +6.5 V Tj(max) maximum junction temperature − 150 °C Tstg storage temperature −55 +150 °C Vesd electrostatic discharge voltage −6 +6 kV human body model; notes 2 and 3 −2 +2 kV machine model; note 4 −200 +200 V card contacts in typical application; notes 1 and 2 pins I/O, RST, VCC, AUX1, AUX2, CLK, PRES and PRES all pins; note 1 Notes 1. All card contacts are protected against any short-circuit with any other card contact. 2. Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM; 1500 Ω and 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground. 3. In accordance with EIA/JESD22-A114-B, June 2000. 4. In accordance with EIA/JESD22-A115-A, October 1997. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ). 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS VALUE UNIT in free air TDA8024T 70 K/W TDA8024AT 70 K/W TDA8024TT 100(1) K/W Note 1. This figure was obtained using the following PCB technology: FR, 4 layers, 0.5 mm thickness, class 5, copper thickness 35 µm, Ni/Go plating, ground plane in internal layers 2004 July 12 16 Philips Semiconductors Product specification IC card interface TDA8024 12 CHARACTERISTICS VDD = 3.3 V; VDDP = 5 V; Tamb = 25 °C; fXTAL = 10 MHz; all currents flowing into the IC are positive; see note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT Temperature ambient temperature −25 − +85 °C VDD supply voltage 2.7 − 6.5 V VDDP DC/DC converter supply voltage 4.0 5.0 6.5 V VCC = 5 V; ICC < 20 mA 3.0 − 6.5 V IDD supply current card inactive − − 1.2 mA card active; fCLK = fXTAL; CL = 30 pF − − 1.5 mA Tamb Supplies IDDP DC/DC converter supply current VCC = 5 V; ICC < 80 mA inactive mode − − 0.1 mA active mode; fCLK = fXTAL; CL = 30 pF; ICC = 0 − − 10 mA VCC = 5 V; ICC = 80 mA − − 200 mA VCC = 3 V; ICC = 65 mA − − 100 mA Vth2 falling threshold voltage on no external resistors at VDD pin PORADJ; VDD level falling 2.35 2.45 2.55 V Vhys2 hysteresis of threshold voltage Vth2 no external resistors at pin PORADJ 50 100 150 mV Pin PORADJ; note 2 Vth(ext)(rise) external rising threshold voltage on VDD external resistor bridge at pin PORADJ; VDD level rising 1.240 1.28 1.310 V Vth(ext)(fall) external falling threshold voltage on VDD external resistor bridge at pin PORADJ; VDD level falling 1.190 1.22 1.26 V Vhys(ext) hysteresis of threshold voltage Vth(ext) external resistor bridge at pin PORADJ 30 60 90 mV ∆Vhys(ext) hysteresis of threshold voltage Vth(ext) variation with temperature external resistor bridge at pin PORADJ − − 0.25 mV/K tw width of internal Power-on reset pulse no external resistors at pin PORADJ 4 8 12 ms external resistor bridge at pin PORADJ 8 16 24 ms −0.1 4 10 µA IL(PORADJ) leakage current on pin PORADJ VPORADJ < 0.5 V VPORADJ > 1 V −1 − +1 µA Ptot total power dissipation continuous operation; Tamb = −25 to +85 °C − − 0.56 W 2004 July 12 17 Philips Semiconductors Product specification IC card interface SYMBOL TDA8024 PARAMETER CONDITIONS MIN. TYP MAX. UNIT DC/DC converter fCLK clock frequency card active 2.2 − 3.2 MHz Vth(vd-vf) threshold voltage for voltage doubler to change to voltage follower 5 V card 5.2 5.8 6.2 V 3 V card 3.8 4.1 4.4 V output voltage on pin VUP (average value) VCC = 5 V 5.2 5.7 6.2 V VCC = 3 V; VDDP = 3.3 V 3.5 3.9 4.3 V 80 − 400 nF card inactive; ICC = 0 mA −0.1 0 +0.1 V card inactive; ICC = 1 mA −0.1 0 +0.3 V VUP(av) Card supply voltage (pin VCC); note 3 CVCC external capacitance on pin VCC note 4 VCC card supply voltage (including ripple voltage) 5 V card card active; ICC < 80 mA 4.75 5.0 5.25 V card active; single current pulse, Ip = −100 mA, tp = 2 ms 4.65 5.0 5.25 V card active; current pulses, Ip = 40 nAs 4.65 5.0 5.25 V card active; current pulses, Ip = 40 nAs with ICC < 200 mA, tp < 400 ns 4.65 5.0 5.25 V card inactive; ICC = 0 mA −0.1 0 +0.1 V card inactive; ICC = 1 mA −0.1 0 +0.3 V card active; ICC < 65 mA 2.85 3.0 3.15 V card active; single current pulse Ip = −100 mA; tp = 2 ms 2.76 3.0 3.20 V card active; current pulses, Ip = 40 nAs 2.76 3.0 3.20 V card active; current pulses, Ip = 40 nAs with ICC < 200 mA, tp < 400 ns 2.76 3.0 3.20 V 3 V card VCC(ripple)(p-p) ripple voltage on VCC (peak to peak value) fripple = 20 kHz to 200 MHz − − 350 mV ICC VCC = 0 to 5 V − − 80 mA VCC = 0 to 3 V − − 65 mA SR 2004 July 12 card supply current slew rate VCC short-circuit to GND 100 120 150 mA slew up or down 0.08 0.15 0.22 V/µs 18 Philips Semiconductors Product specification IC card interface SYMBOL TDA8024 PARAMETER CONDITIONS MIN. TYP MAX. UNIT Crystal oscillator (pins XTAL1 and XTAL2) − − 15 pF crystal frequency 2 − 26 MHz fXTAL1 frequency applied on pin XTAL1 0 − 26 MHz VIL LOW-level input voltage on pin XTAL1 −0.3 − +0.3VDD V VIH HIGH-level input voltage on pin XTAL1 0.7VDD − VDD + 0.3 V CXTAL1, CXTAL2 external capacitance on pins XTAL1 and XTAL2 fXTAL depends on type of crystal or resonator used Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC) td(I/O-I/OUC), td(I/OUC-I/O) I/O to I/OUC, I/OUC to I/O falling edge delay − − 200 ns tpu active pull-up pulse width − − 100 ns fI/O(max) maximum frequency on data lines − − 1 MHz Ci input capacitance on data lines − − 10 pF Data lines to card reader (pins I/O, AUX1 and AUX2; with integrated 11 kΩ pull-up resistors to VCC) Vo(inactive) output voltage inactive mode no load 0 − 0.1 V Io(inactive) = 1 mA − − 0.3 V Io(inactive) output current inactive mode; pin grounded − − −1 mA VOL LOW-level output voltage IOL = 1 mA 0 − 0.3 V IOL ≥ 15 mA VCC − 0.4 − VCC V VOH HIGH-level output voltage no DC load 0.9VCC − VCC + 0.1 V 5 and 3 V cards; IOH < −40 µA 0.75VCC − VCC + 0.1 V IOH ≥ 10 mA 0 − 0.4 V V VIL LOW-level input voltage 0.3 − 0.8 VIH HIGH-level input voltage 1.5 − VCC + 0.3 V IIL LOW-level input current VIL = 0 V − − 600 µA ILIH HIGH-level input leakage current VIH = VCC − − 10 µA tt(DI) data input transition time VIL(max) to VIH(min) − − 1.2 µs tt(DO) data output transition time Vo = 0 to VCC; CL ≤ 80 pF; 10% to 90% − − 0.1 µs Rpu integrated pull-up resistor pull-up resistor to VCC 9 11 13 kΩ Ipu current when pull-up active VOH = 0.9VCC; C = 80 pF −1 − − mA 2004 July 12 19 Philips Semiconductors Product specification IC card interface SYMBOL PARAMETER TDA8024 CONDITIONS MIN. TYP MAX. UNIT Data lines to microcontroller (pins I/OUC, AUX1UC and AUX2UC; with integrated 11 kΩ pull-up resistors to VDD) VOL LOW-level output voltage IOL = 1 mA 0 − 0.3 VOH HIGH-level output voltage no DC load 0.9VDD − VDD + 0.1 V 5 and 3 V cards; IOH < −40 µA 0.75VDD − VDD + 0.1 V V VIL LOW-level input voltage −0.3 − +0.3VDD VIH HIGH-level input voltage 0.7VDD − VDD + 0.3 V ILIH HIGH-level input leakage current VIH = VDD − − 10 µA IL LOW-level input current VIL = 0 V − − 600 µA Rpu integrated pull-up resistor pull-up resistor to VCC 9 11 13 kΩ tt(DI) data input transition time VIL(max) to VIH(min) − − 1.2 µs tt(DO) data output transition time Vo = 0 to VDD; CL < 30 pF; 10% to 90% − − 0.1 µs Ipu current when pull-up active VOH = 0.9VDD; C = 30 pF −1 − − mA inactive mode 55 140 200 kHz active mode 2.2 2.7 3.2 MHz no load 0 − 0.1 V Io(inactive) = 1 mA 0 − 0.3 V V Internal oscillator fOSC(int) frequency of internal oscillator Reset output to card reader (pin RST) Vo(inactive) output voltage inactive mode Io(inactive) output current inactive mode; pin grounded 0 − −1 mA td(RSTIN-RST) RSTIN to RST delay RST enabled − − 2 µs VOL LOW-level output voltage IOL = 200 µA 0 − 0.2 V VOH HIGH-level output voltage IOL = 20 mA (current limit) VCC − 0.4 − VCC V IOH = −200 µA 0.9VCC − VCC V IOH = −20 mA (current limit) 0 − 0.4 V tr rise time CL = 100 pF; VCC = 5 or 3 V − − 0.1 µs tf fall time CL = 100 pF; VCC = 5 or 3 V − − 0.1 µs no load 0 − 0.1 V Io(inactive) = 1 mA 0 − 0.3 V Clock output to card reader (pin CLK) Vo(inactive) output voltage inactive mode Io(inactive) output current CLK inactive; pin grounded 0 − −1 mA VOL LOW-level output voltage IOL = 200 µA 0 − 0.3 V IOL = 70 mA (current limit) VCC − 0.4 − VCC V VOH tr 2004 July 12 HIGH-level output voltage rise time IOH = −200 µA 0.9VCC − VCC V IOH = −70 mA (current limit) 0 − 0.4 V CL = 30 pF; note 5 − − 16 ns 20 Philips Semiconductors Product specification IC card interface SYMBOL PARAMETER TDA8024 CONDITIONS MIN. TYP MAX. UNIT tf fall time CL = 30 pF; note 5 − − 16 ns δ duty factor (except for fXTAL) CL = 30 pF; note 5 45 − 55 % SR slew rate slew up or down; CL = 30 pF 0.2 − − V/ns V Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6 VIL LOW-level input voltage −0.3 − +0.3VDD VIH HIGH-level input voltage 0.7VDD − VDD + 0.3 V ILIL LOW-level input leakage current 0 < VIL < VDD − − 1 µA ILIH HIGH-level input leakage current 0 < VIH < VDD − − 1 µA V Card presence inputs (pins PRES and PRES); note 7 VIL LOW-level input voltage −0.3 − +0.3VDD VIH HIGH-level input voltage 0.7VDD − VDD + 0.3 V ILIL LOW-level input leakage current 0 < VIL < VDD − − 5 µA ILIH HIGH-level input leakage current 0 < VIH < VDD − − 5 µA 0.3 V Interrupt output (pin OFF; NMOS drain with integrated 20 kΩ pull-up resistor to VDD) 0 − VOL LOW-level output voltage IOL = 2 mA VOH HIGH-level output voltage IOH = −15 µA 0.75VDD − − V Rpu integrated pull-up resistor 20 kΩ pull-up resistor to VDD 16 20 24 kΩ Protection and limitation ICC(sd) shutdown and limitation current pin VCC − 130 150 mA II/O(lim) limitation current pins I/O, AUX1 and AUX2 −15 − +15 mA ICLK(lim) limitation current pin CLK −70 − +70 mA IRST(lim) limitation current pin RST −20 − +20 mA Tsd shut-down temperature − 150 − °C Timing tact activation time see Fig.7 50 − 220 µs tde deactivation time see Fig.8 50 80 100 µs t3 start of the window for sending CLK to the card see Fig.7 50 − 130 µs t5 end of the window for sending CLK to the card see Fig.7 140 − 220 µs tdebounce debounce time pins PRES and PRES see Fig.10 5 8 11 ms 2004 July 12 21 Philips Semiconductors Product specification IC card interface TDA8024 Notes 1. All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is specified as a function of VDD or VCC it means their actual value at the moment of measurement. 2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to ground. Pin 18 is not connected in the TDA8024AT 3. To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR both with values of 100 nF, or one 100 nF and one 220 nF (see Fig.13). 4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330 nF. t1 5. Transition time and duty factor definitions are shown in Fig.12; δ = -------------t1 + t2 6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 1. 7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25 µA current source to GND (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active. handbook, full pagewidth tr tf 90% 90% VOH VOH + VOL 2 10% 10% VOL t1 t2 MDB058 Fig.12 Definition of output and input transition times. • Track C3 should be placed as far as possible from the other tracks 13 APPLICATION INFORMATION Performance can be affected by the layout of the application. For example, an additional cross-capacitance of 1 pF between card reader contacts C2 and C3 or C2 and C7 can cause contact C2 to be polluted with high frequency noise from C3 (or C7). In this case, include a 100 pF capacitor between contacts C2 and CGND. • The track connecting CGND to C5 should be straight (the two capacitors on C1 should be connected to this ground track) • Avoid ground loops between CGND, PGND and GND • Decouple VDDP and VDD separately; if the two supplies are the same in the application, then they should be connected in star on the main track. Application recommendations: • Ensure there is ample ground area around the TDA8024 and the connector; place the TDA8024 very near to the connector; decouple the VDD and VDDP lines (these lines are best positioned under the connector) With all these layout precautions, noise should be kept to an acceptable level and jitter on C3 should be less than 100 ps. • The TDA8024 and the microcontroller must use the same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN, PRES, PRES, AUX1UC, I/OUC, AUX2UC, 5V/3V, CMDVCC, and OFF are referred to VDD; if pin XTAL1 is to be driven by an external clock, also refer this pin to VDD 2004 July 12 Reference layouts are provided in “Application note 10141”, available on request. 22 Philips Semiconductors Product specification IC card interface TDA8024 handbook, full pagewidth CLKDIV1 100 nF 10 µF CLKDIV2 5V/3V +5 V PGND 100 nF(1) 100 nF(1) +3.3 V 100 kΩ 1 28 2 27 3 26 4 25 S2 5 VDDP 6 S1 7 VUP TDA8024 8 PRES 9 PRES 10 I/O 11 AUX2 12 AUX1 13 CGND 14 24 AUX2UC AUX1UC I/OUC XTAL2 XTAL1 23 OFF GND 22 VDD 21 RSTIN 20 CMDVCC 19 PORADJ 18 VCC 17 RST 16 CLK 15 33 pF 3.3 V POWERED MICROCONTROLLER 100 nF +3.3 V(2) +3.3 V VDD (3) 58.1 kΩ 100 nF(4) (7) CARD READ (normally closed type) 220 nF(5) C5 C6 C7 C8 C1 C2 C3 C4 41.9 kΩ (6) K1 K2 MDB050 (1) (2) (3) (4) (5) (6) (7) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm). TDA8024 and the microcontroller must use the same VDD supply. Make short, straight connections between CGND, C5 and the ground connection to the capacitor. Mount one low ESR-type 100 nF capacitor close to pin VCC. Mount one low ESR-type 100 or 220 nF capacitor close to C1 contact (less than 100 mm from it). The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks. Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2. Pin 18 is not connected in the TDA8024AT. Fig.13 Application diagram. 2004 July 12 23 Philips Semiconductors Product specification IC card interface TDA8024 14 PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013 2004 July 12 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 24 Philips Semiconductors Product specification IC card interface TDA8024 TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm D SOT361-1 E A X c HE y v M A Z 15 28 Q A2 (A 3) A1 pin 1 index A θ Lp 1 L 14 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.8 0.5 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 2004 July 12 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 25 o Philips Semiconductors Product specification IC card interface TDA8024 To overcome these problems the double-wave soldering method was specifically developed. 15 SOLDERING 15.1 Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON-T and SSOP-T packages 15.4 – for packages with a thickness ≥ 2.5 mm Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2004 July 12 Manual soldering 26 Philips Semiconductors Product specification IC card interface 15.5 TDA8024 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2004 July 12 27 Philips Semiconductors Product specification IC card interface TDA8024 16 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS 18 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 July 12 28 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R63/03/pp29 Date of release: 2004 July 12 Document order number: 9397 750 13195