TDA8024
Standard smart card interface
Rev. 4.0 — 3 June 2016
Product data sheet
1. General description
The TDA8024 is a complete and cost-efficient analog interface for asynchronous 3 V or
5 V smart cards. It can be placed between the card and the microcontroller to perform all
supply, protection and control functions. Very few external components are required. The
TDA8024AT is a direct replacement for the TDA8004AT.
More information can be obtained from the NXP internet site (www.nxp.com) and from
“Application note AN10141”.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
2. Features and benefits
IC card interface
3 V or 5 V supply for the IC (VDD and GND)
Three specifically protected half-duplex bidirectional buffered I/O lines to card contacts
C4, C7 and C8
DC-to-DC converter for VCC generation separately powered from a 5 V 20% supply
(VDDP and PGND)
3 V or 5 V 5% regulated card supply voltage (VCC) with appropriate decoupling has
the following capabilities:
ICC < 80 mA at VDDP = 4 V to 6.5 V
Handles current spikes of 40 nAs up to 20 MHz
Controls rise and fall times
Filtered overload detection at approximately 120 mA
Thermal and short-circuit protection on all card contacts
Automatic activation and deactivation sequences; initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, VDD or VDDP drop-out
Enhanced ESD protection on card side (>6 kV)
26 MHz integrated crystal oscillator
Clock generation for cards up to 20 MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and
CLKDIV2 signals) with synchronous frequency changes
Non-inverted control of RST via pin RSTIN
ISO 7816, GSM11.11 and EMV (payment systems) compatibility
TDA8024
NXP Semiconductors
Standard smart card interface
Supply supervisor for spike-killing during power-on and power-off and Power-on reset
(threshold fixed internally or externally by a resistor bridge); not for TDA8024AT
Built-in debounce on card presence contacts
One multiplexed status signal OFF
3. Applications
IC card readers for banking
Electronic payment
Identification
Pay TV
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7
-
6.5
V
Power supplies
VDD
supply voltage
VDDP
DC-to-DC converter
supply voltage
VCC = 5 V; ICC < 80 mA
4.0
5.0
6.5
V
VCC = 5 V; ICC < 20 mA
3.0
-
6.5
V
IDD
supply current
VDD = 3.3 V; fXTAL = 10 MHz
card inactive
-
-
1.2
mA
card active; fCLK = fXTAL;
CL = 30 pF
-
-
1.5
mA
inactive mode
-
-
0.1
mA
active mode; fCLK = fXTAL;
CL = 30 pF; ICC = 0
-
-
10
mA
card active; ICC < 80 mA DC
4.75
5.0
5.25
V
card active; current pulses
Ip = 40 nAs
4.65
5.0
5.25
V
card active; ICC < 65 mA DC
2.85
3.0
3.15
V
card active; current pulses
Ip = 40 nAs
2.76
3.0
3.20
V
IDDP
DC-to-DC converter
supply current
VDDP = 5 V; fXTAL = 10 MHz
Card supply
VCC
card suppy voltage
(including ripple voltage)
5 V card:
3 V card:
VCC(ripple)(p-p)
ripple voltage on VCC
(peak-to-peak value)
fripple = 20 kHz to 200 MHz
-
-
350
mV
ICC
card supply current
VCC = 0 to 5 V
-
-
80
mA
VCC = 0 to 3 V
-
-
65
mA
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
Table 1.
Quick reference data …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
50
80
100
s
-
-
0.56
W
25
-
+85
C
General
tde
deactivation time
Ptot
total power dissipation
Tamb
ambient temperature
continuous operation;
Tamb = 25 to +85 C
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8024T/C1
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
TDA8024AT/C1
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
TDA8024TT/C1
TSSOP28
plastic thin shrink small outline package; 28 leads; body width 4.4 mm,
gold wires
SOT361-1
TDA8024TT/C1/S1 TSSOP28
plastic thin shrink small outline package; 28 leads; body width 4.4 mm,
copper wire
SOT361-1
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
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TDA8024
NXP Semiconductors
Standard smart card interface
6. Block diagram
100 nF
100 nF
VDD
VDDP
6
21
VDD
S1
7
S2
5
SUPPLY
DC/DC CONVERTER
INTERNAL
REFERENCE
R1
(1)
100 nF
Vref
PORADJ 18
INTERNAL OSCILLATOR
2.5 MHz
VOLTAGE SENSE
R2
4 PGND
100 nF
8 VUP
EN1 CLKUP
POWER_ON
ALARM
OFF
RSTIN
CMDVCC
5V/3V
EN2
VCC
PVCC GENERATOR
23
20
19
CLKDIV2
100 nF
100 nF
14 CGND
3
EN5
SEQUENCER
CLKDIV1
17 VCC
HORSEQ
1
RST
BUFFER
EN4
CLOCK
BUFFER
2
16
15
10
CLOCK
CIRCUITRY
9
RST
CLK
PRES
PRES
CLK
XTAL1
XTAL2
AUX1UC
EN3
24
25
THERMAL
PROTECTION
OSCILLATOR
I/O
TRANSCEIVER
13
28
I/O
TRANSCEIVER
12
26
I/O
TRANSCEIVER
11
27
AUX1
TDA8024
AUX2UC
I/OUC
AUX2
I/O
22
GND
aaa-023220
(1) Optional external resistor bridge. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2. Pin 18
is not connected in the TDA8024AT.
Fig 1.
Block diagram
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
NXP Semiconductors
Standard smart card interface
7. Pinning information
7.1 Pinning
CLKDIV1
CLKDIV2
5V/3V
PGND
S2
VDDP
S1
VUP
PRES
1
2
3
4
5
6
7
8
TDA8024T
9
PRES 10
28 AUX2UC
CLKDIV1
1
28 AUX2UC
27 AUX1UC
CLKDIV2
2
27 AUX1UC
26 I/OUC
5V/3V
3
26 I/OUC
25 XTAL2
PGND
4
25 XTAL2
24 XTAL1
S2
5
24 XTAL1
23 OFF
VDDP
6
23 OFF
22 GND
S1
7
VUP
8
20 RSTIN
PRES
9
19 CMDVCC
PRES 10
21 VDD
AUX2 12
AUX1 13
CGND 14
21 VDD
19 CMDVCC
18 PORADJ
17 VCC
AUX2 12
17 VCC
16 RST
AUX1 13
16 RST
15 CLK
CGND 14
15 CLK
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001aab430
Fig 2.
22 GND
20 RSTIN
I/O 11
18 PORADJ
I/O 11
TDA8024TT
Pin configuration TDA8024T
Fig 3.
Pin configuration TDA8024TT
CLKDIV1
1
28 AUX2UC
CLKDIV2
2
27 AUX1UC
5V/3V
3
26 I/OUC
PGND
4
25 XTAL2
S2
5
24 XTAL1
VDDP
6
23 OFF
S1
7
VUP
8
PRES
9
TDA8024AT
22 GND
21 VDD
20 RSTIN
PRES 10
19 CMDVCC
I/O 11
18 n.c.
AUX2 12
17 VCC
AUX1 13
16 RST
CGND 14
15 CLK
001aab382
Fig 4.
Pin configuration TDA8024AT
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
7.2 Pin description
TDA8024
Product data sheet
Table 3.
Pin description
Symbol
Pin
Type
Description
CLKDIV1
1
I
CLK frequency selection input 1
CLKDIV2
2
I
CLK frequency selection input 2
5V/3V
3
I
card supply voltage selection input; VCC = 5 V (HIGH) or
VCC = 3 V (LOW)
PGND
4
S
DC-to-DC converter power supply ground
S2
5
I/O
VDDP
6
S
S1
7
I/O
DC-to-DC converter capacitor; connected between pins S1
and S2; C = 100 nF with ESR < 100 m
VUP
8
I/O
DC-to-DC converter output decoupling capacitor connection;
C = 100 nF with ESR < 100 m must be connected between
VUP and PGND
PRES
9
I
card presence contact input (active LOW); if PRES or
PRES is active, the card is considered ‘present’ and a
built-in debounce feature of 8 ms (typ.) is activated
PRES
10
I
card presence contact input (active HIGH); if PRES or
PRES is active, the card is considered ‘present’ and a
built-in debounce feature of 8 ms (typ.) is activated
I/O
11
I/O
data line to/from card reader contact C7; integrated 11 k
pull-up resistor to VCC
AUX2
12
I/O
data line to/from card reader contact C8; integrated 11 k
pull-up resistor to VCC
AUX1
13
I/O
data line to/from card reader contact C4; integrated 11 k
pull-up resistor to VCC
CGND
14
S
CLK
15
I/O
card clock to/from card reader contact C3
RST
16
O
card reset output from card reader contact C2
VCC
17
S
card supply voltage to card reader contact C1; decoupled to
CGND via 2 100 nF or 100 + 220 nF capacitors with ESR
< 100 m[1]
PORADJ
18
I
Power-on reset threshold adjustment input for changing the
reset threshold with an external resistor bridge; doubles the
width of the POR pulse when used; this pin is not connected
for the TDA8024AT
CMDVCC
19
I
input from the host to start activation sequence (active LOW)
RSTIN
20
I
card reset input from the host
VDD
21
S
supply voltage
GND
22
S
ground
OFF
23
O
NMOS interrupt output to the host (active LOW); 20 k
integrated pull-up resistor to VDD
XTAL1
24
I
crystal connection or input for external clock
DC-to-DC converter capacitor; connected between pins S1
and S2; C = 100 nF with ESR < 100 m
DC-to-DC converter power supply voltage
card signal ground
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
NXP Semiconductors
Standard smart card interface
Table 3.
Symbol
Pin description …continued
Pin
Type
Description
XTAL2
25
O
crystal connection (leave open-circuit if external clock
source is used)
I/OUC
26
I/O
host data I/O line; integrated 11 k pull-up resistor to VDD
AUX1UC
27
I/O
AUX2UC
28
I/O
auxiliary data line to/from the host; integrated 11 k pull-up
resistor to VDD
[1]
The noise margin on VCC will be higher with the 220 nF capacitor.
8. Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
8.1 Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 V to 6.5 V.
All signals interfacing with the system controller are referred to VDD, therefore VDD should
also supply the system controller. All card reader contacts remain inactive during
power-on or power-off.
The internal circuits are maintained in the reset state until VDD reaches Vth2 + Vhys2 and for
the duration of the internal Power-on reset pulse, tW (see Figure 5). When VDD falls below
Vth2, an automatic deactivation of the contacts is performed.
A DC-to-DC converter is incorporated to generate the 5 V or 3 V card supply voltage
(VCC). The DC-to-DC converter should be supplied separately by VDDP and PGND. Due to
the possibility of large transient currents, the two 100 nF capacitors of the DC-to-DC
converter should be located as near as possible to the IC and have an ESR less than
100 m.
The DC-to-DC converter functions as a voltage doubler or a voltage follower according to
the respective values of VCC and VDDP (both have thresholds with a hysteresis of
100 mV).
The DC-to-DC converter function changes as follows.
•
•
•
•
VCC = 5 V and VDDP > 5.8 V; voltage follower
VCC = 5 V and VDDP < 5.7 V; voltage doubler
VCC = 3 V and VDDP > 4.1 V; voltage follower
VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Supply voltages VDD and VDDP may be applied to the IC in any sequence.
After powering the device, OFF remains LOW until CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the falling threshold voltage.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
NXP Semiconductors
Standard smart card interface
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJ (or with TDA8024AT)
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately
8 ms (tW) is used internally to keep the IC inactive during power-on or power-off of the VDD
supply (see Figure 5).
As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the
command lines. This state also lasts for the duration of tW after VDD has reached a level
higher than Vth2 + Vhys2.
When VDD falls below Vth2, a deactivation sequence of the contacts is performed.
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Voltage supervisor
8.2.2 With an external divider on pin PORADJ (not for the TDA8024AT)
If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure 1), then
the following occurs:
• The internal threshold voltage Vth2 is overridden by the external voltage and by the
hysteresis, therefore:
V hys ext
R1
V th2 ext rise = 1 + ------- V bridge + --------------------
2
R2
V hys ext
R1
V th2 ext fall = 1 + ------- V bridge – --------------------
2
R2
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
• The reset pulse width tW is doubled to approximately 16 ms.
Input PORADJ is biased internally with a pull-down current source of 4 A which is
removed when the voltage on pin PORADJ exceeds 1 V. This ensures that after detection
of the external bridge by the IC during power-on, the input current on pin PORADJ does
not cause inaccuracy of the bridge voltage.
The minimum threshold voltage should be higher than 2 V.
The maximum threshold voltage may be up to VDD.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
NXP Semiconductors
Standard smart card interface
8.2.3 Applications examples
The voltage supervisor is used as Power-on reset and as supply dropout detection during
a card session.
Supply dropout detection is to ensure that a proper deactivation sequence is followed
before the voltage is too low.
For the internal voltage supervisor to function, the system microcontroller should operate
down to 2.35 V to ensure a proper deactivation sequence. If this is not possible, external
resistor values can be chosen to overcome the problem.
8.2.3.1
Microcontroller requiring a 3.3 V 20 % supply
For a microcontroller supplied by 3.3 V with a 5% regulator and with resistors R1, R2
having a 1% tolerance, the minimum supply voltage is 3.135 V.
S1
VPORADJ = k VDD, where k = ------------------- with S1 and S2 the actual values of nominal resistors
S1 + S2
R1 and R2.
This can be shown as:
0.99 R1 < S1 < 1.01 R1 and
0.99 R2 < S2 < 1.01 R2
Transposed, this becomes
R1
0.99
R1 1
1 + 0.98 ------- = 1 + ---------- ------- --
1.01 R2 k
R2
1
1.01
R1
R1
--- 1 + ---------- ------- = 1 + 1.02 -------
0.99 R2
k
R2
If V1 = Vth(ext)(rise)(max) and V2 = Vth(ext)(fall)(min) activation will always be possible if VPORADJ
> V1 and deactivation will always be done for VPORADJ < V2.
V1
V2
Activation is always possible for V DD ------- and deactivation is always possible for V DD ------k
k
That is V1 = 1.31 V and V2 = 1.19 V and ------- ------------- – 1 0.98 = 1.365
R1
R2
3.135
1.31
100 k - = 42.3 k and R1 = 57.7 k.
Suppose R1 + R2 = 100 k, then R2 = ----------------2.365
Deactivation will be effective at V2 (1 + 1.02 1.365) = 2.847 V in any case.
If the microcontroller continues to function down to 2.80 V, the slew rate on VDD should be
less than 2 V/ms to ensure that clock CLK is correctly delivered to the card until time t12
(see Figure 9).
8.2.3.2
Microcontroller requiring a 3.3 V 10% supply
For a microcontroller supplied by a 3.3 V with a 1% regulator and with resistors R1, R2
having a 0.1% tolerance, the minimum supply voltage is 3.267 V.
The same calculations as in Section 8.2.3.1 conclude:
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
NXP Semiconductors
Standard smart card interface
R1 3.267
------- ------------- – 1 0.998 = 1.491
R2 1.310
100 k - = 40.14 k and R1 = 59.86 k.
Therefor R2 = ----------------2.49
Deactivation will be effective at V2 (1 + 1.002 1.491) = 2.967 V in any case.
If the microcontroller continues to function down to 2.97 V, the slew rate on VDD should be
less than 0.20 V/ms to ensure that clock CLK is correctly delivered to the card until time
t12 (see Figure 9).
8.3 Clock circuitry
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a
crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL, 1⁄2 fXTAL, 1⁄4 fXTAL or 1⁄8 fXTAL. Frequency selection
is made via inputs CLKDIV1 and CLKDIV2 (see Table 4).
Table 4.
Clock frequency selection[1]
CLKDIV1
CLKDIV2
0
0
f XTAL
------------8
0
1
f XTAL
------------4
1
1
f XTAL
------------2
1
0
[1]
fCLK
f XTAL
The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is
shorter than 45% of the smallest period, and that the first and last clock pulses about the
instant of change have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of
XTAL1 after the command.
The duty factor of fXTAL depends on the signal present at pin XTAL1.
In order to reach a 45% to 55% duty factor on pin CLK, the input signal on pin XTAL1
should have a duty factor of 48% to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be 45% to 55% depending on the
circuit layout and on the crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed between 45% and 55% of the
clock period.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used,
or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as
shown in the activation sequences shown in Figure 7 and 8.
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse
will be applied to the card when it is sent by the system microcontroller (after completion
of the activation sequence).
8.4 I/O transceivers
The three data lines I/O, AUX1 and AUX2 are identical.
The Idle-state is realized by both I/O and I/OUC lines being pulled HIGH via a 11 k
resistor (I/O to VCC and I/OUC to VDD).
Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus allowing operation when VCC is
not equal to VDD.
The first side of the transceiver to receive a falling edge becomes the master. An anti-latch
circuit disables the detection of falling edges on the line of the other side, which then
becomes a slave.
After a time delay td(edge), an N-transistor on the slave side is turned on, thus transmitting
the logic 0 present on the master side.
When the master side returns to logic 1, a P-transistor on the slave side is turned on
during the time delay tpu and then both sides return to their idle states.
This active pull-up feature ensures fast LOW-to-HIGH transitions; as shown in Figure 6, it
is able to deliver more than 1 mA at an output voltage of up to 0.9VCC into an 80 pF load.
At the end of the active pull-up pulse, the output voltage depends only on the internal
pull-up resistor and the load current.
The current to and from the card I/O lines is limited internally to 15 mA and the maximum
frequency on these lines is 1 MHz.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
aaa-023222
6
Vo
(V)
12
Io
(mA)
(1)
4
8
(2)
2
4
0
0
20
0
60
40
t (ns)
(1) Current
(2) Voltage
Fig 6.
I/O, AUX1 and AUX2 output voltage and current as functions of time during a
LOW-to-HIGH transition.
8.5 Inactive mode
After a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits
are active while waiting for the microcontroller to start a session:
• All card contacts are inactive (approximately 200 to GND)
• Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 k pull-up
resistor to VDD)
•
•
•
•
Voltage generators are stopped
XTAL oscillator is running
Voltage supervisor is active
The internal oscillator is running at its low frequency
8.6 Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can
check the presence of a card using the signals OFF and CMDVCC as shown in Table 5.
Table 5.
Card presence indication
OFF
CMDVCC
Indication
HIGH
HIGH
card present
LOW
HIGH
card not present
If the card is in the reader (this is the case if PRES or PRES is active), the system
microcontroller can start a card session by pulling CMDVCC LOW. The following
sequence then occurs (see Figure 6):
1. CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0).
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
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12 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
2. The voltage doubler is started (between t0 and t1).
3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5 T) where T is 64
times the period of the internal oscillator (approximately 25 s).
4. I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T)
(these were pulled LOW until this moment).
5. CLK is applied to the C3 contact of the card reader (t4).
6. RST is enabled (t5 = t1 + 7T).
The clock may be applied to the card using the following sequence:
1. Set RSTIN HIGH.
2. Set CMDVCC LOW.
3. Reset RSTIN LOW between t3 and t5; CLK will start at this moment.
4. RST remains LOW until t5, when RST is enabled to be the copy of RSTIN.
5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses
before toggling RST.
If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In
this case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t5,
RSTIN may be set HIGH in order to obtain an Answer To Request (ATR) from the card.
Activation should not be performed with RSTIN held permanently HIGH.
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Fig 7.
TDA8024
Product data sheet
DDD
Activation sequence using RSTIN and CMDVCC.
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
&0'9&&
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Fig 8.
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Activation sequence at t3.
8.7 Active mode
When the activation sequence is completed, the TDA8024 will be in its active mode. Data
is exchanged between the card and the microcontroller via the I/O lines. The TDA8024 is
designed for cards without VPP (the voltage required to program or erase the internal
non-volatile memory).
8.8 Deactive sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The
circuit then executes an automatic deactivation sequence by counting the sequencer back
and finishing in the inactive mode (see Figure 9):
1. RST goes LOW (t10).
2. CLK is held LOW (t12 = t10 + 0.5 T) where T is 64 times the period of the internal
oscillator (approximately 25 s).
3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).
4. VCC starts to fall towards zero (t14 = t10 + 1.5 T).
5. The deactivation sequence is complete at tde, when VCC reaches its inactive state.
6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND;
I/OUC, AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 k resistor).
7. The internal oscillator returns to its lower frequency.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
&0'9&&
567
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,2
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Fig 9.
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DDD
Deactivation sequence.
8.9 VCC generator
The VCC generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at
3 V.
An internal overload detector operates at approximately 120 mA. Current samples to the
detector are internally filtered, allowing spurious current pulses up to 200 mA with a
duration in the order of s to be drawn by the card without causing deactivation. The
average current must stay below the specified maximum current value.
For reasons of VCC voltage accuracy, a 100 nF capacitor with an ESR < 100 m should
be tied to CGND near to pin VCC, and a 100 nF or 220 nF capacitor (220 nF is the best
choice) with the same ESR should be tied to CGND near card reader contact C1.
8.10 Fault detection
The following fault conditions are monitored:
•
•
•
•
Short-circuit or high current on VCC
Removal of a card during a transaction
VDD dropping
DC-to-DC converter operating out of the specified values (VDDP too low or current
from VUP too high)
• Overheating
There are two different cases (see Figure 10):
• CMDVCC HIGH outside a card session. Output OFF is LOW if a card is not in the
card reader, and HIGH if a card is in the reader. A voltage drop on the VDD supply is
detected by the supply supervisor, this generates an internal Power-on reset pulse but
does not act upon OFF. No short-circuit or overheating is detected because the card
is not powered-up.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
• CMDVCC LOW within a card session. Output OFF goes LOW when a fault
condition is detected. As soon as this occurs, an emergency deactivation is performed
automatically (see Figure 11). When the system controller resets CMDVCC to HIGH it
may sense the OFF level again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card extraction (OFF goes HIGH
again if a card is present).
Depending on the type of card-present switch within the connector (normally-closed or
normally-open) and on the mechanical characteristics of the switch, bouncing may occur
on the PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms typical duration (see Figure 10).
When a card is inserted, output OFF goes HIGH only at the end of the debounce time.
When the card is extracted, an automatic deactivation sequence of the card is performed
on the first true/false transition on PRES or PRES and output OFF goes LOW.
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Fig 10. Behavior of OFF, CMDVCC, PRES and VCC.
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Fig 11. Emergency deactivation sequence (card extraction)
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
9. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
0.3
+6.5
V
VDDP
DC-to-DC converter supply
voltage
0.3
+6.5
V
VI, VO
voltage on input and output pins XTAL1, XTAL2, 5V/3V, RSTIN,
pins
AUX1UC, AUX2UC, I/OUC, CLKDIV1,
CLKDIV2, CMDVCC, OFF and PORADJ
0.3
+6.5
V
Vcard
voltage on card pins
pins PRES, PRES, I/O, RST, AUX1, AUX2
and CLK
0.3
+6.5
V
Vn
voltage on other pins
pins VUP, S1 and S2
0.3
+6.5
V
Tj(max)
maximum junction
temperature
-
150
C
Tstg
storage temperature
55
+150
C
VESD
electrostatic discharge
voltage
6
+6
kV
2
+2
kV
200
+200
V
card contacts in typical application;[1][2]
pins I/O, RST, VCC, AUX1, AUX2, CLK,
PRES and PRES
all pins;[1]
Human Body Model (HBM)
Machine Model (MM)
[2][3]
[4]
[1]
All card contacts are protected against any short-circuit with any other card contact.
[2]
Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM;
1500 and 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.
[3]
In accordance with EIA/JESD22-A114-B, June 2000.
[4]
In accordance with EIA/JESD22-A115-A, October 1997.
10. Thermal characteristics
Table 7.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction
to ambient
in free air
TDA8024T
TDA8024AT
TDA8024TT
[1]
Typ
Unit
70
K/W
70
K/W
100[1]
K/W
This figure was obtained using the following Printed-Circuit Board (PCB) technology: FR, 4 layers, 0.5 mm thickness, class 5, copper
thickness 35 m, Ni/Go plating, ground plane in internal layers.
TDA8024
Product data sheet
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© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
NXP Semiconductors
Standard smart card interface
11. Characteristics
Table 8.
Characteristics
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 C; fXTAL = 10 MHz; all currents flowing into the IC are positive: see Table note 1; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ambient temperature
25
-
+85
C
VDD
supply voltage
2.7
-
6.5
V
VDDP
DC-to-DC converter
supply voltage
VCC = 5 V; ICC < 80 mA
4.0
5.0
6.5
V
VCC = 5 V; ICC < 20 mA
3.0
-
6.5
V
supply current
card inactive
-
-
1.2
mA
card active; fCLK = fXTAL;
CL = 30 pF
-
-
1.5
mA
-
-
0.1
mA
-
-
10
mA
VCC = 5 V; ICC = 80 mA
-
-
200
mA
VCC = 3 V; ICC = 65 mA
-
-
100
mA
Temperature
Tamb
Supplies
IDD
IDDP
DC-to-DC converter supply inactive mode
current
active mode; fCLK = fXTAL;
CL = 30 pF; ICC = 0
Vth2
falling threshold voltage on no external resistors at pin
VDD
PORADJ; VDD level falling
2.35
2.45
2.55
V
Vhys2
hysteresis of threshold
voltage Vth2
no external resistors at pin
PORADJ
50
100
150
mV
Pin PORADJ[2]
Vth(ext)(rise)
external rising threshold
voltage on VDD
external resistor bridge at pin
PORADJ; VDD level rising
1.240
1.28
1.310
V
Vth(ext)(fall)
external falling threshold
voltage on VDD
external resistor bridge at pin
PORADJ; VDD level falling
1.190
1.22
1.26
V
Vhys(ext)
hysteresis of threshold
voltage Vth(ext)
external resistor bridge at pin
PORADJ
30
60
90
mV
Vhys(ext)
hysteresis of threshold
voltage Vth(ext) variation
with temperature
external resistor bridge at pin
PORADJ
-
-
0.25
mV/K
tw
width of internal Power-on
reset pulse
no external resistors at pin
PORADJ
4
8
12
ms
external resistor bridge at pin
PORADJ
8
16
24
ms
IL(PORADJ)
Ptot
leakage current on pin
PORADJ
total power dissipation
VPORADJ < 0.5 V
0.1
4
10
A
VPORADJ > 1 V
1
-
+1
A
continuous operation;
Tamb = 25 to +85 C
-
-
0.56
W
DC-to-DC converter
fCLK
clock frequency
card active
2.2
-
3.2
MHz
Vth(vd-vf)
threshold voltage for
voltage doubler to change
to voltage follower
5 V card
5.2
5.8
6.2
V
3 V card
3.8
4.1
4.4
V
TDA8024
Product data sheet
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TDA8024
NXP Semiconductors
Standard smart card interface
Table 8.
Characteristics …continued
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 C; fXTAL = 10 MHz; all currents flowing into the IC are positive: see Table note 1; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VUP(av)
output voltage on pin VUP
(average value)
VCC = 5 V
5.2
5.7
6.2
V
VCC = 3 V; VDDP = 3.3 V
3.5
3.9
4.3
V
80
-
400
nF
card inactive; ICC = 0 mA
0.1
0
+0.1
V
card inactive; ICC = 1 mA
0.1
0
+0.3
V
card active; ICC < 80 mA
4.75
5.0
5.25
V
card active; single current
pulse, Ip = 100 mA;
tp = 2 ms
4.65
5.0
5.25
V
card active; current pulses,
Ip = 40 nAs
4.65
5.0
5.25
V
card active; current pulses,
Ip = 40 nAs with ICC <
200 mA; tp < 400 ns
4.65
5.0
5.25
V
card inactive; ICC = 0 mA
0.1
0
+0.1
V
card inactive; ICC = 1 mA
0.1
0
+0.3
V
card active; ICC < 65 mA
2.85
3.0
3.15
V
card active; single current
pulse, Ip = 100 mA;
tp = 2 ms
2.76
3.0
3.20
V
card active; current pulses,
Ip = 40 nAs
2.76
3.0
3.20
V
card active; current pulses,
Ip = 40 nAs with ICC < 200
mA; tp < 400 ns
2.76
3.0
3.20
V
Card supply voltage (pin VCC)[3]
CVCC
external capacitance on
pin VCC
VCC
card supply voltage
(including ripple voltage)
[4]
5 V card
3 V card
VCC(ripple)(p-p) ripple voltage on VCC
(peak to peak value)
fripple = 20 kHz to 200 MHz
-
-
350
mV
ICC
VCC = 0 to 5 V
-
-
80
mA
VCC = 0 to 3 V
-
-
65
mA
SR
card supply current
slew rate
VCC short-circuit to GND
100
120
150
mA
slew up or down
0.08
0.15
0.22
V/s
-
-
15
pF
Crystal oscillator (pins XTAL1 and XTAL2)
CXTAL1,
CXTAL2
external capacitance on
pins XTAL1 and XTAL2
fXTAL
crystal frequency
2
-
26
MHz
fXTAL1
frequency applied on pin
XTAL1
0
-
26
MHz
VIL
LOW-level input voltage on
pin XTAL1
0.3
-
+0.3VDD
V
TDA8024
Product data sheet
depends on type of crystal or
resonator used
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
19 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
Table 8.
Characteristics …continued
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 C; fXTAL = 10 MHz; all currents flowing into the IC are positive: see Table note 1; unless
otherwise specified.
Symbol
Parameter
VIH
HIGH-level input voltage
on pin XTAL1
Conditions
Min
Typ
Max
Unit
0.7VDD
-
VDD + 0.3
V
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC)
td(I/O-I/OUC),
td(I/OUC-I/O)
I/O to I/OUC, I/OUC to I/O
falling edge delay
-
-
200
ns
tpu
active pull-up pulse width
-
-
100
ns
fI/O(max)
maximum frequency on
data lines
-
-
1
MHz
Ci
input capacitance on data
lines
-
-
10
pF
Data lines to card reader (pins I/O, AUX1 and AUX2; with integrated 11 k pull-up resistors to VCC)
Vo(inactive)
output voltage
inactive mode
no load
Io(inactive) = 1 mA
0
-
0.1
V
-
-
0.3
V
Io(inactive)
output current
inactive mode; pin grounded
-
-
1
mA
VOL
LOW-level output voltage
IOL = 1 mA
0
-
0.3
V
IOL 15 mA
VCC 0.4
-
VCC
V
no DC load
0.9VCC
-
VCC + 0.1
V
5 V and 3 V cards;
IOH < 40 A
0.75VCC
-
VCC + 0.1
V
IOH 10 mA
0
-
0.4
V
VOH
HIGH-level output voltage
VIL
LOW-level input voltage
0.3
-
0.8
V
VIH
HIGH-level input voltage
1.5
-
VCC + 0.3
V
IIL
LOW-level input current
VIL = 0 V
-
-
600
A
ILIH
HIGH-level input leakage
current
VIH = VCC
-
-
10
A
tt(DI)
data input transition time
VIL(max) to VIH(min)
-
-
1.2
s
tt(DO)
data output transition time
Vo = 0 to VCC; CL 80 pF;
10% to 90%
-
-
0.1
s
Rpu
integrated pull-up resistor
pull-up resistor to VDD
9
11
13
k
Ipu
current when pull-up active VOH = 0.9VCC; C = 80 pF
1
-
-
mA
Data lines to microcontroller (pins I/OUC, AUX1UC and AUX2UC; with integrated 11 k pull-up resistors to VDD)
VOL
LOW-level output voltage
IOL = 1 mA
0
-
0.3
V
VOH
HIGH-level output voltage
no DC load
0.9VDD
-
VDD + 0.1
V
5 V and 3 V cards;
IOH < 40 A
0.75VDD
-
VDD + 0.1
V
0.3
-
+0.3VDD
V
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
-
VDD + 0.3
V
ILIH
HIGH-level input leakage
current
VIH = VDD
-
-
10
A
IIL
LOW-level input current
VIL = 0 V
-
-
600
A
tt(DI)
data input transition time
VIL(max) to VIH(min)
-
-
1.2
s
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
20 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
Table 8.
Characteristics …continued
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 C; fXTAL = 10 MHz; all currents flowing into the IC are positive: see Table note 1; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tt(DO)
data output transition time
Vo = 0 to VDD; CL < 30 pF;
10% to 90%
-
-
0.1
s
Rpu
integrated pull-up resistor
pull-up resistor to VDD
9
11
13
k
Ipu
current when pull-up active VOH = 0.9VDD; C = 30 pF
1
-
-
mA
inactive mode
55
140
200
kHz
active mode
2.2
2.7
3.2
MHz
no load
0
-
0.1
V
Io(inactive) = 1 mA
0
-
0.3
V
Internal oscillator
fOSC(int)
frequency of internal
oscillator
Reset output to card reader (pin RST)
Vo(inactive)
output voltage
inactive mode
Io(inactive)
output current
inactive mode; pin grounded
-
-
1
mA
td(RSTIN-RST)
RSTIN to RST delay
RST enabled
-
-
2
s
VOL
LOW-level output voltage
IOL = 200 A
0
-
0.2
V
IOL = 20 mA (current limit)
VCC 0.4
-
VCC
V
IOH = 200 A
0.9VCC
-
VCC
V
IOH = 20 mA (current limit)
0
-
0.4
V
VOH
HIGH-level output voltage
tr
rise time
CL = 100 pF; VCC = 5 V or 3 V
-
-
0.1
s
tf
fall time
CL = 100 pF; VCC = 5 V or 3 V
-
-
0.1
s
no load
0
-
0.1
V
Io(inactive) = 1 mA
0
-
0.3
V
Clock output to card reader (pin CLK)
Vo(inactive)
output voltage
inactive mode
Io(inactive)
output current
CLK inactive; pin grounded
0
-
1
mA
VOL
LOW-level output voltage
IOL = 200 A
0
-
0.3
V
IOL = 70 mA (current limit)
VCC 0.4
-
VCC
V
VOH
HIGH-level output voltage
IOH = 200 A
0.9VCC
-
VCC
V
IOH = 70 mA (current limit)
tr
rise time
0
-
0.4
V
CL = 30 pF
[5]
-
-
16
ns
-
-
16
ns
45
-
55
%
0.2
-
-
V/ns
tf
fall time
CL = 30 pF
[5]
duty factor (except for
fXTAL)
CL = 30 pF
[5]
SR
slew rate
slew up or down; CL = 30 pF
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V)[6]
VIL
LOW-level input voltage
0.3
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
VDD + 0.3
V
ILIL
LOW-level input leakage
current
0 < VIL < VDD
-
-
1
A
ILIH
HIGH-level input leakage
current
0 < VIH < VDD
-
-
1
A
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
21 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
Table 8.
Characteristics …continued
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 C; fXTAL = 10 MHz; all currents flowing into the IC are positive: see Table note 1; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Card presence inputs (pins PRES and PRES)[7]
VIL
LOW-level input voltage
0.3
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
VDD + 0.3
V
ILIL
LOW-level input leakage
current
0 < VIL < VDD
-
-
5
A
ILIH
HIGH-level input leakage
current
0 < VIH < VDD
-
-
5
A
Interrupt output (pin OFF; NMOS drain with integrated 20 k pull-up resistor to VDD)
VOL
LOW-level output voltage
IOL = 2 mA
0
-
0.3
V
VOH
HIGH-level output voltage
IOH = 15 A
0.75VDD
-
-
V
Rpu
integrated pull-up resistor
20 k pull-up resistor to VDD
16
20
24
k
Protection and limitation
ICC(sd)
shutdown and limitation
current pin VCC
-
130
150
mA
II/O(lim)
limitation current pins I/O,
AUX1 and AUX2
15
-
+15
mA
ICLK(lim)
limitation current pin CLK
70
-
+70
mA
IRST(lim)
limitation current pin RST
20
-
+20
mA
Tsd
shut-down temperature
-
150
-
C
Timing
tact
activation time
see Figure 7
50
-
220
s
tde
deactivation time
see Figure 8
50
80
100
s
t3
start of the window for
sending CLK to the card
see Figure 7
50
-
130
s
t5
end of the window for
sending CLK to the card
see Figure 7
140
-
220
s
tdebounce
debounce time pins PRES
and PRES
see Figure 10
5
8
11
ms
[1]
All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is specified as a
function of VDD or VCC it means their actual value at the moment of measurement.
[2]
If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to ground. Pin 18 is not connected in
the TDA8024AT.
[3]
To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR both with
values of 100 nF, or one 100 nF and one 220 nF (see Figure 13).
[4]
Permitted capacitor values are 100 nF, or 100 nF + 100 nF, or 220 nF, or 220 nF + 100 nF, or 330 nF.
[5]
Transition time and duty factor definitions are shown in Figure 12; = --------------
[6]
Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 1.
[7]
Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25 A current source to GND (PRES to VDD); the card is
considered present if at least one of the inputs PRES or PRES is active.
t1
t1 + t2
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
22 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
WU
WI
92+
92+92/
W
92/
W
DDD
Fig 12. Definition of output and input transition times
12. Application information
Performance can be affected by the layout of the application. For example, an additional
cross-capacitance of 1 pF between card reader contacts C2 and C3 or C2 and C7 can
cause contact C2 to be polluted with high frequency noise from C3 (or C7). In this case,
include a 100 pF capacitor between contacts C2 and CGND.
Application recommendations:
• Ensure there is ample ground area around the TDA8024 and the connector; place the
TDA8024 very near to the connector; decouple the VDD and VDDP lines (these lines
are best positioned under the connector)
• The TDA8024 and the microcontroller must use the same VDD supply. Pins CLKDIV1,
CLKDIV2, RSTIN, PRES, PRES, AUX1UC, I/OUC, AUX2UC, 5V/3V, CMDVCC, and
OFF are referred to VDD; if pin XTAL1 is to be driven by an external clock, also refer
this pin to VDD
• Track C3 should be placed as far as possible from the other tracks
• The track connecting CGND to C5 should be straight (the two capacitors on C1
should be connected to this ground track)
• Avoid ground loops between CGND, PGND and GND
• Decouple VDDP and VDD separately; if the two supplies are the same in the
application, then they should be connected in star on the main track.
With all these layout precautions, noise should be kept to an acceptable level and jitter on C3
should be less than 100 ps.
Reference layouts are provided in “Application note 10141”, available on request.
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
23 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
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(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm).
(2) TDA8024 and the microcontroller must use the same VDD supply.
(3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor.
(4) Mount one low ESR-type 100 nF capacitor close to pin VCC.
(5) Mount one low ESR-type 100 or 220 nF capacitor close to C1 contact (less than 100 mm from it).
(6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks.
(7) Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be connected to ground;
see Section 8.2.2. Pin 18 is not connected in the TDA8024AT.
Fig 13. Application diagram
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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13. Package outline
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TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
25 of 33
TDA8024
NXP Semiconductors
Standard smart card interface
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
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Fig 15. Package outline SOT361-1 (TSSOP28)
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
28 of 33
TDA8024
NXP Semiconductors
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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15. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDA8024 v.4.0
20160603
Product data sheet
-
TDA8024_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 5 “Ordering information”: updated
TDA8024_3
20040712
Product specification
-
TDA8024_2
TDA8024_2
20030819
Product specification
-
-
TDA8024
Product data sheet
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TDA8024
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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© NXP Semiconductors N.V. 2016. All rights reserved.
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TDA8024
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TDA8024
Product data sheet
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Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
32 of 33
TDA8024
NXP Semiconductors
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18. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 8
Without external divider on pin PORADJ
(or with TDA8024AT) . . . . . . . . . . . . . . . . . . . . 8
8.2.2
With an external divider on pin PORADJ
(not for the TDA8024AT). . . . . . . . . . . . . . . . . . 8
8.2.3
Applications examples . . . . . . . . . . . . . . . . . . . 9
8.2.3.1
Microcontroller requiring
a 3.3 V ± 20 % supply. . . . . . . . . . . . . . . . . . . . 9
8.2.3.2
Microcontroller requiring
a 3.3 V ± 10% supply . . . . . . . . . . . . . . . . . . . . 9
8.3
Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.4
I/O transceivers . . . . . . . . . . . . . . . . . . . . . . . 11
8.5
Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.6
Activation sequence . . . . . . . . . . . . . . . . . . . . 12
8.7
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.8
Deactive sequence . . . . . . . . . . . . . . . . . . . . . 14
8.9
VCC generator . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.10
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Thermal characteristics . . . . . . . . . . . . . . . . . 17
11
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18
12
Application information. . . . . . . . . . . . . . . . . . 23
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25
14
Soldering of SMD packages . . . . . . . . . . . . . . 27
14.1
Introduction to soldering . . . . . . . . . . . . . . . . . 27
14.2
Wave and reflow soldering . . . . . . . . . . . . . . . 27
14.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27
14.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 31
16.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31
16.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16.4
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17
18
Contact information . . . . . . . . . . . . . . . . . . . . 32
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 June 2016
Document identifier: TDA8024