PHILIPS TDA8004T

INTEGRATED CIRCUITS
DATA SHEET
TDA8004T
IC card interface
Product specification
Supersedes data of 1997 Nov 21
File under Integrated Circuits, IC02
1999 Dec 30
Philips Semiconductors
Product specification
IC card interface
TDA8004T
• ISO 7816, GSM11.11 and EMV (payment systems)
compatibility
FEATURES
• 3 or 5 V supply for the IC (GND and VDD)
• Supply supervisor for spikes killing during power-on and
power-off
• Step-up converter for VCC generation (separately
powered with a 5 V ±10% supply, VDDP and PGND)
• One multiplexed status signal OFF.
• 3 specific protected half duplex bidirectional buffered
I/O lines (C4, C7 and C8)
APPLICATIONS
• VCC regulation 5 V ±5% on 2 × 100 nF or 1 × 100 nF
and 1 × 220 nF multilayer ceramic capacitors with low
ESR, ICC < 65 mA at 4.5 V < VDDP < 6.5 V, current
spikes of 40 nAs up to 20 MHz, with controlled rise and
fall times, filtered overload detection approximately
90 mA)
• IC card readers for banking
• Electronic payment
• Identification
• Pay TV.
• Thermal and short-circuit protections on all card
contacts
GENERAL DESCRIPTION
• Automatic activation and deactivation sequences
(initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating or supply
drop-out)
The TDA8004T is a complete low cost analog interface for
asynchronous smart cards. It can be placed betw the card
and the microcontroller with very few external components
to perform all supply protection and control functions.
• Enhanced ESD protection on card side (>6 kV)
• 26 MHz integrated crystal oscillator
• Clock generation for the card up to 20 MHz (divided by
1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)
• Non-inverted control of RST via pin RSTIN
ORDERING INFORMATION
TYPE
NUMBER
TDA8004T
1999 Dec 30
PACKAGE
NAME
SO28
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
2
VERSION
SOT136-1
Philips Semiconductors
Product specification
IC card interface
TDA8004T
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
VDDP
step-up supply voltage
IDD
supply current
IDDP
step-up supply current
2.7
−
6.5
V
4.5
5
6.5
V
inactive mode; VDD = 3.3 V;
fXTAL = 10 MHz
−
−
1.2
mA
active mode; VDD = 3.3 V;
fXTAL = 10 MHz; no load
−
−
1.5
mA
inactive mode; VDDP = 5 V;
fXTAL = 10 MHz
−
−
0.1
mA
active mode; VDDP = 5 V;
fXTAL = 10 MHz; no load
−
−
18
mA
DC ICC < 65 mA
4.75
−
5.25
V
AC current spikes of 40 nAs
4.65
−
5.25
V
−
−
350
mV
−
−
65
mA
Card supply
VCC
card supply voltage including
ripple
f 200 MHz≤
Vi(ripple)(p-p) ripple voltage on VCC
(peak-to-peak value)
20 kHz
ICC
VCC from 0 to 5 V
card supply current
General
fCLK
card clock frequency
0
−
20
MHz
tde
deactivation cycle duration
60
80
100
µs
Ptot
continuous total power dissipation
−
−
0.56
W
Tamb
ambient temperature
−25
−
+85
°C
1999 Dec 30
Tamb = −25 to +85 °C
3
Philips Semiconductors
Product specification
IC card interface
TDA8004T
BLOCK DIAGRAM
handbook, full pagewidth
VDD
VDDP
100 nF
100 nF
21
6
100 nF
S1
7
S2
5
4 PGND
SUPPLY
STEP-UP CONVERTER
INTERNAL
REFERENCE
Vref
INTERNAL OSCILLATOR
2.5 MHz
8 VUP
100 nF
VOLTAGE SENSE
ALARM
OFF
RSTIN
CMDVCC
RFU1
EN1
CLKUP
EN2
23
PVCC
20
VCC
GENERATOR
19
17 VCC
14 CGND
EN5
3
RST
BUFFER
16
CLOCK
BUFFER
15
RST
SEQUENCER
CLKDIV1
CLKDIV2
1
EN4
2
HORSEQ
CLOCK
CIRCUITRY
10
9
CLK
PRES
PRES
CLK
XTAL1
XTAL2
AUX1UC
EN3
24
25
OSCILLATOR
THERMAL
PROTECTION
27
I/O
TRANSCEIVER
13
I/O
TRANSCEIVER
12
I/O
TRANSCEIVER
11
AUX1
TDA8004T
AUX2UC
I/OUC
28
26
22
18
GND
n.c.
MGM175
All capacitors are mandatory.
Fig.1 Block diagram.
1999 Dec 30
4
AUX2
I/O
100
nF
100
nF
Philips Semiconductors
Product specification
IC card interface
TDA8004T
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
CLKDIV1
1
I
control with CLKDIV2 for choosing CLK frequency
CLKDIV2
2
I
control with CLKDIV1 for choosing CLK frequency
RFU1
3
I
reserved for future use (to be connected to VDD or microcontroller I/O; active HIGH)
PGND
4
S2
5
VDDP
6
S1
7
I/O
capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ
must be connected between pins S1 and S2)
VUP
8
I/O
output of step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be
connected to PGND)
PRES
9
I
card presence contact input (active LOW); if PRES or PRES is true, then the card is
considered as present
PRES
10
I
card presence contact input (active HIGH); if PRES or PRES is true, then the card is
considered as present
I/O
11
I/O
data line to and from card (C7) (internal 10 kΩ pull-up resistor connected to VCC)
AUX2
12
I/O
auxiliary line to and from card (C8) (internal 10 kΩ pull-up resistor connected to VCC)
AUX1
13
I/O
auxiliary line to and from card (C4) (internal 10 kΩ pull-up resistor connected to VCC)
CGND
14
CLK
15
supply power ground for step-up converter
I/O
capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ
must be connected between pins S1 and S2)
supply power supply voltage for step-up converter
supply ground for card signals
O
clock to card (C3)
RST
16
O
card reset (C2)
VCC
17
O
Supply for card (C1); decouple to CGND with 2 × 100 nF or 1 × 100 nF and 1 × 220 nF
capacitors with ESR < 100 mΩ (with 220 nF, the noise margin on VCC will be higher).
n.c.
18
−
not connected
CMDVCC
19
I
start activation sequence input from microcontroller (active LOW)
RSTIN
20
I
card reset input from microcontroller (active HIGH)
VDD
21
supply supply voltage
GND
22
supply ground
OFF
23
O
NMOS interrupt to microcontroller (active LOW) with 20 kΩ internal pull-up resistor
connected to VDD (refer section “Fault detection”)
XTAL1
24
I
crystal connection or input for external clock
XTAL2
25
O
crystal connection (leave open if an external clock source is used)
I/OUC
26
I/O
microcontroller data I/O line (internal 10 kΩ pull-up resistor connected to VDD)
AUX1UC
27
I/O
auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to
VDD)
AUX2UC
28
I/O
auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to
VDD)
1999 Dec 30
5
Philips Semiconductors
Product specification
IC card interface
TDA8004T
FUNCTIONAL DESCRIPTION
Throughout this document, it is assumed that the reader is
familiar with ISO 7816 norm terminology.
Power supply
The supply pins for the IC are VDD and GND. VDD should
be in the range from 2.7 to 6.5 V. All interface signals with
the system controller are referenced to VDD; so, be sure
the supply voltage of the system controller is also VDD. All
card contacts remain inactive during powering up or
powering down. The sequencer is not activated until VDD
reaches Vth2 + Vhys(th2) (see Fig.3). When VDD falls below
Vth2, an automatic deactivation of the contacts is
performed.
handbook, halfpage
CLKDIV1 1
28 AUX2UC
CLKDIV2 2
27 AUX1UC
RFU1 3
26 I/OUC
PGND 4
25 XTAL2
S2 5
24 XTAL1
VDDP 6
For generating a 5 V ±5% VCC supply to the card, an
integrated voltage doubler is incorporated. This step-up
converter should be separately supplied by VDDP and
PGND (from 4.5 to 6.5 V). Due to large transient currents,
the 2 × 100 nF capacitors of the step-up converter should
have an ESR less than 100 mΩ and be located as near as
possible to the IC.
23 OFF
S1 7
22 GND
TDA8004T
21 VDD
VUP 8
PRES 9
20 RSTIN
PRES 10
19 CMDVCC
I/O 11
The supply voltages VDD and VDDP may be applied to
the IC in any time sequence.
18 n.c.
AUX2 12
17 VCC
AUX1 13
16 RST
CGND 14
15 CLK
If a voltage between 7 and 9 V is available within the
application, this voltage may be tied to pin VUP, thus
blocking the step-up converter. In this case, VDDP must be
tied to VDD and the capacitor between pins S1 and S2 may
be omitted.
MGM174
Voltage supervisor
This block surveys the VDD supply. A defined reset pulse
of approximately 10 ms (tW) is used internally for
maintaining the IC in the inactive mode during powering up
or powering down of VDD (see Fig.3).
As long as VDD is less than Vth2 + Vhys(th2), the IC will
remain inactive whatever the levels on the command lines.
This also lasts for the duration of tW after VDD has reached
a level higher than Vth2 + Vhys(th2).
The system controller should not try to start an activation
during this time.
Fig.2 Pin configuration.
When VDD falls below Vth2, a deactivation sequence of the
contacts is performed.
1999 Dec 30
6
Philips Semiconductors
Product specification
IC card interface
TDA8004T
handbook, full pagewidth
Vth2 + Vhys(th2)
VDD
Vth2
tW
tW
ALARM
(internal signal)
MGM176
Fig.3 ALARM as a function of VDD (tW = 10 ms).
Clock circuitry
In the other cases, it is guaranteed between 45% and 55%
of the period.
The clock signal (CLK) to the card is either derived from a
clock signal input on pin XTAL1 or from a crystal up to
26 MHz connected between pins XTAL1 and XTAL2.
The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
XTAL1 is permanent, then the clock pulse will be applied
to the card according to the timing diagram of the
activation sequence (see Fig.5).
The frequency may be chosen at
fXTAL, 1⁄2fXTAL, 1⁄4fXTAL or 1⁄8fXTAL via pins CLKDIV1 and
CLKDIV2.
If the signal applied to XTAL1 is controlled by the system
controller, then the clock pulse will be applied to the card
when the system controller will send it (after completion of
the activation sequence).
The frequency change is synchronous, which means that
during transition, no pulse is shorter than 45% of the
smallest period and that the first and last clock pulse
around the change has the correct width.
In the case of fXTAL, the duty factors are dependent on the
signal at XTAL1.
Table 1
In order to reach a 45% to 55% duty factor on pin CLK the
input signal on XTAL1 should have a duty factor of
48% to 52% and transition times of less than 5% of the
input signal period.
CLKDIV1
CLKDIV2
0
0
1⁄
8fXTAL
1
1⁄
4fXTAL
1
1
1⁄
2fXTAL
1
0
0
If a crystal is used with fXTAL, the duty factor on pin CLK
may be 45% to 55% depending on the layout and on the
crystal characteristics and frequency.
1999 Dec 30
Clock circuitry definition
7
CLK
fXTAL
Philips Semiconductors
Product specification
IC card interface
TDA8004T
I/O circuitry
Inactive state
The three data lines I/O, AUX1 and AUX2 are identical.
After power-on reset, the circuit enters the inactive state. A
minimum number of circuits are active while waiting for the
microcontroller to start a session.
The Idle state is realized by both lines (I/O and I/OUC)
being pulled HIGH via a 10 kΩ resistor (I/O to VCC and
I/OUC to VDD).
• All card contacts are inactive (approximately 200 Ω to
GND)
I/O is referenced to VCC and I/OUC to VDD, thus allowing
operation with VCC ≠ VDD.
• I/OUC, AUX1UC and AUX2UC are high impedance
(10 kΩ pull-up resistor connected to VDD)
The first side on which a falling edge occurs becomes the
master. An anti-latch circuit disables the detection of falling
edges on the other line, which becomes a slave.
• Voltage generators are stopped
• XTAL oscillator is running
• Voltage supervisor is active.
After a time delay td(edge) (approximately 200 ns), the
N transistor on the slave side is turned on, thus
transmitting the logic 0 present on the master side.
Activation sequence
After power-on and after the internal pulse width delay, the
system controller may check the presence of the card with
the signal OFF (OFF = HIGH while CMDVCC is HIGH
means that the card is present; OFF = LOW while
CMDVCC is HIGH means that no card is present).
When the master side returns to logic 1, the P transistor on
the slave side is turned on during the time delay td(edge) and
then both sides return to their Idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA up to an
output voltage of 0.9VCC on a 80 pF load. At the end of the
active pull-up pulse, the output voltage only depends on
the internal pull-up resistor and on the load current (see
Fig.4).
If the card is in the reader (which is the case if PRES or
PRES is true), the system controller may start a card
session by pulling CMDVCC LOW.
The following sequence then occurs (see Fig.5):
• CMDVCC is pulled LOW (t0)
The maximum frequency on these lines is 1 MHz.
• The voltage doubler is started (t1 ~ t0)
FCE270
6
handbook, halfpage
Vo
(V)
• VCC rises from 0 to 5 V with a controlled slope
(t2 = t1 + 1⁄23T) (I/O, AUX1 and AUX2 follow VCC with a
slight delay)
12
• I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T)
Io
(mA)
(1)
• CLK is applied to the C3 contact (t4)
(2)
• RST is enabled (t5 = t1 + 7T).
8
4
In the timing informations above and below, T is 64 times
the period of the internal oscillator, about 25 µs.
The clock may be applied to the card in the following way:
4
2
0
20
0
40
t (ns)
• Set RSTIN HIGH before setting CMDVCC LOW and
reset it LOW between t3 and t5; CLK will start at this
moment. RST will remain LOW until t5, where RST is
enabled to be the copy of RSTIN. After t5, RSTIN has no
further action on CLK. This is to allow a precise count of
CLK pulses before toggling RST.
0
60
If this feature is not needed, then CMDVCC may be set
LOW with RSTIN LOW. In this case, CLK will start at t3 and
after t5, RSTIN may be set HIGH in order to get the Answer
To Request (ATR) from the card.
(1) Current.
(2) Voltage.
Fig.4
I/O, AUX1, and AUX2 output voltage and
current as a function of time during a
LOW-to-HIGH transition.
1999 Dec 30
8
Philips Semiconductors
Product specification
IC card interface
TDA8004T
tact
handbook, full pagewidth
OSC_INT/64
(T ≈ 25 µs)
CMDVCC
VUP
t1
t2
VCC
ATR
I/O
high - Z t3
t4
t5
CLK
RSTIN
RST
t0
MGM177
Fig.5 Activation sequence.
Active state
With all these layout precautions, noise should be at an
acceptable level and jitter on C3 should be less than
100 ps. Refer to Application Note AN97036 for specimen
layouts
When the activation sequence is completed, the
TDA8004T will be in the active state. Data is exchanged
between the card and the microcontroller via the I/O lines.
The TDA8004T is designed for cards without VPP (this is
the voltage required to program or erase the internal
non-volatile memory).
Deactivation sequence
When a session is completed, the microcontroller sets the
CMDVCC line to the HIGH state. The circuit then executes
an automatic deactivation sequence by counting the
sequencer back and ends in the inactive state (see Fig.6):
Depending on the layout and on the application test
conditions (for example with an additional 1 pF cross
capacitance between C2/C3 and C2/C7) it is possible
that C2 is polluted with high frequency noise from C3. In
this case, it will be necessary to connect a 220 pF
capacitance between C2 and CGND.
• RST goes LOW → (t11 = t10)
• CLK is stopped LOW → (t12 = t11 + 1⁄2T)
• I/O, AUX1 and AUX2 are output into high-impedance
state → (t13 = t11 + T); 10 kΩ pull-up resistor connected
to VCC
It is recommended to:
1. Keep track C3 as far as possible from other tracks
• VCC falls to zero → (t14 = t11 + 1⁄23T); the deactivation
sequence is completed when VCC reaches its inactive
state
2. Have straight connection between CGND and C5 (the
2 capacitors on C1 should be connected to this ground
track)
• VUP falls to zero → (t15 = t11 + 5T) and all card contacts
become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain pulled up to VDD via a 10 kΩ resistor.
3. Avoid ground loops between CGND, PGND and GND
4. Decouple VDDP and VDD separately; if the 2 supplies
are the same in the application, then they should be
connected in star on the main track.
1999 Dec 30
9
Philips Semiconductors
Product specification
IC card interface
TDA8004T
tde
handbook, full pagewidth
OSC_INT/64
(T ≈ 25 µs)
CMDVCC
t10
t15
VUP
t14
VCC
t13
I/O
high - Z
t12
CLK
RST
t11
MGE739
Fig.6 Deactivation sequence.
Fault detection
When the system controller sets CMDVCC back to
HIGH, it may sense OFF again in order to distinguish
between a hardware problem or a card extraction. If a
supply voltage drop on VDD is detected whilst the card
is activated, then an emergency deactivation will be
performed, but OFF remains HIGH.
The following fault conditions are monitored by the circuit:
• Short-circuit or high current on VCC
• Removing card during transaction
• VDD dropping
• Overheating.
Depending on the type of card presence switch within the
connector (normally closed or normally open) and on the
mechanical characteristics of the switch, a bouncing may
occur on presence signals at card insertion or withdrawal.
There are two different cases (see Fig.7):
1. CMDVCC HIGH: (outside a card session) then, OFF is
LOW if the card is not in the reader and HIGH if the
card is in the reader. A supply voltage drop on VDD is
detected by the supply supervisor, generates an
internal power-on reset pulse, but don’t act upon OFF.
The card is not powered-up, so no short-circuit or
overheating is detected.
There is no debounce feature in the device, so the
software has to take it into account; however, the detection
of card take off during active phase, which initiates an
automatic deactivation sequence is done on the first
true/false transition on PRES or PRES and is memorized
until the system controller sets CMDVCC HIGH.
2. CMDVCC LOW: (within a card session) then, OFF falls
LOW if the card is extracted, or if a short-circuit has
occurred on VCC, or if the temperature on the IC has
become too high. As soon as the fault is detected, an
emergency deactivation is automatically performed
(see Fig.8).
1999 Dec 30
So, the software may take some time waiting for presence
switches to be stabilized without causing any delay on the
necessary fast and normalized deactivation sequence.
10
Philips Semiconductors
Product specification
IC card interface
handbook, full pagewidth
TDA8004T
PRES
OFF
CMDVCC
VCC
Deactivation caused by
cards withdrawal
Deactivation caused by
short circuit
FCE271
Fig.7 Behaviour of OFF, CMDVCC, PRES and VCC.
tde
handbook, full pagewidth
OSC_INT/64
(T ≈ 25 µs)
OFF
t10
PRES
t14
VCC
t13
I/O
high - Z
t12
CLK
RST
t11
MGE740
Fig.8 Emergency deactivation sequence.
VCC regulator
VCC buffer is able to deliver up to 65 mA continuously. It has an internal overload detection at approximately 90 mA.
This detection is internally filtered, allowing spurious current pulses up to 200 mA to be drawn by the card without causing
a deactivation (the average current value must stay below 65 mA).
For VCC accuracy reasons, a 100 nF capacitor with ESR < 100 mΩ should be tied to CGND near pin 17 and a 100 nF
(or better 220 nF) with same ESR should be tied to CGND near C1 contact.
1999 Dec 30
11
Philips Semiconductors
Product specification
IC card interface
TDA8004T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); notes 1 and 2.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD, VDDP
supply voltage
−0.3
+7
V
Vn1
voltage on pins: XTAL1, XTAL2, RFU1, RSTIN,
AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2,
CMDVCC and OFF
−0.3
+7
V
Vn2
voltage on card contact pins PRES, PRES, I/O, RST,
AUX1, AUX2 and CLK
−0.3
+7
V
Vn3
voltage on pin VUP, S1 and S2
−
9
V
Tstg
IC storage temperature
−55
+125
°C
Ptot
continuous total power dissipation
−
0.56
W
Tj
junction temperature
−
150
°C
Ves1
electrostatic voltage on pins: I/O, RST, VCC, AUX1,
CLK, AUX2, PRES and PRES
−6
+6
kV
Ves2
electrostatic voltage on all other pins
−2
+2
kV
Tamb = −25 to +85 °C
Notes
1. All card contacts are protected against any short with any other card contact.
2. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional
operation of the device under this condition is not implied.
HANDLING
Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500 Ω; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Dec 30
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
12
VALUE
UNIT
70
K/W
Philips Semiconductors
Product specification
IC card interface
TDA8004T
CHARACTERISTICS
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the
temperature range; fXTAL = 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a
parameter is specified as a function of VDD or VCC, it means their actual value at the moment of measurement.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Temperature
Tamb
−25
ambient temperature
−
+85
°C
Supplies
VDD
supply voltage
2.7
−
6.5
V
VDDP
supply voltage for the voltage
doubler
4.5
5
6.5
V
Vo(VUP)
output voltage on pin VUP from
step-up converter
−
5.5
−
V
Vi(VUP)
input voltage to be applied on VUP
in order to block the step-up
converter
7
−
9
V
IDD
supply current
inactive mode
−
−
1.2
mA
active mode; fCLK = fXTAL;
CL = 30 pF
−
−
1.5
mA
inactive mode
−
−
0.1
mA
ICC = 0
−
−
18
mA
ICC = 65 mA
IP
supply current for the step-up
converter
active mode; fCLK = fXTAL;
CL = 30 pF
−
−
150
mA
Vth2
threshold voltage on VDD (falling)
2.2
−
2.4
V
Vhys(th2)
hysteresis on Vth2
50
−
150
mV
tW
width of the internal ALARM pulse
6
−
20
ms
inactive mode
−0.1
−
+0.1
V
Card supply voltage (VCC); note 1
VCC
output voltage including ripple
inactive mode; ICC = 1 mA
−0.1
−
+0.4
V
active mode;
ICC < 65 mA DC
4.75
−
5.25
V
active mode; single current
pulse of −100 mA; 2 µs
4.65
−
5.25
V
active mode; current pulses 4.65
of 40 nAs with
ICC < 200 mA; t < 400 ns;
−
5.25
V
−
−
350
mV
f 200 MHz≤
Vi(ripple)(p-p)
peak-to-peak ripple voltage on VCC
20 kHz
ICC
output current
from 0 to 5 V;
−
−
65
mA
VCC short-circuit to ground
−
−
120
mA
SR
slew rate
up and down
0.11
0.17
0.22
V/µs
1999 Dec 30
13
Philips Semiconductors
Product specification
IC card interface
SYMBOL
PARAMETER
TDA8004T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal connections (XTAL1 and XTAL2)
depending on specification −
of crystal or resonator used
−
15
pF
crystal input frequency
2
−
26
MHz
VIH(XTAL)
HIGH-level input voltage on XTAL1
0.8VDD
−
VDD + 0.2 V
VIL(XTAL)
LOW-level input voltage on XTAL1
−0.3
−
0.2VDD
V
Cext
external capacitance on
XTAL1 and XTAL2
fi(XTAL)
Data lines (I/O, I/OUC, AUX1, AUX2, AUXUC1 and AUXUC2)
GENERAL
td(edge)
delay between falling edge on pins
I/OUC and I/O (or I/O and I/OUC)
and width of active pull-up pulse
−
200
−
ns
fI/O(max)
maximum frequency on data lines
−
−
1
MHz
Ci
input capacitance on data lines
−
−
10
pF
DATA LINES; I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC)
VOH
HIGH-level output voltage on data
lines
no DC load
0.9VCC
−
VCC + 0.1 V
IOH = −40 µA
0.75VCC
−
VCC + 0.1 V
I = 1 mA
−
−
300
VOL
LOW-level output voltage on data
lines
VIH
HIGH-level input voltage on data
lines
1.8
−
VCC + 0.3 V
VIL
LOW-level input voltage on data
lines
−0.3
−
+0.8
V
Vinactive
voltage on data lines outside a
session
no load
−
−
0.1
V
II/O = 1 mA
−
−
0.3
V
Iedge
current from data lines when active
pull-up active
VOH = 0.9VCC; Co = 80 pF
−1
−
−
mA
ILIH
input leakage current HIGH on data
lines
VIH = VCC
−
−
10
µA
IIL
LOW-level input current on data
lines
VIL = 0 V
−
−
600
µA
Rpu(int)
internal pull-up resistance between
data lines and VCC
9
11
13
kΩ
tr, tf
input transition times on data lines
from VIL(max) to VIH(min)
−
−
1
µs
output transition times on data lines
Co = 80 pF, no DC load;
10% to 90% of VCC (see
Fig.9)
−
−
0.1
µs
mV
DATA LINES; I/OUC, AUX1UC AND AUX2UC (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD)
VOH
VOL
1999 Dec 30
HIGH-level output voltage on data
lines
LOW-level output voltage on data
lines
no DC load
0.9VDD
−
VDD + 0.2 V
IOH = −40 µA
0.75VDD
−
VDD + 0.2
IOL = 1 mA
−
−
300
14
mV
Philips Semiconductors
Product specification
IC card interface
SYMBOL
PARAMETER
TDA8004T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIH
HIGH-level input voltage on data
lines
0.7VDD
−
VDD + 0.3 V
VIL
LOW-level input voltage on data
lines
0
−
0.3VDD
V
ILIH
input leakage current HIGH on data
lines
VIH = VDD
−
−
10
µA
IIL
LOW-level input on data lines
VIL = 0 V
−
−
600
µA
Rpu(int)
internal pull-up resistance between
data lines and VDD
9
11
13
kΩ
tr, tf
input transition times on data lines
from VIL(max) to VIH(min)
−
−
1
µs
output transition times on data lines
Co = 30 pF; 10% to 90%
of VDD (see Fig.9)
−
−
0.1
µs
2.2
−
3.2
MHz
no load
0
−
0.1
V
Io = 1 mA
0
−
0.3
V
td(RSTIN-RST) delay between pins RSTIN and RST RST enabled
Internal oscillator
fosc(int)
frequency of internal oscillator
Reset output to the card (RST)
Vo(inactive)
output voltage in inactive mode
−
−
2
µs
VOL
LOW-level output voltage
IOL = 200 µA
0
−
0.3
V
VOH
HIGH-level output voltage
IOH = −200 µA
0.9VCC
−
VCC
V
tr, tf
rise and fall times
Co = 250 pF
−
−
0.1
µs
no load
0
−
0.1
V
Clock output to the card (CLK)
Vo(inactive)
output voltage in inactive mode
Io = 1 mA
0
−
0.3
V
VOL
LOW-level output voltage
IOL = 200 µA
0
−
0.3
V
VOH
HIGH-level output voltage
IOH = −200 µA
0.9VCC
−
VCC
V
tr, tf
rise and fall times
CL = 35 pF; note 2
−
−
8
ns
δ
duty factor (except for fXTAL)
CL = 35 pF; note 2
45
−
55
%
SR
slew rate (rise and fall)
CL = 35 pF
0.2
−
−
V/ns
Logic inputs (CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN and RFU1); note 3
VIL
LOW-level input voltage
−
−
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
−
−
V
ILIL
input leakage current LOW
0 < VIL < VDD
−
−
5
µA
ILIH
input leakage current HIGH
0 < VIH < VDD
−
−
5
µA
OFF output (OFF is an open drain with an internal 20 kΩ pull-up resistor to VDD)
VOL
LOW-level output voltage
IOL = 2 mA
−
−
0.4
V
VOH
HIGH-level output voltage
IOH = −15 µA
0.75VDD
−
−
V
Protections
Tsd
shut-down temperature
−
135
−
°C
ICC(sd)
shut-down current at VCC
−
−
110
mA
1999 Dec 30
15
Philips Semiconductors
Product specification
IC card interface
SYMBOL
TDA8004T
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing
tact
activation sequence duration
see Fig.5
−
180
220
µs
tde
deactivation sequence duration
see Fig.6
60
80
100
µs
t3
start of the window for sending CLK
to the card
see Fig.5
−
−
130
µs
t5
end of the window for sending CLK
to the card
see Fig.5
140
−
−
µs
Notes
1. To meet these specifications VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR
with values of either 100 nF or one 100 nF and one 220 nF.
t1
2. The transition times and duty factor definitions are shown in Fig.9; δ = ------------------( t1 + t2 )
3. PRES and CMDVCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1;
RFU1 must be tied HIGH.
handbook, full pagewidth
tr
tf
90%
90%
VCC or VDD
(VOH + VOL)/2
10%
10%
0
t1
t2
MGM178
Fig.9 Definition of output transition times.
APPLICATION INFORMATION
VDD for the TDA8004T must be the same as for the microcontroller and CLKDIV1, CLKDIV2, RSTIN, PRES, PRES,
AUX1UC, AUX2UC, I/OUC, RFU1, CMDVCC and OFF should be referenced to VDD and XTAL1 also when driven by an
external clock.
For optimum layout be sure that there is enough ground area around the TDA8004T and the connector. Place the
TDA8004T very near to the connector, ideally under the connector, and decouple VDD and VDDP properly.
Refer to AN97036 for further application information for proper implementation of the TDA8004T.
1999 Dec 30
16
Philips Semiconductors
Product specification
IC card interface
TDA8004T
VDD for the TDA8004 must be the same as controller
supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES,
PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC,
OFF should be referenced to VDD, and also XTAL1
if driven by external clock.
More application information on
application report AN97036
100 nF
10 µF
CLKDIV1
CLKDIV2
+5 V
+3.3 V
RFU1
GNDP
S2
100 nF
VDDP
S1
VUP
100 nF
PRES
PRES
These capacitors
must be placed
near the IC and
have LOW ESR
(Less than 1 cm)
+3.3 V
100 k
Straight and short
connextions between
CGND, C5 and capacitors
GND. (No loop)
I/O
AUX2
AUX1
CGND
1
28
2
27
3
26
4
25
5
24
6
23
7
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
GND
22
TDA8004T
VDD
21
8
9
20
10
19
11
18
12
17
13
16
14
15
3.3 V POWERED
MICROCONTROLLER
33 pF
100 nF
RSTIN
+3.3 V
CMDVCC
n.c.
+3.3 V
VCC
RST
CLK
One 100nF
with LOW ESR
near pin 17,
100 nF
CARD READ
(Normally closed type)
220 nF
C5
C1
C6
C2
C7
C3
C8
C4
K1
K2
One 100nF or 220nF
with LOW ESR
near C1 contact
(less than 1cm)
C3 should be routed
far from C2, C7, C4 and C8
and, better, surrounded
with ground tracks.
MGM179
Fig.10 Application diagram.
1999 Dec 30
17
Philips Semiconductors
Product specification
IC card interface
TDA8004T
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
w M
bp
0
detail X
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013
1999 Dec 30
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-05-22
99-12-27
18
Philips Semiconductors
Product specification
IC card interface
TDA8004T
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Dec 30
19
Philips Semiconductors
Product specification
IC card interface
TDA8004T
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
suitable(2)
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Dec 30
20
Philips Semiconductors
Product specification
IC card interface
TDA8004T
NOTES
1999 Dec 30
21
Philips Semiconductors
Product specification
IC card interface
TDA8004T
NOTES
1999 Dec 30
22
Philips Semiconductors
Product specification
IC card interface
TDA8004T
NOTES
1999 Dec 30
23
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 68
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/02/pp24
Date of release: 1999
Dec 30
Document order number:
9397 750 06034