June 26, 2008 LMH0307 3 Gbps HD/SD SDI Dual Cable Driver with Cable Detect General Description Features The LMH0307 3 Gbps HD/SD SDI Dual Cable Driver with Cable Detect is designed for use in SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M serial digital video applications. The LMH0307 implements two complementary output drivers and drives 75Ω transmission lines (Belden 1694A, Belden 8281, or equivalent) at data rates up to 2.97 Gbps. The LMH0307 includes intelligent sensing capabilities to improve system diagnostics. The cable detect feature senses near-end termination to determine if a cable is correctly attached to the output BNC. Input loss of signal (LOS) detects the presence of a valid signal at the input of the cable driver. These sensing features may be used to alert the user of a system fault and activate a deep power save mode, reducing the cable driver's power consumption to 3 mW. These features are accessible via an SMBus interface. The LMH0307 provides two selectable slew rates for SMPTE 259M and SMPTE 424M / 292M compliance. The output amplitude is adjustable ±10% in 5 mV steps via the SMBus. The LMH0307 is powered from a single 3.3V supply. Power consumption is typically 230 mW in SD mode and 275 mW in HD mode. The LMH0307 is available in a 16-pin LLP package. The LMH0307 interfaces with National's LMH0356 for additional system control and power consumption savings (see Typical Application). ■ SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 259M compliant Data rates to 2.97 Gbps Cable detect on output Loss of signal detect at input Output driver power down control Typical power consumption: 230 mW in SD mode and 275 mW in HD mode Power save mode typical power consumption: 4 mW Single 3.3V supply operation Differential input Dual complementary 75Ω outputs Selectable slew rate Industrial temperature range: −40°C to +85°C 16–pin LLP package Applications ■ SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M serial digital interfaces ■ Digital video routers and switches ■ Distribution amplifiers Typical Application 30047903 © 2008 National Semiconductor Corporation 300479 www.national.com LMH0307 3 Gbps HD/SD SDI Dual Cable Driver with Cable Detect PRELIMINARY LMH0307 ESD Rating (HBM) ESD Rating (MM) ESD Rating (CDM) Absolute Maximum Ratings (Note 1) Supply Voltage: Input Voltage (all inputs) Output Current Storage Temperature Range Junction Temperature Lead Temperature (Soldering 4 Sec) Package Thermal Resistance θJA 16-pin LLP θJC 16-pin LLP −0.5V to 3.6V −0.3V to VCC+0.3V 28 mA −65°C to +150°C +125°C 8 kV 400V 2 kV Recommended Operating Conditions Supply Voltage (VCC – VEE): Operating Free Air Temperature (TA) +260°C 3.3V ±5% −40°C to +85°C +43°C/W +7°C/W DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter VCMIN Input Common Mode Voltage VSDI Input Voltage Swing VCMOUT Output Common Mode Voltage VSDO Output Voltage Swing VIH Input Voltage High Level VIL InputVoltage Low Level ICC Supply Current Conditions Reference SDI, SDI Differential Min Max Units 1.6 + VSDI/2 VCC – VSDI/2 V 100 2200 mVP−P SDO, SDO Single-ended, 75Ω load, RREF = 750Ω 1% VCC – VSDO 720 SD/HD, ENABLE Typ 800 V 880 2.0 mVP-P V 0.8 V 84 98 mA SD/HD = 1, SDO/SDO enabled 70 77 mA SDO/SDO disabled 1.3 2.5 mA 0.8 V VSDD V SD/HD = 0, SDO/SDO enabled SMBus DC Specifications VSIL Data, Clock Input Low Voltage VSIH Data, Clock Input High Voltage ISPULLUP Current through pullup resistor or VOL = 0.4V current source VSDD Nominal Bus Voltage ISLEAKB Input Leakage per bus segment ISLEAKP Input Leakage per pin CSI Capacitance for SDA and SCL www.national.com 2.1 4 (Note 6) (Notes 6, 7) 2 mA 3.0 3.6 V −200 200 µA −10 10 µA 10 pF Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter DRSDI Input Data Rate tjit Additive Jitter tr,tf Output Rise Time, Fall Time Conditions Reference Min Typ SDI, SDI 2.97 Gbps SDO, SDO Output Overshoot tSK SDO1 to SDO0 Skew RLSDO Output Return Loss 2970 Mbps psP-P 1.485 Gbps 18 psP-P 270 Mbps 15 SD/HD = 0, 20% – 80%, 90 psP-P 130 ps 800 ps 30 ps SD/HD = 0, 2.97 Gbps, (Note 4) 27 ps SD/HD = 0, 1.485 Gbps, (Note 4) 30 ps SD/HD = 1, (Note 4) 100 ps SD/HD = 0, (Note 4) 10 % SD/HD = 1, (Note 4) 8 % SD/HD = 1, 20% – 80% tOS Units 20 400 Mismatch in Rise/Fall Time Duty Cycle Distortion Max TBD TBD ps 5 MHz - 1.5 GHz, (Note 5) 15 dB 1.5 GHz - 3.0 GHz, (Note 5) 10 dB SMBus AC Specifications fSMB Bus Operating Frequency 10 tBUF Bus free time between Stop and Start Condition 4.7 µs tHD:STA Hold time after (repeated) Start Condition. After this period, the first clock is generated. 4.0 µs 100 kHz At ISPULLUP = MAX tSU:STA Repeated Start Condition setup time 4.7 µs tSU:STO Stop Condition setup time 4.0 µs tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 250 ns tLOW Clock low period 4.7 µs tHIGH Clock high period 4.0 50 µs tF Clock/Data Fall Time 300 ns tR Clock/Data Rise Time 1000 ns tPOR Time in which device must be operational after power on 500 ms Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics" specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VEE = 0 Volts. Note 3: Typical values are stated for VCC = +3.3V and TA = +25°C. Note 4: Specification is guaranteed by characterization. Note 5: Output return loss is dependent on board design. The LMH0307 meets this specification on the SD307 evaluation board. Note 6: Recommended value — Parameter not tested. Note 7: Recommended maximum capacitive load per bus segment is 400 pF. 3 www.national.com LMH0307 AC Electrical Characteristics LMH0307 Timing Diagram 30047906 SMBus Timing Parameters Connection Diagram 30047905 The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage. 16-Pin LLP Order Number LMH0307SQ See NS Package Number SQB16A www.national.com 4 LMH0307 Pin Descriptions Pin Name Description 1 SDI Serial data true input. 2 SDI Serial data complement input. 3 VEE Negative power supply (ground). 4 RREF Bias resistor. Connect a 750Ω resistor to VCC. 5 RSTI Reset input. H = Normal operation. L = Device reset. The device operates with default register settings. Forcing RSTI low also forces RSTO low. 6 ENABLE Output driver enable (with internal pullup). H = Normal operation. L = Output driver powered off. 7 SDA SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin requires an external pullup. 8 SCL SMBus clock input. SCL is input only. This pin requires an external pullup. 9 VCC Positive power supply (+3.3V). 10 SD/HD Output slew rate control. H = Output rise/fall time complies with SMPTE 259M. L = Output rise/fall time complies with SMPTE 424M / 292M. 11 SDO0 Serial data output 0 complement output. 12 SDO0 Serial data output 0 true output. 13 FAULT Fault open drain output flag. Requires external pullup resistor and may be wire ORed with multiple cable drivers. H = Normal operation. L = Loss of signal or termination fault for any output. 14 SDO1 Serial data output 1 true output. 15 SDO1 Serial data output 1 complement output. 16 RSTO Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset back to zero by forcing RSTI to zero to reset the device. Used to daisy chain multiple cable drivers on the same SMBus. VEE Connect exposed DAP to negative power supply (ground). DAP 5 www.national.com LMH0307 several internal configuration registers which may be accessed via the SMBus. The 7-bit default address for the LMH0307 is 17h. The LSB is set to 0b for a WRITE and 1b for a READ, so the 8-bit default address for a WRITE is 2Eh and the 8-bit default address for a READ is 2Fh. The SMBus address may be dynamically changed. In applications where there might be several LMH0307s, the SDA, SCL, and FAULT pins can be shared. The SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0307s may have the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be masked from the FAULT pin. TRANSFER OF DATA VIA THE SMBus During normal operation the data on SDA must be stable during the time when SCL is High. There are three unique states for the SMBus: START: A High-to-Low transition on SDA while SCL is High indicates a message START condition. STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition. IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus TRANSACTIONS The device supports WRITE and READ transactions. See Register Description table for register address, type (Read/ Write, Read Only), default value and function information. WRITING A REGISTER To write a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drives the 8-bit data byte. 6. The Device drives an ACK bit (“0”). 7. The Host drives a STOP condition. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. READING A REGISTER To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drives a START condition. 6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 7. The Device drives an ACK bit “0”. 8. The Device drives the 8-bit data value (register contents). 9. The Host drives a NACK bit “1”indicating end of the READ transfer. 10. The Host drives a STOP condition. Device Operation INPUT INTERFACING The LMH0307 accepts either differential or single-ended input. For single-ended operation, the unused input must be properly terminated. OUTPUT INTERFACING The LMH0307 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75Ω AC-coupled coaxial cable with an RREF resistor of 750Ω. The RREF resistor is connected between the RREF pin and VCC. The only resistor value that should be used for RREF is 750Ω. The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane layers below the RREF network should be removed to minimize parasitic capacitance. OUTPUT SLEW RATE CONTROL The LMH0307 output rise and fall times are selectable for either SMPTE 259M or SMPTE 424M / 292M compliance via the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set high. For faster rise and fall times, or SMPTE 424M and SMPTE 292M compliance, SD/HD is set low. SD/HD may also be controlled using the SMBus, provided the SD/HD pin is held low. OUTPUT ENABLE The SDO0/SDO0 and SDO1/SDO1output drivers can be enabled or disabled with the ENABLE pin. When set low, both output drivers are powered off and the LMH0307 enters a deep power save mode. ENABLE has an internal pullup. INPUT LOSS OF SIGNAL DETECTION (LOS) The LMH0307 detects when the input signal does not have a video-like pattern. Self oscillation and low levels of noise are rejected. This loss of signal detect allows a very sensitive input stage that is robust against coupled noise without any degradation of jitter performance. Via the SMBus, the loss of signal detect can either add an input offset or mute the outputs. An offset is added by default. Additionally, the loss of signal detect can be linked to the ENABLE functionality so that when the LOS goes low, ENABLE will also go low. OUTPUT CABLE DETECTION The LMH0307 detects when an output is locally terminated. When a video signal (or AC test signal) is present on SDI, the device senses the SDO and SDO amplitudes. If the output is not properly terminated (via a terminated cable or local termination), the amplitude will be higher than expected, and the Termination Fault signal is asserted. The Termination Fault signal is de-asserted when the proper termination is applied. This feature allows the system designer the flexibility to react to cable attachment and removal. Note that a long length of cable will look like a proper termination at the device output. Also note that the cable driver must be enabled for the termination detection to operate. SMBus Interface The System Management Bus (SMBus) is a two-wire interface designed for the communication between various system component chips. By accessing the control functions of the circuit via the SMBus, pincount is kept to a minimum while allowing a maximum amount of versatility. The LMH0307 has www.national.com 6 LMH0307 Application Information Figure 1 shows the application circuit for the LMH0307. 30047902 FIGURE 1. Application Circuit device. This signal acts as a “Enable / Reset” signal. Additional LMH0307s are controlled from the upstream device. In this control scheme, multiple LMH0307s may be controlled via the two-wire SMBus and the use of one GPO (General Purpose Output) signal. Other SMBus devices may also be connected to the two wires, assuming they have their own unique SMBus addresses. COMMUNICATING WITH MULTIPLE LMH0307 CABLE DRIVERS VIA THE SMBus A common application for the LMH0307 will utilize multiple cable driver devices. Even though the LMH0307 devices all have the same default SMBus device ID (address), it is still possible for them share the SMBus signals as shown in Figure 2. A third signal is required from the host to the first 7 www.national.com LMH0307 30047907 FIGURE 2. SMBus Configuration for Multiple LMH0307 Cable Drivers The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0307 RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next device and so on. The procedure at initialization is to: 1. Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the next device in RESET in the chain. 2. Raise the host GPO signal to LMH0307 #1 RSTI input pin 3. Write to Address 8’h2E (7’h17) Register 0 with the new address value (e.g. 8’h2C (7’h16) 4. Upon writing Register 0 in LMH0307 #1, its RSTO signal will switch High. Its new address is 8’h2C (7’h16), and www.national.com the next LMH0307 in the chain will now respond to the default address of 8’h2E (7’h17). 5. The process is repeated until all LMH0307 devices have a unique address loaded. 6. Direct SMBus writes and reads may now take place between the host and any addressed device. The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of the LMH0307 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the bus have unique device IDs. If power is toggled to the system, the SMBus address routine needs to be repeated. 8 LMH0307 TABLE 1. SMBus Registers Address R/W Name 00h 01h 02h R/W ID R STATUS R/W MASK Bits Field Default Description 7:1 DEVID 0010111 Device ID. Writing this register will force the RSTO pin high. Further accesses to the device must use this 7-bit address. 0 RSVD 0 7:5 RSVD 000 4 TFN1 0 Termination Fault for SDI1. 0: No Termination Fault Detected 1: Termination Fault Detected 3 TFP1 0 Termination Fault for SDI1. 0: No Termination Fault Detected 1: Termination Fault Detected 2 TFN0 0 Termination Fault for SDI0. 0: No Termination Fault Detected 1: Termination Fault Detected 1 TFP0 0 Termination Fault for SDI0. 0: No Termination Fault Detected 1: Termination Fault Detected 0 LOS 0 Loss Of Signal (LOS) detect at input. 0: No Signal Detected 1: Signal Detected 7 SD 0 SD Rate select bit. If the SD/HD pin is set to VCC, it overrides this bit. With the SD/HD pin set to ground, this pin selects the output edge rate as follows: 0: HD edge rate 1: SD edge rate 6 PD1 0 Power Down for SDO1 output stage. If the ENABLE pin is set to ground, it overrides this bit. With the ENABLE pin set to VCC, PD1 functions as follows: 0: SDO1 active 1: SDO1 powered down 5 PD0 0 Power Down for SDO0 output stage. If the ENABLE pin is set to ground, it overrides this bit. With the ENABLE pin set to VCC, PD0 functions as follows: 0: SDO0 active 1: SDO0 powered down 4 MTFN1 0 Mask TFN1 from affecting FAULT pin. 0: TFN1=1 will cause FAULT to be 0. 1: TFN1=1 will not affect FAULT; the condition is masked off. 3 MTFP1 0 Mask TFP1 from affecting FAULT pin. 0: TFP1=1 will cause FAULT to be 0. 1: TFP1=1 will not affect FAULT; the condition is masked off. 2 MTFN0 0 Mask TFN0 from affecting FAULT pin. 0: TFN0=1 will cause FAULT to be 0. 1: TFN0=1 will not affect FAULT; the condition is masked off. 1 MTFP0 0 Mask TFP0 from affecting FAULT pin. 0: TFP0=1 will cause FAULT to be 0. 1: TFP0=1 will not affect FAULT; the condition is masked off. 0 MLOS 0 Mask LOS from affecting FAULT pin. 0: LOS=0 will cause FAULT to be 0. 1: LOS=0 will not affect FAULT; the condition is masked off. 9 Reserved as 0. Always write 0 to this bit. Reserved www.national.com LMH0307 Address R/W Name 03h 04h R/W DIRECTION R/W OUTPUT0 www.national.com Bits Field Default Description 7 HDTFThresh0LSB 0 Least Significant Bit for HDTFThresh0 detection threshold. Combines with HDTFThresh0 bits in register 04h. 6 SDTFThresh0LSB 0 Least Significant Bit for SDTFThresh0 detection threshold. Combines with SDTFThresh0 bits in register 05h. 5 RSVD 0 Reserved as 0. Always write 0 to this bit. 4 DTFN1 0 Direction of TFN1 that affects FAULT pin (when not masked). 0: TFN1=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFN1=0 will cause FAULT to be 0 (when the condition is not masked off). 3 DTFP1 0 Direction of TFP1 that affects FAULT pin (when not masked). 0: TFP1=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFP1=0 will cause FAULT to be 0 (when the condition is not masked off). 2 DTFN0 0 Direction of TFN0 that affects FAULT pin (when not masked). 0: TFN0=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFN0=0 will cause FAULT to be 0 (when the condition is not masked off). 1 DTFP0 0 Direction of TFP0 that affects FAULT pin (when not masked). 0: TFP0=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFP0=0 will cause FAULT to be 0 (when the condition is not masked off). 0 DLOS 0 Direction of LOS that affects FAULT pin (when not masked). 0: LOS=0 will cause FAULT to be 0 (when the condition is not masked off). 1: LOS=1 will cause FAULT to be 0 (when the condition is not masked off). 100 Sets the Termination Fault threshold for SDO0, when SD is set to HD rates (0). Combines with HDTFThresh0LSB in register 03h (default for combined value is 1000). 7:5 HDTFThresh0 4:0 AMP0 10000 10 SDO0 output amplitude in roughly 5 mV steps. 05h R/W OUTPUT0CTRL 06h R/W OUTPUT1 07h R/W OUTPUT1CTRL Bits Field Default Description 7 RSVD 0 Reserved as 0. Always write 0 to this bit. 6 FLOSOF 0 Force LOS to always OFF (signal never detected). This forces the device into either the mute or “add offset” state. The device will behave as if there is no signal regardless of the input. 0: LOS operates normally, muting of adding offset as specified by the MUTE bit. 1: Signal is never detected. Muting or adding offset is always in place as specified by the MUTE bit. 5 FLOSON 0 Force LOS to always ON (signal always detected). This prevents the device from muting or adding offset and makes the LOS have no effect on device operation. (The LOS bit in register 01h still reflects the state of LOS). 0: LOS operates normally, muting or adding offset as specified in the MUTE bit. 1: LOS never causes muting or the addition of offset. 4 LOSEN 0 Configures LOS to be combined with the ENABLE functionality. 0: Only the PD bits and ENABLE pin affect the power down state of the output drivers. 1: If the ENABLE pin is set to ground, it powers down the output drivers regardless of the state of LOS or the PD bits. With the ENABLE pin set to VCC, LOS=0 will power down the output drivers, and LOS=1 will leave the power down state dependent on the PD bits. 3 MUTE 0 Selects whether the device will MUTE when loss of signal is detected or add an offset to prevent self oscillation. When an input signal is detected (LOS=1), the device will operate normally. 0: Loss of signal will force a small offset to prevent self oscillation. 1: Loss of signal will force the channel to MUTE. 2:0 SDTFThresh0 010 Sets the Termination Fault threshold for SDO0, when SD is set to SD rates (1). Combines with SDTFThresh0LSB in register 03h (default for combined value is 0100). 7:5 HDTFThresh1 100 Sets the Termination Fault threshold for SDO1, when SD is set to HD rates (0). Combines with HDTFThresh1LSB in register 07h (default for combined value is 1000). 4:0 AMP1 10000 SDO1 output amplitude in roughly 5 mV steps. 7 HDTFThresh1LSB 0 Least Significant Bit for HDTFThresh1 detection threshold. Combines with HDTFThresh1 bits in register 06h. 6 SDTFThresh1LSB 0 Least Significant Bit for SDTFThresh1 detection threshold. Combines with SDTFThresh1 bits in register 07h. 5:3 RSVD 011 Reserved as 011. Always write 011 to these bits. 2:0 SDTFThresh1 010 Sets the Termination Fault threshold for SDO1, when SD is set to SD rates (1). Combines with SDTFThresh1LSB in bit 6 (default for combined value is 0100). 11 www.national.com LMH0307 Address R/W Name LMH0307 Address R/W Name 08h 09h 0Ah 0Bh 0Ch 0Dh R/W TEST R R R R R www.national.com REV TFCOUNT0P TFCOUNT0N TFCOUNT1P TFCOUNT1N Bits Field Default Description 7:5 CMPCMD 000 4:0 RSVD 00000 7:5 RSVD 000 Reserved 4:3 DIEREV 00 Die Revision 2:0 PARTID 010 Part Identifier. Note that single output devices (LMH0303) have the LSB=1. Dual output devices (LMH0307) have the LSB=0. 7:5 RSVD 000 Reserved 4:0 TFCOUNT0P 7:5 RSVD 4:0 TFCOUNT0N 7:5 RSVD 4:0 TFCOUNT1P 7:5 RSVD 4:0 TFCOUNT1N 00000 000 00000 000 00000 000 00000 12 Compare command. Determines whether the peak value or the current value of the Termination Fault counters is read in registers 0Ah-0Dh. 000: Resets compare value to 00; registers 0Ah-0Dh all show current counter values. Sets detection to look for MAX peak values. 001: Capture counter 0. Register 0Ah shows peak value. 010: Capture counter 1. Register 0Bh shows peak value. 011: Capture counter 2. Register 0Ch shows peak value. 100: Capture counter 3. Register 0Dh shows peak value. 101: Resets compare value to 1Fh. Sets detection to look for MIN peak values. 110, 111: Reserved Reserved as 00000. Always write 00000 to these bits. This is either the current value of TF Counter 0 P, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved This is either the current value of TF Counter 0 N, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved This is either the current value of TF Counter 1 P, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved This is either the current value of TF Counter 1 N, or the peak value of the counter, depending on CMPCMD in register 08h. LMH0307 Physical Dimensions inches (millimeters) unless otherwise noted 16-Pin LLP Order Number LMH0307SQ NS Package Number SQB16A 13 www.national.com LMH0307 3 Gbps HD/SD SDI Dual Cable Driver with Cable Detect Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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