TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP723 Series SP723 Series 5pF 8kV Diode Array RoHS Pb GREEN Description The SP723 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection of sensitive input circuits. The SP723 has 2 protection SCR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Overvoltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) to V+ or V-. The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ (Pin 8) or a -VBE diode threshold below V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input. Pinout SP723 (PDIP, SOIC) TOP VIEW IN 1 8 V+ IN 2 7 IN IN 3 6 IN V- 4 5 IN Functional Block Diagram V+ 8 3, 5-7 IN 1 IN 2 IN V- 4 Additional Information Datasheet Resources Features • ESD Interface per HBM Standards - IEC 61000-4-2, Direct Discharge........... 8kV (Level 4) - IEC 61000-4-2, Air Discharge................15kV (Level 4) - MIL-STD-3015.7..................................................25kV • Peak Current Capability - IEC 61000-4-5 8/20µs Peak Pulse Current........... ±7A - Single Transient Pulse, 100µs Pulse Width.......... ±4A • Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to......................... +30V - Differential Voltage Range to............................. ±15V • Fast Switching...............................................2ns Risetime • Low Input Leakages.............................2nA at 25ºC Typical • Low Input Capacitance......................................5pF Typical • An Array of 6 SCR/Diode Pairs • Operating Temperature Range....................-40ºC to 105ºC Applications Samples Life Support Note: Not Intended for Use in Life Support or Life Saving Applications The products shown herein are not designed for use in life sustaining or life saving applications unless otherwise expressly indicated. © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/20/13 Refer to Fig 1 and Table 1 for further details. Refer to Application Note AN9304 and AN9612 for further detail. • Microprocessor/Logic Input Protection • Analog Device Input Protection • Data Bus Protection • Voltage Clamp TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP723 Series Thermal Information Absolute Maximum Ratings Parameter Continuous Supply Voltage, (V+) - (V-) Forward Peak Current, IIN to VCC, IIN to GND (Refer to Figure 5) Peak Pulse Current, 8/20µs Rating +35 Units V ±4, 100µs A ±7 A Parameter Thermal Resistance (Typical, Note 1) Note: 160 o SOIC Package 170 o C/W C/W C -65 to 150 o 150 o 260 o C C 1. θJA is measured with the component mounted on an evaluation PC board in free air. Load Dump and Reverse Battery (Note 2) Electrical Characteristics Units oC/W PDIP Package Storage Temperature Range Maximum Junction Temperature (Plastic Package) Lead Temperature (Soldering 20-40s) (SOIC Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ESD Ratings and Capability (Figure 1, Table 1) Rating θJA TA = -40oC to 105oC, VIN = 0.5VCC , Unless Otherwise Specified Parameter Symbol Operating Voltage Range, VSUPPLY =[(V+)-(V-)] Test Conditions VSUPPLY Min Typ Max Units - 2 to 30 - V - 2 - V Forward Voltage Drop IIN=2A(Peak Pulse) IN to V- VFWDL IN to V+ VFWDH - 2 - V IIN -20 5 20 nA IQUIESCENT - 50 200 nA Note 3 - 1.1 - V VFWD/IFWD; Note 3 - 0.5 - Ω Input Leakage Current Quiescent Supply Current Equivalent SCR ON Threshod Equivalent SCR ON Resistance Input Capacitance CIN - 5 - PF Input Switching Speed tON - 2 - ns Notes: 2.In automotive ans battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, acurrent limiting resistor should be connectied in series between the external supply and the SP723 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- Pins to ground are recommended. 3.Refer to the Figure 3 graph for determine peak current and dessipation under EOS conditions. Typical Application of the SP723 (Application as an Input Clamp for Over-voltage, Greater than 1VBE Above V+ or less than -1VBE below V-) +VCC +VCC INPUT DRIVERS OR SIGNAL SOURCES LINEAR OR DIGITAL IC INTERFACE IN 1 - 3 IN 5 - 7 TO +VCC V+ SP723 V- SP723 INPUT PROTECTION CIRCUIT (1 OF 6 SHO WN) FIGURE 4. TYPICAL APPLICA TION OF THE SP723 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1VBE ABOVE V+ OR LESS THAN -1V BE BELO W V- © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/20/13 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP723 Series ESD Capability ESD capability is dependent on the application and defined test standard.The evaluation results for various test standards and methods based on Figure 1 are shown in Table 1. Figure 1: Electrostatic Discharge Test R1 The SP723 has a Level 4 HBM capability when tested as a device to the IEC 61000-4-2 standard. Level 4 specifies a required capability greater than 8kV for direct discharge and greater than 15kV for air discharge. CHARGE SWITCH Table 1: ESD Test Conditions Standard 40 0 0 600 800 800 1000 1000 FORWARD FORWARD SCR VOLTAGE SCR VOLTAGE DROP (mV) DROP (mV) © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/20/13 1200 330 Ω 150pF 15kV 330 Ω 150pF 8kV 1.5k Ω 100pF 25kV 1.5k Ω 100pF 10kV EIAJ IC121 Machine Model 0k Ω 200pF 2kV EIAJ IC121 Machine Model 0kΩ 200pF 1kV 5 TA = 25ºC TA = 25ºC SINGLE PULSE SINGLE PULSE 4 3 2 1 0 600 ±VD Modified HBM FORWARD SCR CURRENT (A) 80 CD Standard HBM 5 FORWARD SCR CURRENT (A) 40 FORWARD SCT CURRENT (mA) FORWARD SCT CURRENT (mA) 80 RD Figure 3: High Current SCR Forward Voltage Drop Curve 200 TA = 25°C TA = 25°C SINGLE PULSE SINGLE PULSE 120 Type/Mode IEC 1000-4-2 HBM, Air Discharge (Level 4) HBM, Direct Discharge Figure 2: Low Current SCR Forward Voltage Drop Curve 120 IN DUT FIGURE 1. ELECTR OSTATIC DISCHARGE TEST MILSTD-3015.7 160 CD IEC 1000-4-2: R 1 50 to 100M MIL-STD-3015.7: R 1 1 to 10M For the SP723 EIAJ IC121 Machine Model (MM) standard, the ESD capability is typically greater than 2kV from 200pF with no series resistance. 160 DISCHARGE SWITCH H.V. SUPPLY VD For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit” method of ESD testing, the V+ and V- pins have a return path to ground and the SP723 ESD capability is typically greater than 25kV from 100pF through 1.5kΩ. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing, the ESD voltage capability is greater than 10kV. 200 RD 1200 4 3 2 I FWD EQUIV. SAT.EQUIV. ON. SAT. ON. THRESHOLD THRESHOLD ~ 1.1V ~ 1.1V 1 0 0 0 1 1 V FWD 2 I FWD V FWD 2 FORWARD FORWARD SCR VOLTAGE SCR VOLTAGE DROP (V)DROP (V) 3 3 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP723 Series Peak Transient Current Capability of the SP723 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP723’s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure 4. Figure 4: T ypical SP723 Peak Current Test Circuit with a Variable Pulse Width Input The test circuit of Figure 4 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP723 ‘IN’ input pin and the (+) current pulse input goes to the SP723 V- pin. The V+ to V- supply of the SP723 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 5 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. Note that adjacent input pins of the SP723 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin. VX CURRENT SENSE (-) (+) 3 IN VOLTAGE PROBE V+ 8 1 IN 2 IN SP723 + IN 7 IN 6 C1 - IN 5 4 V- R 1 ~ 10 TYPICAL VX ADJ. 10V/ATYPICAL C1 ~ 100 µF Figure 5: S P723 Typical Single Peak Current Pulse Capability Showing the Measured Point of Overstress in Amperes vs pulse width time in milliseconds 14 CAUTION: SAFE OPERATING CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EACH CURVE. 12 PEAK CURRENT (A) The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 25ºC and 105ºC and a 15V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of Figure 5. - VARIABLE TIME DURATION CURRENT PULSE GENERA TOR R1 + TA = 25°C 10 V+ TO V-SUPPLY = 15V 8 6 TA = 105°C 4 2 0 0.001 0.01 0.1 1 10 100 1000 PULSE WIDTH TIME (ms) © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/20/13 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP723 Series Soldering Parameters Pb – Free assembly Pre Heat - Temperature Min (Ts(min)) 150°C - Temperature Max (Ts(max)) 200°C - Time (min to max) (ts) 60 – 180 secs Average ramp up rate (Liquidus) Temp (TL) to peak 5°C/second max TS(max) to TL - Ramp-up Rate 5°C/second max Reflow - Temperature (TL) (Liquidus) 217°C - Temperature (tL) 60 – 150 seconds 260+0/-5 °C Time within 5°C of actual peak Temperature (tp) 20 – 40 seconds Ramp-down Rate 5°C/second max Time 25°C to peak Temperature (TP) 8 minutes Max. Do not exceed 260°C Critical Zone TL to TP Ramp-up TL TS(max) tL Ramp-do Ramp-down Preheat TS(min) 25 Peak Temperature (TP) tP TP Temperature Reflow Condition tS time to peak temperature Time Package Dimensions — Dual-In-Line Plastic Packages (PDIP) N Package E1 INDEX AREA 1 2 3 N/2 -B- Pins 8 JEDEC MS-001 Millimeters -AD E BASE PLANE -C- SEATING PLANE Min A2 A L D1 e B1 D1 B CL eA A1 eC 0.010 (0.25) M C A B S C eB NOTES: Notes: 1. ControllingDimensions:INCH. In case of conflictbetween 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, English and Metric dimensions, the inch dimensions control. the inch dimensions control. 2. Dimensioningand tolerancingper ANSI Y14.5M-1982. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbolsare definedin the “MOSeries SymbolList”in Section 3. Symbols in the “MO 2.2are ofdefined Publication No. 95. Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with thewith package seated in JEDEC seating plane 4. Dimensions A, A1 and L are measured the package seated gauge GS-3. in JEDEC seating plane gauge GS-3. 5. D, D1, andD1, E1 and dimensions do not include flash or protrusions. Mold flash or 5. D, E1 dimensions do notmold include mold flash or protruprotrusions shall notflash exceed inch (0.25mm). sions. Mold or0.010 protrusions shall not exceed 0.010 inch 6. E and e (0.25mm). A are measured with the leads unconstrained to be perpendicular to datum -C- 6. . E and e are measuredwiththe leads constrainedto be perA eC are measured at the-Clead 7.eB and pendicular to datum . tips with the leads uncon-strained. eC must be zero or greater. 7. e and e are measuredat the lead tips withthe leads unconB C 8. B1 maximum dimensions do zero not include dambar protrusions. Dambar protrusions shall not or greater. strained. eC must be exceed 0.010 inch (0.25mm). 8. B1 maximumdimensionsdo not includedambarprotrusions. 9. N is theDambar maximum number of terminal positions. protrusions shall not exceed 0.010 inch (0.25mm). 10.Corner leads (1,maximum N, N/2 andnumber N/2 + 1) E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 9. N is the offor terminal positions. dimension of 0.030 0.045 inchand (0.76 - 1.14mm). 10. Corner leads- (1, N, N/2 N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimensionof 0.030 - 0.045 inch (0.76 - 1.14mm). © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/20/13 PDIP A A1 A2 B B1 C D D1 E E1 e eA eB L N Max 5.33 0.39 2.93 4.95 0.356 0.558 1.15 1.77 0.204 0.355 9.01 10.16 0.13 7.62 8.25 6.1 7.11 2.54 BSC 7.62 BSC 10.92 2.93 3.81 8 Inches Min Max 0.210 0.015 0.115 0.195 0.014 0.022 0.045 0.070 0.008 0.014 0.355 0.400 0.005 0.300 0.325 0.240 0.280 0.100 BSC 0.300 BSC 0.430 0.115 0.150 8 Notes 4 4 8, 10 5 5 6 5 6 7 4 9 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP723 Series Package Dimensions — Small Outline Plastic Packages (SOIC) N INDEX AREA H 0.25(0.010) M B M E Package SOIC Pins 8 JEDEC -B- MS-012 Millimeters 1 2 3 -A- Max Min Max 1.35 1.75 0.0532 0.0688 A1 0.10 0.25 0.0040 0.0098 - B 0.33 0.51 0.013 0.020 9 A h x 45o A D -C- e μ A1 B C 0.10(0.004) - C 0.19 0.25 0.0075 0.0098 - D 4.80 5.00 0.1890 0.1968 3 E 3.80 4.00 0.1497 0.1574 4 1.27 BSC e 0.25(0.010) M C A M B S Notes Min L SEATING PLANE Inches 0.050 BSC - Notes: H 5.80 6.20 0.2284 0.2440 - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. h 0.25 0.50 0.0099 0.0196 5 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. L 0.40 1.27 0.016 0.050 6 3.NOTES: Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. N 4. Dimension “E” does not include interlead flash or protrusions. Inter-lead flash PublicationNumber95. and protrusions shall not exceed 0.25mm (0.010 inch) per side. µ 8º 0º 1. Symbolsare definedin the “MOSeries SymbolList”in Section 2.2 of Y14.5M-1982. 5. 2. TheDimensioning chamfer on the and bodytolerancing is optional. Ifper it is ANSI not present, a visual index feature must be located “D” within thenot crosshatched area.flash, protrusionsor gate burrs. 3. Dimension does includemold and gate burrs not exceed 0.15mm(0.006 6. “L” Mold is the flash, length protrusion of terminal for soldering to a shall substrate. side.of terminal positions. 7. “N”inch) is theper number Dimension “E” notforinclude interlead 8. 4. Terminal numbers aredoes shown reference only. flash or protrusions.Interflash “B” and protrusions shall not exceed inch) per 9. Thelead eadl width , as measured 0.36mm (0.014 inch)0.25mm or greater(0.010 above the side. seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 5. The chamfer on the bodyis optional. If itinch is not present,are a visual 10.Controlling dimension:MILLIMETER. Converted dimensions not index necessarily featureexact. must be located withinthe crosshatchedarea. 6. “L” is the lengthof terminalfor solderingto a substrate. 7. “N” is the numberof terminalpositions. Part Numbering System 8. Terminal numbersare shownfor reference only. 9. The lead width“B”, as measured0.36mm (0.014 inch) or greater SPplane, 723shall * above the seating a maximum value of ** not * exceed 0.61mm (0.024 inch). TVS Diode Arrays 10. Controlling dimension:MILLIMETER. Convertedinch dimensions ® G=Green Diodes) exact. are(SPA not necessarily P=Lead Free T= Tape and Reel Series Package AB = 8 Ld SOIC AP = 8 Ld PDIP 8 8 0º 7 8º - Product Characteristics Lead Plating Matte Tin Lead Material Copper Alloy Lead Coplanarity 0.004 inches (0.102mm) Substitute Material Silicon Body Material Molded Epoxy Flammability UL 94 V-0 Ordering Information Part Number Temp. Range (ºC) Package Environmental Informaton Marking Min. Order SP723APP -40 to 105 8 Ld PDIP Lead-free SP723AP(P) 1 2000 SP723ABG -40 to 105 8 Ld SOIC Green SP723A(B)G 2 1960 SP723ABTG -40 to 105 8 Ld SOIC Tape and Reel Green SP723A(B)G 2500 2 Notes: 1. SP723AP(P) means device marking either SP723AP or SP723APP. 2. SP723A(B)G means device marking either SP723AG or SP723ABG which are good for types SP723ABG and SP723ABTG. © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/20/13