LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP The MPC940L is a 1:18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS compatible and feature the drive strength to drive 50 Ω series or parallel terminated transmission lines. With output-to-output skews of 150 ps, the MPC940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5 V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. For a similar device at a lower price/performance point, the reader is referred to the MPC9109. • • • • • • • LVPECL or LVCMOS Clock Input 2.5 V LVCMOS Outputs for Pentium II Microprocessor Support 150 ps Maximum Output-to-Output Skew Maximum Output Frequency of 250 MHz 32-Lead LQFP Packaging 32-Lead Pb-Free Package Available Dual or Single Supply Device: • Dual VCC Supply Voltage, 3.3 V Core and 2.5 V Output • Single 3.3 V VCC Supply Voltage for 3.3 V Outputs • Single 2.5 V VCC Supply Voltage for 2.5 V I/O MPC940L MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 With a low output impedance (≈20 Ω), in both the HIGH and LOW logic states, the output buffers of the MPC940L are ideal for driving series terminated transmission lines. With a 20 Ω output impedance the 940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet. AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_SEL pin will select the LVCMOS level clock input. All inputs of the MPC940L have internal pullup/pulldown resistors so they can be left open if unused. The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP has a 7x7 mm body size with a conservative 0.8 mm pin spacing. Pentium II is a trademark of Intel Corporation. IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 1 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP LOGIC DIAGRAM PECL_CLK PECL_CLK 0 LVCMOS_CLK 1 Q0 16 LVCMOS_CLK_SEL (Internal Pulldown) Q1–Q16 Q17 Q6 Q7 Q8 VCCI Q9 Q10 Q11 GND Pinout: 32-Lead LQFP (Top View) 24 23 22 21 20 19 18 17 GNDO 25 16 VCCO FUNCTION TABLE Q5 26 15 Q12 LVCMOS_CLK_SEL Input Q4 27 14 Q13 0 1 PECL_CLK LVCMOS_CLK Q3 28 13 Q14 VCCO 29 12 GNDO Q2 30 11 Q15 Supply Pin Voltage Level Q1 31 10 Q16 VCCI VCCO 2.5 V or 3.3 V ± 5% 2.5 V or 3.3 V ± 5% Q0 32 9 Q17 4 5 GNDI LVCMOS_CLK LVCMOS_CLK_SEL PECL_CLK 6 7 8 VCCO 3 VCCI 2 PECL_CLK 1 GNDO MPC940L POWER SUPPLY VOLTAGES Table 1. Pin Configurations Pin PECL_CLK PECL_CLK LVCMOS_CLK I/O Type Function Input LVPECL Reference Clock Input Input LVCMOS Alternative Reference Clock Input LVCMOS_CLK_SEL Input LVCMOS Selects Clock Source Q0–Q17 Output LVCMOS Clock Outputs VCCO Supply Output Positive Power Supply VCCI Supply Core Positive Power Supply GNDO Supply Output Negative Power Supply GNDI Supply Core Negative Power Supply IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 2 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP Table 2. Absolute Maximum Ratings(1) Symbol Min Max Unit Supply Voltage –0.3 3.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA 125 °C VCC TStor Parameter Storage Temperature Range –40 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%) Symbol Characteristic Min VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK VCMR VOH Output HIGH Voltage VOL Output LOW Voltage Typ Max Unit VCCI V 0.8 V 500 1000 mV VCCI – 1.4 VCCI – 0.6 V 2.4 2.4 V IOH = –20 mA 0.5 V IOL = 20 mA ±200 µA IIN Input Current CIN Input Capacitance 4.0 pF Cpd Power Dissipation Capacitance 10 pF ZOUT ICC Output Impedance 18 Maximum Quiescent Supply Current Condition per output 23 28 Ω 0.5 1.0 mA Max Unit 250 MHz Table 4. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 3.3 V ±5%) Symbol Characteristic Min Typ Condition Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK ≤ 150 MHz CMOS_CLK ≤ 150 MHz 2.0 1.8 2.7 2.5 3.4 3.0 ns tPLH Propagation Delay PECL_CLK > 150 MHz CMOS_CLK > 150 MHz 2.0 1.8 2.9 2.4 3.7 3.2 ns tsk(o) Output-to-Output Skew PECL_CLK CMOS_CLK 150 150 ps tsk(pp) Part-to-Part Skew PECL_CLK ≤ 150 MHz CMOS_CLK ≤ 150 MHz 1.4 1.2 ns Note (1) tsk(pp) Part-to-Part Skew PECL_CLK > 150 MHz CMOS_CLK > 150 MHz 1.7 1.4 ns Note (1) tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK 850 750 ps Note (2) DC Output Duty Cycle fCLK < 134 MHz fCLK ≤ 250 MHz 55 60 % % Input DC = 50% Input DC = 50% tr, tf Output Rise/Fall Time 1.1 ns 0.5 – 2.4 V 45 40 50 50 0.3 1. Across temperature and voltage ranges. Includes output skew. 2. For specific temperature and voltage. Includes output skew. IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 3 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP Table 5. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 2.5 V ±5%) Symbol Characteristic Min VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK VCMR VOH Output HIGH Voltage VOL Output LOW Voltage Typ Max Unit VCCI V 0.8 V 500 1000 mV VCCI – 1.4 VCCI – 0.6 V 2.4 1.8 V IOH = –12 mA 0.5 V IOL = 12 mA ±200 µA IIN Input Current CIN Input Capacitance 4.0 pF Cpd Power Dissipation Capacitance 10 pF Output Impedance 23 Ω Maximum Quiescent Supply Current 0.5 ZOUT ICC Condition per output 1.0 mA Max Unit 250 MHz Table 6. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3 V ±5%; VCCO = 2.5 V ±5%) Symbol Characteristic Min Typ Condition Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK ≤ 150 MHz CMOS_CLK ≤ 150 MHz 2.0 1.7 2.8 2.5 3.5 3.0 ns tPLH Propagation Delay PECL_CLK > 150 MHz CMOS_CLK > 150 MHz 2.0 1.8 2.9 2.5 3.8 3.3 ns tsk(o) Output-to-Output Skew PECL_CLK CMOS_CLK 150 150 ps tsk(pp) Part-to-Part Skew PECL_CLK ≤ 150 MHz CMOS_CLK ≤ 150 MHz 1.5 1.3 ns Note (1) tsk(pp) Part-to-Part Skew PECL_CLK > 150 MHz CMOS_CLK > 150 MHz 1.8 1.5 ns Note (1) tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK 850 750 ps Note (2) DC Output Duty Cycle fCLK < 134 MHz fCLK ≤ 250 MHz 55 60 % % Input DC = 50% Input DC = 50% tr, tf Output Rise/Fall Time 1.2 ns 0.5 – 1.8 V 45 40 50 50 0.3 1. Across temperature and voltage ranges. Includes output skew. 2. For specific temperature and voltage. Includes output skew. IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 4 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP Table 7. DC Characteristics (TA = 0° to 70°C, VCCI = 2.5 V ±5%; VCCO = 2.5 V ±5%) Symbol Characteristic Min VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK VCMR VOH Output HIGH Voltage VOL Output LOW Voltage Typ Max Unit VCCI V 0.8 V 500 1000 mV VCCI – 1.0 VCCI – 0.6 V 2.0 1.8 V IOH = –12 mA 0.5 V IOL = 12 mA ±200 µA IIN Input Current CIN Input Capacitance 4.0 pF Cpd Power Dissipation Capacitance 10 pF ZOUT ICC Output Impedance 18 Maximum Quiescent Supply Current Condition per output 23 28 Ω 0.5 1.0 mA Max Unit Table 8. AC Characteristics (TA = 0° to 70°C, VCCI = 2.5 V ±5%; VCCO = 2.5 V ±5%) Symbol Characteristic Min Typ Condition Fmax Maximum Input Frequency 200 MHz tPLH Propagation Delay PECL_CLK ≤ 150 MHz CMOS_CLK ≤ 150 MHz 2.6 2.3 4.0 3.1 5.2 4.0 ns tPLH Propagation Delay PECL_CLK > 150 MHz CMOS_CLK > 150 MHz 2.8 2.3 3.8 3.1 5.0 4.0 ns tsk(o) Output-to-Output Skew PECL_CLK CMOS_CLK 200 200 ps tsk(pp) Part-to-Part Skew PECL_CLK ≤ 150 MHz CMOS_CLK ≤ 150 MHz 2.6 1.7 ns Note (1) tsk(pp) Part-to-Part Skew PECL_CLK > 150 MHz CMOS_CLK > 150 MHz 2.2 1.7 ns Note (1) tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK 1.2 1.0 ns Note (2) DC Output Duty Cycle fCLK < 134 MHz fCLK ≤ 200 MHz 55 60 % % Input DC = 50% Input DC = 50% tr, tf Output Rise/Fall Time 1.2 ns 0.5 - 1.8 V 45 40 50 50 0.3 1. Across temperature and voltage ranges. Includes output skew. 2. For specific temperature and voltage. Includes output skew. IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 5 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP MPC940L DUT ZO = 50Ω Pulse Generator Z = 50Ω ZO = 50Ω RT = 50Ω RT = 50Ω VTT VTT Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V MPC940L DUT ZO = 50Ω Differential Pulse Generator Z = 50Ω ZO = 50Ω RT = 50Ω RT = 50Ω VTT VTT Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V VCC PCLK_CLK VCMR VPP PCLK_CLK VCC ÷ 2 LVCMOS_CLK GND VCC VCC ÷2 Q GND GND tPD tPD Figure 4. LVCMOS Propagation Delay (tPD) Test Reference Figure 3. Propagation Delay (tPD) Test Reference tP VCC VCC ÷ 2 Q VCC VCC ÷ 2 VCC ÷ 2 GND GND VCC VOH T0 VCC ÷ 2 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device. Figure 6. Output-to-Output Skew TSK(O) Figure 5. Output Duty Cycle (DC) VCC = 3.3 V VCC = 2.5 V tF VCC = 3.3 V VCC = 2.5 V 2.4 1.8 V 2.0 1.7 V 0.55 0.6 V 0.8 0.7 V tR tF Figure 7. Output Transition Time Test Reference IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP GND tSK(O) tR Figure 8. Input Transition Time Test Reference 6 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 7 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 8 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 9 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Termperature MPC940LFA MPC940L 32 Lead LQFP Tray 0°C to 70°C MPC940LFAR2 MPC940L 32 Lead LQFP 2500 Tape & Reel 0°C to 70°C MPC940LAC MPC940LAC Lead-Free, 32 Lead LQFP Tray 0°C to 70°C MPC940LACR2 MPC940LAC Lead-Free, 32 Lead LQFP 2500 Tape & Reel 0°C to 70°C IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP 10 MPC940L REV 7 JUNE 5, 2007 MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA