Revised August 2000 100354 Low Power 8-Bit Register with Cut-Off Drivers General Description The 100354 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN input goes HIGH it overrides all other inputs, disables the clock, and the Q outputs maintain the last state. A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cutoff state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100354 outputs are designed to drive a doubly terminated 50Ω transmission line (25Ω load impedance). All inputs have 50 kΩ pull-down resistors. Features ■ Cut-off drivers ■ Drives 25Ω load ■ Low power operation ■ 2000V ESD protection ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range Ordering Code: Order Number Package Number 100354PC N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100354QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100354QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names D0–D7 Description 28-Pin PLCC Data Inputs CEN Clock Enable Input CP Clock Input (Active Rising Edge) OEN Output Enable Input Q0–Q7 Data Outputs © 2000 Fairchild Semiconductor Corporation DS010610 www.fairchildsemi.com 100354 Low Power 8-Bit Register with Cut-Off Drivers October 1989 100354 Truth Table Inputs Dn CEN L L H L X X X Outputs OEN X X H X L NC X X X H Cutoff L L L H L L NC H L NC H = HIGH Voltage Level L = LOW Voltage Level NC = No Change X = Don’t Care Cutoff = Lower-than-LOW State = LOW-to-HIGH Transition Logic Diagram www.fairchildsemi.com Qn CP 2 Storage Temperature (TSTG) VEE Pin Potential to Ground Pin Recommended Operating Conditions −65°C to +150°C +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V −5.7V to −4.2V Supply Voltage (VEE) ≥2000V ESD (Note 2) −40°C to +85°C Industrial −100 mA Output Current (DC Output HIGH) 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) 100354 Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 VOL Output LOW Voltage −1830 −1705 −1620 VOHC Output HIGH Voltage −1035 VOLC Output LOW Voltage −1610 VOLZ Cutoff LOW Voltage −1950 VIH Input HIGH Voltage −1165 VIL Input LOW Voltage −1830 IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current Units mV mV Conditions VIN =VIH (Max) Loading with or VIL (Min) 25Ω to −2.0V VIN = VIH (Min) Loading with or VIL (Max) 25Ω to −2.0V mV VIN = VIH (Min) OEN = HIGH −870 mV Guaranteed HIGH Signal for All Inputs −1475 mV Guaranteed LOW Signal for All Inputs µA VIN = VIL (Min) or VIL (Max) 240 µA VIN = VIH (Max) Inputs Open −202 −105 −209 −105 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100354 Commercial Version (Continued) DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter Min fMAX Toggle Frequency tPLH Propagation Delay tPHL CP to Output tPZH TC = +25°C Max Min 250 Max 250 TC = +85°C Min Units Conditions Max 250 MHz 1.40 3.00 1.40 3.00 1.50 3.10 Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20 tPHZ OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 tTLH Transition Time tTHL 20% to 80%, 80% to 20% 0.45 2.00 0.45 2.00 0.45 2.00 tS Setup Time ns ns Figures 1, 4 Figures 1, 4 (Note 4) Figures 3, 7 (Note 4) ns Figures 1, 4 ns Figures 2, 5 Dn 1.10 1.10 1.10 CEN (Disable Time) 0.40 0.40 0.40 CEN (Release Time) 1.10 1.10 1.10 0.10 0.10 0.10 ns Figures 1, 6 2.00 2.00 2.00 ns Figures 1, 4 tH Hold Time tPW(H) Pulse Width HIGH Dn CP Note 4: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter Min TC = +25°C Max Min 1.40 2.80 Min 1.40 2.80 1.50 2.90 fMAX Toggle Frequency Propagation Delay tPHL CP to Output tPZH Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00 tPHZ OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 tTLH Transition Time tTHL 20% to 80%, 80% to 20% 0.45 1.90 0.45 1.90 0.45 1.90 tS Setup Time MHz ns ns Conditions Figures 1, 4 Figures 1, 4 (Note 5) Figures 3, 7 (Note 5) ns Figures 1, 4 ns Figures 2, 5 Dn 1.00 1.00 1.00 0.30 0.30 0.30 CEN (Release Time) 1.00 1.00 1.00 0.00 0.00 0.00 ns Figures 1, 6 2.00 2.00 2.00 ns Figures 1, 4 Hold Time Pulse Width HIGH CP tOSHL 250 Units CEN (Disable Time) Dn tPW(H) 250 Max tPLH tH 250 TC = +85°C Max Maximum Skew Common Edge Output-to-Output Variation 280 280 280 ps (Note 6) 340 340 340 ps (Note 6) 340 340 340 ps (Note 6) 250 250 250 ps (Note 6) Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Clock to Output Path Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 4 100354 Industrial Version PLCC DC Electrical Characteristics (Note 7) VEE=−4.2V to −5.7V, VCC= VCCA= GND, TC=−40°C to +85°C TC = −40°C Symbol Parameter Min Max TC = 0° to +85°C Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 VOL Output LOW Voltage −1830 −1575 −1830 −1620 −1095 −1035 VOHC Output HIGH Voltage VOLC Output LOW Voltage −1565 −1610 VOLZ Cutoff LOW Voltage −1900 −1950 Units mV mV mV Conditions VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH (Min) Loading with or VIL (Max) 50Ω to −2.0V VIN = VIH (Min) OEN = HIGH or VIL (Max) VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current for All Inputs for All Inputs µA 0.50 240 240 µA VIN = VIL (Min) VIN = VIH (Max) Inputs Open −202 −105 −202 −105 −209 −105 −209 −105 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = −40°C Parameter fMAX Toggle Frequency tPLH Propagation Delay tPHL CP to Output tPZH Min TC = +25°C Max Min 250 Max 250 TC = +85°C Min Max 250 MHz 1.40 2.80 1.40 2.80 1.50 2.90 Propagation Delay 1.50 4.10 1.60 4.00 1.60 4.00 tPHZ OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 tTLH Transition Time tTHL 20% to 80%, 80% to 20% 0.45 1.90 0.45 1.90 0.45 1.90 tS Setup Time tH ns ns Conditions Figures 1, 4 Figures 1, 4 (Note 8) Figures 3, 5 (Note 8) ns Figures 1, 4 ns Figures 2, 5 Dn 1.00 1.00 CEN (Disable Time) 0.30 0.30 0.30 CEN (Release Time) 1.00 1.00 1.00 0.00 0.00 0.00 ns Figures 1, 6 2.00 2.00 2.00 ns Figures 1, 4 Hold Time Dn tPW(H) Units Pulse Width High CP 1.00 Note 8: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 5 www.fairchildsemi.com 100354 Test Circuitry FIGURE 1. Toggle Frequency Test Circuit FIGURE 2. AC Test Circuit FIGURE 3. AC Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 25Ω to GND CL = Fixture and stray capacitance ≤ 3 pF www.fairchildsemi.com 6 100354 Switching Waveforms FIGURE 4. Propagation Delay (Clock) and Transition Times FIGURE 5. Setup and Pulse Width Times Notes: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 6. Data Setup and Hold Time Note: The output AC measurement point for cut-off propagation delay testing = the 50% voltage point between active VOL and VOH. FIGURE 7. Cutoff Times 7 www.fairchildsemi.com 100354 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 8 100354 Low Power 8-Bit Register with Cut-Off Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com