IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion – – – – – – – The LVC16374A 16-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable (OE) and clock (CLK) controls are organized to operate this device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16374A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. Drive Features for LVC16374A: – High Output Drivers: ±24mA – Reduced system switching noise The LVC16374A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1 OE 1 2 OE 48 2 CLK 1 CLK 1D1 47 D 2D 1 2 C 24 25 36 D 13 C 1Q 1 2Q 1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS EXTENDED COMMERCIAL TEMPERATURE RANGE OCTOBER 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4752/1 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (1) Symbol VTERM Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 Unit V 1 OE 1 48 1 CLK TSTG Storage Temperature – 65 to +150 °C 1Q 1 2 47 1D 1 IOUT DC Output Current – 50 to +50 mA 1Q 2 3 1D 2 4 45 GND Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through mA GND IIK IOK ICC – 50 46 ±100 mA ISS each VCC or GND 1Q 3 5 44 1D 3 1Q 4 6 V CC 7 42 V CC 1Q 5 8 41 1D 5 1Q 6 9 40 1D 6 GND 10 39 GND 1Q 7 11 38 1D 7 37 1D 8 36 2D 1 43 1D 4 2Q 1 SO48-1 12 SO48-2 13 SO48-3 2Q 2 14 35 2D 2 GND 15 34 GND 16 33 2D 3 17 32 2D 4 18 31 V CC 2Q 5 19 30 2D 5 2Q 6 20 29 2D 6 GND 21 28 GND 2Q 7 22 27 2D 7 23 26 2D 8 24 25 2 CLK 1Q 8 2Q 3 2Q 4 V CC 2Q 8 2 OE LVC Link NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25oC, f = 1.0MHz) Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 6.5 8 pF VIN = 0V 6.5 8 pF CI/O LVC Link NOTE: 1. As applicable to the device type. FUNCTION TABLE (each flip-flop) (1) Inputs xDx SSOP/ TSSOP/ TVSOP TOP VIEW PIN DESCRIPTION Pin Names xDx Data Inputs xCLK Clock Inputs xQx 3-State Outputs xOE 3-State Output Enable Inputs (Active LOW) Outputs xCLK xOE xQx X L H Z X H H Z L L L H ↑ ↑ L L H L H Q0 H L L Q0 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition Q0 = Output level of Q before the indicated steady-stte input conditions were established. Description c 1998 Integrated Device Technology, Inc. Symbol CIN 2 DSC-123456 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Test Conditions VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 ∆ICC Quiescent Power Supply Current Variation — — 500 One input at VCC - 0.6V other inputs at VCC or GND µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. 3 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per Flip-Flop Outputs enabled CPD Power Dissipation Capacitance per Flip-Flop Outputs disabled Test Conditions CL = 0pF, f = 10Mhz SWITCHING CHARACTERISTICS OVER OPERATING RANGE VCC = 2.7V Symbol Parameter fMAX Typical 58 Unit pF 24 pF (1) VCC = 3.3V±0.3V Min. 150 Max. — Min. 150 Max. — Unit MHz — 4.9 1.5 4.5 ns — 5.3 1.5 4.6 ns — 6.1 1.5 5.5 ns 1.9 — 1.9 — ns tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay xCLK to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Set-up Time HIGH or LOW, xDx to xCLK tH Hold Time HIGH or LOW, xDx after xCLK 1.1 — 1.1 — ns tW xCLK Pulse Width HIGH or LOW 3.3 — 3.3 — ns tSK(o) Output Skew (2) — — — 500 ps NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF t PHL V IH VT 0V ENABLE AND DISABLE TIMES V LOAD V IN t PLH DISABLE ENABLE GND V IH CONTROL INPUT V OUT VT tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT V OH VT V OL LVC Link Open Pulse (1, 2) Generator tPHL OPPOSITE PHASE INPUT TRANSITION TEST CIRCUITS FOR ALL OUTPUTS 500 Ω t PLH OUTPUT LVC Link V CC V IH VT 0V SAME PHASE INPUT TRANSITION CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 0V tPLZ V LOAD/2 V LOAD/2 VT V OL+ V LZ V OL tPHZ VT V OH V OH-V HZ 0V 0V LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION SET-UP, HOLD, AND RELEASE TIMES Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD DATA INPUT tSU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIMING INPUT GND tREM ASYNCHRONOUS CONTROL Open LVC Link SYNCHRONOUS CONTROL OUTPUT SKEW - tsk (x) t SU tH LVC Link V IH INPUT VT 0V tPHL1 tPLH1 PULSE WIDTH V OH OUTPUT 1 tSK (x) tSK (x) LOW -HIGH-LOW PULSE VT V OL tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT LVC Link t PLH2 t PHL2 tSK (x) = tPLH2 - tPLH1 or t PHL2 - tPHL1 LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link 5 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX LVC Tem p. R ange X XX XXXX XX Bus-Hold Fam ily Device Type Package PV PA PF Shrink S m all Outline Package (S O 48-1) Thin Shrink Sm all O utline Packag e (SO 48-2) Thin Very Sm all O utline Package (SO 48-3) 374A 16-Bit Edge-Triggered D-Type Flip-Flop with 3-State O utputs, 5 volt Tolerant I/O 16 Double-Density with Resistors, ±24m A Blank No Bus-hold 74 -40°C to +85 °C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6