AOZ5019
High-Current, High-Performance
DrMOS Power Module
General Description
Features
The AOZ5019 is a high efficiency synchronous buck
power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The high side MOSFET has low
capacitance and gate charge for fast switching with low
duty cycle operation. The low side MOSFET has ultra low
RDS(ON) to minimize conduction losses.
4.5 V to 25 V input voltage range
The AOZ5019 is intended for use with TTL and tri-state
compatible, which allows both power MOSFETs to be
turned off.
Diode Emulation mode of operation
4.5 V to 5.5 V driver supply range
Up to 30 A output current
Up to 1.5 MHz PWM operation
Tri-state PWM input
Undervoltage protection
Integrated boot supply diode
Small 5x3.5 QFN-23L package
A number of features are provided making the AOZ5019
a highly versatile power module. The boot supply diode is
integrated in the driver. The low side MOSFET can be
driven into diode emulation mode to provide
asynchronous operation when required. The pin-out is
optimized for low inductance routing of the converter
keeping the parasitics and their effects to the minimum.
Applications
Servers
Notebook computers
VRMs for motherboards
Point of load DC/DC converters
Memory and graphic cards
Video gaming consoles
Typical Application Circuit
AOZ5019
+5V
VCC
VIN
VIN
5V to 25V
BOOT
Cboot
PWM
Controller
Drive Logic
and
Dead Time
Control
PWM
SMOD
EN
Lout
VSWH
Cin
CGND
Cout
PGND
CGND
Rev. 2.1 April 2014
VOUT
PGND
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Page 1 of 13
AOZ5019
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ5019QI
-40 °C to +85 °C
5x3.5 QFN-23L
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
PGND
PGND
GL
CGND
VIN
EN
PWM
Pin Configuration
1
SMOD
VSWH
VCC
BOOT
VSWH
VIN
GH
VSWH
PGND
VSWH
PGND
PGND
PGND
PGND
VIN
VIN
VIN
VSWH
5x3.5 QFN-23
(Top View)
Rev. 2.1 April 2014
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Page 2 of 13
AOZ5019
Pin Description
Pin Number
Pin Name
Pin Function
1
SMOD
Skip Mode input. When the pin is held active low, Diode Emulation or Skip Mode is enabled for
the LS FET.
2
VCC
3
BOOT
4
GH
5
VSWH
6, 7, 8
VIN
9, 10, 11, 12,
17, 18
PGND
Power ground.
13, 14, 15, 16
VSWH
Switching or phase node connected to source of high side MOSFET and drain of the low side
MOSFET. Electrically attached to the LS FET drain tab.
19
GL
20
CGND
Control or analog ground for return of control signals and bypass capacitors.
21
VIN
Power input to the switching MOSFETs. Attached to the HS FET drain tab.
22
EN
Disable pin for the controller. Both gates are held active low when EN is grounded.
23
PWM
Control and Driver supply input. Nominal 5 V.
Gate drive supply for the HS FET. Nominal 5 V. The bootstrap diode is internal to the module.
Connect a 0.1 F or higher ceramic capacitor between VSWH node at pin 5.
Gate of the HS FET. Used for module testing during production. No user connections.
Switching or phase node connected to source of high side MOSFET and drain of the low side
MOSFET. Electrically attached to the LS FET drain tab, this pin is dedicated for BOOT Cap
connection and needs to be connected to Pin 13 externally on PCB.
Power input to the switching MOSFETs. Attached to the HS FET drain tab.
Gate of the LS FET. Used for module testing during production. No user connections.
Pulse Width Modulated Tri-State input from external controller.
Functional Block Diagram
VCC
BOOT
VIN
VCC
UVLO
PWM
EN
Complementary
Control Logic
Shoot
Through
Control
VSWH
VCC
SMOD
PGND
CGND
Rev. 2.1 April 2014
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Page 3 of 13
AOZ5019
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum ratings may damage the
device.
Parameter
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Rating
Parameter
Supply Voltage (VIN)
-0.3 V to 30 V
Switch Node Voltage (VSWH)
-0.3 V to 30 V
Switch Node Voltage Transient(1)
38V
Bootstrap Voltage (VBOOT)
VBOOT Voltage Transient
-0.3 V to 30 V
(1)
40 V
Supply and Gate Drive Voltages:
{VCC, (VBOOT – VSWH)}
Control Inputs
(PWM, SMOD, EN)
-0.3 V to 7 V
Supply Voltage (VIN)
4.5 V to 25 V
Supply and Gate Drive Voltages
{VCC, (VBOOT – VSWH)}
4.5 V to 5.5 V
Control Inputs
(PWM, SMOD, EN)
0 V to VCC – 0.3 V
Operating Frequency
200 kHz to 1.5 MHz
-0.3 V to VCC +0.3 V
Storage Temperature (TS)
-65 °C to +150 °C
Junction Temperature (TJ)
150 °C
ESD Rating
Rating
(2)
2 kV
Notes:
1. Peak voltages can be applied for 100 nS per switching cycle.
2. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 k in series with 100 pF.
Electrical Characteristics(3)
TA = 25°C, VIN = 12V, VCC = 5 V unless otherwise specified.
Symbol
VIN
Parameter
Conditions
Operating Voltage
VCC
RJC(4)
RJA (4)
Thermal Resistance
Min.
Typ.
Max.
Units
4.5
25
V
4.5
5.5
V
PCB Temp = 100 °C
3
°C / W
AOS Evaluation Board
10
°C / W
INPUT SUPPLY AND UVLO
VCC
Undervoltage Lockout
VCC Rising
3.5
Control Circuit Bias Current
EN = 0, VCC = 5 V
50
75
A
EN = High, VPWM = Open
350
500
A
EN = High, VPWM = 0 V
650
A
Drive Circuit Operating
Current
EN = High, VPWM = 300 kHz @ 50%
25
mA
EN = High, VPWM = 1 MHz @ 50%
60
mA
PWM Input High Threshold
VPWM Rising, VCC = 5 V
3.6
0.8
550
VCCHYST
IVCC
IVC
3.9
V
mV
PWM INPUT
VPWMH
3.9
4.1
1.0
1.2
V
PWM Input Low Threshold
VPWM Falling, VCC = 5 V
IPWM
PWM Pin Input Current
Source or Sink, VPWM = 0 V to 5 V
VTRIH
PWM Input Tri-State
Threshold
VPWM Rising, VCC = 5 V
1.0
1.3
1.6
V
VPWM Falling, VCC = 5 V
3.4
3.7
4.0
V
Tri-State Threshold
Hysteresis
VPWM Rising, VCC = 5 V
280
mV
VPWM Falling, VCC = 5 V
170
mV
VPWML
VTRIL
VTRRH
VTRFH
Rev. 2.1 April 2014
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V
A
±250
Page 4 of 13
AOZ5019
Electrical Characteristics(3) (Continued)
TA = 25°C, VIN = 12V, VCC = 5 V unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
0.8
V
EN INPUT
VENON
Outputs Enable Threshold
VCC = 5 V
VENOFF
Outputs Disable Threshold
VCC = 5 V
EN Pin Input Current
Source or Sink
IEN
2.0
V
A
±10
SMOD INPUT
VSMODH
SMOD Enable Threshold
VCC = 5 V
VSMODL
SMOD Disable Threshold
VCC = 5 V
2.0
V
ISMOD
SMOD Pin Input Current
Source or Sink
±10
A
0.8
V
GATE DRIVER TIMINGS
tPDLU
PWM to HS Gate
PWM H L, GH H L
18
ns
tPDLL
PWM to LS Gate
PWM L H, GL H L
25
ns
tPDHU
LS to HS Gate Deadtime
GL H L, GH L H
20
ns
tPDHL
HS to LS Gate Deadtime
GH H L, GL L H
20
ns
tTSSHD
Tri-State Shutdown Delay
150
ns
Tri-State Propagation Delay
35
ns
tPTS
Notes:
4. All voltages are specified with respect to the corresponding GND pin
5. Characterisation value. Not tested in production.
Rev. 2.1 April 2014
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Page 5 of 13
AOZ5019
Typical Performance Characteristics
Unless otherwise noted, VCC = 5 V, FSW = 800 kHz, LOUT = 200 nH, VOUT = 1.8 V, IOUT = 20 A, module loss measured on
AOS evaluation board at TA = 25 °C natural convection. Module loss does not include inductor loss.
Fig 1. Module Loss vs. Load Current
Fig 2. Output Current vs. Temperature
7
35
6
30
19 Vin 800KHz
12 Vin 500KHz
25
Current (A)
Loss (Watts)
5
4
3
20
15
2
10
1
5
0
3
5
10
15
20
0
25
VIN = 12V
VOUT = 1.8V
F = 500KHz
L = 0.2µH
0
20
40
Load Current (Amps)
80
100
120
140
Fig 4. Normalised Module Loss vs. Input Voltage
1.04
1.30
1.03
1.25
Module Loss (Normalised)
Module Loss (Normalised)
Fig 3. Normalised Module Loss vs. VCC
1.02
1.01
1.00
0.99
0.98
1.20
1.15
1.10
1.05
1.00
0.95
0.97
0.90
0.96
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
5
7
9
VCC (Volts)
11
13
15
17
19
21
Input Voltage (Volts)
Fig 5. IVcc vs. Vcc
Fig 6. IVcc vs. Frequency
33
50
31
45
40
IVcc (mAmps)
29
IVcc (mAmps)
60
Temperature (°C)
27
25
23
35
30
25
20
21
15
19
4.3
4.5
4.7
4.9
5.1
5.3
5.5
5.5
10
0.3
Rev. 2.1 April 2014
0.5
0.7
0.9
1.1
1.3
1.5
Switch Frequency (MHz)
Vcc (Volts)
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Page 6 of 13
AOZ5019
Typical Performance Characteristics (Continued)
Fig 7. IVcc vs. Temperature
Fig 8. Vcc UVLO Threshold vs. Temperature
1.035
3.7
IOUT = 0A
3.6
1.025
3.5
Vcc Threshold (Volts)
IVcc (mAmps)
IOUT = 0A
1.030
1.020
1.015
1.010
1.005
1.000
0.995
3.4
3.3
VCC Rising Threshold
VCC Falling Threshold
3.2
3.1
3.0
2.9
0.990
-40
-20
0
20
40
60
80
100
120
2.8
-40
140
-20
0
20
Fig 9. PWM Input Threshold vs. Temperature
60
80
100
120
140
Fig 10. PWM Input Tri State Hold Off Time vs. Temperature
240
4.5
Tri State Hold Off Time (ns)
4.0
PWM Threshold (Volts)
40
Temperature (°C)
Temperature (°C)
3.5
PWM Rising Threshold
3.0
PWM Falling Threshold
2.5
2.0
1.5
220
200
180
160
140
1.0
0.5
120
-40
-20
0
20
40
60
80
100
120
-40
140
-20
0
20
Temperature (°C)
40
60
80
100
120
140
Temperature (°C)
Fig 12. SMOD Input Threshold vs. Temperature
Fig 11. EN Input Threshold vs. Temperature
1.8
1.8
IOUT = 0A
1.7
1.6
SMOD Threshold (Volts)
Enable Threshold (Volts)
1.7
EN Ramp Down
EN Ramp Up
1.5
1.4
1.6
SMOD Threshold High
SMOD Threshold Low
1.5
1.4
1.3
1.3
1.2
1.2
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Rev. 2.1 April 2014
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
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Page 7 of 13
AOZ5019
Timing Diagram
PWM Tri State Band
PWM
tPDLL
tPDLU
tTSSHD
tTSSHD
GH
tPTS
tPTS
GL
tPDHU
tPDHL
Figure 13. Timing Diagram
Application Information
AOZ5019QI is a fully integrated power module designed
to work over an input voltage range of 4.5 V to 25 V with
5 V supplies for gate drive and internal control circuits. A
number of features are provided making the AOZ5019QI
a highly versatile power module. High side and low side
power MOSFETs are combined in one package with the
pin outs optimized for power routing with minimum
parasitic inductances. The MOSFETs are individually
tailored for efficient operation as either high side or low
side switches in a low duty cycle synchronous buck
converter. A high current driver is also included in the
package which minimizes the gate drive loop and results
in extremely fast switching. The modules are fully
compatible with Intel DrMOS specification Rev 4.0 in
form fit and function.
Powering the Module and the Gate Drives
An external supply VCC of 5 V is required for driving the
MOSFETs. The MOSFETs are designed with low gate
thresholds so that lower drive voltage can be used to
reduce the switching and drive losses without
compromising the conduction losses. The integrated gate
driver is capable of supplying several amperes of peak
current into the LS FET to achieve extremely fast
switching. A ceramic bypass capacitor of 1 F or higher is
recommended from VCC to CGND. For effective filtering
it is strongly recommended to have a direct connection
from this Capacitor to CGND, see Figure 14.
The boost supply for driving the high side MOSFET is
generated by connecting a small capacitor between
Rev. 2.1 April 2014
BOOT pin and the switching node VSWH. It is
recommended that this capacitor Cboot be connected as
close as possible to the device across pins 3 and 5.
Boost diode is integrated into the package. Rboot is an
optional resistor used by designers to slow down the turn
on speed of the high side MOSFET. The value is a
compromise between the need to keep both the
switching time and VSWH node spikes as low as
possible and is typically 1Ω to 5 Ω
Undervoltage Lockout and Enable
VCC is monitored for UVLO conditions and both outputs
are actively held low unless adequate gate supply is
available. The under-voltage lockout is set at 3.5 V with a
550 mV hysteresis. Since the PWM control signals are
provided typically from an external controller or a digital
processor extra care must be taken during start up.
The AOZ5019QI must be powered up and enabled
before the PWM input is applied. It should be ensured
that PWM signal goes through a proper soft start
sequence to minimize inrush current in the converter
during start up. Powering the module with a full duty
cycle PWM signal already applied may lead to a number
of undesirable consequences as explained below.
Outputs can also be turned off through the DISB pin.
When this input is grounded the drivers are disabled and
held active low. The module is in standby mode with low
quiescent current of less than 75 A.
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Page 8 of 13
AOZ5019
IMPORTANT: If the EN is used it is necessary to ensure
proper coordination with soft start and enable features of
the external PWM controller in the system. Every time
AOZ5019QI is disabled through EN there will be no
output and the external controller may enter into open
loop and put out a PWM signal with maximum duty ratio
possible. If the AOZ5019QI is re-enabled by taking EN
high, there will be extremely large inrush currents while
the output voltage builds up again which may drive the
system into current limit. There might be undesirable
consequences such as inductor saturation, overloading
of the input or even a catastrophic failure of the device. It
is recommended that the PWM controller be disabled
when AOZ5019QI is disabled or non operational
because of UVLO. The PWM controller should always be
enabled with a soft start to minimize stresses on the
converter.
PWM Input
In general it should be noted that AOZ5019QI is a
combination of two MOSFETs with an unintelligent driver,
all of which are optimized for switching at the highest
efficiency. Other than UVLO and thermal protection, it
does not have any monitoring or protection functions built
in. The PWM controller should be designed in to perform
these functions under all possible operating and transient
conditions.
Table 1. PWM Input and Tri-State Thresholds
Input Voltage VIN
AOZ5019QI is rated to operate over a wide input range of
4.5 V to 25 V. As with any other synchronous buck
converter, large pulse currents at high frequency and
extremely high di/dt rates will be drawn by the module
during normal operation. It is strongly recommended to
bypass the input supply very close to package leads with
X7R or X5R quality ceramic capacitors.
The high side MOSFET in AOZ5019QI is optimized for
fast switching with low duty ratios. It has ultra low gate
charges which have been achieved as a trade off with
higher RDS(ON) value. When the module is operated at
low VIN the duty ratio will be higher and conduction
losses in the HS FET will also be correspondingly higher.
This will be compensated to some extent by reduced
switching losses. The total power loss in the module may
appear to be low even though in reality the HS MOSFET
losses may be disproportionately high. Since the two
MOSFETs have their own exposed pads and PCB
copper areas for heat dissipation, the HS FET may be
much hotter than the LS FET. It is recommended that
worst case junction temperature be measured and
ensured to be within safe limits when the module is
operated with high duty ratios.
Rev. 2.1 April 2014
AOZ5019QI is offered in two versions which can be
interfaced with PWM logic compatible with either 5 V
(TTL) or 3V (CMOS). Refer to Figure 13 for the timing
and propagation delays between the PWM input and the
gate drives. The PWM is also a tri-state compatible input.
When the input is high impedance or unconnected both
the gate drives will be off and the gates are held active
low. The PWM Threshold Table (Table 1) lists the
thresholds for high and low level transitions as well as tristate operation. As shown in Figure 13, there is a hold off
delay between the time PWM signal enters the tri-state
window and the corresponding gate drive is pulled low.
This delay is typically 170 ns and intended to prevent
spurious triggering of the tri-state mode which may be
caused either by noise induced glitches in the PWM
waveform or slow rise and fall times.
Thresholds
VPWMH
VPWML
VTRIH
VTRIL
AOZ5019QI
3.9 V
1.0 V
1.3 V
3.7 V
Note: See Figure 13 for propagation delays and tri-state window.
Diode Mode Emulation of Low Side MOSFET (SMOD)
AOZ5019QI can be operated in the diode emulation or
skip mode using the SMOD pin. This is useful if the
converter has to operate in asynchronous mode during
start up, light load or under pre bias conditions. If SMOD
is taken high, the controller will use the PWM signal as
reference and generate both the high and low side
complementary gate drive outputs with the minimal
delays necessary to avoid cross conduction. When the
pin is taken low the HS FET drive is not affected but
diode emulation mode is activated for the LS FET. See
Table 2 for a comprehensive view of all logic inputs and
corresponding drive conditions.
Table 2. Control Logic Truth Table
EN
SMOD
PWM
GH
GL
L
X
X
L
L
H
L
H
H
L
H
L
L
L
See Note
H
X
Tri-State
L
L
H
H
H
H
L
H
H
L
L
H
Note: Diode emulation mode is activated when SMOD pin is held low.
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Page 9 of 13
AOZ5019
Gate Drives
AOZ5019QI has an internal high current high speed
driver that generates the floating gate drive for the HS
FET and a complementary drive for the LS FET.
Propagation delays between transitions of the PWM
waveform and corresponding gate drives are kept to the
minimum. An internal shoot through protection scheme
ensures that neither MOSFET turns on while the other
one is still conducting, thereby preventing shoot through
condition of the input current. When the PWM signal
makes a transition from H to L or L to H, the
corresponding gate drive GH or GL begins to turn off.
The adaptive timing circuit monitors the falling edge of
the gate voltage and when the level goes below 1V, the
complementary gate driver is turned on. The dead time
between the two switches is minimized, at the same time
preventing cross conduction across the input bus. The
adaptive circuit also monitors the switching node VSWH
and ensures that transition from one MOSFET to another
always takes place without cross conduction, even under
transient and abnormal conditions of operation.
The gate pins GH and GL are brought out on pins 4 and
19 respectively. However these connections are not
made directly to MOSFET gate pads and their voltage
measurement may not reflect the actual gate voltage
applied inside the package. The gate connections are
primarily for functional tests during manufacturing and no
connections should be made to them in the application.
buck converter layout, the critical requirement is to
minimize the area of the primary switching current loop,
formed by the HS FET, LS FET and the input bypass
capacitor Cin. The PCB design is somewhat simplified
because of the optimized pin out in AOZ5019QI. The
bulk of VIN and PGND pins are located adjacent to each
other and the input bypass capacitors should be placed
as close as possible to these pins. The area of the
secondary switching loop, formed by LS FET, output
inductor and output capacitor Cout is the next critical
parameter, this requires second layer or “Inner 1” should
always be an uninterrupted GND plane with sufficient
GND vias placed as close as possible to by-pass
Capacitors GND pads. MOSFETs in the package are
directly attached to individual exposed pads, VIN and
PGND to simplify thermal management. Using vias, Both
VIN and GND pads should be attached to VIN and GND
plane directly as shown below. Thermal reliefs should be
avoided to ensure proper heat dissipation to the board.
Vcc By-pass capacitor CVcc should connect directly to
CGND as shown below, use a via to connect CGND
directly to GND, connect Cboot and Rboot directly to pins
3 and 5.
Figure 14 illustrates the various copper pours and bypass
capacitor locations.
PCB Layout Guidelines
AOZ5019 is a high current module rated for operation up
to 1.5 MHz. This requires extremely fast switching
speeds to keep the switching losses and device
temperatures within limits. Having a robust gate driver
integrated in the package eliminates driver-to-MOSFET
gate pad parasitics of the package or PCB. While
excellent switching speeds are achieved,
correspondingly high levels of dv/dt and di/dt will be
observed throughout the power train which requires
careful attention to PCB layout to minimize voltage
spikes and other transients. As with any synchronous
Rev. 2.1 April 2014
Rb
Cb
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Figure 14. PCB Layout Illustration
Page 10 of 13
AOZ5019
Package Dimensions, QFN3.5x5_23L EP2_S
L4
L5
A
D
L2
D1
d
E1
f
E
e
E2
L
b
C 0.25
L1
Pin #1 Dot
By Marking
TOP VIEW
L3
SIDE VIEW
BOTTOM VIEW
A2
A1
SIDE VIEW
1.225
0.331
0.725
1.850
1.325
RECOMMENDED LAND PATTERN
2.600
1.924
1.699
2.175
1.069
0.375
0.175
0.000
0.375
0.325
1.855
2.050
2.600
2.125
1.85
1.12
1.13
1.11
0.000
1.85
1.30
0.50
Dimensions in millimeters
Symbols
A
A1
A2
E
E1
E2
D1
D
L
L1
L2
L3
L4
L5
b
d
f
e
Min.
1.00
0.00
4.90
1.63
1.15
1.65
3.40
0.35
0.22
0.30
0.58
1.02
0.58
0.20
0.33
0.70
Typ.
1.10
0.2 REF
5.00
1.73
1.25
1.75
3.50
0.40
0.27
0.35
0.63
1.12
0.63
0.25
0.38
0.75
0.50 BSC
Max.
1.20
0.05
5.10
1.83
1.35
1.85
3.60
0.45
0.32
0.40
0.68
1.22
0.68
0.30
0.43
0.80
Dimensions in inches
Symbols
A
A1
A2
E
E1
E2
D1
D
L
L1
L2
L3
L4
L5
b
d
f
e
Min.
0.039
0.000
Typ.
0.043
0.008 REF
0.193 0.197
0.064 0.068
0.045 0.049
0.065 0.069
0.134 0.138
0.014 0.016
0.009 0.011
0.012 0.014
0.023 0.025
0.040 0.044
0.023 0.025
0.008 0.010
0.013 0.015
0.028 0.030
0.02 BSC
Max.
0.047
0.002
0.201
0.072
0.053
0.073
0.142
0.018
0.013
0.016
0.027
0.048
0.027
0.012
0.017
0.031
Unit: mm
Note:
Controlling dimension are in millimeters. Converted inch dimensions are not necessarily exact.
Rev. 2.1 April 2014
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Page 11 of 13
AOZ5019
Tape and Reel Dimensions, QFN3.5x5_23L EP2_S
Carrier Tape
P0
P2
D1
P1
A
R
T
30
0.
.
AX
M
E1
E2
D0
E
B0
A
A0
K0
Feeding Direction
UNIT: MM
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
QFN3.5x5
(12mm)
3.89
±0.10
5.31
±0.10
1.30
±0.10
1.50
MIN.
1.50
+0.1
-0.0
12.0
±0.30
1.75
±0.10
5.50
±0.05
8.00
±0.10
4.00
±0.10
2.00
±0.05
0.30
±0.05
Reel
W1
S
G
N
M
K
V
R
H
W
UNIT: MM
Tape Size
12mm
Reel Size
Ø330
M
N
W
W1
H
S
K
G
R
V
Ø330
±2.00
Ø101.6
±2.00
12.40
+2.00
-0.00
12.40
+3.00
-0.20
Ø13.20
±0.30
1.70-2.60
---
---
---
---
Leader/Trailer and Orientation
Unit Per
Reel:
3000pcs
Trailer Tape
300mm min.
Rev. 2.1 April 2014
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min.
Page 12 of 13
AOZ5019
Part Marking
AOZ5019QI
(5x3.5 QFN)
Z5019QI
Part Number Code
FA YW LT
Assembly Lot Code
Fab Code & Assembly Location
Year Code & Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 2.1 April 2014
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 13 of 13