DATASHEET

DATASHEET
40A DrMOS Power Module with Integrated Diode
Emulation and Thermal Warning Output
ISL99140
Features
The ISL99140 is a high performance DrMOS power module
designed for high frequency power conversion. By combining a
high performance FET driver and MOSFETs in an advanced
package, high density DC/DC converters may be created.
Combined with an Intersil PWM controller, a complete voltage
regulator solution can be created with reduced external
components and minimum overall PCB real estate.
• Compliant with Intel DrMOS rev 4.0 specifications
The ISL99140 features a three-state PWM input that, working
together with Intersil’s multiphase PWM controllers, will
provide a robust solution in the event of abnormal operating
conditions. To further support robust applications, the
ISL99140 features a thermal warning output that may be used
to notify the power system of an impending thermal fail event.
The ISL99140 supports high efficiency operation not only at
heavy loads, but also at light loads via its diode emulation
capability. Diode emulation can be disabled for those
applications where variable frequency operation is not desired
at light loads.
• 40A average output current capability
• Supports 3-state 3.3V PWM input
• Supports 2-state 5V PWM input
• Thermal warning output
• Diode emulation option
• Adaptive shoot-through protection
• Integrated high-side gate-to-source resistor to prevent self
turn-on due to high input bus dV/dt
• Undervoltage lockout
• Switching frequencies up to 2MHz
• Pb-free (RoHS compliant)
• 6x6 QFN package
Applications
Related Literature
• High frequency and high efficiency VRM and VRD
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• High density VR for server, networking and cloud computing
• Core, graphic and memory regulators for microprocessors
• POL DC/DC converters and video gaming consoles
+12V
SMOD
PWM
GND
VIN
BOOT
LOUT
VOUT
PVCC
THDN
LOGIC
CONTROL
AGND
EN
PHASE
VCC
SHOOTTHROUGH
PROTECTION
COUT
PG ND
INTERSIL
CONTROLLER
PVCC
EN
+5V
FIGURE 1. SIMPLIFIED APPLICATION BLOCK DIAGRAM
January 7, 2016
FN8642.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL99140
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL99140IRZ-T
PART
MARKING
99140 IRZ
TEMP RANGE
(°C)
TAPE AND REEL QUANTITY
(UNITS)
-40 to +85
3k
PACKAGE
(Pb-Free)
40 Ld Exposed Pad 6x6 QFN
PKG.
DWG. #
L40.6X6A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL99140. For more information on MSL, please see tech brief TB363.
Pin Configuration
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VIN
11
VIN
12
VIN
13
VIN
VIN
VIN
VIN
PHASE
GH
AGND
BOOT
PVCC
VCC
SMOD
ISL99140
(40 LD QFN)
TOP VIEW
10
9
8
7
6
5
4
3
2
1
40
PWM
39
EN
38
THDN
14
37
GND
SW
15
36
GL
PGND
16
35
SW
PGND
17
34
SW
PGND
18
33
SW
PGND
19
32
SW
PGND
20
31
SW
2
VIN
PAD2
AGND
PAD1
21
22
23
24
25
26
27
28
29
30
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SW
SW
SW
PAD3
FN8642.1
January 7, 2016
ISL99140
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1
SMOD
Input pin to enable or disable Diode Emulation with built-in pull up of 10μA. When SMOD is
LOW, diode emulation is allowed. Otherwise, continuous conduction mode is forced.
2
VCC
+5V logic bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
3
PVCC
+5V driver bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
VCC and PVCC often share the decoupling capacitor (~1μF/0402~0603/ X5R~X7R).
4
BOOT
Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic
capacitor (~0.1μF to 0.22μF) in close proximity across BOOT and PHASE pins.
5, 37, PAD1
AGND, GND
6
GH
7
PHASE
Return of bootstrap capacitor. Internally connected to SW node. External connection is not
needed.
8, 9, 10, 11, 12, 13, 14, PAD2
VIN
Input of Power Stage. Place couple high quality low ESR ceramic capacitor (couple 10μF or
higher, X7R) in close proximity across VIN and GND planes.
16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28
PGND
15, 29, 30, 31, 32, 33, 34, 35,
PAD3
SW
Switching junction node between low and high-side MOSFETs. Connect directly to output
inductor.
36
GL
Low-side gate drive output for monitoring/testing. No circuit connection needed.
38
THDN
39
EN
40
PWM
Return of logic bias supply VCC. Connect directly to system ground plane.
High-side gate drive output for monitoring/testing. No circuit connection needed.
Power Stage return. Connect directly to system ground plane.
Thermal warning flag, an output open-drain pin. High = Normal operation; Low = Shutdown.
Enable input pin with 2μA internal weak pull-down. High = Enable; Low = Disable.
PWM input of gate driver. The PWM signal can enter three distinct states during operation.
Connect this pin to the PWM output of the controller.
Functional Block Diagram
VCC
BOOT PHASE GH
PVCC
THDN
VIN
THERMAL
MONITOR
EN
POR
29.16k
PWM
LOGIC
PWM
12.5k
20k
SHOOTTHROUGH
PROTECTION
SW
PVCC
500k
AGND
ZERO
DETECT
SW
GL
GH
PGND
SMOD
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3
GL
PGND
FN8642.1
January 7, 2016
ISL99140
Typical Application Circuit with ISL6388
+5V
VCC
VSEN_OVP
VSEN
VIN
RGND
SVDATA
ISENIN-
SVALERT#
RISENIN1
VINF
RSENIN
RISENIN2
ISENIN+
SVCLK
VR_RDY
VR_HOT#
VINF
+5V
SM_PM_I2DA
VCC
SM_PMALERT#
ISL99140
BOOT
UG
SM_PM_I2CLK
PWM1
VINF
PHASE
PWM LG
ISEN1EN_PWR_CFP
ISEN1+
+5V
CFP
ISL99140
VINF
BOOT
VCC
ISL6388
UG
PWM4
IMON
PHASE
PWM LG
ISEN4+5V
ISEN4+
PWM2,5
NVM_BANK_BT
2X
ISEN2,5-
VRSEL_ADDR
ISEN2,5+
AUTO
+5V
ISL99140
VINF
BOOT
VCC
UG
PWM3
RSET
LOAD
PHASE
PWM LG
ISEN3ISEN3+
+5V
+5V
ISL99140
VCC
UG
TM_EN_OTP
PWM6
NTC
VINF
BOOT
PHASE
PWM LG
ISEN6GND
ISEN6+
NTC1 NETWORK IS NOT NEEDED
IF TMS IS USED FOR VR1, GPU
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January 7, 2016
ISL99140
Typical Application Circuit with ZL8800
VIN
10.8 TO 13.2V
R14
C3
1µF
1 m
CIN1
IINN
VDD
IINP
5V
V25
V5
V6
C11
10µF
U3
VCC
C4
1µF
VIN
C10
10µF
PVCC
C9
10µF
ISL99140
U1
AGND
SYNC
SA
PHASE
BOOT
PWMH0
PWM
PWML0
EN
PGND
R10
L1
SW
C5
0.1 µF
C1
R1
THDN
SMOD
VOUT
VSET0
R11
UVLO
R12
ISENA0
COUT
ISENB0
R13
5V
VIN
ZL8800
VCC
PG
C7
1µF
V5
VIN
EN
CONTROL
AND
STATUS
PVCC
CIN2
ISL99140
AGND
L2
SW
U2 PHASE
PWMH1
PWM
PWML1
EN
PGND
BOOT
R9
10 k
R2
C2
C8
0.1µF
THDN
SMOD
DDC
INTER-DEVICE
COORDINATION
(OPTIONAL)
SYNC
ISENA1
SDA
VSEN0N
ISENB1
PMBus
(OPTIONAL)
SCL
VSEN0P
DGND SGND
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January 7, 2016
ISL99140
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
I/O Voltage (VEN, VPWM, VSMOD, V THDN). . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . . . . . . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 30V
(GND - 10V) (<20ns Pulse Width, 10µJ)
Thermal Resistance
JA (°C/W) JC (°C/W)
50
5
40 Ld 6x6 QFN Package (Notes 4, 5). . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
Input Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. Jedec Class II pulse conditions and failure criterion used.
/
Electrical Specifications TA = +25°C; VIN = 12V, VVCC = VPVCC = 5V unless otherwise noted. Boldface limits apply across the
recommended operating temperature range.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNIT
SUPPLY CURRENT
VCC Standby Supply Bias Current
IVCC
PVCC Supply Bias Current
IPVCC
EN = Low, VVCC = 5V
187
µA
EN = High, VPWM = Open
467
µA
EN = High, VPWM = 0V
664
µA
EN = High, VPWM = 300kHz, 50% duty cycle
23
mA
EN = High, VPWM = 1MHz, 50% duty cycle
51
mA
POWER-ON RESET AND ENABLE
POR Rising Threshold
VPORR
POR Falling Threshold
VPORF
POR Hysteresis
VPORH
EN High Threshold
VENH
EN Low Threshold
VENL
EN Pull-Down Current
IENL
3.40
2.3
3.90
V
2.92
V
570
mV
2.0
V
0.8
V
2
µA
Pull-Up Impedance
29.1
kΩ
Pull-Down Impedance
12.5
kΩ
PWM INPUT
PWM Rising Threshold
VPWMH
VVCC = 5V
1.70
2.05
2.35
V
PWM Falling Threshold
VPWML
VVCC = 5V
0.75
1.00
1.25
V
PWM Tri-State Rising Threshold
VTRIH
VVCC = 5V
1.10
1.32
1.50
V
PWM Tri-State Falling Threshold
V TRIL
VVCC = 5V
1.60
1.75
1.95
V
PWM Tri-State Rising Hysteresis
V TRRH
VVCC = 5V
310
mV
PWM Tri-State Falling Hysteresis
V TRFH
VVCC = 5V
310
mV
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ISL99140
Electrical Specifications TA = +25°C; VIN = 12V, VVCC = VPVCC = 5V unless otherwise noted. Boldface limits apply across the
recommended operating temperature range. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNIT
SWITCHING TIME
GH Turn-On Propagation Delay
tPDHU
VVCC = 5V, see Figure 2 (GL Low to GH High)
15
ns
GH Turn-Off Propagation Delay
tPDLU
VVCC = 5V, see Figure 2 (PWM Low to GH Low)
18
ns
GL Turn-On Propagation Delay
tPDHL
VVCC = 5V, see Figure 2 (GH Low to GL High)
20
ns
GL Turn-Off Propagation Delay
tPDLL
VVCC = 5V, see Figure 2 (PWM High to GL Low)
18
ns
GH/GL Exit Tri-State Propagation Delay
tPDTS
VVCC = 5V, see Figure 2 (Tri-State to GH/GL High)
20
ns
Tri-State Shutdown Hold-Off Time
tTSSHD
VVCC = 5V, see Figure 2
Minimum GL On-Time in DCM
tLGMIN
VVCC = 5V
75
150
225
350
ns
ns
SMOD INPUT
SMOD High Threshold
VSMODH
SMOD Low Threshold
VSMODL
SMOD Pin Pull-Up Current
2.0
V
0.8
ISMOD
V
10
µA
THERMAL SHUTDOWN (THDN)
Pull-Down Impedance
1mA
60
Ω
Output Low
1mA
70
mV
Thermal Shutdown Flag Set
(Note 8)
150
°C
Thermal Shutdown Flag Clear
(Note 8)
135
°C
Hysteresis
(Note 8)
15
°C
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Limits established by characterization and are not production tested.
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ISL99140
PWM
tPDLU
tPDHU
tPDTS
tTSSHD
tPDTS
UGATE
tFU
tRU
tPDHL
LGATE
tRL
tFL
tTSSHD
tPDLL
FIGURE 2. TIMING DIAGRAM
TABLE 1. GATE DRIVE TRUTH TABLE
ENABLE
SMOD
PWM
GL
GH
L
X
X
L
L
H
L
L
H*
L
H
L
H
L
H
H
H
L
H
L
H
H
H
L
H
NOTE: The LG stays high until inductor current drops to zero.
Operation
determines a safe time for the upper MOSFET to turn-on. This
prevents the MOSFET’s from conducting simultaneously.
The ISL99140 is an optimized driver and power stage solution for
high density synchronous DC/DC power conversion. The
ISL99140 includes a high performance driver, integrated
Schottky bootstrap diode and MOSFET pair optimized for high
switching frequency buck voltage regulators. The ISL99140
includes a driver with advanced power management features
that allow direct control of the Lower MOSFET, Diode Emulation
and thermal protection.
Power-On Reset (POR) and EN
During initial start-up, the VCC voltage rise is monitored. Once the
rising VCC voltage exceeds 3.5V (typically), normal operation of
the driver is enabled. If VCC drops below the falling threshold of
2.95V (typically), operation of the driver is disabled.
Should the EN pin be pulled low, the driver will immediately force
both MOSFETS to their off states. This action does not depend on
the state of the PWM input.
Shoot-Through Protection
The falling PWM transition causes the upper FET to turn-off and the
lower FET to turn-on. Adaptive shoot-through circuitry monitors the
GH to SW voltage to determine a safe time for low-side MOSFET
turn-on. This prevents the MOSFET’s from conducting
simultaneously.
Should the driver have no bias voltage applied and be unable to
actively hold the MOSFETs off, an integrated 20kΩ resistor from
the upper MOSFET gate-to-source will aid in keeping the device in
its off state. This can be especially critical in applications where
the input voltage rises prior to the ISL99140 VCC /PVCC supplies.
Tri-State PWM Input
The ISL99140 supports a tri-level input on the PWM pin. Should
the pin be pulled into and remain in the tri-state window for a set
holdoff time, the driver will force both MOSFETs to their off
states. When the PWM signal moves outside the shutdown
window, the driver immediately resumes driving the MOSFETs
according to the PWM commands.
Prior to VCC exceeding its POR level, the undervoltage protection
function is activated and both GH and GL are held active low (off).
Once the VCC voltage surpasses the Rising Threshold (see
“Electrical Specifications” on page 6) the PWM, SMOD and DE
signals are used to control both high-side and low-side MOSFETs.
This feature is utilized by Intersil PWM controllers as a method of
forcing both MOSFETs off. Should the PWM input be left floating,
the pin will be pulled into the tri-state window internally and force
both MOSFETs to a safe off state. The ISL99140’s tri-state levels
are compatible with 3.3V PWM logic.
The rising edge on PWM initiates the turn-off of the lower MOSFET.
Adaptive shoot-through circuitry monitors the GL voltage and
Although PWM input can sustain as high as VCC, the ISL99140 is
not compatible with a controller (such as ISL637x family) that
actively drives its mid level in tri-state higher than 1.7V. However,
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FN8642.1
January 7, 2016
ISL99140
the ISL99140 can be configured to be compatible with ZL8800
by connecting PWMH to PWM and PWML to EN, as shown in
“Typical Application Circuit with ZL8800” on page 5. In this
example, the tri-state operation is controlled by PWML output of
ZL8800 through ISL99140’s EN input. For detailed design
information, consult the ZL8800 datasheet.
Diode Emulation
Diode emulation allows for higher converter efficiency under light
load situations. With diode emulation active (SMOD pulled low),
the ISL99140 will detect the zero current crossing of the output
inductor and turn off the low-side gate after the minimum LGATE
ON time of 350ns expires. This ensures that Discontinuous
Conduction Mode (DCM) is achieved to minimize losses. Diode
emulation is asynchronous to the PWM signal. Therefore, the
ISL99140 will respond to the SMOD input immediately after it
changes state.
Bootstrap Function
The ISL99140 features an internal bootstrap Schottky diode. A
high quality ceramic capacitor should be place in close proximity
across BOOT and PHASE pins. The bootstrap capacitor can range
between 0.1µF~0.22µF/0402~0603/X5R~X7R for normal buck
switching applications.
Thermal Shutdown Warning (THDN)
The THDN pin is an open drain output and is pulled low when the
internal junction temperature exceeds +150°C. The ISL99140
does not stop operation when the flag is set. This signal is often
fed back to the controller to issue a system thermal shutdown.
When the junction temperature drops below +135°C, the device
will clear the THDN signal.
PCB Layout Considerations
Proper PCB layout will reduce noise coupling to other circuits,
improve thermal performance, and maximize the efficiency. The
following is meant to lead to an optimized layout:
• Place multiple 10µF or greater ceramic capacitors directly at
device between VIN and PGND as indicated in Figure 3. This is
the most critical decoupling and reduced parasitic inductance
in the power switching loop. This will reduce overall electrical
stress on the device as well as reduce coupling to other
circuits. Best practice is to place the decoupling capacitors on
the same PCB side as the device.
• Connect PGND to the system GND plane with a large via array
as close to the PGND pins as design rules allow. This improves
thermal and electrical performance.
• Place PVCC, VCC and BOOT-PHASE decoupling capacitors at
the IC pins as shown in Figure 3.
• Note that the SW plane connecting the ISL99140 and inductor
must carry full load current and will create resistive loss if not
sized properly. However, it is also a very noisy node that should
not be oversized or routed close to any sensitive signals. Best
practice is to place the inductor as close to the device as
possible and thus minimizing the required area for the SW
connection. If one must choose a long route of either the VOUT
side of the inductor or the SW side, choose the quiet VOUT side.
Best practice is to locate the ISL99140 as close to the final
load as possible and thus avoid noisy or lossy routes to the
load.
TABLE 2. AVAILABLE EVALUATION BOARDS
EVALUATION BOARDS
DESCRIPTION
SMBus/
PMBus/I2C
ISL6388EVAL1Z
6-Phase Core VR with ISL99140, 6x6 DrMOS, and the ISL6388, EAPP Digital Controller; Socket R3
Yes
ISL6398EVAL1Z
3-Phase POL VR with ISL99140, 6x6 DrMOS, and the ISL6388, EAPP Digital Controller; On-board Transient Load
Yes
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ISL99140
FIGURE 3. PCB LAYOUT FOR MINIMIZING CURRENT LOOPS
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ISL99140
Typical Performance Characteristics
300kHz
800kHz
EFFICIENCY (%)
EFFICIENCY (%)
600kHz
300kHz
800kHz
OUTPUT CURRENT (A)
600kHz
OUTPUT CURRENT (A)
FIGURE 5. 1.8V VOUT POWER STAGE EFFICIENCY (VIN = 12V,
VCC = PVCC = 5V; LOUT = 0.23µH, 0.23mΩ,
SLC1175-231; INCLUDE INDUCTOR AND ISL99140
LOSSES)
FIGURE 4. 1.0V VOUT POWER STAGE EFFICIENCY (VIN = 12V,
VCC = PVCC = 5V; LOUT = 0.23µH, 0.23mΩ,
SLC1175-231; INCLUDE INDUCTOR AND ISL99140
LOSSES)
300kHz
600kHz
800kHz
OUTPUT CURRENT (A)
FIGURE 6. 1.0V VOUT POWER STAGE DISSIPATION (VIN = 12V,
VCC = PVCC = 5V; LOUT = 0.23µH, 0.23mΩ,
SLC1175-231; INCLUDE INDUCTOR AND ISL99140
LOSS)
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POWER LOSS (W)
POWER LOSS (W)
300kHz
600kHz
800kHz
OUTPUT CURRENT (A)
FIGURE 7. 1.8V VOUT POWER STAGE DISSIPATION (VIN = 12V,
VCC = PVCC = 5V; LOUT = 0.23µH, 0.23mΩ,
SLC1175-231; INCLUDE INDUCTOR AND ISL99140
LOSSES)
FN8642.1
January 7, 2016
ISL99140
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
January 7, 2016
FN8642.1
Updated the Ordering Information table on page 2 by adding the tape and reel quantity.
Under “Absolute Maximum Ratings” on page 6, added the following:
“Phase Voltage............................(GND - 0.3V) to 30V
(GND-10V) (<20ns Pulse Width, 10µJ)
May 5, 2014
FN8642.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
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information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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12
FN8642.1
January 7, 2016
ISL99140
Package Outline Drawing
L40.6x6A
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/14
D
30
D1
A
D/2
PIN #1 IDA
C0.30 x 45°
B
21
20
31
e
e/2
L6
10
40
E/2
2
1
D1
E1
INDEX AREA
(D/2 x E/2)
11
E1
L1
L2
L1
L3
E
L5
L
2x
aaa C
E2
e
40
11
10
1
2x
aaa C
20
31
30
A3
L
21
L4
L5
D2
BOTTOM VIEW
TOP VIEW
A3
ccc C
C
A
4
ddd C
SEATING
PLANE
40 x b
A1
3
bbb M C A B
SIDE VIEW
DIMENSIONS IN MILLIMETERS
SYMBOLS
MIN
TYP
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
b
0.20 REF
0.20
D
0.25
0.35
6.00 BSC
D1
1.90
2.00
2.10
D2
4.30
4.40
4.50
E
6.00 BSC
1.
Dimensions are in millimeters.
2.
The location of the terminal #1 identifier and
terminal numbering convention conforms to
JEDEC publication 95 SPP-002.
3.
Dimension b applies to metallized terminal and is
measured between 0.20mm and 0.35mm from the
terminal tip. If the terminal has the optional radius
on the other end of the terminal, the dimension b
should not be measured in that radius area.
4.
Coplanarity applies to the terminals and all other
bottom surface metallization.
E1
1.40
1.50
1.60
E2
2.17
2.27
2.37
e
0.50 BSC
L
0.30
0.40
0.50
L1
0.15
0.20
0.25
L2
0.15
0.21
0.26
L3
0.63
0.73
0.83
L4
0.44
0.54
0.64
L5
0.30
0.40
0.50
L6
0.27
0.37
0.47
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.08
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13
NOTES:
FN8642.1
January 7, 2016
ISL99140
4.40
2.20
0.40
0.25
0.75
0.54
0.55
2.87
2.27
0.20
0.21
0.52
0.73
2.23
1.50
0.20
0.37
2.87
0.30 x 45°
0.50 REF
0.25
2.00
2.87
2.00
2.87
RECOMMENDED LAND PATTERN
NOTE:
1.
Dimensions are in millimeters.
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14
FN8642.1
January 7, 2016