AOZ5066
60A DrMOS Power Module
General Description
Features
The AOZ5066 is a high efficiency synchronous buck
power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The high side MOSFET has low
capacitance and gate charge for fast switching with low
duty cycle operation. The low side MOSFET has ultra low
RDS(ON) to minimize conduction losses.
Fully complies with Intel DrMOS Rev 4.0 specifications
The AOZ5066 is available with two PWM options.
AOZ5066QI is intended for use with TTL compatible
PWM inputs. AOZ5066QI-01 has lower thresholds on the
PWM signal and can operate with 3V inputs. All other
parameters are identical for the two versions. Both
versions are tri-state compatible that allows both power
MOSFETs to be turned off.
Integrated boot supply diode
A number of features are provided making the AOZ5066
a highly versatile power module. The boot supply diode is
integrated in the driver. The low side MOSFET can be
driven into diode emulation mode to provide
asynchronous operation when required. The pinout is
optimized for low inductance routing of the converter
keeping the parasitics and their effects to the minimum.
4.5V to 25V input voltage range
4.5V to 5.5V driver supply range
Up to 60A output current
Up to 1MHz PWM operation
Tri state PWM input
Undervoltage protection
Diode Emulation mode of operation
Thermal shutdown alarm with flag
Small 6x6 QFN-40L package
Applications
Servers
VRMs for motherboards
Point of load DC/DC converters
Memory and graphic cards
Video gaming consoles
Typical Application Circuit
AOZ5066
+5V
VDRV
VIN
VIN
12V
BOOT
VCIN
Cboot
PWM
Controller
Drive Logic
and
Dead Time
Control
PWM
SMOD
DISB#
THDN
Cin
CGND
VOUT
Cout
PGND
CGND
Rev. 3.0 December 2013
Lout
VSWH
PGND
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Page 1 of 16
AOZ5066
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
-40°C to +85°C
6x6 QFN-40L
Green Product
AOZ5066QI
AOZ5066QI-01
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
SMOD
VCIN
VDRV
BOOT
CGND
GH
VSWH
VIN
VIN
VIN
Pin Configuration
10
1
11
40
VIN
PWM
VIN
VIN
VIN
DISB#
CGND
THDN
VIN
CGND
VSWH
GL
PGND
VSWH
PGND
VSWH
VSWH
PGND
VSWH
PGND
VSWH
PGND
VSWH
20
31
VSWH
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
30
PGND
21
6x6 QFN-40
(Top View)
Rev. 3.0 December 2013
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Page 2 of 16
AOZ5066
Pin Description
Pin Number
Pin Name
Pin Function
1
SMOD
Skip Mode input. When the pin is held active low, Diode Emulation or Skip Mode is enabled for
the LS FET.
2
VCIN
Control supply input. Nominal 5V. Can be derived from the gate drive supply VDRV with an RC
filter for noise bypass.
3
VDRV
Gate drive supply input. Nominal 5V.
4
BOOT
Gate drive supply for the HS FET. Nominal 5V. The bootstrap diode is internal to the module.
Connect a 0.1F or higher ceramic capacitor between VSWH node at pin 7.
5, 37
CGND
Control or analog ground for return of control signals and bypass capacitors.
Attached to exposed pad in the driver section.
6
GH
7
VSWH
Gate of the HS FET. Used for module testing during production. No user connections.
8 to 14
VIN
15
VSWH
Switching or the phase node for bootstrap capacitor connection.
Power input to the switching MOSFETs. Attached to the HS FET drain tab.
Switching or the phase node pin. Not for power connections.
16 to 28
PGND
Power ground.
29 to 35
VSWH
Switching or phase node connected to source of high side MOSFET and drain of the low side
MOSFET. Electrically attached to the LS FET drain tab.
36
GL
Gate of the LS FET. Used for module testing during production. No user connections.
38
THDN
Open drain output of the thermal shutdown circuit. Active low.
39
DISB#
Disable pin for the controller. Both gates are held active low when DISB# is grounded.
40
PWM
Pulse Width Modulated Tri State input from external controller.
Functional Block Diagram
VDRV
BOOT
VCIN
VIN
PWM
DISB#
Complementary
Control Logic
Shoot
Through
Control
VSWH
VDRV
SMOD
THDN
CGND
Rev. 3.0 December 2013
PGND
Temp
SHDN
VCIN
UVLO
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Page 3 of 16
AOZ5066
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum ratings may damage the
device.
Parameter
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Rating
Supply Voltage (VIN)
Parameter
-0.3V to 30V
Switch Node Voltage (VSWH) (1)
-8V to 30V
Bootstrap Voltage (VBOOT)
-0.3V to 30V
VBOOT Voltage Transient (1)
36V
Supply and Gate Drive Voltages
{VCIN, VDRV, (VBOOT – VSWH)}
Control Inputs
(PWM, SMOD, DISB#)
-0.3V to 7V
Rating
Supply Voltage (VIN)
4.5V to 25V
Supply and Gate Drive Voltages
{VCIN, VDRV, (VBOOT – VSWH)}
4.5V to 5.5V
Control Inputs
(PWM, SMOD, DISB#)
0V to VCIN – 0.3V
Operating Frequency
200kHz to 1MHz
-0.3V to VCIN + 0.3 V
Storage Temperature (TS)
-65°C to +150°C
Junction Temperature (TJ)
+150°C
ESD Rating(2)
2kV
Notes:
1. Peak voltages can be applied for 100nS per switching cycle.
2. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k in series with 100pF.
Electrical Characteristics(3)
TA = 25°C, VIN = 12V, VDRV = VCIN = 5V unless otherwise specified.
Symbol
VIN
Parameter
Operating Voltage
VCIN
RJC(4)
Conditions
Typ.
4.5
VDRV Tied to VCIN
Thermal Resistance
Min.
4.5
PCB Temp = 100°C
RJA (4)
Max.
Units
25
V
5.5
V
5.0
°C / W
50
°C / W
INPUT SUPPLY AND UVLO
VCINON
Undervoltage Lockout
VCINHYST
IVCIN
IVDRV
Control Circuit Bias Current
Drive Circuit Operating
Current
VCIN Rising
3.5
VCIN Falling
550
3.9
V
DISB# = 0, VCIN = 5V
50
75
A
DISB# = High, VPWM = Open
350
500
A
DISB# = High, VPWM = 0V
650
A
DISB# = High, VPWM = 300kHz @ 50%
46
mA
DISB# = High, VPWM = 1MHz @ 50%
152
mA
mV
PWM INPUT (AOZ5066QI)
VPWMH
PWM Input High Threshold
VPWM Rising, VCIN = 5V
3.6
3.9
4.1
V
VPWML
PWM Input Low Threshold
VPWM Falling, VCIN = 5V
0.8
1.0
1.2
V
IPWM
PWM Pin Input Current
Source or Sink, VPWM = 0V to 5V
VTRIH
PWM Input Tri State
Threshold
VPWM Rising, VCIN = 5V
1.0
VPWM Falling, VCIN = 5V
3.4
Tri State Threshold
Hysteresis
VPWM Rising, VCIN = 5V
280
mV
VPWM Falling, VCIN = 5V
170
mV
VTRIL
VTRRH
VTRFH
Rev. 3.0 December 2013
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A
±250
1.3
1.6
3.7
4.0
V
V
Page 4 of 16
AOZ5066
Electrical Characteristics(3) (Continued)
TA = 25°C, VIN = 12V, VDRV = VCIN = 5V unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
PWM INPUT (AOZ5066QI-01)
VPWMH
PWM Input High Threshold
VPWM Rising, VCIN = 5V
1.8
2.0
2.2
V
VPWML
PWM Input Low Threshold
VPWM Falling, VCIN = 5V
0.8
1.0
1.2
V
IPWM
PWM Pin Input Current
Source or Sink, VPWM = 0V to 3V
VTRIH
PWM Input Tri State
Threshold
VPWM Rising, VCIN = 5V
1.0
1.3
1.6
V
VPWM Falling, VCIN = 5V
1.5
1.75
2.0
V
VTRIL
VTRRH
VTRFH
Tri State Threshold
Hysteresis
A
±10
VPWM Rising, VCIN = 5V
300
mV
VPWM Falling, VCIN = 5V
300
mV
DISB# INPUT
VDISBON
Outputs Enable Threshold
VCIN = 5V
VDISBOFF
Outputs Disable Threshold
VCIN = 5V
DISB# pin input current
Source or Sink
IDISB
2.0
V
0.8
V
A
±10
SMOD INPUT
VSMODH
SMOD Enable Threshold
VCIN = 5V
2.0
V
VSMODL
SMOD Disable Threshold
VCIN = 5V
ISMOD
SMOD Pin Input Current
Source or Sink
±10
A
0.8
V
GATE DRIVER TIMINGS
tPDLU
PWM to HS Gate
PWM H L, GH H L
20
ns
tPDLL
PWM to LS Gate
PWM L H, GL H L
35
ns
tPDHU
LS to HS Gate Deadtime
GL H L, GH L H
16
ns
tPDHL
HS to LS Gate Deadtime
GH H L, GL L H
17
ns
tTSSHD
Tri State Shutdown Delay
170
ns
Tri State Propagation Delay
35
ns
tPTS
THERMAL
SHUTDOWN(5)
TJTHDN
Shutdown Threshold
150
°C
TJHYST
Hysteresis
15
°C
VTHDNL
THDN Pin Output Low
0.06
V
RTHDNL
THDN Pull Down
Resistance
60
5k pull up resistor to VCIN
Notes:
3. All voltages are specified with respect to the corresponding GND pin
4. Characterisation value. Not tested in production.
5. Temperature sensed on the driver pad
Rev. 3.0 December 2013
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Page 5 of 16
AOZ5066
Typical Performance Characteristics
Unless otherwise noted, VIN = 12V, VDRV = VCIN = 5V, Fsw = 670kHz, Lout = 470nH, Vout = 1.2V.
Loss and efficiency measured on AOS evaluation board at TA = 25°C. No forced air for module loss < 7W.
Module loss includes power MOSFET loss plus drive circuit loss.
Power train consists of AOZ5066 power module plus output inductor IHLP6767GZERR47M01.
Power train efficiency does not include other losses in the test board.
Fig 1. Power Loss vs. Load Current
Fig 2. Load Current vs. Temperature
65
25
60
55
Load Current (A)
Power Loss (W)
20
15
10
50
45
40
5
0
800khz
300khz
35
800khz
300khz
30
5
10
15
20
25
30
35
40
45
50
55
0
60
10
20
30
Load Current (A)
50
60
70
80
90 100 110 120
PCB Temperature (°C)
Fig 3. Normalised Module Loss and Power Train Efficiency
vs. Drive Voltage
Fig 4. IDRV + IVCIN vs. Drive Voltage
1.05
40
1.04
39
Driver Current IDRV + IVCIN (mA)
Normalised Loss and Efficiency
40
1.03
1.02
1.01
1.00
0.99
0.98
0.97
Loss
Efficiency
0.96
38
37
36
35
34
33
32
31
0.95
30
4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
6
Rev. 3.0 December 2013
4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
6
Drive Voltage
Drive Voltage
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Page 6 of 16
AOZ5066
Typical Performance Characteristics (Continued)
Fig 6. IDRV + IVCIN vs. Temperature
Fig 5. Normalised IDRV + IVCIN vs. Operating Frequency
1.035
1.030
3.5
Normalised Driver Current (mA)
Normalised Driver Current (mA)
4.0
3.0
2.5
2.0
1.5
1.0
1.025
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.5
300
600
1000
-40
-25
0
Operating Frequency (kHz)
25
50
85
100
125
Temperature (°C)
Fig 8. PWM Input Threshold vs. Temperature
Fig 7. VCIN UVLO Threshold vs. Temperature
(PWM = 5V)
4.50
3.70
3.60
4.00
3.50
PWM Threshold (V)
VCIN Threshold (V)
3.50
3.40
3.30
3.20
3.10
3.00
3.00
2.50
PWM Rising Threshold
2.00
PWM Falling Threshold
1.50
2.90
VCIN Rising Threshold
2.80
1.00
VCIN Falling Threshold
0.50
2.70
-40
-25
0
25
50
85
100
125
-40
-25
0
Temperature (°C)
85
100
125
Fig 10. PWM Input Tri State Hold Off Time vs. Temperature
(PWM = 5V)
240
4.00
220
Tri State Hold Off Time (ns)
Tri State Threshold (V)
50
Temperature (°C)
Fig 9. PWM Input Tristate Threshold vs. Temperature
4.50
25
3.50
3.00
2.50
Tri State Rising Threshold
2.00
Tri State Falling Threshold
1.50
200
180
160
140
120
1.00
0.50
100
-40
-25
0
25
50
85
100
125
Temperature (°C)
Rev. 3.0 December 2013
-40
-25
0
25
50
85
100
125
Temperature (°C)
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Page 7 of 16
AOZ5066
Typical Performance Characteristics (Continued)
Fig 12. SMOD Input Threshold vs. Temperature
1.75
1.70
1.70
1.65
1.65
SMOD Thresholds (V)
DISB# Thresholds (V)
Fig 11. DISB# Input Threshold vs. Temperature
1.75
1.60
1.55
1.50
DISB# Rising Threshold
1.45
DISB# Falling Threshold
1.40
1.60
1.55
1.50
SMOD Rising Threshold
1.45
SMOD Falling Threshold
1.40
1.35
1.35
1.30
1.30
1.25
1.25
-40
-25
0
25
50
85
100
125
Temperature (°C)
Rev. 3.0 December 2013
-40
-25
0
25
50
85
100
125
Temperature (°C)
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Page 8 of 16
AOZ5066
Timing Diagram
PWM Tri State Band
PWM
tPDLL
tPDLU
tTSSHD
tTSSHD
GH
tPTS
tPTS
GL
tPDHU
tPDHL
Figure 13. Timing Diagram
Application Information
AOZ5066QI and AOZ5066QI-01 are fully integrated
power modules designed to work over an input voltage
range of 4.5V to 25V with 5V supplies for gate drive and
internal control circuits. A number of features are
provided making the AOZ5066QI a highly versatile power
module. High side and low side power MOSFETs are
combined in one package with the pin outs optimized for
power routing with minimum parasitic inductances. The
MOSFETs are individually tailored for efficient operation
as either high side or low side switches in a low duty
cycle synchronous buck converter. A high current driver
is also included in the package which minimizes the gate
drive loop and results in extremely fast switching. The
modules are fully compatible with Intel DrMOS
specification Rev 4.0 in form fit and function.
Powering the Module and the Gate Drives
An external supply VDRV of 5V is required for driving the
MOSFETs. The MOSFETs are designed with low gate
thresholds so that lower drive voltage can be used to
reduce the switching and drive losses without
compromising the conduction losses. The control logic
supply VCIN can be derived from the gate drive supply
VDRV through an RC filter to bypass the switching noise.
See Figure 14 for recommended gate drive supply
connections. The gate driver is capable of supplying
several amperes of peak current into the LS FET to
achieve extremely fast switching. A ceramic bypass
capacitor of 1F or higher is recommended from VDRV to
CGND.
Rev. 3.0 December 2013
The boost supply for driving the high side MOSFET is
generated by connecting a small capacitor between
BOOT pin and the switching node VSWH. It is
recommended that this capacitor Cboot be connected as
close as possible to the device across pins 4 and 7.
Boost diode is integrated into the package. Rboot is an
optional resistor used by designers to slow down the turn
on speed of the high side MOSFET. The value is a
compromise between the need to keep both the
switching time and VSWH node spikes as low as
possible and is typically 1 to 5
Undervoltage Lockout and Enable
VCIN is monitored for UVLO conditions and both outputs
are actively held low unless adequate gate supply is
available. The undervoltage lockout is set at 3.5V with a
550mV hysteresis. Since the PWM control signals are
provided typically from an external controller or a digital
processor extra care must be taken during start up.
The AOZ5066QI must be powered up and enabled
before the PWM input is applied. It should be ensured
that PWM signal goes through a proper soft start
sequence to minimise inrush current in the converter
during start up. Powering the module with a full duty
cycle PWM signal already applied may lead to a number
of undesirable consequences as explained below.
Outputs can also be turned off through the DISB# pin.
When this input is grounded the drivers are disabled and
held active low. The module is in standby mode with low
quiescent current of less than 75A.
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Page 9 of 16
AOZ5066
AOZ5066
+5V
VDRV
VIN
VIN
BOOT
VCIN
Rboot
Drive Logic
and
Dead Time
Control
PWM
SMOD
DISB#
THDN
CGND
CGND
Cboot
VSWH
PGND
PGND
Figure 14. Applying VDRV and Generating BOOT Supply
IMPORTANT: If the DISB# is used it is necessary to
ensure proper coordination with soft start and enable
features of the external PWM controller in the system.
Every time AOZ5066QI is disabled through DISB# there
will be no output and the external controller may enter
into open loop and put out a PWM signal with maximum
duty ratio possible. If the AOZ5066QI is re-enabled by
taking DSBL# high, there will be extremely large inrush
currents while the output voltage builds up again which
may drive the system into current limit. There might be
undesirable consequences such as inductor saturation,
overloading of the input or even a catastrophic failure of
the device. It is recommended that the PWM controller
be disabled when AOZ5066QI is disabled or non
operational because of UVLO. The PWM controller
should always be enabled with a soft start to minimise
stresses on the converter.
The high side MOSFET in AOZ5066QI is optimized for
fast switching with low duty ratios. It has ultra low gate
charges which have been achieved as a trade off with
higher RDS(ON) value. When the module is operated at
low VIN the duty ratio will be higher and conduction
losses in the HS FET will also be correspondingly higher.
This will be compensated to some extent by reduced
switching losses. The total power loss in the module may
appear to be low even though in reality the HS MOSFET
losses may be disproportionately high. Since the two
MOSFETs have their own exposed pads and PCB
copper areas for heat dissipation, the HS FET may be
much hotter than the LS FET. It is recommended that
worst case junction temperature be measured and
ensured to be within safe limits when the module is
operated with high duty ratios.
PWM Input
In general it should be noted that AOZ5066QI is a
combination of two MOSFETs with an unintelligent driver,
all of which are optimized for switching at the highest
efficiency. Other than UVLO and thermal protection, it
does not have any monitoring or protection functions built
in. The PWM controller should be designed in to perform
these functions under all possible operating and transient
conditions.
Input Voltage VIN
AOZ5066QI is rated to operate over a wide input range of
4.5V to 25V. As with any other synchronous buck
converter, large pulse currents at high frequency and
extremely high di/dt rates will be drawn by the module
during normal operation. It is strongly recommended to
bypass the input supply very close to package leads with
X7R or X5R quality ceramic capacitors.
Rev. 3.0 December 2013
AOZ5066QI is offered in two versions which can be
interfaced with PWM logic compatible with either 5V
(TTL) or 3V (CMOS). Refer to Figure 13 for the timing
and propagation delays between the PWM input and the
gate drives. The PWM is also a tri state compatible input.
When the input is high impedance or unconnected both
the gate drives will be off and the gates are held active
low. The PWM Threshold Table (Table 1) lists the
thresholds for high and low level transitions as well as tri
state operation. As shown in Figure 13, there is a hold off
delay between the time PWM signal enters the tri state
window and the corresponding gate drive is pulled low.
This delay is typically 170ns and intended to prevent
spurious triggering of the tri state mode which may be
caused either by noise induced glitches in the PWM
waveform or slow rise and fall times.
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Page 10 of 16
AOZ5066
Table 1. PWM Input and Tri State Thresholds
Thresholds
VPWMH
VPWML
VTRIH
VTRIL
AOZ5066QI
3.9V
1.0V
1.3V
3.7V
AOZ5066QI-01
2V
1V
1.3V
1.75V
Note: See Figure 13 for propagation delays and tri state window.
Diode Mode Emulation of Low Side MOSFET (SMOD)
AOZ5066QI can be operated in the diode emulation or
skip mode using the SMOD pin. This is useful if the
converter has to operate in asynchronous mode during
start up, light load or under pre bias conditions. If SMOD
is taken high, the controller will use the PWM signal as
reference and generate both the high and low side
complementary gate drive outputs with the minimal
delays necessary to avoid cross conduction. When the
pin is taken low the HS FET drive is not affected but
diode emulation mode is activated for the LS FET. See
Table 2 for a comprehensive view of all logic inputs and
corresponding drive conditions.
Table 2. Control Logic Truth Table
DISB#
SMOD
PWM
GH
GL
L
X
X
L
L
H
L
H
H
L
H
L
L
L
See Note
H
X
Tri State
L
L
H
H
H
H
L
H
H
L
L
H
Note: Diode emulation mode is activated when SMOD pin is held low.
Gate Drives
AOZ5066QI has an internal high current high speed
driver that generates the floating gate drive for the
HS FET and a complementary drive for the LS FET.
Propagation delays between transitions of the PWM
waveform and corresponding gate drives are kept to the
minimum. An internal shoot through protection scheme
ensures that neither MOSFET turns on while the other
one is still conducting, thereby preventing shoot through
condition of the input current. When the PWM signal
makes a transition from H L or L H, the
corresponding gate drive GH or GL begins to turn off.
The adaptive timing circuit monitors the falling edge of
the gate voltage and when the level goes below 1V, the
complementary gate driver is turned on. The dead time
between the two switches is minimized, at the same time
preventing cross conduction across the input bus. The
adaptive circuit also monitors the switching node VSWH
and ensures that transition from one MOSFET to another
Rev. 3.0 December 2013
always takes place without cross conduction, even under
transient and abnormal conditions of operation.
The gate pins GH and GL are brought out on pins 6 and
36 respectively. However these connections are not
made directly to MOSFET gate pads and their voltage
measurement may not reflect the actual gate voltage
applied inside the package. The gate connections are
primarily for functional tests during manufacturing and no
connections should be made to them in the application.
Thermal Shutdown
The module temperature is internally sensed and an
alarm is asserted if it exceeds 150°C. The alarm is reset
when the temperature cools down to 135°C. The THDN
is an open drain pin that is pulled to CGND to indicate an
overtemperature condition. It may be pulled up to VCIN
through a resistor for monitoring purposes.
PCB Layout Guidelines
AOZ5066 is a high current module rated for operation up
to 1MHz. This requires extremely fast switching speeds
to keep the switching losses and device temperatures
within limits. Having a robust gate driver integrated in the
package helps to minimise the driver-to-MOSFET gate
pad connections without involving the parasitics of the
package or PCB traces. While excellent switching
speeds are achieved, correspondingly high levels of dv/dt
and di/dt will be observed throughout the power train
which requires careful attention to PCB layout to
minimise voltage spikes and other transients. As with any
synchronous buck converter layout the critical
requirement is to minimise the area of the primary
switching current loop, formed by the VIN, VSWH and
the input bypass capacitor Cin. The PCB design is
somewhat simplified because of the optimized pin out in
AOZ5066QI. The bulk of VIN and PGND pins are located
adjacent to each other and the input bypass capacitors
should be placed as close as possible to these pins. The
area of the secondary switching loop, formed by VSWH,
output inductor and output capacitor Cout is the next
critical parameter. The ground plane should be extended
and the negative pins of Cout should be returned to it,
again as close as possible to the device pins.
While AOZ5066QI is extremely efficient it can still
dissipate up to 6W of heat which requires attention to
thermal design. MOSFETs in the package are directly
attached to individual exposed pads to simplify thermal
management. Both VIN and VSWH pads should be
attached to large areas of PCB copper. Thermal reliefs
should be avoided to ensure proper heat dissipation to
the board. An inner power plane layer dedicated to VIN,
typically the 12V system input, is desirable and vias
should be provided near the device to connect the VIN
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Page 11 of 16
AOZ5066
copper pour to the power plane. Though ground does not
form a part of any device tabs, significant amount of heat
is dissipated though multiple PGND pins. A large copper
pour connected to PGND pins and further to the system
ground plane through vias will further improve thermal
management of the system.
VIN
Figure 15 illustrates the various copper pours and bypass
capacitor locations.
CGND
VSWH
Figure 15. PCB Layout Illustration for Minimizing Current Loops
Rev. 3.0 December 2013
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Page 12 of 16
AOZ5066
Package Dimensions, 6x6 QFN-40 EP3_S
D
A
D/2
30
B
21
20
31
E/2
2
INDEX AREA
(D/2xE/2)
E
2x
aaa C
e
40
11
1
2x 2x
aaa C
10
A3
TOP VIEW
A3
ccc C
C
A
SEATING
PLANE
4
3
40 x b
ddd C
A1
bbb M C A B
SIDE VIEW
D1
PIN#1 IDA
C0.30 x 45°
1
D1
e
e/2
L6
10
40
11
E1
E1
L2
L1
L1
L3
L5
E2
L
20
31
21
30
L
L4
L5
D2
BOTTOM VIEW
Notes:
1. All dimensions are in millimeters.
2. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002.
3. Dimension b applies to metallized terminal and is measured between 0.20mm and 0.35mm from the terminal tip. If the terminal
has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
4. Coplanarity applies to the terminals and all other bottom surface metalization.
Rev. 3.0 December 2013
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Page 13 of 16
AOZ5066
Package Dimensions, 6x6 QFN-40 EP3_S (Continued)
4.40
0.40
0.25
2.87
2.27
0.21
0.20
2.87
0.20
0.37
2.23
1.50
0.73
0.52
0.55
0.75
0.54
2.20
0.30X45°
0.25
2.00
2.87
0.50 REF
2.00
2.87
UNIT: mm
RECOMMENDED LAND PATTERN
Dimensions in millimeters
Dimensions in inches
Symbols
Min.
Typ.
Max.
Symbols
Min.
Typ.
Max.
A
A1
A3
b
D
0.70
0.00
0.75
0.02
0.20 REF
0.25
6.00 BSC
0.80
0.05
A
A1
A3
b
D
0.028
0.000
0.030
0.001
0.008 REF
0.010
0.236 BSC
0.031
0.002
0.20
0.008
0.014
D1
1.90
2.00
2.10
D1
0.075
0.079
0.083
D2
4.30
4.40
4.50
D2
0.169
0.173
0.177
E
Rev. 3.0 December 2013
0.35
E
6.00 BSC
0.236 BSC
E1
E2
1.40
2.17
1.50
2.27
1.60
2.37
E1
E2
0.055
0.085
0.059
0.089
0.063
0.093
e
L
L1
L2
L3
L4
L5
L6
aaa
0.30
0.15
0.15
0.63
0.44
0.30
0.27
0.50 BSC
0.40
0.20
0.21
0.73
0.54
0.40
0.37
0.15
0.50
0.25
0.26
0.83
0.64
0.50
0.47
e
L
L1
L2
L3
L4
L5
L6
aaa
0.012
0.006
0.006
0.024
0.017
0.012
0.011
0.020 BSC
0.016
0.008
0.008
0.028
0.021
0.016
0.015
0.006
0.020
0.010
0.010
0.032
0.025
0.020
0.019
bbb
ccc
0.10
0.10
bbb
ccc
0.004
0.004
ddd
0.08
ddd
0.003
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Page 14 of 16
AOZ5066
Tape and Reel Dimensions, 6x6 QFN
Carrier Tape
P1
D1
P2
E1
T
E2
E
C
L
B0
K0
D0
P0
A0
Feeding Direction
UNIT: MM
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
QFN6x6
(16mm)
6.30
±0.20
6.30
±0.20
1.10
±0.20
1.50
MIN.
1.50
+0.1
-0.0
16.0
±0.3
1.75
±0.10
7.5
±0.1
12.00
±0.20
4.00
±0.20
2.00
±0.10
0.30
±0.05
Reel
W1
S
G
N
M
K
V
R
H
W
UNIT: MM
Tape Size
Reel Size
M
N
W
W1
H
K
S
16mm
Ø330
Ø330
Max.
Ø100
Min.
16.4
+2.0
-0.0
22.4
Max.
Ø13.0
+0.5
-0.2
10.1
Min.
1.5
Min.
G
R
V
---
---
---
Leader/Trailer and Orientation
Trailer Tape
300mm min.
or 75 Empty Pockets
Rev. 3.0 December 2013
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min.
or 125 Empty Pockets
Page 15 of 16
AOZ5066
Part Marking
AOZ5066QI
(6.0 x 6.0 QFN)
Z5066QI
Part Number Code
Assembly Lot Code
Fab Code & Assembly Location
Year Code & Week Code
AOZ5066QI-01
(6.0 x 6.0 QFN)
Z5066QI1
Part Number Code
Assembly Lot Code
Fab Code & Assembly Location
Year Code & Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 3.0 December 2013
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 16 of 16