AOZ5166QI-01
High-Current, High-Performance
DrMOS Power Module
General Description
Features
The AOZ5166QI-01 is a high efficiency synchronous
buck power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The High-Side (HS) MOSFET has
low capacitance and gate charge for fast switching with
low duty cycle operation. The Low-Side (LS) MOSFET
has ultra low RDS(ON) to minimize conduction losses.
Fully complies with Intel DrMOS Rev 4.0 specifications
The AOZ5166QI-01 is intended for use with 3V (CMOS)
and Tri-state input compatibility by using both the PWM
and DISB# inputs for accurate control of the power
MOSFET’s switching activities.
Single pin control for diode
A number of features are provided making the
AOZ5166QI-01 a highly versatile power module. The
boot supply diode is integrated in the driver. The LS
MOSFET can be driven into diode emulation mode to
provide asynchronous operation when required. The
pinout is optimized for low parasitics, keeping their
effects to the minimum.
Applications
4.5V to 18V input voltage range
4.5V to 5.5V driver supply range
Up to 60A output current
Up to 1MHz PWM operation
3V PWM / Tri-state input compatible
Under-voltage lockout protection
Emulation / CCM operation
6mm x 6mm QFN-40L package
Servers
VRMs for Motherboards
Point-of-Load DC/DC Converters
Memory and Graphic Cards
Video Gaming Consoles
Typical Application Circuit
AOZ5166QI-01
+12V
VIN
CVIN
SMOD
BOOT
CBOOT
DISB#
Drive
Logic
and
Delay
Controller
PWM
VSWH
L
VOUT
THDN
COUT
CGND
PGND
VCIN
CGND
+5V
Rev. 1.0 March 2016
VDRV
CVCIN
PGND
CDRV
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Page 1 of 17
AOZ5166QI-01
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ5166QI-01
-40°C to +85°C
6x6 QFN-40L
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
VIN
11
VIN
12
VIN
VIN
VIN
VSWH
GH
CGND
BOOT
VDRV
VCIN
SMOD
Pin Configuration
10
9
8
7
6
5
4
3
2
1
40
PWM
39
DISB#
CGND
VIN
VIN
13
38
THDN
VIN
14
37
CGND
VSWH
15
36
GL
PGND
16
35
VSWH
PGND
17
34
VSWH
PGND
18
33
VSWH
PGND
19
32
VSWH
PGND
20
31
VSWH
PGND
27
28
29
31
VSWH
PGND
26
VSWH
PGND
25
PGND
24
PGND
23
PGND
22
PGND
21
PGND
VSWH
6x6 QFN-40
(Top View)
Rev. 1.0 March 2016
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Page 2 of 17
AOZ5166QI-01
Pin Description
Pin Number
Pin Name
Pin Function
1
SMOD
Pull Low to Enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode
2
VCIN
Control Supply Voltage Input (5V) for all MOSFET Driver Control functions.(NOT a LS MOSFET Gate Driver Supply Rail - see VDRV pin). Place a 1µF capacitor to CGND (Pin 5).
3
VDRV
Power Supply Voltage Rail (5V) for the BOOT capacitor charging diode and LS MOSFET
Driver. Nominal 5V.
4
BOOT
HS MOSFET Gate Driver Supply Rail (5V Nominal). Mount a 100nF ceramic capacitor across
this pin and the VSWH pin at Pin 7.
5, 37
CGND
Control or analog ground for return of control signals and bypass capacitors.
Attached to exposed pad in the driver section Pins 5 & 37.
6
GH
Gate of the HS MOSFET. Used for module testing during production. No user connections.
7
VSWH
HS MOSFET Gate Driver Return Rail. A 100nF ceramic capacitor is mounted to this pin and
the BOOT pin.
8 ~ 14
VIN
Power input to the switching MOSFETs. Connected to the HS MOSFET drain pad.
15
VSWH
Switching or the phase node pin. Not for power connections.
16 ~ 28
PGND
Power Ground Return Rail for the LS MOSFET Driver. A 1µF ceramic capacitor is connected
between this pin and VDRV (Pin 3).
29 ~ 35
VSWH
High Current Switching terminal of both the HS and LS MOSFETs. Pins to the internal circuitry
for Zero Cross Detect, Boost UVLO and Anti-Overlap Control.
36
GL
38
THDN
Active Low. Thermal Monitor. Open drain outputs a Flag signal to the controller when a thermal
fault has occurred.
39
DISB#
Enable pin for all MOSFET Driver functionality. When pulled low, the GH and GL outputs will
be pulled low leaving the VSWH node floating.
40
PWM
PWM input signal from the controller IC. This input can accept zero to 5V logic and Tri-state
logic levels.
Rev. 1.0 March 2016
LS MOSFET Gate. Used for module testing during production. No user connections.
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Page 3 of 17
AOZ5166QI-01
Functional Block Diagram
VCIN
BOOT
VIN
VDRV
REF/BIAS
UVLO
SMOD
PSKIP/ZCD
Enable
VBST
UVLO EN
Diode
DISB#
Control
Logic
Sequencing
and
Propagation
Delay Bank
HS Gate
Driver
40kΩ
HS
Output
Check
UVLO EN
LS Min ON
PWM/
Tri-State
Logic
Level
Translator
Driver
Logic
LS
PWM
GH
VSWH
HS
ENABLE
UVLO
EN
VSWH
BST
UVLO
ZCD
2mV
PWM
Tri-State
Irev
LS Check
Tri-State
Clamps
Warning
VDRV
UVLO EN
UVLO EN
LS Gate
Driver
THDN
Thermal
Monitor
Thermal
Monitor
OTP
UVLO
VSWH
GL
40kΩ
PGND
Temp Fault
PGND
Rev. 1.0 March 2016
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Page 4 of 17
AOZ5166QI-01
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Rating
Supply Voltage (VIN)
Parameter
-0.3V to 25V
Switch Node Voltage (VSWH)
(1)
-8V to 30V
(2)
-0.3V to 35V
Bootstrap Voltage (VBOOT)
VBOOT Voltage Transient
(1)
40V
VCIN Supply Voltage to CGND
(DC)
-0.3V to 6.5V
VCIN and Gate Drive Voltages
{VCIN, VDRV, (VBOOT –
VSWH)}(1)
-0.3V to 7V
(Transient)
Control Inputs
(PWM, SMOD, DISB#)
Rating
Supply Voltage (VIN)
4.5V to 18V
Supply and Gate Drive Voltages
{VCIN, VDRV, (VBOOT – VSWH)}
4.5V to 5.5V
Control Inputs
(PWM, SMOD, DISB#)
0V to VCIN – 0.3V
Operating Frequency
200kHz to 1MHz
-0.3V to VCIN +0.3V
Storage Temperature (TS)
-65°C to +150°C
Junction Temperature (TJ)
+150°C
(3)
2kV
ESD Rating
Notes:
1. Peak voltages can be applied for 25nS per switching cycle.
2. Switching node Absolute Maximum Rating.
3. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Electrical Characteristics(3)
TA = 25°C, VIN = 12V, VCIN = VDRV = 5V unless otherwise specified.
Symbol
VIN
Parameter
Operating Voltage
RθJA (4)
Thermal Resistance
Min.
Typ.
4.5
VDRV Tied to VCIN
VCIN
RθJC(4)
Conditions
PCB Temp = 100°C
4.5
Max.
Units
18
V
5.5
V
5.0
°C / W
50
°C / W
INPUT SUPPLY AND UVLO
VCINON
VCINHYST
Undervoltage Lockout
VCIN Rising
3.5
VCIN Hyst
600
mV
1
µA
DISB# = 0, VCIN = 5V (Shutdown)
IVCIN
IVDRV
Control Circuit Bias Current
Drive Circuit Operating
Current
Rev. 1.0 March 2016
3.8
V
SMOD = High, DISB# = High, VPWM = 0V
(No Switching)
400
SMOD = Low, DISB# = High, VPWM = 0V
(No Switching)
400
µA
SMOD = Low, DISB# = High,
VPWM = 1.5V (Tri-State, No Switching)
300
µA
DISB# = High, VPWM = 300kHz
22
mA
DISB# = High, VPWM = 1MHz
72
mA
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Page 5 of 17
AOZ5166QI-01
Electrical Characteristics(3) (Continued)
TA = 25°C, VIN = 12V, VCIN = VDRV = 5V unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
PWM INPUT
VPWMH
PWM Input High Threshold
VPWM Rising, VCIN = 5V
2.2
VPWML
PWM Input Low Threshold
VPWM Falling, VCIN = 5V
IPWM
PWM Pin Input Current
Source or Sink, VPWM = 0V to 3V
VTRIH
PWM Input Tri State
Threshold Window
VCIN = 5V
-40°C < Temp < +85°C
1.35
Outputs Enable Threshold
VCIN = 5V
2.0
VDISBOFF
Outputs Disable Threshold
VCIN = 5V
RDISB
DISB# Pin Input Resistance
V
0.8
30
V
µA
1.65
V
DISB# INPUT
VDISBON
V
0.8
1000
V
kΩ
SMOD INPUT
SMOD Enable Threshold
VCIN = 5V
VSMODL
SMOD Disable Threshold
VCIN = 5V
RSMOD
SMOD Pin Input Resistance
VSMODH
2.0
V
0.8
V
1000
kΩ
26
ns
GATE DRIVER TIMINGS
tPDLU
PWM to HS Gate
PWM H → L, GH H → L
tPDLL
PWM to LS Gate
PWM L → H, GL H → L
18
ns
tPDHU
LS to HS Gate Deadtime
GL H → L, GH L → H
12
ns
tPDHL
HS to LS Gate Deadtime
VHWH H → L, GL L → H
13
ns
tTSSHD
Tri State Shutdown Delay
155
ns
tTSEXIT
Tri State Propagation Delay
18
ns
THERMAL SHUTDOWN
TJTHDN
Junction Thermal Threshold
150
°C
TJHYST
Junction Thermal Hysteresis
30
°C
VTHDNL
THDN Pin Output Low
60
mV
RTHDNL
THDN Pull Down
Resistance
60
Ω
Notes:
3. All voltages are specified with respect to the corresponding GND pin.
4. Characterisation value. Not tested in production.
Rev. 1.0 March 2016
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Page 6 of 17
AOZ5166QI-01
Timing Diagrams
PWM
2.2V
0.8V
tPDHL
tPDLL
GL
10%
tPDLU
GH
tPDHU
VSWH
1V
Figure 1. PWM Logic Input Timing Diagram
PWM
2.2V
tTSSHD
0.8V
tTSSHD
tTSSHD
0.8V
tTSSHD
GL
10%
tTSEXIT
tTSEXIT
tTSEXIT
tTSEXIT
GH - VSWH
Figure 2. PWM Tri-State Input Logic Timing Diagram
Rev. 1.0 March 2016
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Page 7 of 17
AOZ5166QI-01
Typical Performance Characteristics
TA = 25°C, VIN = 12V, VOUT = 1.8V, VCIN = VDRV = 5V unless otherwise specified.
Fig 3. Efficiency vs. Load Current
Fig 4. Power Loss vs. Load Current
95
20
94
18
93
16
92
Power Loss (W)
Efficiency (%)
91
90
89
88
87
86
85
14
12
10
8
6
84
4
83
82
F = 600kHz
2
81
0
80
5
10
15
20
25
30
35
40
45
50
55
60
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60
Load Current (A)
Load Current (A)
Fig 5. Supply Current (IDRV) vs. Temperature
Fig 6. PWM Input Threshold vs. Temperature
118
2.25
112
2.10
106
PWM Logic High to Tri-State Threshold
1.5MHz
1.95
94
PWM Threshold (V)
Supply Current (mA)
100
88
82
76
70
1MHz
64
58
800kHz
52
1.80
1.65
Tri-State Window
(300mV)
1.50
1.35
1.20
1.05
PWM Tri-State to Logic High Threshold
46
40
0.90
600kHz
0.75
34
-40
-20
0
20
40
60
80
100
120
-40
140
-20
0
20
Temperature (°C)
40
60
80
100
120
140
Temperature (°C)
Fig 7. PWM Logic Threshold vs. Temperature
Fig 8. UVLO (VCIN) vs. Temperature
2.15
3.50
3.45
2.00
3.40
PWM Logic High Threshold
UVLO High
3.35
UVLO Threshold (V)
PWM Threshold (V)
1.85
1.70
1.55
1.40
1.25
PWM Logic Low Threshold
3.30
3.25
3.20
3.15
3.10
3.05
3.00
1.10
UVLO Low
2.95
0.95
2.90
0.80
-40
-20
0
20
40
60
80
100
120
140
2.85
-40
Temperature (°C)
Rev. 1.0 March 2016
-20
0
20
40
60
80
100
120
140
Temperature (°C)
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Page 8 of 17
AOZ5166QI-01
Typical Performance Characteristics (Continued)
TA = 25°C, VIN = 12V, VOUT = 1.8V, VCIN = VDRV = 5V unless otherwise specified.
Fig 9. DISB# Threshold vs. Temperature
1.70
1.65
DISB# Threshold (V)
1.60
Enable Threshold
1.55
1.50
1.45
1.40
Disable Threshold
1.35
1.30
1.25
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Rev. 1.0 March 2016
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Page 9 of 17
AOZ5166QI-01
Application Information
AOZ5166QI-01 is a fully integrated power module
designed to work over an input voltage range of 4.5V to
18V with a separate 5V supply for gate drive and internal
control circuits. A number of desirable features makes
AOZ5166QI-01 a highly versatile power module. The
MOSFETs are individually optimized for efficient
operation on either HS or LS switches in a low duty cycle
synchronous buck converter. A high current driver is also
integrated in the package that minimizes the gate drive
loop and results in extremely fast switching. The modules
are fully compatible with Intel DrMOS specification Rev
4.0 in form fit and function.
Powering the Module and the Gate Drives
An external supply VDRV of 5V is required for driving the
MOSFETs. The MOSFETs are designed with low gate
thresholds so that lower drive voltage can be used to
reduce the switching and drive losses without
compromising the conduction losses. The control logic
supply VCIN can be derived from the gate drive supply
VDRV through an RC filter to bypass the switching noise.
See Figure 11 for recommended gate drive supply
connections. The gate driver is capable of supplying
several amperes of peak current into the Low Side
MOSFET to achieve extremely fast switching. A ceramic
bypass capacitor of 1µF or higher is recommended from
VDRV to CGND.
The boost supply for driving the HS MOSFET is
generated by connecting a small capacitor between
BOOT pin and the switching node VSWH. It is
recommended that this capacitor CBOOT be connected as
close as possible to the device across Pins 4 and 7.
Boost diode is integrated into the package. RBOOT is an
optional resistor used by designers to slow down the turn
on speed of the HS MOSFET. Typical values between
1Ω to 5Ω is a compromise between the need to keep
both the switching time and VSWH node spikes as low
as possible.
signal may lead to a number of undesirable
consequences as explained below. In general it should be
noted that AOZ5166QI-01 is a combination of two
MOSFETs with an Intel DrMOS specification Rev 4.0
compliant driver, all of which are optimized for switching at
the highest efficiency. Other than UVLO and thermal
monitor, it does not have any current monitoring or
protection response functions built in. The PWM
controller should be designed in to perform these
functions under all possible operating and transient
conditions.
Outputs can also be turned off through the DISB# pin.
When this input is grounded the drivers are disabled and
held active low. The module is in standby mode with low
quiescent current of less than 1µA.
IMPORTANT: If the DISB# is used, it is necessary to
ensure proper coordination with soft start and enable
features of the external PWM controller in the system.
Every time AOZ5166QI-01 is disabled through DISB#
there will be no output and the external controller may
enter into open loop and put out a PWM signal with
maximum duty ratio possible. If the AOZ5166QI-01 is reenabled by taking DISB# high, there will be in-rush
currents while the output voltage ramps up that may drive
the system into current limit. There may be undesirable
consequences such as inductor saturation, overloading
of the input or even catastrophic failure of the device. It is
recommended that the PWM controller be disabled when
AOZ5166QI-01 is disabled or non operational because of
UVLO. The PWM controller should always be enabled
employing soft start to minimize stresses on the
converter.
In general it should be noted that AOZ5166QI-01 is a
combination of two MOSFETs and MOSFET Drivers, all
of which are optimized for switching at the highest
efficiency. The PWM controller should be designed in to
perform these functions under all possible operating and
transient conditions.
Undervoltage Lockout and Enable
Input Voltage VIN
VCIN is monitored for UVLO conditions and both outputs
are actively held low unless adequate gate supply is
available. The under-voltage lockout is set at 3.5V with
550mV of hysteresis. Since the PWM control signals are
provided typically from an external controller or a digital
processor extra care must be taken during start up.
AOZ5166QI-01 is rated to operate over a wide input range
of 4.5V to 18V. As with any other synchronous buck
converter, large pulse currents at high frequency and
extremely high di/dt rates will be drawn by the module
during normal operation. It is strongly recommended to
bypass the input supply (VIN) very close to package leads
with X7R or X5R quality surface mount ceramic
capacitors.
Since the PWM control signals are provided typically from
an external controller or a digital processor, extra care
must be taken during start up. It should be ensured that
PWM signal goes through a proper soft start sequence to
minimize in-rush current through the converter during
start up. Powering the module with a full duty cycle PWM
Rev. 1.0 March 2016
The HS MOSFET in AOZ5166QI-01 is optimized for fast
switching with low duty ratios. It has low gate charges
(QT) that have been achieved as a trade off with higher
RDS(ON) value. When the module is operated at low VIN
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Page 10 of 17
AOZ5166QI-01
the duty ratio will be higher and conduction losses in the
HS MOSFET will also be correspondingly higher. This will
be compensated to some extent by reduced switching
losses. The total power loss in the module may appear to
be low even though in reality the HS MOSFET losses
may be disproportionately high. Since the two MOSFETs
have their own exposed pads and PCB copper areas for
heat dissipation, the HS MOSFET may be much hotter
than the LS MOSFET. It is recommended that worst case
junction temperature be measured and ensured to be
within safe limits when the module is operated with high
duty ratios.
Table 2. Control Logic Truth Table
DISB#
SMOD
PWM
GH
GL
L
X
X
L
L
H
L
H
H
L
H
L
L
L
H
H
L
L
L
L
H
X
Tri State
L
L
H
H
H
H
L
H
H
L
L
H
Note: Diode emulation mode is activated when SMOD pin is held low.
PWM Input
AOZ5166QI-01 is offered to be interfaced with 3V
(CMOS) PWM logic. Refer to Figure 1 for timing and
propagation delays diagram between PWM input and
the MOSFET Gate drives.
The PWM is also a tri-state compatible input. When the
input is high impedance or unconnected both the gate
drives will turn off and the MOSFET gates are held
actively low. The PWM Threshold Table (below) lists the
thresholds for high and low level transitions as well as
tri- state operation window. As shown in Figure 2, there
is a hold off delay between the corresponding PWM tristate signal and the output gate drive being pulled low.
This delay is typically 155ns and intended to prevent
spurious triggering caused by tri-state mode entrance.
Table 1. PWM Input and Tri State Thresholds
Thresholds →
VPWMH
VPWML
VTRIH
VTRIL
AOZ5166QI-01
2.2V
0.8V
1.35V
1.65V
Note: See Figure 2 for propagation delays and tri state window.
Diode Mode Emulation of Low Side MOSFET (SMOD)
AOZ5166QI-01 can be operated in the diode emulation
or skip mode using the SMOD pin. This is useful if the
converter has to operate in asynchronous mode during
start up, light load or under pre bias conditions. If SMOD
is taken high, the controller will use the PWM signal as
reference and generate both the HS and LS
complementary gate drive outputs with minimal antioverlap delays necessary to avoid cross conduction.
When the pin is taken low the HS MOSFET drive is not
affected but diode emulation mode is activated for the LS
MOSFET. See Table 2 for all possible logic inputs and
corresponding output drive conditions.
Rev. 1.0 March 2016
Gate Drives
AOZ5166QI-01 has an internal high current high speed
driver that generates the floating gate drive for the HS
MOSFET and a complementary drive for the LS
MOSFET. Propagation delays between transitions of the
PWM waveform and corresponding gate drives are kept
to the minimum. An internal shoot through protection
scheme ensures that neither MOSFET turns on while
the other one is still conducting, thereby preventing
shoot through condition of the input current. When the
PWM signal makes a transition from H to L or L to H, the
corresponding gate drive GH or GL begins to turn off.
The adaptive timing circuit monitors the falling edge of
the gate voltage and when the level goes below 1V, the
complementary gate driver is turned on. The dead time
between the two switches is minimized, at the same time
preventing cross conduction across the input bus. The
adaptive circuit also monitors the switching node VSWH
and ensures that transition from one MOSFET to
another always takes place without cross conduction,
even under transient and abnormal conditions of
operation.
The gate pins GH and GL are brought out on Pins 6 and
36, respectively. However these connections are not
made directly to MOSFET gate pads and their voltage
measurement may not reflect the actual gate voltage
applied inside the package. The gate connections are
primarily for functional tests during manufacturing and
no connections should be made to them in the
application.
Thermal Shutdown
The module temperature is internally sensed and an
alarm is asserted if it exceeds 150°C. The alarm is reset
when the temperature cools down to 120°C. The THDN
is an open drain pin that is pulled to CGND to indicate an
over-temperature condition. It may be pulled up to VCIN
through a resistor for monitoring purposes. The
AOZ5166QI-01 device will not power down during the
over temperature condition.
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Page 11 of 17
AOZ5166QI-01
PCB Layout Guidelines
AOZ5166QI-01 is a high current module rated for
operation up to 1MHz. This requires fast switching
speeds to keep the switching losses and device
temperatures within limits. Having a robust gate driver
integrated in the package eliminates driver-to-MOSFET
gate pad parasitics of the package or PCB.
While excellent switching speeds are achieved,
correspondingly high levels of dv/dt and di/dt will be
observed throughout the power train which requires
careful attention to PCB layout to minimize voltage
spikes and other transients. As with any synchronous
buck converter layout the critical requirement is to
minimize the area of the primary switching current loop,
formed by the VIN, VSWH and the input bypass capacitor
CVIN. The PCB design is somewhat simplified because
of the optimized pin out in AOZ5166QI-01. The bulk of
VIN and PGND pins are located adjacent to each other
and the input capacitors should be placed as close as
possible to these pins. The area of the secondary
switching loop, formed by LS MOSFET, output inductor
and output capacitor COUT is the next critical parameter,
this requires second layer or “Inner 1” should always be
an unobstructed PGND plane with sufficient PGND vias
placed as close as possible to input capacitors’ PGND
pads.
While AOZ5166QI-01 is optimally efficient, it can still
dissipate up to 6W which requires attention to thermal
design. MOSFETs in the package are directly attached to
individual exposed pads to simplify thermal management.
Both VIN and VSWH pads should be attached to large
areas of PCB copper. Thermal relief pad should be
placed correspondingly to ensure proper heat dissipation
to the board. An inner power plane layer dedicated to
VIN, typically the 12V system input, is desirable and vias
should be provided near the device to connect the VIN
copper pour to the power plane. Significant amount of
heat is dissipated through multiple PGND pins. A large
copper pour connected to the PGND pins in addition to
the system ground plane through vias will further improve
thermal dissipation.
Figure 11 illustrates the various copper pours and bypass
capacitor locations.
Rev. 1.0 March 2016
VSWH
PGND
VIN
CVIN
Figure 10. Top Layer of Demo Board, VIN, VSWH
and PGND Copper Planes
As shown above in Figure 10, the top most layer of the
PCB should comprise of un-obstructed copper flooding
for the primary AC current loop that runs along the VIN
copper plane originating from the input capacitors that
are mounted to a large PGND copper plane, as well as
on the top most layer of the PCB. These copper planes
also serve as thermal relief as heat flows down to the VIN
exposed pad and onto the top layer VIN copper plane
which fans out to a wider area moving away from the 6x6
QFN package. Adding vias will only help transfer heat to
cooler regions of the PCB board through the other layers
beneath but serve no purpose to AC activity as all the AC
current sees the lowest impedance on the top layer only.
Due to the optimized bonding technique used on the
AOZ5166QI-01 internal package, the VIN input
capacitors are optimally placed for AC current activities
on both the primary and complementary current loops.
The return path of the current during the complimentary
period flows through PGND copper plane that is
symmetrically proportional to the VIN copper plane.
Due to the PGND exposed pad, heat is optimally
dissipated by flowing down through the vertically
structured lower MOSFET, through the exposed PGND
pad and down to the PCB top layer PGND copper plane
that also fans outward, moving away from the package.
As the primary and secondary (complementary) AC
current loops move through VIN to VSWH and through
PGND to VSWH, large positive and negative voltage
spike appear at the VSWH terminal which are caused by
the large internal dI/dts produced by the in-package
parastics. To minimize the effects of this interference, the
VSWH terminal at which the main inductor L1 is mounted
to, is sized just so the inductor can physically fit. The goal
is to employ the least amount of copper area for this
VSWH terminal just enough so the inductor can be
securely mounted.
www.aosmd.com
Page 12 of 17
AOZ5166QI-01
To minimize the effects of switching noise coupling to the
rest of the sensitive areas of the PCB, the area directly
underneath the designated VSWH copper plane on the
top layer is voided and the shape of this void is replicated
descending down through the rest of the layers.
Figure 11. Various Copper Pours and Bypass Capacitor Locations
Rev. 1.0 March 2016
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Page 13 of 17
AOZ5166QI-01
Package Dimensions, 6x6 QFN-40 EP3_S
D
A
D/2
30
B
21
20
31
E/2
2
INDEX AREA
(D/2xE/2)
E
2x
aaa C
e
40
11
1
2x 2x
aaa C
10
A3
TOP VIEW
A3
ccc C
C
A
SEATING
PLANE
4
3
40 x b
ddd C
A1
bbb M C A B
SIDE VIEW
D1
PIN#1 IDA
C0.30 x 45°
1
D1
e
e/2
L6
10
40
11
E1
E1
L2
L1
L1
L3
L5
E2
L
20
31
21
30
L
L4
L5
D2
BOTTOM VIEW
Notes:
1. All dimensions are in millimeters.
2. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002.
3. Dimension b applies to metallized terminal and is measured between 0.20mm and 0.35mm from the terminal tip. If the terminal
has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
4. Coplanarity applies to the terminals and all other bottom surface metalization.
Rev. 1.0 March 2016
www.aosmd.com
Page 14 of 17
AOZ5166QI-01
Package Dimensions, 6x6 QFN-40 EP3_S (Continued)
4.40
0.40
0.25
2.87
2.27
0.21
0.20
2.87
0.20
0.37
2.23
1.50
0.73
0.52
0.55
0.75
0.54
2.20
0.30X45°
0.25
2.00
2.87
0.50 REF
2.00
2.87
UNIT: mm
RECOMMENDED LAND PATTERN
Dimensions in millimeters
Symbols
Min.
Typ.
Max.
Symbols
Min.
Typ.
Max.
A
A1
A3
b
D
0.70
0.00
0.75
0.02
0.20 REF
0.25
6.00 BSC
0.80
0.05
A
A1
A3
b
D
0.028
0.000
0.030
0.001
0.008 REF
0.010
0.236 BSC
0.031
0.002
0.20
0.35
0.008
0.014
D1
1.90
2.00
2.10
D1
0.075
0.079
0.083
D2
4.30
4.40
4.50
D2
0.169
0.173
0.177
E
Rev. 1.0 March 2016
Dimensions in inches
E
6.00 BSC
0.236 BSC
E1
E2
1.40
2.17
1.50
2.27
1.60
2.37
E1
E2
0.055
0.085
0.059
0.089
0.063
0.093
e
L
L1
L2
L3
L4
L5
L6
aaa
0.30
0.15
0.15
0.63
0.44
0.30
0.27
0.50 BSC
0.40
0.20
0.21
0.73
0.54
0.40
0.37
0.15
0.50
0.25
0.26
0.83
0.64
0.50
0.47
e
L
L1
L2
L3
L4
L5
L6
aaa
0.012
0.006
0.006
0.024
0.017
0.012
0.011
0.020 BSC
0.016
0.008
0.008
0.028
0.021
0.016
0.015
0.006
0.020
0.010
0.010
0.032
0.025
0.020
0.019
bbb
ccc
0.10
0.10
bbb
ccc
0.004
0.004
ddd
0.08
ddd
0.003
www.aosmd.com
Page 15 of 17
AOZ5166QI-01
Tape and Reel Dimensions, 6x6 QFN
Carrier Tape
P1
D1
P2
E1
T
E2
E
C
L
B0
K0
D0
P0
A0
Feeding Direction
UNIT: MM
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
QFN6x6
(16mm)
6.30
±0.20
6.30
±0.20
1.10
±0.20
1.50
MIN.
1.50
+0.10
-0.00
16.00
±0.30
1.75
±0.10
7.50
±0.10
12.00
±0.20
4.00
±0.20
2.00
±0.10
0.30
±0.05
Reel
W1
S
G
N
M
K
V
R
H
W
UNIT: MM
Tape Size
Reel Size
M
N
W
W1
H
K
S
16mm
Ø330
Ø330
Max.
Ø100
Min.
16.40
+2.00
-0.00
22.40
Max.
Ø13.00
+0.50
-0.20
10.10
Min.
1.50
Min.
G
R
V
---
---
---
Leader/Trailer and Orientation
Trailer Tape
300mm min.
or 75 Empty Pockets
Rev. 1.0 March 2016
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min.
or 125 Empty Pockets
Page 16 of 17
AOZ5166QI-01
Part Marking
AOZ5166QI-01
(6.0 x 6.0 QFN)
Z5166QI1
Part Number Code
Assembly Lot Code
Fab Code & Assembly Location
Year Code & Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 March 2016
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 17 of 17