w WM5102 Audio Hub CODEC with Voice Processor DSP DESCRIPTION FEATURES The WM5102[1] is a highly-integrated low-power audio system for smartphones, tablets and other portable audio devices. It combines wideband telephony voice processing with a flexible, high-performance audio hub CODEC. Audio hub CODEC with integrated voice processor DSP Programmable DSP capability for audio processing Fixed function signal processing functions The WM5102 digital core provides a powerful combination of fixed-function signal processing blocks with a programmable DSP. These are supported by a fully-flexible, all-digital audio mixing and routing engine with sample rate converters, for wide use-case flexibility. The programmable DSP supports a range of audio processing software packages (supplied separately); user-programmed solutions can also be supported. Fixed-function signal processing blocks include filters, EQ, dynamics processors and sample rate converters. A SLIMbus interface supports multi-channel audio paths and host control register access. Multiple sample rates are supported concurrently via the SLIMbus interface. Three further digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial interface formats. Automatic sample rate detection enables seamless wideband/narrowband voice call handover. Two stereo headphone drivers each provide stereo groundreferenced or mono BTL outputs, with noise levels as low as 2.3μVRMS for hi-fi quality line or headphone output. The CODEC also features stereo 2W Class-D speaker outputs, a dedicated BTL earpiece output and PDM for external speaker amplifiers. A signal generator for controlling haptics devices is included; vibe actuators can connect directly to the Class-D speaker output, or via an external driver on the PDM output interface. All inputs, outputs and system interfaces can function concurrently. The WM5102 supports up to six microphone inputs, each either analogue or PDM digital. Microphone activity detection with interrupt is available. A smart accessory interface supports most standard 3.5mm accessories. Impedance sensing and measurement is provided for external accessory and push-button detection. The WM5102 power, clocking and output driver architectures are all designed to maximise battery life in voice, music and standby modes. Low-power ‘Sleep’ is supported, with configurable wake-up events. The WM5102 is powered from a 1.8V external supply. A separate supply is required for the Class D speaker drivers (typically direct connection to 4.2V battery). Two integrated FLLs provide support for a wide range of system clock frequencies. The WM5102 is configured using the I2C, SPI or SLIMbus interfaces. The fully-differential internal analogue architecture, minimal analogue signal paths and on-chip RF noise filters ensure a very high degree of noise immunity. Wind noise, sidetone and other programmable filters Dynamic Range Control, Fully parametric EQs - Tone, Noise, PWM, Haptic control signal generators Multi-channel asynchronous sample rate conversion Integrated 6/7 channel 24-bit hi-fi audio hub CODEC - 6 ADCs, 96dB SNR microphone input (48kHz) - 7 DACs, 113dB SNR headphone playback (48kHz) Audio inputs - Up to 6 analogue or digital microphone inputs - Single-ended or differential mic/line inputs Multi-purpose headphone / earpiece / line output drivers - 2 stereo output paths - 29mW into 32Ω load at 0.1% THD+N 100mW into 32Ω BTL load at 5% THD+N - 6.5mW typical headphone playback power consumption Pop suppression functions - 2.3µVRMS noise floor (A-weighted) Mono BTL earpiece output driver 2 x 2W stereo Class D speaker output drivers - Direct drive of external haptics vibe actuators Two-channel digital speaker (PDM) interface SLIMbus® audio and control interface 3 full digital audio interfaces - Standard sample rates from 4kHz up to 192kHz - Ultrasonic accessory function support TDM support on all AIFs - 8 channel input and output on AIF1 Flexible clocking, derived from MCLKn, BCLKn or SLIMbus 2 low-power FLLs support reference clocks down to 32kHz Advanced accessory detection functions - Low-power standby mode and configurable wake-up Configurable functions on 5 GPIO pins Integrated LDO regulators and charge pumps Support for single 1.8V supply operation Small W-CSP package, 0.4mm pitch APPLICATIONS Smartphones and Multimedia handsets Tablets and Mobile Internet Devices (MID) General-purpose low-power audio CODEC hub WOLFSON MICROELECTRONICS plc Product Brief, June 2014, Rev 4.2 [1] This product is protected by Patents US 7,622,984, US 7,626,445, US 7,765,019 and GB 2,432,765 Copyright 2014 Wolfson Microelectronics plc w CIF1ADDR CIF1SCLK CIF1SDA CIF2MOSI CIF2MISO CIF2SCLK CIF2SS GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 SLIMCLK SLIMDAT AIF3TXDAT AIF3RXDAT AIF3BCLK AIF3LRCLK AIF2TXDAT AIF2RXDAT AIF2BCLK AIF2LRCLK AIF1TXDAT AIF1RXDAT AIF1BCLK AIF1LRCLK IRQ RESET TRST TMS TDO TDI TCK LDOVOUT LDOENA LDOVDD DCVDD DBVDD3 DBVDD2 DBVDD1 DGND CPGND CPVDD CP1VOUTN CP1VOUTP CP1CB CP1CA CP2CB CP2CA CP2VOUT MICVDD WM5102 Production Data BLOCK DIAGRAM Product Brief, June 2014, Rev 4.2 2 WM5102 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 2 TABLE OF CONTENTS ......................................................................................... 3 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 8 RECOMMENDED OPERATING CONDITIONS ..................................................... 9 ELECTRICAL CHARACTERISTICS ................................................................... 10 TERMINOLOGY ............................................................................................................... 21 DEVICE DESCRIPTION ...................................................................................... 22 INTRODUCTION .............................................................................................................. 22 HI-FI AUDIO CODEC ....................................................................................................... 22 DIGITAL AUDIO CORE ................................................................................................... 23 DIGITAL INTERFACES ................................................................................................... 23 OTHER FEATURES......................................................................................................... 24 RECOMMENDED EXTERNAL COMPONENTS.................................................. 25 PACKAGE DIMENSIONS .................................................................................... 26 IMPORTANT NOTICE ......................................................................................... 27 ADDRESS: ....................................................................................................................... 27 REVISION HISTORY ........................................................................................... 28 w Product Brief, June 2014, Rev 4.2 3 WM5102 Production Data PIN CONFIGURATION A 1 2 IN3LN/ DMICCLK3 IN3LP B C IN2LN/ DMICCLK2 IN2LP D IN2RN/ DMICDAT2 IN2RP E F MICVDD AGND G SPKVDDL SPKVDDL H 4 5 6 7 8 9 10 11 12 13 EPOUTP EPOUTN HPOUT2L AVDD HPOUT1R CP1VOUTP CP1VOUTN CP2VOUT HPDETR HPOUT1FB1 /MICDET2 AGND AGND HPOUT2R HPOUT2FB AGND HPOUT1L CP1CA CP1CB CP2CB HPDETL MICDET1/ HPOUT1FB2 AGND AGND AGND AGND AGND AGND CPVDD CPGND CP2CA MICBIAS1 MICBIAS3 VREFC MICBIAS2 LDOVDD MICVDD LDOVOUT RESET LDOENA MCLK2 IRQ DCVDD DGND DBVDD1 SLIMDAT SLIMCLK MCLK1 AIF1RXDAT AIF1LRCLK AIF1BCLK 3 IN1LN/ DMICCLK1 DGND DGND DGND DGND DGND AGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND AGND J SPKGNDL SPKGNDL K SPKGNDR SPKGNDR L M SPKVDDR SPKVDDR JACKDET GPIO5 AIF1TXDAT AGND AIF3RXDAT AIF2BCLK TDO TMS SPKDAT CIF2MISO GPIO4 CIF1SDA CIF1SCLK GPIO1 AGND AIF3TXDAT AIF3BCLK AIF2TXDAT GPIO2 AIF2LRCLK TCK SPKCLK CIF2SS CIF2SCLK CIF1ADDR AVDD DBVDD3 AIF3LRCLK DBVDD2 DGND DCVDD AIF2RXDAT DBVDD1 TDI TRST CIF2MOSI ORDERING INFORMATION ORDER CODE WM5102ECS/R TEMPERATURE RANGE -40C to +85C PACKAGE W-CSP (Pb-free, Tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260C Note: Reel quantity = 5000 w Product Brief, June 2014, Rev 4.2 4 WM5102 Production Data PIN DESCRIPTION A description of each pin on the WM5102 is provided below. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated. PIN NO B3, B4, B7, C3, C4, C5, C6, C7, C8, F2, F3, G3, H3, J3, L3 NAME AGND TYPE Supply DESCRIPTION Analogue ground (Return path for AVDD) J13 AIF1BCLK Digital Input / Output Audio interface 1 bit clock J11 AIF1RXDAT Digital Input Audio interface 1 RX digital audio data J12 AIF1LRCLK Digital Input / Output Audio interface 1 left / right clock J8 AIF1TXDAT Digital Output Audio interface 1 TX digital audio data K5 AIF2BCLK Digital Input / Output Audio interface 2 bit clock M9 AIF2RXDAT Digital Input Audio interface 2 RX digital audio data L8 AIF2LRCLK Digital Input / Output Audio interface 2 left / right clock L6 AIF2TXDAT Digital Output Audio interface 2 TX digital audio data L5 AIF3BCLK K4 AIF3RXDAT Digital Input / Output Audio interface 3 bit clock Digital Input Audio interface 3 RX digital audio data M5 AIF3LRCLK Digital Input / Output Audio interface 3 left / right clock L4 AIF3TXDAT Digital Output Audio interface 3 TX digital audio data A3, A7, M3 AVDD Supply Analogue supply Control interface 2 Slave Select (SS) L11 CIF2SS ¯¯¯¯¯¯ Digital Input L12 CIF2SCLK Digital Input Control interface 2 clock input M13 CIF2MOSI Digital Input Control interface 2 Master Out / Slave In data Control interface 2 Master In / Slave Out data K9 CIF2MISO Digital Output L13 CIF1ADDR Digital Input Control interface 1 (I2C) address select K12 CIF1SCLK Digital Input Control interface 1 clock input K11 CIF1SDA Digital Input / Output Control interface 1 data input and output / acknowledge output. B9 CP1CA Analogue Output Charge pump 1 fly-back capacitor pin B10 CP1CB Analogue Output Charge pump 1 fly-back capacitor pin A10 CP1VOUTN Analogue Output Charge pump 1 negative output decoupling pin A9 CP1VOUTP Analogue Output Charge pump 1 positive output decoupling pin C11 CP2CA Analogue Output Charge pump 2 fly-back capacitor pin B11 CP2CB Analogue Output Charge pump 2 fly-back capacitor pin A11 CP2VOUT Analogue Output Charge pump 2 output decoupling pin / Supply for LDO2 C10 CPGND Supply Charge pump 1 & 2 ground (Return path for CPVDD) The output function is implemented as an Open Drain circuit. C9 CPVDD Supply Supply for Charge Pump 1 & 2 G13, M10 DBVDD1 Supply Digital buffer (I/O) supply (core functions and Audio Interface 1) M6 DBVDD2 Supply Digital buffer (I/O) supply (for Audio Interface 2) M4 DBVDD3 Supply Digital buffer (I/O) supply (for Audio Interface 3) G11, M8 DCVDD Supply Digital core supply E5, E6, E7, E8, E9, F5, F6, F7, F8, F9, G5, G6, G7, G8, G9, G12, H5, H6, H7, H8, H9, M7 DGND Supply Digital ground (Return path for DCVDD, DBVDD1, DBVDD2 and DBVDD3) A4 EPOUTP Analogue Output Earpiece positive output A5 EPOUTN Analogue Output Earpiece negative output w Product Brief, June 2014, Rev 4.2 5 WM5102 PIN NO Production Data NAME TYPE DESCRIPTION K13 GPIO1 Digital Input / Output General Purpose pin GPIO1. L7 GPIO2 Digital Input / Output General Purpose pin GPIO2. The output function is implemented as an Open Drain circuit. The output function is implemented as an Open Drain circuit. K3 GPIO3 Digital Input / Output General Purpose pin GPIO3. The output function is implemented as an Open Drain circuit. K10 GPIO4 Digital Input / Output General Purpose pin GPIO4. GPIO5 Digital Input / Output General Purpose pin GPIO5. Headphone left (HPOUT1L) sense input The output function is implemented as an Open Drain circuit. G10 The output function is implemented as an Open Drain circuit. B12 HPDETL Analogue Input A12 HPDETR Analogue Input Headphone right (HPOUT1R) sense input A13 HPOUT1FB1/ Analogue Input HPOUT1L and HPOUT1R ground feedback pin 1/ B8 HPOUT1L Analogue Output Left headphone 1 output A8 HPOUT1R Analogue Output Right headphone 1 output B6 HPOUT2FB Analogue Input HPOUT2L and HPOUT2R ground loop noise rejection feedback A6 HPOUT2L Analogue Output Left headphone 2 output B5 HPOUT2R Analogue Output Right headphone 2 output IN1LN/ Analogue Input / Digital Output Left channel negative differential MIC input / DMICCLK1 IN1LP Analogue Input Microphone & accessory sense input 2 MICDET2 E3 D3 Digital MIC clock output 1 Left channel single-ended MIC input / Left channel line input / Left channel positive differential MIC input E1 E2 DMICDAT1 Analogue input / Digital Input IN1RP Analogue Input IN1RN/ Right channel negative differential MIC input / Digital MIC data input 1 Right channel single-ended MIC input / Right channel line input / Right channel positive differential MIC input C1 C2 DMICCLK2 Analogue Input / Digital Output IN2LP Analogue Input IN2LN/ Left channel negative differential MIC input / Digital MIC clock output 2 Left channel single-ended MIC input / Left channel line input / Left channel positive differential MIC input D1 D2 DMICDAT2 Analogue input / Digital Input IN2RP Analogue Input IN2RN/ Right channel negative differential MIC input / Digital MIC data input 2 Right channel single-ended MIC input / Right channel line input / Right channel positive differential MIC input A1 A2 Left channel negative differential MIC input / DMICCLK3 Analogue Input / Digital Output IN3LP Analogue Input Left channel single-ended MIC input / IN3LN/ Digital MIC clock output 3 Left channel line input / Left channel positive differential MIC input B1 B2 DMICDAT3 Analogue input / Digital Input IN3RP Analogue Input IN3RN/ Right channel negative differential MIC input / Digital MIC data input 3 Right channel single-ended MIC input / Right channel line input / Right channel positive differential MIC input F13 IRQ ¯¯¯ Digital Output Interrupt Request (IRQ) output (default is active low). The pin configuration is selectable CMOS or Open Drain. E10 JACKDET Analogue Input Jack detect input F11 LDOENA Digital Input Enable pin for LDO1 D13 LDOVDD Supply Supply for LDO1 w Product Brief, June 2014, Rev 4.2 6 WM5102 Production Data PIN NO E12 NAME LDOVOUT TYPE Analogue Output DESCRIPTION LDO1 output H13 MCLK1 Digital Input Master clock 1 F12 MCLK2 Digital Input Master clock 2 C12 MICBIAS1 Analogue Output Microphone bias 1 D12 MICBIAS2 Analogue Output Microphone bias 2 C13 MICBIAS3 Analogue Output Microphone bias 3 B13 MICDET1/ Analogue Input E11, F1 MICVDD Microphone & accessory sense input 1/ HPOUT1L and HPOUT1R ground feedback pin 2 HPOUT1FB2 Analogue Output LDO2 output decoupling pin (generated internally by WM5102). (Can also be used as reference/supply for external microphones.) Digital Input Digital Reset input (active low) Digital Input / Output SLIM Bus Clock input / output SLIMDAT Digital Input / Output SLIM Bus Data input / output SPKCLK Digital Output Digital speaker (PDM) clock output SPKDAT Digital Output Digital speaker (PDM) data output E13 RESET ¯¯¯¯¯¯ H12 SLIMCLK H11 L10 K8 J1, J2 SPKGNDL Supply Left speaker driver ground (Return path for SPKVDDL) K1, K2 SPKGNDR Supply Right speaker driver ground (Return path for SPKVDDR) H2 SPKOUTLN Analogue Output Left speaker negative output H1 SPKOUTLP Analogue Output Left speaker positive output L2 SPKOUTRN Analogue Output Right speaker negative output L1 SPKOUTRP Analogue Output Right speaker positive output G1, G2 SPKVDDL Supply Left speaker driver supply M1, M2 SPKVDDR Supply Right speaker driver supply L9 TCK Digital Input JTAG clock input. Internal pull-down holds this pin at logic 0 for normal operation. M11 TDI Digital Input JTAG data input. K6 TDO Digital Output JTAG data output K7 TMS Digital Input Internal pull-down holds this pin at logic 0 for normal operation. JTAG mode select input. Internal pull-down holds this pin at logic 0 for normal operation. M12 TRST Digital Input JTAG Test Access Port reset (active low). Internal pull-down holds this pin at logic 0 for normal operation. D11 VREFC w Analogue Output Bandgap reference decoupling capacitor connection Product Brief, June 2014, Rev 4.2 7 WM5102 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX Supply voltages (DBVDD1, LDOVDD, AVDD, DCVDD, CPVDD) CONDITION -0.3V +2.0V Supply voltages (DBVDD2, DBVDD3, MICVDD) -0.3V +4.0V Supply voltages (SPKVDDL, SPKVDDR) -0.3V +6.0V Voltage range digital inputs (DBVDD1 domain) AGND - 0.3V DBVDD1 + 0.3V Voltage range digital inputs (DBVDD2 domain) AGND - 0.3V DBVDD2 + 0.3V Voltage range digital inputs (DBVDD3 domain) AGND - 0.3V DBVDD3 + 0.3V Voltage range digital inputs (DMICDATn) AGND - 3.3V MICVDD + 0.3V Voltage range analogue inputs (INnLN) AGND - 0.3V MICVDD + 0.3V Voltage range analogue inputs (INnLP, INnRN, INnRP) AGND - 3.3V MICVDD + 0.3V Ground (DGND, CPGND, SPKGNDL, SPKGNDR) AGND - 0.3V AGND + 0.3V Operating temperature range, TA -40ºC +85ºC Operating junction temperature, TJ -40ºC +125ºC Storage temperature after soldering -65ºC +150ºC w Product Brief, June 2014, Rev 4.2 8 WM5102 Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER TYP MAX DCVDD (≤24.576MHz clocking) 1.14 1.2 1.9 DCVDD (>24.576MHz clocking) 1.71 1.8 1.9 Digital supply range (I/O) DBVDD1 1.7 1.9 V Digital supply range (I/O) DBVDD2, DBVDD3 1.7 3.47 V Digital supply range (Core) See notes 3, 5, 6 LDO supply range SYMBOL MIN UNIT V LDOVDD 1.7 1.8 1.9 V CPVDD 1.7 1.8 1.9 V Speaker supply range SPKVDDL, SPKVDDR 2.4 Analogue supply range AVDD 1.7 Microphone Bias supply MICVDD 2.375 Charge Pump supply range 5.5 V 1.8 1.9 V 2.5 3.6 V See note 7 Ground Power supply rise time DGND, AGND, CPGND, SPKGNDL, SPKGNDR 0 All supplies 1 TA -40 V µs See notes 8, 9, 10 Operating temperature range 85 °C Notes: 1. The grounds must always be within 0.3V of AGND. 2. AVDD must be supplied before or simultaneously to DCVDD. DCVDD must not be powered if AVDD is not present. There are no other power sequencing requirements. 3. An internal LDO (powered by LDOVDD) can be used to provide the DCVDD supply. 4. The RESET ¯¯¯¯¯¯ input must be asserted (logic 0) during power-up, and held asserted until after the AVDD, DBVDD1 and DCVDD supplies are within the recommended operating limits. If DCVDD is powered from the internal LDO, then the RESET ¯¯¯¯¯¯ pin must be held asserted until at least 1.5ms after the LDO has been enabled. 5. ‘Sleep’ mode is supported when DCVDD is below the limits noted, provided AVDD and DBVDD1 are present. 6. Under default conditions, digital core clocking rates above 24.576MHz are inhibited. The register-controlled clocking limit should only be raised when the applicable DCVDD voltage is present. 7. An internal Charge Pump and LDO (powered by CPVDD) provide the Microphone Bias supply; the MICVDD pin should not be connected to an external supply. 8. DCVDD and MICVDD minimum rise times do not apply when these domains are powered using the internal LDOs. 9. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Wolfson strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. 10. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. w Product Brief, June 2014, Rev 4.2 9 WM5102 Production Data ELECTRICAL CHARACTERISTICS Test Conditions AVDD = 1.8V, With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Signal Level (IN1L, IN1R, IN2L, IN2R, IN3L, IN3R) Full-scale input signal level VINFS (0dBFS output) Single-ended PGA input, 6dB PGA gain 0.5 -6 VRMS dBV Differential PGA input, 0dB PGA gain 1 VRMS 0 dBV Notes: 1. The full-scale input signal level is also the maximum analogue input level, before clipping occurs. 2. The full-scale input signal level changes in proportion with AVDD. For differential input, it is calculated as AVDD / 1.8. 3. A 1.0VRMS differential signal equates to 0.5VRMS/-6dBV per input. 4. A sinusoidal input signal is assumed. Test Conditions TA = +25ºC With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Pin Characteristics (IN1L, IN1R, IN2L, IN2R, IN3L, IN3R) Input resistance Input capacitance RIN Differential input, All PGA gain settings 24 Single-ended input, 0dB PGA gain 16 k 5 CIN pF Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Input Programmable Gain Amplifiers (PGAs) Minimum programmable gain 0 dB Maximum programmable gain 31 dB 1 dB Programmable gain step size Guaranteed monotonic Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Microphone Input Signal Level (DMICDAT1, DMICDAT2, DMICDAT3) Full-scale input signal level 0dB gain -6 dBFS (0dBFS output) Notes: 5. The digital microphone input signal level is measured in dBFS, where 0dBFS is a signal level equal to the full-scale range (FSR) of the PDM input. The FSR is defined as the amplitude of a 1kHz sine wave whose positive and negative peaks are represented by the maximum and minimum digital codes respectively - this is the largest 1kHz sine wave that will fit in the digital output range without clipping. Note that, because the definition of FSR is based on a sine wave, the PDM data format can support signals larger than 0dBFS. w Product Brief, June 2014, Rev 4.2 10 WM5102 Production Data Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Line / Headphone / Earpiece Output Driver (HPOUTnL, HPOUTnR) Load resistance Load capacitance DC offset at Load Normal Mode 15 Mono Mode (BTL) 30 Device survival with load applied indefinitely 0.1 Ω Direct connection, Normal Mode 400 Direct connection, Mono Mode (BTL) 200 Connection via 16Ω series resistor 2 Single-ended mode 0.1 Differential (BTL) mode 0.2 pF nF mV Earpiece Output Driver (EPOUTP+EPOUTN) Load resistance Load capacitance Normal operation 15 Device survival with load applied indefinitely 0.1 Ω Direct connection (BTL) 200 pF Connection via 16Ω series resistor 2 nF DC offset at Load 0.2 mV Speaker Output Driver (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN) Load resistance 3 Ω Load capacitance 200 pF DC offset at Load 5 mV SPKVDD leakage current 1 µA w Product Brief, June 2014, Rev 4.2 11 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Paths (INnL, INnR) to ADC (Differential Input Mode, INn_MODE = 00) Signal to Noise Ratio SNR (A-weighted) High performance mode 85 95 dB (INn_OSR = 1) Normal mode 93 (INn_OSR = 0) Total Harmonic Distortion Total Harmonic Distortion Plus Noise THD -1dBV input -88 THD+N -1dBV input -86 Channel separation (Left/Right) Input noise floor dB -76 dB 100 dB 3.2 µVRMS PGA gain = +30dB 65 dB PGA gain = 0dB 70 100mV (peak-peak) 217Hz 70 100mV(peak-peak) 10kHz 65 A-weighted, PGA gain = +18dB Common mode rejection ratio PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) CMRR PSRR dB Analogue Input Paths (INnL, INnR) to ADC (Single-Ended Input Mode, INn_MODE = 01) PGA Gain = +6dB unless otherwise stated. Signal to Noise Ratio SNR (A-weighted) High performance mode 94 dB (INn_OSR = 1) Normal mode 90 (INn_OSR = 0) Total Harmonic Distortion Total Harmonic Distortion Plus Noise THD -7dBV input -81 dB THD+N -7dBV input -80 dB Channel separation (Left/Right) Input noise floor 100 dB 3.2 µVRMS 100mV (peak-peak) 217Hz 60 dB 100mV(peak-peak) 10kHz 55 A-weighted, PGA gain = +18dB PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR DAC to Headphone Output (HPOUT1L, HPOUT1R; RL = 32) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PO 0.1% THD+N 29 mW SNR A-weighted, Output signal = 1Vrms 112 dB THD PO = 20mW -86 dB THD+N PO = 20mW -84 dB THD PO = 5mW -89 dB THD+N PO = 5mW -85 dB Channel separation (Left/Right) PO = 20mW 75 dB Output noise floor A-weighted 2.5 µVRMS 100mV (peak-peak) 217Hz 57 dB 100mV (peak-peak) 10kHz 57 PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) w PSRR Product Brief, June 2014, Rev 4.2 12 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Headphone Output (HPOUT1L, HPOUT1R; RL = 16) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PO 0.1% THD+N SNR A-weighted, Output signal = 1Vrms 102 34 mW 112 dB THD PO = 20mW -78 dB THD+N PO = 20mW -76 dB THD PO = 5mW -78 THD+N PO = 5mW -77 Channel separation (Left/Right) PO = 20mW 75 Output noise floor A-weighted 2.5 PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 57 100mV (peak-peak) 10kHz 57 dB -67 dB 8 µVRMS dB dB DAC to Line Output (HPOUT1L, HPOUT1R; Load = 10k, 50pF) Full-scale output signal level VOUT 0dBFS input 1 Vrms 0 Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise A-weighted, Output signal = 1Vrms THD 0dBFS input -83 THD+N 0dBFS input -81 Channel separation (Left/Right) 110 dB dB -71 dB 8 µVRMS 100 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) 101 dBV SNR A-weighted PSRR 2.8 100mV (peak-peak) 217Hz 57 100mV (peak-peak) 10kHz 57 dB dB DAC to Earpiece Output (HPOUT1L, HPOUT1R, Mono Mode, RL = 32 BTL) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise 0.1% THD+N 89 5% THD+N 104 SNR A-weighted, Output signal = 2Vrms 113 dB PO THD PO = 50mW -92 dB THD+N PO = 50mW -90 dB THD PO = 5mW -86 dB THD+N PO = 5mW -88 dB A-weighted 2.5 µVRMS PSRR 100mV (peak-peak) 217Hz 57 dB 100mV (peak-peak) 10kHz 57 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) w mW Product Brief, June 2014, Rev 4.2 13 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Headphone Output (HPOUT2L, HPOUT2R; RL = 32) Maximum output power Signal to Noise Ratio Total Harmonic Distortion PO 0.1% THD+N 27 mW SNR A-weighted, Output signal = 1Vrms 109 dB THD PO = 20mW -90 dB THD+N PO = 20mW -88 dB THD PO = 5mW -90 dB THD+N PO = 5mW -88 dB Channel separation (Left/Right) PO = 20mW 75 dB Output noise floor A-weighted 3 µVRMS 100mV (peak-peak) 217Hz 57 dB 100mV (peak-peak) 10kHz 57 Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR DAC to Headphone Output (HPOUT2L, HPOUT2R; RL = 16) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PO 0.1% THD+N SNR A-weighted, Output signal = 1Vrms 101 32 mW 111 dB THD PO = 20mW -88 dB THD+N PO = 20mW -87 dB THD PO = 5mW -85 THD+N PO = 5mW -83 Channel separation (Left/Right) PO = 20mW 75 Output noise floor A-weighted 2.8 PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 57 100mV (peak-peak) 10kHz 57 dB -73 dB 10 µVRMS dB dB DAC to Line Output (HPOUT2L, HPOUT2R; Load = 10k, 50pF) Full-scale output signal level VOUT 0dBFS input 1 Vrms 0 Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise A-weighted, Output signal = 1Vrms THD 0dBFS input -87 THD+N 0dBFS input -85 Channel separation (Left/Right) w 110 dB dB -75 dB 10 µVRMS 105 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) 100 dBV SNR A-weighted PSRR 3.5 100mV (peak-peak) 217Hz 57 100mV (peak-peak) 10kHz 57 dB dB Product Brief, June 2014, Rev 4.2 14 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Earpiece Output (HPOUT2L, HPOUT2R, Mono Mode, RL = 32 BTL) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise 0.1% THD+N 85 5% THD+N 100 SNR A-weighted, Output signal = 2Vrms 112 dB PO THD PO = 50mW -90 dB THD+N PO = 50mW -88 dB THD PO = 5mW -90 dB THD+N PO = 5mW -88 dB A-weighted 6 µVRMS PSRR 100mV (peak-peak) 217Hz 57 dB 100mV (peak-peak) 10kHz 57 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) mW DAC to Earpiece Output (EPOUTP+EPOUTN, RL = 32 BTL) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PO 80 5% THD+N 100 SNR A-weighted, Output signal = 2Vrms 99 mW 109 dB THD PO = 50mW -86 dB THD+N PO = 50mW -84 dB THD PO = 5mW -85 THD+N PO = 5mW -83 -73 dB A-weighted 3.5 10.5 µVRMS PSRR 100mV (peak-peak) 217Hz 52 100mV (peak-peak) 10kHz 52 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) 0.1% THD+N dB dB DAC to Earpiece Output (EPOUTP+EPOUTN, RL = 16 BTL) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PO 0.1% THD+N 80 10% THD+N 105 SNR A-weighted, Output signal = 2Vrms 111 dB THD PO = 50mW -92 dB THD+N PO = 50mW -90 dB THD PO = 5mW -84 dB THD+N PO = 5mW -82 dB A-weighted 3 µVRMS PSRR 100mV (peak-peak) 217Hz 52 dB 100mV (peak-peak) 10kHz 52 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) w mW Product Brief, June 2014, Rev 4.2 15 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Speaker Output (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN, Load = 8, 22µH, BTL) High Performance mode (OUT4_OSR=1) Maximum output power Signal to Noise Ratio Total Harmonic Distortion PO SPKVDD = 5.0V, 1% THD+N 1.4 SPKVDD = 4.2V, 1% THD+N 1.0 SPKVDD = 3.6V, 1% THD+N 0.7 SNR A-weighted, Output signal = 3.3Vrms 82 W 97 dB THD PO = 0.9W -70 dB THD+N PO = 0.9W -68 dB THD PO = 0.5W -70 THD+N PO = 0.5W -68 Channel separation (Left/Right) PO = 0.5W 105 Output noise floor A-weighted 55 Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz 60 100mV (peak-peak) 10kHz 60 100mV (peak-peak) 217Hz 70 100mV (peak-peak) 10kHz 70 dB -57 dB 300 µVRMS dB dB dB DAC to Speaker Output (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN, Load = 4, 15µH, BTL) High Performance mode (OUT4_OSR=1) Maximum output power Signal to Noise Ratio Total Harmonic Distortion SPKVDD = 5.0V, 1% THD+N 2.5 SPKVDD = 4.2V, 1% THD+N 1.8 SPKVDD = 3.6V, 1% THD+N 1.3 SNR A-weighted, Output signal = 3.3Vrms 95 dB PO W THD PO = 1.0W -64 dB THD+N PO = 1.0W -62 dB THD PO = 0.5W -66 dB THD+N PO = 0.5W -64 dB Channel separation (Left/Right) PO = 0.5W 105 dB Output noise floor A-weighted 55 µVRMS 100mV (peak-peak) 217Hz 60 dB 100mV (peak-peak) 10kHz 60 Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR w 100mV (peak-peak) 217Hz 70 100mV (peak-peak) 10kHz 70 dB Product Brief, June 2014, Rev 4.2 16 WM5102 Production Data Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Input / Output (except DMICDATn and DMICCLKn) Digital I/O is referenced to DBVDD1, DBVDD2 or DBVDD3. See “Recommended Operating Conditions” for the valid operating voltage range of each DBVDDn domain. Input HIGH Level Input LOW Level VIH VIL VDBVDDn =1.8V ±10% 0.65 VDBVDDn VDBVDDn =3.3V ±10% 0.7 VDBVDDn V VDBVDDn =1.8V ±10% 0.35 VDBVDDn VDBVDDn =3.3V ±10% 0.3 VDBVDDn V Note that digital input pins should not be left unconnected or floating. Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA 0.9 VDBVDDn Input capacitance V 0.1 VDBVDDn V 1 µA 10 pF Input leakage -1 Pull-up resistance 42 49 56 kΩ 80 105 130 kΩ (where applicable) Pull-down resistance (where applicable) Digital Microphone Input / Output (DMICDATn and DMICCLKn) DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP, according to the INn_DMIC_SUP registers 0.65 VSUP DMICDATn input HIGH Level VIH DMICDATn input LOW Level VIL DMICCLKn output HIGH Level VOH IOH = 1mA DMICCLKn output LOW Level VOL IOL = -1mA V 0.35 VSUP V 0.2 VSUP V 1 µA 0.8 VSUP Input capacitance V 10 Input leakage -1 pF SLIMbus Digital Input / Output (SLIMCLK and SLIMDAT) 1.8V I/O Signalling (ie. 1.65V ≤ DBVDD1 ≤1.95V) 0.65 VDBVDD1 Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA V 0.35 VDBVDD1 Pin capacitance 0.9 VDBVDD1 V V 0.1 VDBVDD1 V 5 pF 26.5 MHz General Purpose Input / Output (GPIOn) Clock output frequency w GPIO pin configured as OPCLK or FLL output Product Brief, June 2014, Rev 4.2 17 WM5102 Production Data Test Conditions fs ≤ 48kHz With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ADC Decimation Filters Passband +/- 0.05dB 0 -6dB 0.454 fs 0.5 fs Passband ripple Stopband Stopband attenuation Signal path delay +/- 0.05 dB 2 ms 0.546 fs f > 0.546 fs 85 dB Analogue input to Digital AIF output DAC Interpolation Filters Passband +/- 0.05dB 0 -6dB Passband ripple Stopband Stopband attenuation Signal path delay w 0.454 fs 0.5 fs +/- 0.05 dB 1.5 ms 0.546 fs f > 0.546 fs Digital AIF input to Analogue output 85 dB Product Brief, June 2014, Rev 4.2 18 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Bias (MICBIAS1, MICBIAS2, MICBIAS3) Note - No capacitor on MICBIASn Note - In regulator mode, it is required that VMICVDD - VMICBIASn > 200mV Minimum Bias Voltage Maximum Bias Voltage Regulator mode (MICBn_BYPASS=0) Bias Voltage output step size Load current ≤ 1.0mA VMICBIAS Bias Voltage accuracy 1.5 V 2.8 V 0.1 -5% Bias Current Regulator mode (MICBn_BYPASS=0), V +5% V 2.4 mA VMICVDD - VMICBIAS >200mV Bypass mode (MICBn_BYPASS=1) Output Noise Density Integrated noise voltage Power Supply Rejection Ratio (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR Load capacitance 5.0 Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, Measured at 1kHz 50 nV/Hz Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, 100Hz to 7kHz, A-weighted 4 µVrms 100mV (peak-peak) 217Hz 95 dB 100mV (peak-peak) 10kHz 65 50 Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=0 Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=1 Output discharge resistance 1.8 MICBn_ENA=0, pF 4.7 µF 5 kΩ MICBn_DISCH=1 External Accessory Detect Load impedance detection range (HPDETL or HPDETR) HP_IMPEDANCE_ RANGE=00 4 80 HP_IMPEDANCE_ RANGE=01 70 1000 HP_IMPEDANCE_ RANGE=10 1000 10000 -30 +30 % Ω Load impedance detection accuracy (HPDETL or HPDETR) Load impedance detection range for MICD_LVL[0] = 1 0 3 (MICDET1 or MICDET2) for MICD_LVL[1] = 1 17 21 2.2kΩ (2%) MICBIAS resistor. for MICD_LVL[2] = 1 36 44 Note these characteristics assume no other component is connected to MICDETn. for MICD_LVL[3] = 1 62 88 for MICD_LVL[4] = 1 115 160 for MICD_LVL[5] = 1 207 381 for MICD_LVL[8] = 1 475 30000 Jack Detection input threshold voltage (JACKDET) w VJACKDET Jack insertion 0.5 x AVDD Jack removal 0.85 x AVDD Ω V Product Brief, June 2014, Rev 4.2 19 WM5102 Production Data Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX 1.7 2.7 3.3 UNIT MICVDD Charge Pump and Regulator (CP2 and LDO2) Output voltage VMICVDD Programmable output voltage step size Maximum output current Start-up time 4.7µF on MICVDD, IMICBIASn = 1mA V 50 mV 8 mA 4.5 ms Frequency Locked Loop (FLL1, FLL2) Output frequency Normal operation, input reference supplied Lock Time 13 52 Free-running mode, no reference supplied 30 FREF = 32kHz, FOUT = 24.576MHz 10 FREF = 12MHz, FOUT = 24.576MHz 1 MHz ms RESET pin Input RESET input pulse width 1 µs (To trigger a Hardware Reset, the RESET input must be asserted for longer than this duration) Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. Device Reset Thresholds AVDD Reset Threshold VAVDD 0.54 0.96 V DCVDD Reset Threshold VDCVDD 0.59 0.81 V DBVDD1 Reset Threshold VDBVDD1 0.54 0.96 V Note that the reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to this section for the WM5102 power-up sequencing requirements. w Product Brief, June 2014, Rev 4.2 20 Production Data WM5102 TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal and the output with no input signal applied. (Note that this is measured without any mute function enabled.) 2. Total Harmonic Distortion (dB) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. Total Harmonic Distortion plus Noise (dB) – THD+N is the ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. 3. 4. Power Supply Rejection Ratio (dB) - PSRR is the ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions. 5. Common Mode Rejection Ratio (dB) – CMRR is the ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it. 6. Channel Separation (L/R) (dB) – left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. 7. Multi-Path Crosstalk (dB) – is the difference in level between the output of the active path and the measured signal level in the idle path at the test signal frequency. The active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. 8. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. 9. All performance measurements are specified with a 20kHz low pass ‘brick-wall’ filter and, where noted, an A-weighted filter. Failure to use these filters will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise. w Product Brief, June 2014, Rev 4.2 21 WM5102 Production Data DEVICE DESCRIPTION INTRODUCTION The WM5102 is a highly integrated low-power audio hub CODEC for mobile telephony and portable devices. It provides flexible, high-performance audio interfacing for handheld devices in a small and cost-effective package. It supports programmable DSP for wideband voice processing, ideally suited for multimedia phones and smartphones. The WM5102 digital core provides an extensive capability for signal processing algorithms, including echo cancellation, wind noise, side-tone and other programmable filters. Parametric equalisation (EQ) and dynamic range control (DRC) are also supported. Highly flexible digital mixing, including stereo full-duplex asynchronous sample rate conversion, provides use-case flexibility across a broad range of system architectures. A signal generator for controlling haptics vibe actuators is included. The WM5102 provides multiple digital audio interfaces, including SLIMbus, in order to provide independent and fully asynchronous connections to different processors (eg. application processor, baseband processor and wireless transceiver). A flexible clocking arrangement supports a wide variety of external clock references, including clocking derived from the digital audio interface. Two integrated Frequency Locked Loop (FLL) circuits provide additional flexibility. Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. Configurable ‘Wake-Up’ actions can be associated with the low-power standby (Sleep) mode. Versatile GPIO functionality is provided, and support for external accessory / push-button detection inputs. Comprehensive Interrupt (IRQ) logic and status readback are also provided. HI-FI AUDIO CODEC The WM5102 is a high-performance low-power audio CODEC which uses a simple analogue architecture. 6 ADCs and 7 DACs are incorporated, providing a dedicated ADC for each input and a dedicated DAC for each output channel. The analogue outputs comprise two 29mW (113dB SNR) stereo headphone amplifiers with groundreferenced output, a 100mW differential (BTL) earpiece driver, and a Class D stereo speaker driver capable of delivering 2W per channel into a 4Ω load. Six analogue inputs are provided, each supporting single-ended or differential input modes. In differential mode, the input path SNR is 96dB. The ADC input paths can be bypassed, supporting up to 6 channels of digital microphone input. The audio CODEC is controlled directly via register access. The simple analogue architecture, combined with the integrated tone generator, enables simple device configuration and testing, minimising debug time and reducing software effort. The WM5102 output drivers are designed to support as many different system architectures as possible. Each output has a dedicated DAC which allows mixing, equalisation, filtering, gain and other audio processing to be configured independently for each channel. This allows each signal path to be individually tailored for the load characteristics. All outputs have integrated pop and click suppression features. The headphone output drivers are ground-referenced, powered from an integrated charge pump, enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. Ground loop feedback is incorporated, providing rejection of noise on the ground connections. A mono mode is available on the headphone outputs; this configures the drivers as differential (BTL) outputs, suitable for an earpiece or hearing aid coil. The Class D speaker drivers deliver excellent power efficiency. High PSRR, low leakage and optimised supply voltage ranges enable powering from switching regulators or directly from the battery. Battery current consumption is minimised across a wide variety of voice communication and multimedia playback use cases. w Product Brief, June 2014, Rev 4.2 22 WM5102 Production Data The WM5102 is cost-optimised for a wide range of mobile phone applications, and features two channels of Class D power amplification. For applications requiring more than two channels of power amplification (or when using the integrated Class D path to drive a haptics actuator), the PDM output channels can be used to drive two external PDM-input speaker drivers. In applications where stereo loudspeakers are physically widely separated, the PDM outputs can ease layout and EMC by avoiding the need to run the Class-D speaker outputs over long distances and interconnects. DIGITAL AUDIO CORE The WM5102 uses a core architecture based on all-digital signal routing, making digital audio effects available on all signal paths, regardless of whether the source data input is analogue or digital. The digital mixing desk allows different audio effects to be applied simultaneously on many independent paths, whilst also supporting a variety of sample rates concurrently. This helps support many new audio use-cases. Soft mute and un-mute control allows smooth transitions between use-cases without interrupting existing audio streams elsewhere. The WM5102 digital core provides an extensive capability for programmable signal processing algorithms. The DSP can support functions such as echo cancellation, wind noise, side-tone and other programmable filters. The DSP is optimised for advanced voice processing, but a wide range of application-specific filters and audio enhancements can also be implemented. Highly flexible digital mixing, including mixing between audio interfaces, is possible. The WM5102 performs stereo full-duplex asynchronous sample rate conversion, providing use-case flexibility across a broad range of system architectures. Automatic sample rate detection is provided, enabling seamless wideband/narrowband voice call handover. Dynamic Range Controller (DRC) functions are available for optimising audio signal levels. In playback modes, the DRC can be used to maximise loudness, while limiting the signal level to avoid distortion, clipping or battery droop, in particular for high-power output drivers such as speaker amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable. The 5-band parametric equaliser (EQ) functions can be used to compensate for the frequency characteristics of the output transducers. EQ functions can be cascaded to provide additional frequency control. Programmable high-pass and low-pass filters are also available for general filtering applications such as removal of wind and other low-frequency noise. DIGITAL INTERFACES Three serial digital audio interfaces (AIFs) each support PCM, TDM and I2S data formats for compatibility with most industry-standard chipsets. AIF1 supports eight input/output channels; AIF2 and AIF3 each support two input/output channels. Bidirectional operation at sample rates up to 192kHz is supported. Six digital PDM input channels are available (three stereo interfaces); these are typically used for digital microphones, powered from the integrated MICBIAS power supply regulators. Two PDM output channels are also available (one stereo interface); these are typically used for external power amplifiers. Embedded mute codes provide a control mechanism for external PDM-input devices. The WM5102 features a MIPI-compliant SLIMbus interface, providing eight channels of audio input/output. Mixed audio sample rates are supported on the SLIMbus interface. The SLIMbus interface also supports read/write access to the WM5102 control registers. The WM5102 is equipped with an I2C slave port (at up to 1MHz), and an SPI port (at up to 26MHz). Full access to the register map is also provided via the SLIMbus port. w Product Brief, June 2014, Rev 4.2 23 WM5102 Production Data OTHER FEATURES The WM5102 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. The phase relationship between the two generators is configurable, providing flexibility in creating differential signals, or for test scenarios. A white noise generator is provided, which can be routed within the digital core. The noise generator can provide ‘comfort noise’ in cases where silence (digital mute) is not desirable. Two Pulse Width Modulation (PWM) signal generators are incorporated. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. The PWM signal generators can be output directly on a GPIO pin. The WM5102 provides 5 GPIO pins, supporting selectable input/output functions for interfacing, detection of external hardware, and to provide logic outputs to other devices. Comprehensive Interrupt (IRQ) functionality is also provided for monitoring internal and external event conditions. A signal generator for controlling haptics devices is included, compatible with both Eccentric Rotating Motor (ERM) and Linear Resonant Actuator (LRA) haptic devices. The haptics signal generator is highly configurable, and can execute programmable drive event profiles, including reverse drive control. An external vibe actuator can be driven directly by the Class D speaker output. The WM5102 can be powered from a 1.8V external supply. A separate supply (4.2V) is typically required for the Class D speaker driver. Integrated Charge Pump and LDO Regulators circuits are used to generate supply rails for internal functions and to support powering or biasing of external microphones. A smart accessory interface is included, supporting most standard 3.5mm accessories. Jack detection, accessory sensing and impedance measurement is provided, for external accessory and push-button detection. Accessory detection can be used as a ‘Wake-Up’ trigger from low-power standby. Microphone activity detection with interrupt is also available. System clocking can be derived from the MCLK1 or MCLK2 input pins. Alternatively, the SLIMbus interface, or the audio interfaces (configured in Slave mode), can be used to provide a clock reference. Two integrated Frequency Locked Loop (FLL) circuits provide support for a wide range of clocking configurations, including the use of a 32kHz input clock reference. w Product Brief, June 2014, Rev 4.2 24 Production Data WM5102 RECOMMENDED EXTERNAL COMPONENTS w Product Brief, June 2014, Rev 4.2 25 WM5102 Production Data PACKAGE DIMENSIONS w Product Brief, June 2014, Rev 4.2 26 Production Data WM5102 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. 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Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w Product Brief, June 2014, Rev 4.2 27 WM5102 Production Data REVISION HISTORY DATE REV DESCRIPTION OF CHANGES PAGE CHANGED BY 15/09/11 1.0 Customer preview under NDA MP 24/10/11 1.1 Updates to Control Interface, Haptics description and Pin names MP 11/11/11 1.2 Removed DACVDD MP 7/12/11 1.3 Updated power pins to reflect implementation, and block diagram to match. MP 17/02/12 1.4 Updates to all sections, and alignment with datasheet standards. 7/03/12 1.4 Pin Configuration / Ballout details added 4-7 PH 22/03/12 1.4 Package Drawing added 27 PH 13/04/12 1.4 Reel quantity added 4 PH 19/04/12 1.5 Updates to Electrical Characteristics KOL 01/05/12 1.6 Signal Timing Requirements deleted PH 08/06/12 1.6 Sample rates greater than 192kHz deleted. PH Updated filter spec delay wording PH DCVDD requirements for 50MHz clocking added. Analogue connections updated on External Components figure. Maximum LDO2 output voltage amended to 3.25V. 08/08/12 1.6 Pin Descriptions updated to show single-ended analogue input is on the INxP pins (not INxN). PH 23/10/12 2.0 PH 13/11/12 2.0 Electrical Characteristics updated Package Drawing updated Electrical Characteristics updated. PH Correction to Pin Numbering (SPKOUTLP, SPKOUTLN, SPKOUTRP, SPKOUTRN) 14/12/12 3.0 Block diagram update, showing gain in AEC Loopback path PH Package drawing updated 19/02/13 3.0 Electrical Characteristics updated 22/02/13 3.0 Pin Description updated. JMacD 04/06/13 4.0 Electrical Characteristics updated JMacD 26/02/14 4.1 Power-up timing and Reset requirements updated. JMacD PH SNR test conditions clarified. Headphone impedance measurement control updated. Clarification to maximum input signal levels (analogue & digital). 27/06/14 4.2 JTAG Interface input pins all have internal pull-down resistors. 7 Updated Pull-up/Pull-down resistances, and Reset thresholds. 17, 20 w PH Product Brief, June 2014, Rev 4.2 28