WM8816 Stereo Digital Volume Control Advanced Information, September 2000, Rev 1.1 DESCRIPTION FEATURES • • • • • • • • The WM8816 is a highly linear stereo volume control for audio systems. The design is based on resistor chains with external op-amps, which provides flexibility for the supply voltage, signal swing, noise floor and cost optimisation. The gain of each channel can be independently programmed from -111.5dB to +15.5dB through a digital serial control interface. Audible clicks on gain changes are eliminated by changing gains only when a zero crossing has been detected in the signal. The device also features peak level detection, which can be used for Automatic Gain Control. The WM8816 operates from a single +5V supply and accepts signal input levels up to ±18V. Gain range from -111.5dB to +15.5dB 0.5dB Gain step size Total Harmonic Distortion 0.001% (100dB) typical Crosstalk -110dB typical Input signals up to ±18V Zero Detection for Gain Changes Hardware and Software Mute Power On/Off Transient Suppression APPLICATIONS • • • • The WM8816 is available in a 16-pin SOIC package. It is guaranteed over a temperature range of -40° to 85°C. Audio Amplifiers Consumer Audio / Entertainment Systems Mixing Desks Audio Recording Equipment BLOCK DIAGRAM (3) LFO LIN (4) (2) LMO LGND (5) LEFT OUT Zero Crossing Detector + Peak Level Detector CSB (6) External Opamps MUTEB (8) Control DATA (9) CCLK (10) DAC WM8816 Zero Crossing Detector Peak Level Detector + RIGHT OUT (15) RMO RGND (12) - (14) RFO RIN (13) (1) AVDD (16) AGND (7) DVDD WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk (11) DGND Advanced information data sheets contain preliminary data on new products in the pre-production phase of development. Supplementary data will be published at a later date. 2000 Wolfson Microelectronics Ltd. WM8816 Advanced Information PIN CONFIGURATION ORDERING INFORMATION AVDD 1 16 AGND LMO 2 15 RMO LFO 3 14 RFO LIN 4 13 RIN LGND 5 12 RGND CSB 6 11 DGND DVDD 7 10 CCLK MUTEB 8 9 DATA DEVICE TEMP. RANGE PACKAGE XWM8816EDW -40 to +85oC 16-pin SOIC (plastic) PIN DESCRIPTION PIN NAME TYPE DESCRIPTION 1 AVDD Supply Supply Voltage for Analogue Circuitry 2 LMO Analogue Output 3 LFO Analogue Input 4 LIN Analogue Input Input Signal (Left Channel) 5 LGND Analogue Input Input Signal Ground (Left Channel) 6 CSB Digital Input 7 DVDD Supply 8 MUTEB Digital Input 9 DATA Digital In / Out 10 CCLK Digital Input 11 DGND Supply 12 RGND Analogue Input Input Signal Ground (Right Channel) 13 RIN Analogue Input Input Signal (Right Channel) 14 RFO Analogue Input 15 RMO Analogue Output 16 AGND Supply WOLFSON MICROELECTRONICS LTD External Op-amp Inverting Input (Left Channel) External Op-amp Feedback Signal (Left Channel) Chip Select (active low) Supply Voltage for Digital Circuitry Mute (active low) Serial Interface Data Input / Output (tri-state) Serial Interface Clock Digital Ground External Op-amp Feedback Signal (Right Channel) External Op-amp Inverting Input (Right Channel) Analogue Ground AI Rev 1.1 September 2000 2 WM8816 Advanced Information ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore susceptible to damage from excessive static voltages. To optimise the distortion and noise performance of pins 3, 4, 13 and 14, the on-chip ESD protection circuitry has been restricted, and consequently only achieves 300V when characterised to the Human Body Model. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specification JESD22-A112-A, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 3 and is therefore supplied in vacuum-sealed moisture barrier bags. CONDITION MIN MAX Input signal voltage -20V +20V Positive supply voltage (AVDD to AGND, DVDD to DGND) -0.5V 6V Input voltage (all other pins) -0.5V AVDD + 0.5V Operating temperature -40°C 85°C Storage temperature -55°C 125°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN Input signal voltage TYP -18 Positive supply voltage AVDD, DVDD Negative supply voltage AGND, DGND Input signal grounds LGND, RGND 4.5 MAX UNIT +18 V 5 5.5 0 0 Operating temperature -20 V V V 60 60 °C ELECTRICAL CHARACTERISTICS TEST CONDITIONS AVDD = 5.0V, AGND = 0V, TA = 25°C, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP Input resistance RIN For any gain 7 10 Input capacitance CIN For any gain Voffset External OP275 opamp, gain = 1 IDD From AVDD / AGND 2.5 PSRR From AVDD 80 MAX UNIT Analogue Inputs / Outputs Input offset voltage Supply current Power supply rejection ratio (Note 1) kΩ 2 pF 1 mV 5 mA dB Gain Control Gain range G Gain step size D Gain error (Note 1) Gain match error (Note 1) Mute attenuation WOLFSON MICROELECTRONICS LTD -111.5 DE Lowest gains guaranteed by design, not tested in production. ME Between channels MATT +15.5 0.5 113 dB dB 0.5 dB 0.2 dB dB AI Rev 1.1 September 2000 3 WM8816 Advanced Information TEST CONDITIONS AVDD = 5.0V, AGND = 0V, TA = 25°C, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT N Gain = -60dB 4 Gain = mute 2.5 VIN= 1Vrms, gain=0dB, VOUT with OP275, DC to 20 kHz 0.001 (100) % (dB) 120 130 dB -100 -110 dB Audio Performance Noise (Note 1) VIN = 0V, VOUT with OP275, A-weighed Total Harmonic Distortion plus Noise Gain = 0dB THD+N 13 Dynamic Range (Note 1) DR Crosstalk (Note 1) CR Between channels, gain=0dB, fIN=1kHz Input low voltage VIL All digital inputs Input high voltage VIH All digital inputs Output low voltage VOL ILoad = 2mA Output high voltage VOH ILoad = 2mA DVDD -0.4 µV rms Digital Inputs / Outputs 0.3 DVDD 0.7 DVDD V V 0.4 V V Control Interface Timing Clock Frequency fCCLK Period of CCLK high tWHC VIH to VIH 500 Period of CCLK low tWLC VIL to VIL 500 Rise time of CCLK tRC VIL to VIH 100 ns Fall time of CCLK tFC VIH to VIL 100 ns 1 MHz ns ns Hold time, CCLK high to CSB low tHCHS 20 ns Setup time, CSB low to CCLK high tSSLCH 100 ns Setup time, valid DATA to CCLK high tSDCH 100 ns Hold time, CCLK high to invalid DATA tHCHD 100 ns Setup time, CCLK low to valid DATA tDCLD Load = 100pF Hold time, CSB high or 16th CCLK low to invalid DATA tDSZ Load = 3.3kΩ Hold time, 16th CCLK high to CSB high tHLCHS 200 ns Setup time, CSB high to CCLK high tSSHCH 200 ns 20 200 ns 200 ns Note: 1. Guaranteed by design. WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 4 WM8816 Advanced Information CONTROL INTERFACE TIMING DIAGRAM tWLC tWHC tRC tFC CCLK tHCSH tHLCHS tSSLCH tDSSHCH CSB tSDCH tHCHD DATA (IN) A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tDSZ tDCLD DATA (OUT) D7 ADDRESS BYTE D6 D5 D4 D3 D2 D1 D0 DATA BYTE Figure 1 Control Interface Timing Diagram WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 5 WM8816 Advanced Information DEVICE DESCRIPTION The WM8816 is a stereo digital volume control designed for audio systems. The levels of the left and right analogue channels can be programmed independently through the serial interface. The resistor values in the internal resistor chains are decoded to 0.5 dB resolution with multiplexers, giving a gain range of -111.5 to +15.5 dB. The code for -112 dB activates mute for maximum attenuation. The WM8816 has two constant impedance signal inputs. The left channel input is between LIN and LGND, and the right channel between RIN and RGND. The output pins LFO, LMO (left) and RFO, RMO (right) are designed to interface directly to two external op-amps, which produce the volume controlled output signals. This provides flexibility for the supply voltage and signal swing; while the WM8816 runs at 5V, the output signal swing depends solely on the op-amp supply. INTERFACES Control information is written into or read back from the internal register via the serial control port. This port consists of a bi-directional data pin (DATA), an active low chip select pin (CSB) and the control clock (CCLK). Control data is shifted into the serial input register on the rising edges of CCLK pulses, while CSB is low. All control instructions require two bytes of data. The first byte contains a 4bit register address and a read/write bit, and the second byte is the control word. CSB must return to high at the end of each word. When reading from the control registers, data is shifted out on the falling edges of CCLK. When CSB is high, the DATA pin is in a high impedance state. In a multi-channel system, the same DATA and CCLK lines can thus be connected to several WM8816 volume controllers, and each device can be independently addressed by pulling its CSB pin low. OPERATING MODES When power is first applied, a power-on reset initialises the control registers mutes the WM8816. To activate the device, the MUTEB pin must be high and a non-zero value must be written to the gain register. After that the device can be muted again either by pulling the MUTEB pin low or by writing zero (00hex) to the gain register. For device testing, the MUTEB pin becomes an output when Bit 1 of the test register is high. Internal signals can then be directed to MUTEB and monitored. CHANGING THE GAIN OF THE CHANNEL The WM8816 has two gain registers for the left and right channels respectively. There is also an alias register address to update both gain registers simultaneously. When a new gain value is written into a gain register the WM8816 will wait until the next falling edge zero crossing in the input signal before changing the gain. This ensures that no audible click is produced at the output. If there are no zero crossings in the signal after 18ms, the gain is changed regardless. If both gain registers are changed simultaneously, the gain is changed first on the right and then the left channel. PEAK LEVEL DETECTION The WM8816 has an on-chip 8-bit digital-to-analogue converter (DAC) used for monitoring the peak level of the output signal. The DAC input value is programmed via the serial interface. The reference value VREF is calculated from VREF = k/256 × 18V, where k is the DAC input code. When a positive peak signal level exceeds this value, the peak detector sets Bit 1 (for the left channel) or Bit 0 (right channel) of the status register. These bits remain set until the status register is read. WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 6 WM8816 Advanced Information REGISTER MAP REGISTER ADDRESS BYTE BITS DATA BYTE 7 6 5 4 3 2 1 0 MSB…LSB Function Peak Detector Status CR4 X 1 0 1 1 R/W X X Output code 00000000 00000001 00000010 00000011 No overload Right overload Left overload Both overload Peak Detector Reference CR3 X 1 1 0 0 R/W X X Input code 11111111 11111110 11111101 : 00000010 00000001 00000000 DAC output 255/256 × 18V 254/256 × 18V 253/256 × 18V : 2/256 × 18V 1/256 × 18V AGND Left Channel Gain CR2 X 1 1 0 1 R/W X X Input code 11111111 11111110 11111101 : 11100000 00000010 00000001 00000000 Gain dB +15.5 +15.0 +14.5 : 0.0 -111.0 -111.5 mute Right Channel Gain CR1 X 1 1 1 0 R/W X X Input code 11111111 11111110 11111101 : 11100000 00000010 00000001 00000000 Gain dB +15.5 +15.0 +14.5 : 0.0 -111.0 -111.5 mute Test, CR5 X 1 1 1 1 R/W X X Reserved Both Channel Gains X 1 0 0 1 W X X Write to both gain registers Table 1 Register Map Description Notes: 1. Address bit 2 is the read / write bit (1 for read, 0 for write). 2. X are don’t cares, set to 1 for minimum power consumption. 3. All registers are set to their default value (all zeros) during power-on reset, except CR3 which is set to 255. WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 7 WM8816 Advanced Information TEST REGISTER When bit 1 in register CR5 is set, MUTEB becomes an output pin. Bits 2, 3 and 4 select different internal signals which can then be seen via the MUTEB pin. CONDITION FUNCTION DATA BYTE BITS Normal (MUTEB configured as input) Test Mode (MUTEB configured as output) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 Latch the new gain value to resistor network 0 0 0 0 0 0 1 0 Left delay generator 0 0 0 0 0 1 1 0 Left peak detector 0 0 0 0 1 0 1 0 Left zero crossing 0 0 0 0 1 1 1 0 Left enable for zero crossing and delay generator 0 0 0 1 0 0 1 0 Right delay generator 0 0 0 1 0 1 1 0 Right peak detector 0 0 0 1 1 0 1 0 Right zero crossing 0 0 0 1 1 1 1 0 Right enable for zero crossing and delay generator Table 2 Test Register Description PERFORMANCE GRAPHS -70 -80 -90 THD+N (dB) -100 -110 -120 -60 -50 -40 -30 -20 -10 +0 +10 Input Signal Level (dBV) Figure 2 THD + Noise versus input level at gains of +6dB, 0dB, -6dB, -12dB and mute +0 -20 -40 d B V -60 -80 -100 -120 -140 5k 10k 15k 20k 25k 30k Frequency (Hz) Figure 3 FFT of output signal with 1kHz, 1V rms sine wave input WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 8 WM8816 Advanced Information +0 -20 -40 d B V -60 -80 -100 -120 -140 5k 10k 15k 20k 25k 30k Frequency (Hz) Figure 4 FFT of output signal with 10kHz, 1V rms sine wave input POWER SUPPLY DECOUPLING For best audio performance, all digital activities should be avoided during analogue signal processing. Special attention should be paid to power and ground decoupling. If possible separate analogue and digital power supplies should be used. A clean analogue power supply should be used for AVDD. DVDD should be the same as AVDD to avoid latch-up phenomena. Decoupling capacitors should be located as close to the WM8816 as possible. WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 9 WM8816 Advanced Information RECOMMENDED EXTERNAL COMPONENTS LFO 3 4 +18V LIN - LMO 2 LEFT CHANNEL INPUT 5 + LGND -18V RFO 14 13 RIGHT CHANNEL INPUT +18V RIN - RMO 15 12 + RGND -18V +5V DC WM8816 6 Micro Controller 9 10 8 CSB AVDD DATA AGND CCLK DVDD MUTEB DGND 1 16 C1 7 11 + C2 C3 Note: Connect signal ground and non-inverting opamp input together on the PCB Figure 5 Typical Application RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION C1 220nF Analogue Supply Decoupling C2 220nF Digital Supply Decoupling C3 10µF General Supply Decoupling Table 3 Recommended External Components Values WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 10 WM8816 Advanced Information LFO 3 4 LMO 2 5 Balanced Output 2K - +18V WM8816 -18V - RFO 14 13 2K + LGND DAC +18V LIN RMO 15 12 + +18V RIN 2K - -18V + RGND -18V 2K Figure 6 Configuration for Double Balanced Output (One Channel) WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 11 WM8816 Advanced Information PACKAGE DIMENSIONS DM019.A DW: 16 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch e B 16 9 E H L 1 8 D h x 45o A1 SEATING PLANE -CA Symbols A A1 B C D e E h H L α REF: α C 0.10 (0.004) Dimensions (mm) MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 1.27 BSC 7.40 7.60 0.25 0.75 10.00 10.65 0.40 1.27 o o 0 8 Dimensions (Inches) MIN MAX 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.3465 0.3622 0.0500 BSC 0.2914 0.2992 0.0100 0.0290 0.3940 0.4190 0.0160 0.0500 o o 0 8 JEDEC.95, MS-013 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-013, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 12