TI SN74SSTV32852

SN74SSTV32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003
D
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
1-to-2 Outputs Support Stacked DDR
DIMMs
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II
Specifications
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
RESET Input
D
D
D
D
D
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Pinout Optimizes DIMM PCB Layout
One Device Per DIMM Required
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C
LFBGA – GKF
Tape and reel SN74SSTV32852GKFR
SV852
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74SSTV32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003
GKF PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
Q2A
Q1A
CLK
CLK
Q1B
Q2B
B
B
Q3A
C
Q5A
VDDQ
Q4A
VDDQ
Q4B
Q3B
C
D
D
Q7A
Q6A
Q6B
Q7B
E
E
Q8A
GND
F
F
Q10A
Q9A
G
G
Q12A
Q11A
H
Q13A
VDDQ
GND
H
J
K
L
M
N
J
Q14A
VCC
Q15A
K
Q17A
Q16A
L
Q18A
Q19A
M
Q20A
N
Q22A
VDDQ
Q21A
GND
GND
VDDQ
GND
VDDQ
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
Q8B
Q9B
Q10B
GND
GND
Q11B
Q12B
VDDQ
GND
VDDQ
GND
VCC
Q15B
Q13B
VDDQ
GND
Q16B
Q17B
Q19B
Q18B
VDDQ
Q21B
Q20B
VDDQ
VCC
Q23B
D13
D14
GND
GND
VDDQ
GND
VDDQ
GND
Q14B
Q22B
P
Q23A
P
R
Q24A
VDDQ
VCC
RESET
R
T
D2
D1
D6
VREF
D18
T
U
D4
D3
D10
D22
D15
D16
U
V
D5
D7
D11
D23
D19
D17
V
W
D8
D9
D12
D24
D21
D20
W
2
Q5B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Q24B
SN74SSTV32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003
FUNCTION TABLE
INPUTS
RESET
CLK
CLK
D
OUTPUT
Q
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q0
L
X or floating
X or floating
X or floating
L
logic diagram (positive logic)
RESET
CLK
CLK
VREF
R3
A3
A4
R4
One of 24 Channels
D1
T2
A2
1D
Q1A
C1
R
A5
Q1B
To 23 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74SSTV32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003
recommended operating conditions (see Note 4)
MIN
NOM
MAX
VCC
VDDQ
Supply voltage
VDDQ
2.3
VREF
VTT
Reference voltage (VREF = VDDQ/2)
VI
VIH
Input voltage
AC high-level input voltage
Data inputs
VIL
VIH
AC low-level input voltage
Data inputs
DC high-level input voltage
Data inputs
VIL
VIH
DC low-level input voltage
Data inputs
High-level input voltage
RESET
VIL
VICR
Low-level input voltage
RESET
Common-mode input voltage range
CLK, CLK
0.97
VI(PP)
IOH
Peak-to-peak input voltage
CLK, CLK
360
High-level output current
–20
IOL
TA
Low-level output current
20
Output supply voltage
1.15
Termination voltage
VREF–40mV
0
V
2.7
V
1.35
V
VREF+40mV
VCC
V
1.25
VREF
UNIT
2.7
VREF+310mV
V
VREF–310mV
VREF+150mV
V
V
VREF–150mV
1.7
V
V
0.7
Operating free-air temperature
V
V
1.53
V
mV
0
mA
_C
70
NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC
2.3 V
II = –18 mA
IOH = –100 µA
VOH
2.3 V to 2.7 V
IOH = –16 mA
IOL = 100 µA
VOL
2.3 V
0.2
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
Dynamic operating –
clock only
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
Dynamic operating –
per each data input
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle,
One data input switching at one-half clock
frequency, 50% duty cycle
rOH
Output high
IOH = –20 mA
2.3 V to 2.7 V
7
rOL
Output low
IOL = 20 mA
VI = VREF ± 310 mV
2.3 V to 2.7 V
7
Data inputs
Ci
CLK, CLK
VICR = 1.25 V, VI(PP) = 360mV
VI = VCC or GND
27V
2.7
• DALLAS, TEXAS 75265
V
±5
µA
10
µA
35
mA
46
µA/
MHz
12
µA/
clock
MHz/
D input
2.7 V
2.5 V
RESET
† All typical values are at VCC = 2.5 V, TA = 25°C.
POST OFFICE BOX 655303
V
2.7 V
IO = 0
V
0.35
RESET = GND
ICCD
UNIT
–1.2
2.3 V
Static standby
IO = 0
MAX
2.3 V to 2.7 V
All inputs
ICC
TYP†
VDDQ–0.2
1.95
IOL = 16 mA
VI = VCC or GND
II
4
MIN
20
Ω
20
Ω
3
3.75
4.25
3
3.5
4
3.5
4.35
5
pF
SN74SSTV32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
MIN
fclock
tw
Clock frequency
tact
200
Differential inputs active time (see Note 5)
tinact
Differential inputs inactive time (see Note 6)
Pulse duration, CLK, CLK high or low
tsu
Setup time
th
Hold time
2.5
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
MHz
ns
22
ns
22
ns
0.75
D t before
Data
b f
CLK↑,
CLK↑ CLK↓
UNIT
MAX
ns
0.9
0.75
Data after CLK↑,
CLK↑ CLK↓
ns
0.9
NOTES: 5. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
6. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken
low.
7. Data signal input slew rate ≥1 V/ns
8. Data signal input slew rate ≥0.5 V/ns and <1 V/ns
9. CLK, CLK input slew rates are ≥1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK and CLK
Q
tPHL
RESET
Q
VCC = 2.5 V
± 0.2 V
MIN
200
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.1
UNIT
MAX
MHz
3.1
ns
5
ns
5
SN74SSTV32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
VTT
50 Ω
From Output
Under Test
Test Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT
tw
VIH
VREF
Input
VIL
VCC
LVCMOS
RESET
Input
VCC/2
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tinact
ICC
(see
Note B)
VREF
VI(PP)
tact
90%
10%
ICC (operating)
Timing
Input
ICC (standby)
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VICR
VICR
tPLH
tPHL
VOH
Output
VTT
VTT
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VI(PP)
Timing
Input
tsu
VIH
LVCMOS
RESET
Input
VICR
VCC/2
VIL
tPHL
th
VOH
VIH
Input
VREF
Output
VREF
VTT
VOL
VIL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E. VTT = VREF = VDDQ/2
F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74SSTV32852GKFR
ACTIVE
LFBGA
GKF
114
1000
SN74SSTV32852ZKFR
ACTIVE
LFBGA
ZKF
114
1000 Green (RoHS &
no Sb/Br)
TBD
Lead/Ball Finish
MSL Peak Temp (3)
SNPB
Level-3-220C-168 HR
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
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