SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 D D D D D D D D Member of the Texas Instruments Widebus Family Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200 Pinout and Functionality Compatible With JEDEC Standard SSTV32852 Pinout Optimizes 1U DDR DIMM Layout 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV32852 in PC2700 DIMM Applications 1-to-2 Outputs Support Stacked DDR DIMMs One Device Per DIMM Required Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line D D D D D D D Outputs Meet SSTL_2 Class I Specifications Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description/ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications. The SN74SSTVF32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C LFBGA – GKF Tape and reel SN74SSTVF32852KR SVF852 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 GKF PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A Q2A Q1A CLK CLK Q1B Q2B B B Q3A C Q5A VDDQ Q4A VDDQ Q4B Q3B C D D Q7A Q6A Q6B Q7B E E Q8A GND F F Q10A Q9A G G Q12A Q11A H Q13A VDDQ GND H J K L M N J Q14A VCC Q15A K Q17A Q16A L Q18A Q19A M Q20A N Q22A VDDQ Q21A GND GND VDDQ GND VDDQ GND VDDQ VDDQ VDDQ VDDQ GND Q8B Q9B Q10B GND GND Q11B Q12B VDDQ GND VDDQ GND VCC Q15B Q13B VDDQ GND Q16B Q17B Q19B Q18B VDDQ Q21B Q20B VDDQ VCC Q23B D13 D14 GND GND VDDQ GND VDDQ GND Q14B Q22B P Q23A P R Q24A VDDQ VCC RESET R T D2 D1 D6 VREF D18 T U D4 D3 D10 D22 D15 D16 U V D5 D7 D11 D23 D19 D17 V W D8 D9 D12 D24 D21 D20 W FUNCTION TABLE INPUTS 2 Q5B RESET CLK CLK D OUTPUT Q H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q24B SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 logic diagram (positive logic) RESET CLK CLK VREF R3 A3 A4 R4 One of 24 Channels D1 T2 A2 1D Q1A C1 R A5 Q1B To 23 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, qJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 recommended operating conditions (see Note 4) MIN NOM MAX VCC Supply voltage VDDQ Output supply voltage VREF Reference voltage (VREF = VDDQ/2) VTT VI Termination voltage VIH VIL AC high-level input voltage Data inputs AC low-level input voltage Data inputs VIH VIL DC high-level input voltage Data inputs DC low-level input voltage Data inputs VIH VIL High-level input voltage RESET Low-level input voltage RESET VICR VI(PP) Common-mode input voltage range CLK, CLK 0.97 Peak-to-peak input voltage CLK, CLK 360 IOH IOL High-level output current –8 Low-level output current 8 PC1600, PC2100, PC2700 PC3200 VDDQ 2.3 2.7 2.5 2.7 1.15 1.25 1.35 PC3200 1.25 1.3 1.35 Input voltage V 2.7 PC1600, PC2100, PC2700 VREF–40mV 0 UNIT VREF V V VREF+40mV VCC VREF+310mV V V V VREF–310mV VREF+150mV V V VREF–150mV 1.7 V V 0.7 V 1.53 V mV mA TA Operating free-air temperature 0 70 _C NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = –18 mA IOH = –100 µA VOH ICC ICCD 2.3 V All inputs IOL = 8 mA VI = VCC or GND Static standby RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle Data inputs Ci 2.3 V to 2.7 V IOH = –8 mA IOL = 100 µA VOL II VCC† 2.3 V TEST CONDITIONS CLK, CLK IO = 0 IO = 0 VI = VREF ± 310 mV VICR = 1.25 V, VI(PP) = 360mV • DALLAS, TEXAS 75265 MAX UNIT –1.2 V VDDQ–0.2 1.95 V 2.3 V to 2.7 V 0.2 2.3 V 0.35 ±5 27V 2.7 V µA 10 µA 35 mA 38 µA/ MHz 7 µA/ clock MHz/ D input 2.5 V 2.5 V VI = VCC or GND † For this test condition, VDDQ always is equal to VCC. ‡ All typical values are at VCC = 2.5 V, TA = 25°C. POST OFFICE BOX 655303 TYP‡ 2.7 V RESET 4 MIN 2.8 3.3 3.8 2.5 3 3.5 3 4 4.5 pF SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 electrical characteristics for PC3200 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = –18 mA IOH = –100 µA VOH ICC ICCD 2.5 V All inputs IOL = 8 mA VI = VCC or GND Static standby RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle Data inputs Ci CLK, CLK MIN 2.5 V to 2.7 V IOH = –8 mA IOL = 100 µA VOL II VCC† 2.5 V TEST CONDITIONS TYP‡ MAX UNIT –1.2 V VDDQ–0.2 1.95 V 2.5 V to 2.7 V 0.2 2.5 V 0.35 2.7 V IO = 0 IO = 0 VI = VREF ± 310 mV VICR = 1.25 V, VI(PP) = 360mV 27V 2.7 ±5 µA 10 µA 35 RESET VI = VCC or GND † For this test condition, VDDQ always is equal to VCC. ‡ All typical values are at VCC = 2.6 V, TA = 25°C. mA 38 µA/ MHz 7 µA/ clock MHz/ D input 2.6 V 2.6 V V 2.8 3.3 3.8 2.5 3 3.5 3 4 4.5 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V† MIN MAX VCC = 2.6 V ± 0.1 V† MIN 500 UNIT MAX fclock tw Clock frequency tact tinact Differential inputs active time (see Note 5) 22 22 ns Differential inputs inactive time (see Note 6) 22 22 ns Pulse duration, CLK, CLK high or low tsu Setup time th Hold time 1 Fast slew rate (see Notes 7 and 9) Slow slew rate (see Notes 8 and 9) Fast slew rate (see Notes 7 and 9) Slow slew rate (see Notes 8 and 9) D t before Data b f CLK↑, CLK↑ CLK↓ Data after CLK↑, CLK↑ CLK↓ 500 1 0.75 0.75 0.9 0.9 0.75 0.75 0.9 0.9 MHz ns ns ns † For this test condition, VDDQ always is equal to VCC. NOTES: 5. VREF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 6. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. 7. For data signal input slew rate ≥1 V/ns. 8. For data signal input slew rate ≥0.5 V/ns and <1 V/ns. 9. CLK, CLK signals input slew rates are ≥1 V/ns. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER fmax tpd tPHL FROM (INPUT) TO (OUTPUT) MIN MAX 500 CLK and CLK Q RESET Q † For this test condition, VDDQ always is equal to VCC. 6 VCC = 2.5 V ± 0.2 V† POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.1 VCC = 2.6 V ± 0.1 V† MIN 500 2.6 5 1.1 UNIT MAX MHz 2.6 ns 5 ns SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES426A – FEBRUARY 2003 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 30 pF (see Note A) RL = 500 Ω LOAD CIRCUIT tw VIH VREF Input VIL VCC LVCMOS RESET Input VCC/2 VCC/2 VOLTAGE WAVEFORMS PULSE DURATION 0V tinact ICC (see Note B) VREF VI(PP) tact 90% 10% ICC (operation) Timing Inputs ICC (standby) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR tPLH Output tsu VOH VDDQ/2 VOL VDDQ/2 VIH LVCMOS RESET Input VICR tPHL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VI(PP) Timing Inputs VICR VCC/2 VIL tPHL th VOH VIH Input VREF Output VREF VDDQ/2 VOL VIL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A. CL includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time with one transition per measurement. E. VREF = VDDQ/2 F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 14-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74SSTVF32852ZKFR ACTIVE LFBGA ZKF 114 1000 Green (RoHS & no Sb/Br) SN74SSTVF32852KR ACTIVE LFBGA GKF 114 1000 TBD Lead/Ball Finish MSL Peak Temp (3) SNAGCU Level-3-260C-168 HR SNPB Level-3-220C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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