IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK™ W FEATURES: • • • • DESCRIPTION Ref input is 5V tolerant 8 pairs of programmable skew outputs Two separate A and B banks for individual control Low skew: 185ps same pair, 250ps same bank, 350ps both banks Selectable positive or negative edge synchronization on each bank: excellent for DSP applications Synchronous output enable on each bank Input frequency: 2MHz to 200MHz Output frequency: 6MHz to 200MHz 3-level inputs for skew and PLL range control 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4) PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Power-down mode on each bank Lock indicator on each bank Available in BGA package • • • • • • • • • • • • • IDT5V9955 The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9955 has sixteen programmable skew outputs in eight banks of 2. The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs except x2Q0 and x2Q1 are synchronously disabled. The xLOCK is high when the xbank PLL has achieved phase lock. Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the xbank outputs are synchronized with the negative edge of REF. The IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM ALOCK APE AFS REF BPE TEST BFS BPD APD BsOE AsOE 3 3 3 PLL 3 /N 3 A1Q0 Skew Select A1Q1 3 3 ADS1:0 BDS1:0 A1F1:0 B1F1:0 Skew Select A2Q1 Skew Select A3Q1 A4Q0 Skew Select Skew Select 3 3 B2F1:0 A2F1:0 Skew Select 3 3 3 B3F1:0 A3F1:0 3 3 B4F1:0 A4F1:0 3 B2Q0 B2Q1 Skew Select 3 3 B1Q0 B1Q1 3 3 A4Q1 3 3 3 3 A3Q0 PLL /N BFB AFB 3 A2Q0 BLOCK B3Q0 B3Q1 Skew Select B4Q0 B4Q1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2002 1 c 2002 Integrated Device Technology, Inc. DSC 5974/9 IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 6 A3Q1 A4Q0 A4Q1 APE APD A4F1 A3F1 AFS B2F1 B1F1 BDS1 BLOCK BVDDQ B1Q0 B1Q1 B2Q0 5 A3Q0 AGND AGND AGND ASOE A4F0 A3F0 AVDD BGND B2F0 B1F0 BDS0 BVDDQ BGND BGND B2Q1 4 AGND AGND AGND AVDDQ AVDDQ AVDDQ AVDDQ AVDDQ TEST BVDDQ BVDDQ BVDDQ BVDDQ BGND BGND BFB 3 AFB AGND AGND AVDDQ AVDDQ AVDDQ AVDDQ REF BVDDQ BVDDQ BVDDQ BVDDQ BVDDQ BGND BGND BGND 2 A2Q1 AGND AGND AVDDQ ADS0 A1F0 A2F0 AGND BVDD B3F0 B4F0 BSOE BGND BGND BGND B3Q0 1 A2Q0 A1Q1 A1Q0 AVDDQ ALOCK ADS1 A1F1 A2F1 BFS B3F1 B4F1 BPD BPE B4Q1 B4Q0 B3Q1 G H J K L M N P R T A B C E D F FPBGA TOP VIEW 96 BALL FPBGA PACKAGE ATTRIBUTES 1.5mm Max. 1.4mm Nom. 1.3mm Min. 0.8mm 6 5 4 TOP VIEW 3 2 1 A B C D E F G H J K L M N P R T A B C D E F G H J K L M N P R T 1 2 3 5.5mm 4 5 6 13.5mm 2 IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) Unit Parameter CIN VDDQ, VDD Supply Voltage to Ground –0.5 to +4.6 V VI DC Input Voltage –0.5 to VDD+0.5 V REF Input Voltage –0.5 to +5.5 V W TSTG Maximum Power TA = 85°C 1.1 Dissipation TA = 55°C 1.9 Storage Temperature Range –65 to +150 INDUSTRIAL TEMPERATURE RANGE Description Input Capacitance Typ. Max. Unit REF 8 10 pF Others 5 7 NOTE: 1. Capacitance applies to all inputs except TEST, xFS, xnF[1:0], and xDS[1:0]. °C NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. PIN DESCRIPTION Pin Name Type Description REF IN Reference Clock Input xFB IN Individual Feedback Inputs for A and B banks TEST (1) IN When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See xsOE(1) IN xPE IN Control Summary Table) remain in effect. Set LOW for normal operation. Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q0 and x2Q1) in a LOW state (for xPE = H) - x2Q0 and x2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when xnF[1:0] = LL. Set xsOE LOW for normal operation (has internal pull-down). Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/ positive edge of the reference clock (has internal pull-up). xnF[1:0] IN xFS IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A and B banks. xnQ[1:0] OUT xDS[1:0] IN Eight banks of two outputs with programmable skew 3-level inputs for feedback divider selection for A and B banks xPD IN Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up). xLOCK OUT VDDQ PWR Power supply for output buffers VDD PWR Power supply for phase locked loop, lock output, and other internal circuitry GND PWR Ground PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the inputs. NOTE: 1. When TEST = MID and xsOE = HIGH, PLL remains active with xnF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless xnF[1:0] = LL. 3 IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE PROGRAMMABLE SKEW Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 625ps to 1.3ns (see Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the xnF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MIDLOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the xnF1:0 control pins. EXTERNAL FEEDBACK By providing two separate external feedbacks, the IDT5V9955 gives users flexibility with regard to skew adjustment. The xFB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE xFS = LOW xFS = MID xFS = HIGH Timing Unit Calculation (tU) 1/(32 x FNOM) 1/(16 x FNOM) 1/(8 x FNOM) VCO Frequency Range (FNOM)(1,2) 24 to 50MHz 48 to 100MHz 96 to 200MHz ±7.8125ns ±7.8125ns ±7.8125ns Comments Skew Adjustment Range(3) Max Adjustment: ns ±67.5° ±135° ±270° Phase Degrees ±18.75% ±37.5% ±75% % of Cycle Time Example 1, FNOM = 25MHz tU = 1.25ns — — Example 2, FNOM = 37.5MHz tU = 0.833ns — — Example 3, FNOM = 50MHz tU = 0.625ns tU = 1.25ns — Example 4, FNOM = 75MHz — tU = 0.833ns — Example 5, FNOM = 100MHz — tU = 0.625ns tU = 1.25ns Example 6, FNOM = 150MHz — — tU = 0.833ns Example 7, FNOM = 200MHz — — tU = 0.625ns NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. The level to be set on xFS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at x1Q1:0, x2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and xFB inputs will be FNOM when the output connected to xFB is undivided and xDS[1:0] = MM. The frequency of the REF and xFB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the xFB input and setting xDS[1:0] = MM. Using the xDS[1:0] inputs allows a different method for frequency multiplication (see Divide Selection Table). 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed xQ output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value. 4 IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE DIVIDE SELECTION TABLE xDS [1:0] xFB Divide-by-n Permitted Output Divide-by-n connected to xFB(1) LL 2 1 or 2 LM 3 1 LH 4 1, 2, or 4 ML 5 1 or 2 MM 1 1, 2, or 4 MH 6 1 or 2 HL 8 1 or 2 HM 10 1 HH 12 1 NOTE: 1. Permissible output division ratios connected to xFB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided output for xFB and setting xDS[1:0] to N (N = 1-6, 8, 10, 12). CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS nF1:0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4) LL (1) –4tU Divide by 2 Divide by 2 LM –3tU –6tU –6tU LH –2tU –4tU –4tU ML –1tU –2tU –2tU MM Zero Skew Zero Skew Zero Skew MH 1tU 2tU 2tU HL 2tU 4tU 4tU HM 3tU 6tU 6tU HH 4tU Divide by 4 Inverted (2) NOTES: 1. LL disables outputs if TEST = MID and xsOE = HIGH. 2. When pair #4 is set to HH (inverted), xsOE disables pair #4 HIGH when xPE = HIGH, xsOE disables pair #4 LOW when xPE = LOW. RECOMMENDED OPERATING RANGE Symbol Description VDD/VDDQ Power Supply Voltage TA Ambient Operating Temperature 5 Min. Typ. Max. Unit 3 3.3 3.6 V -40 +25 +85 °C IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Conditions(1) Min. Max. Unit 2 — V — 0.8 V VDD−0.6 — V VDD/2−0.3 VDD/2+0.3 V VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, xFB Inputs Only) VIL Input LOW Voltage Guaranteed Logic LOW (REF, xFB Inputs Only) VIHH Input HIGH Voltage(2) 3-Level Inputs Only VIMM Input MID Voltage 3-Level Inputs Only VILL Input LOW Voltage 3-Level Inputs Only — 0.6 V IIN Input Leakage Current VIN = VDD or GND −5 +5 µA — +400 −100 −400 −25 +100 — µA (2) (2) (REF, xFB Inputs Only) I3 VDD = Max. VIN = VDD HIGH Level 3-Level Input DC Current VIN = VDD/2 MID Level LOW Level µA (TEST, xFS, xnF[1:0], xDS[1:0]) VIN = GND IPU Input Pull-Up Current (xPE, xPD) VDD = Max., VIN = GND IPD Input Pull-Down Current (xsOE) VDD = Max., VIN = VDD — +100 µA VOH Output HIGH Voltage VDD = Min., IOH = −2mA (xLOCK Output) 2.4 — V 2.4 — VDDQ = Min., IOH = −12mA (xnQ[1:0] Outputs) VOL Output LOW Voltage — VDD = Min., IOL = 2mA (xLOCK Output) — 0.4 VDDQ = Min., IOL = 12mA (xnQ[1:0] Outputs) — 0.4 V NOTES: 1. All conditions apply to A and B banks. 2. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. POWER SUPPLY CHARACTERISTICS Symbol Parameter IDDQ Quiescent Power Supply Current Test Conditions(1) Typ.(2) Max. Unit 40 60 mA — 50 µA 1 60 µA xFS = L 190 290 xFS = M 150 230 xFS = H 130 200 VDD = Max., TEST = MID, REF = LOW, xPE = LOW, xsOE = LOW, xPD = HIGH xFS = MID, All outputs unloaded IDDPD Power Down Current VDD = Max., PD = LOW, xsOE = LOW xPE = HIGH, TEST = HIGH, xFS = HIGH xnF[1:0] = HH, xDS[1:0] = HH ∆IDD Power Supply Current per Input HIGH VIN = 3V, VDD = Max., xPD = LOW, TEST = HIGH (REF and xFB inputs only) IDDD ITOT Dynamic Power Supply Current per Output Total Power Supply Current xFS = L, FVCO = 50MHz, CL = 0pF 112 — xFS = M, FVCO = 100MHz, CL = 0pF 160 — xFS = H, FVCO = 200MHz, CL = 0pF 250 — NOTES: 1. Measurements are for divide-by-1 outputs, xnF[1:0] = MM, and xDS[1:0] = MM. All conditions apply to A and B banks. 2. For nominal voltage and temperature. 6 µA/MHz mA IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE INPUT TIMING REQUIREMENTS Description(1) Symbol Min. Max. Unit — 10 ns/V tR, tF Maximum input rise and fall times, 0.8V to 2V tPWC Input clock pulse, HIGH or LOW 2 — ns DH Input duty cycle 10 90 % FREF Reference clock input frequency xFS = LOW 2 50 xFS = MID 4 100 xFS = HIGH 8 200 NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. 7 MHz IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Min. Typ. Max. Unit FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table tRPWH REF Pulse Width HIGH(1) 2 tRPWL REF Pulse Width LOW 2 tU (1) Programmable Skew Time Unit — — ns — — ns See Control Summary Table tSKEWPR Zero Output Matched-Pair Skew (xnQ0, xnQ1)(2,3) — 50 185 ps tSKEWB Bank Skew(4) — 0.1 0.35 ns tSKEW0 Zero Output Skew (All Outputs from the same A or B bank) — 0.1 0.25 ns tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) — 0.1 0.25 ns tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)(6) — 0.2 0.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(6) — 0.15 0.5 ns tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(2) — 0.3 0.9 ns — — 0.75 ns −0.25 −0.25 −0.5 −0.7 −1 −1 — 0.25 ns — 0.25 ns — 0.5 ns — 0.7 ns — 1 ns 0 1 ns — — 1.5 ns (5) (6) tDEV Device-to-Device Skew(2,7) t(φ)1-3 Static Phase Offset (xFS = L, M, H) (FB Divide-by-n = 1, 2, 3) t(φ)H Static Phase Offset (xFS = H)(8) t(φ)M Static Phase Offset (xFS = M) (8) (8) t(φ)L1-6 Static Phase Offset (xFS = L) (xFB Divide-by-n = 1, 2, 3, 4, 5, 6)(8) t(φ)L8-12 Static Phase Offset (xFS = L) (xFB Divide-by-n = 8, 10, 12) tODCV Output Duty Cycle Variation from 50% tPWH Output HIGH Time Deviation from 50%(9) (8) tPWL Output LOW Time Deviation from 50% — — 2 ns tORISE Output Rise Time 0.15 0.7 1.5 ns tOFALL Output Fall Time 0.15 0.7 1.5 ns tLOCK PLL Lock Time ms tCCJH Cycle-to-Cycle Output Jitter (peak-to-peak) (10) (11,12) — — 0.5 — — 100 — — 150 — — 150 — — 200 — — 300 (divide by 1 output frequency, xFS = H, FB divide-by-n=1,2) tCCJHA Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = H, FB divide-by-n=any) tCCJM Cycle-to-Cycle Output Jitter (peak-to-peak) ps (divide by 1 output frequency, xFS = M) tCCJL Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = L, FREF > 3MHz) tCCJLA Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = L, FREF < 3MHz) NOTES: 1. Refer to Input Timing Requirements table for more detail. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xnQ0 and xnQ1) when all sixteen outputs are selected for 0tU. 4. tSKEWB is the skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU. 5. tSK(0) is the skew between outputs when they are selected for 0tU. 6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (x4Q0 and x4Q1 only with x4F0 = x4F1 = HIGH), and Divided (x3Q1:0 and x4Q1:0 only in Divideby-2 or Divide-by-4 mode). Test condition: xnF0:1=MM is set on unused outputs. 7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) 8. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on xFB. 8. Measured at 2V. 10. Measured at 0.8V. 11. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or xFB until tPD is within specified limits. 12. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter. 8 IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDDQ 150Ω Output Output 150Ω 20pF For LOCK output For all other outputs tOFALL tORISE tPWH 2.0V VTH = 1.5V 0.8V tPWL LVTTL Output Waveform ≤1ns 3.0V 2.0V VTH = 1.5V 0.8V 0V LVTTL Input Test Waveform 9 ≤1ns 20pF IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM tRPWL tREF tRPWH REF t(φ) tODCV tODCV FB tCCJH, HA, M, L, LA Q tSKEWPR,B tSKEW0, 1 tSKEWPR,B tSKEW0, 1 OTHER Q tSKEW2 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1, 3, 4 tSKEW2, 4 REF DIVIDED BY 4 NOTES: PE: Skew: The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ω to VDDQ/2. tSKEWPR: The skew between a pair of outputs (xnQ0 and xnQ1) when all eight outputs are selected for 0tU. tSKEWB: The skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0tU. tDEV: The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tPWH is measured at 2V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 10 IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 I -40°C to +85°C (Industrial) BF Fine Pitch Ball Grid Array 5V9955 3.3V Programmable Skew Dual PLL Clock Driver TurboClock W for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 11 for Tech Support: [email protected] (408) 654-6459