RENESAS M63155FP

M63155FP
3 PHASE BRUSHLESS MOTOR CONTROLLER
REJ03F0037-0100Z
Rev.1.0
Sep.16.2003
Outline
The M63155FP is a three phase brushless motor controller with six external N-channel Power MOSFETs. The motor
coil current is controlled by either a PWM pulse duty or a D/A signal level from an external controller.
Both VCC1 and VCC2 can be supplied by either external power supply or internal 5V regulator. Also voltage monitor
is available, and whichever of power supplies drops down, it generates an error signal.
Either fast or slow current-decay, either coast(free-run) or dynamic brake(short-brake) can be selected. Several
protection circuits are built in, thermal shut down and so on.
Internal tachometer, direction control and oscillator for internal logic are also available.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Wide voltage range: From 10V to 40V (VM)
5V regulator with the external PNP transistor
Internal gate supply voltage generator (Charge pump)
Voltage monitor
(VM , SVCC , External FET gate & External FET drain-source)
(Voltage monitor of External FET gate & External drain-source can be disabled.)
Motor current control by either a PWM duty or a D/A level
Selectable fast or slow current-decay
Selectable coast (free-run) or dynamic brake (short-brake)
FG internal tachometer (3phase mixed)
Direction control
Thermal Shut Down (TSD)
Power loss brake
Protection for invalid hall codes
Application
• High Power Three Phase Brushless Motor.
Rev.1.0, Sep.16.2003, page 1 of 40
M63155FP
Pin Configuration (TOP VIEW)
1
52
2
51
3
50
5
6
XXX
XXX
4
49
48
47
7
46
8
45
9
44
10
43
11
42
12
41
13
40
14
39
15
38
16
37
17
36
18
35
19
34
20
33
21
22
23
M63
155
FP
UT
U
UB
VT
V
VB
WT
W
WB
RSM
GND
NC
RSS
HU
HV
GND
HW
VCC1
TCL
CTL
CCFB
FCE
FG
FLT
RST
DS
32
31
30
24
29
25
28
26
27
52pin HSSOP (52P9Y)
Rev.1.0, Sep.16.2003, page 2 of 40
VM
VGT
CP6
CP5
VGB
CP4
CP3
VCP
CP2
CP1
GND
SVCC
VCC2
OSC1
OSC2
GND
SGND
REGR
REGC
REGB
REGE
REGL
BRK
BRS
FR
PWM
M63155FP
Block Diagram
SVCC
CP1 CP2 VCP CP3 CP4 VGB CP5 CP6 VGT
41
43
46
47
48
49
50
VM
51
52
C D
B
120 / 60 degree Switching Matrix / Pre-Driver
charge pump
for
upper gate
charge pump
for
lower gate 2
VGB Monitor
VGT Monitor
Hall Monitor
D-S Monitor
VM Monitor
B
45
charge pump
for
lower gate 1
5V Monitor
TSD Monitor
A
44
VCC2 40
OSC1 39
Current Control
Toff
circuit
Input Logic Circuit
OSC2 38
SGND 36
TSD
+
Bandgap
Reference
REGC 34
REGB 33
5V
Regulator
REGE 32
28
27
26 25
24 23
4
VT
5
V
6
VB
7
WT
8
W
9
WB
B
D
A
12 NC
13 RSS
22
21
20 19
BRK BRS FR PWM DS RST FLT FG FCE CCFB CTL TCL
Rev.1.0, Sep.16.2003, page 3 of 40
UB
A
C
29
3
D
C
30
U
B
C
GND
2
10 RSM
REGL 31
42, 37
UT
A
FG
(Tacho Meter)
REGR 35
-
Oscillator
1
D
18
VCC1
17
15
14
HW HV HU
16 , 11
GND
M63155FP
Pin Description
Pin No.
Symbol
Function
Pin No.
Symbol
Function
1
UT
52
VM
Motor Power Supply
2
U
Phase-U Top-side
Gate Drive Output
Phase-U Motor Output
51
VGT
Top-side Gate
Supply Voltage Output
3
UB
50
CP6
Charge-pump Capacitor 6
4
VT
Phase-U Bottom-side
Gate Drive Output
Phase-V Top-side
Gate Drive Output
49
CP5
Charge-pump Capacitor 5
5
V
Phase-V Motor Output
48
VGB
6
VB
Phase-V Bottom-side
Gate Drive Output
47
CP4
Bottom-side Gate
Supply Voltage Output
Charge-pump Capacitor 4
7
WT
46
CP3
Charge-pump Capacitor 3
8
W
Phase-W Top-side
Gate Drive Output
Phase-W Motor Output
9
WB
10
RSM
11
12
45
VCP
Charge-pump Voltage Output
Phase-W Bottom-side
Gate Drive Output
Motor Current Sensing Input for
big signal line
44
CP2
Charge-pump Capacitor 2
43
CP1
Charge-pump Capacitor 1
-
NC
NC
42
41
GND
SVCC
GND
External 5V Sensing Input
13
RSS
40
VCC2
Big Signal 5V Power Supply
14
HU
Motor Current Sensing Input for
small signal line
HU Hall Sensor Amp. Input
39
OSC1
Oscillator Output 1
15
16
HV
GND
HV Hall Sensor Amp. Input
GND
38
37
OSC2
GND
Oscillator Output 2
GND
17
18
HW
VCC1
HW Hall Sensor Amp. Input
Small Signal 5V Power Supply
36
35
SGND
REGR
Oscillator GND
5V Regulator
Phase Compensation
19
20
TCL
CTL
Current Control Off Time Input
Current Control Input
34
33
REGC
REGB
5V Regulator Output
5V Regulator Current Sink
21
22
CCFB
FCE
Output of current comparator
Voltage monitor enable input
32
31
REGE
REGL
5V Regulator Current Sensing
5V Regulator
Phase Compensation
23
24
FG
FLT
FG Output
Voltage Monitor Fault Output
30
29
BRK
BRS
Braking Input
Braking Mode Select Input
25
26
RST
DS
Reset Input
Fast / Slow Current Decay Mode
Select Input
28
27
FR
PWM
Forward / Reverse Select Input
PWM Input
Rev.1.0, Sep.16.2003, page 4 of 40
M63155FP
Absolute Maximum Rating
(unless otherwise noted Ta=25°C centigrade)
Limits
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Vm
Motor Power Supply
at VM
10
-
40
V
Vcc
Vto
5V Power Supply
Top Side Gate Drive
Output Voltage
at VCC1, VCC2
at UT, VT, WT
4.0
-
VM
+10.8
6.0
-
V
V
Vo
Motor Output Voltage
-
-
50
V
Vbo
Bottom Side Gate Drive
Output Voltage
at U, V, W
including motor coil over
shoot
at UB, VB, WB
-
12.2
-
V
Vin1
Logic Input Voltage
-
-
6
V
Vin2
Logic Input Voltage
Open Drain Output
Voltage
Open Drain Output
Current
at BRK, BRS, FR, DS,
RST, HU, HV, HW
PWM
-
-
15
V
at FG, FLT, TCL
-
-
6
V
at FG, FLT, TCL
0
-
5
mA
Free Air
Free Air
-
1.2
9.6
-
W
mW/°C
Vdo
Ido
Pt
Kt
Power Dissipation
Thermal Derating
Tj
Topr
Junction Temperature
Operating Temperature
0
-
150
75
°C
°C
Tstg
Storage Temperature
-20
-
125
°C
Recommended Operating Condition
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
Limits
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Vm
Motor Power Supply
at VM
10
12
40
V
Vcc
5V Power Supply
at VCC1, VCC2
at VCC1 on Power Fail
4.5
3.5
5.0
-
5.5
5.5
V
V
Fpwm
PWM Input Frequency
at PWM
10
20
30
kHz
Rev.1.0, Sep.16.2003, page 5 of 40
M63155FP
Power Dissipation Pdp (W)
Thermal Derating
5.0
using T-type board
4.0
using U-type / V-type
board
3.0
2.0
1.0
0
25
50
75
100
125
150
Ambient Temperature Ta (degree centigrade)
This IC's package is POWER-SSOP, so improving the board on which the IC is mounted enables a large power
dissipation without a heat sink. For example, using an 1 layer glass epoxy resin board, the IC's power dissipation is
2.6W at least. And it comes to 3.6W by using an improved 2 layer board.
The information of the T, U, V type board is shown in next page.
Rev.1.0, Sep.16.2003, page 6 of 40
M63155FP
The boards for thermal derating evaluation
1st layer [TOP view]
2nd layer [BACK view]
Conditions
Board material ;
Glass-epoxy FR-4
Size ; 70 X 70 mm2
T-type
Board thickness ; 1.6 mm
[2 layer]
1 and 2 layers
Metal material ; copper
Metal thickness ; 18 µm
U-type
[2 layer]
V-type
[1 layer]
Lead
Heat sink
Chip
Package inner structure
52P9Y-K
Rev.1.0, Sep.16.2003, page 7 of 40
IC mounting on the evaluation board
M63155FP
Electrical characteristics
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
Limits
Symbol
Parameter
Conditions
POWER SUPPLY (VM, VCC1, VCC2, VCP, VGB, VGT)
Motor Power Supply
at VM
Im
Normal Control Mode
Current
The motor is not driven
Ivcc
5V Power Supply
at VCC1
Current
Normal Control Mode
The motor is not driven
at VCC2
Normal Control Mode
The motor is not driven
Vcp
Charge-pump Output
at VCP,
Voltage
no gate driving
Bottom-side Gate
at VGB,
Vgb
Supply Voltage
ILVGB=ILVGT=7.0mA
Vgt
Top-side Gate Supply
at VGT,
Voltage
ILVGB=ILVGT=7.0mA
Charge-pump (VCP)
fosc=1MHz,
Tcp
Cp1=470nF, Ccp=4.7µF
Pre-charge Time
*Refer to the Fig.1.
Tgb
Charge-pump (VGB)
fosc=1MHz,
Pre-charge Time
Cp2=470nF, Cgb=33µF
* Refer to the Fig.1.
Charge-pump (VGT)
fosc=1MHz,
Tgt
Cp3=470nF, Cgt=4.7µF
Pre-charge Time
* Refer to the Fig.1.
Fosc
Oscillator Frequency
Rosc=15kΩ
Min.
Typ.
Max.
Unit
-
2.3
5.0
mA
-
4
7
mA
-
16
33
mA
7.0
8.5
10.0
V
8.5
11.5
-
V
VM
+7.5
VM
+9.5
-
V
-
4
4.8
msec
-
28
33.6
msec
-
4
4.8
msec
6.4
8.0
9.6
MHz
12V
VM
(VCC2=REGC)
50%
0V
90%
8.6V
(12.2V, VM+10.8V)
VCP
(VGB, VGT)
0V
Tcp
(Tgb, Tgt)
Fig.1 Charge-pump Pre-charge Time Definition
Rev.1.0, Sep.16.2003, page 8 of 40
M63155FP
Electrical characteristics
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
Limits
Symbol
Parameter
Conditions
REGULATOR (REGE, REGB, REGC, REGR)
Regulator Output
Io=50mA
Vr
Voltage
*Note1
Vm=10~40V, Io=50mA
Vrin
Regulator Output
*Note1
Voltage Stability for
Input Vm Voltage
Regulator Output
Vrout
Io=0~200mA *Note1
Voltage Stability for
Load Current
Vlim
RS Threshold Voltage
REGE terminal voltage
*Note1
* Note1 :
Min.
Typ.
Max.
Unit
4.75
5.0
5.25
V
-
0.0
30.0
mV
-
0.0
30.0
mV
0.8
1.0
1.2
V
The values of the external parts are in the “The recommended values of the external parts” table. The hFE of
External PNP transistor is “100” minimum.
Rev.1.0, Sep.16.2003, page 9 of 40
M63155FP
Electrical characteristics
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
Limits
Symbol
Parameter
Conditions
VOLTAGE MONITOR (VM, SVCC, FLT)
External 5V Monitor
Vsvi
at SVCC
Input Voltage Range
Isvi
External 5V Monitor
at SVCC SVCC=5V
Input Current
External 5V Monitor
External 5V Drop Down
Vths
Threshold Voltage
*Refer to the Fig.2.
Vshy
External 5V Monitor
External 5V Rise up
Hysteresis Voltage
*Refer to the Fig.2.
VM Monitor
VM Drop Down
Vthm
Threshold Voltage
*Refer to the Fig.2.
Vmhy
VM Monitor
VM Rise Up
Hysteresis Voltage
*Refer to the Fig.2.
Hi-side FETs gate
Vthug
monitor
Threshold Voltage
Vughy
Hi-side FETs gate
monitor
Hysteresis Voltage
Low-side FETs gate
Vthlg
monitor
Threshold Voltage
Vlghy
Low-side FETs gate
monitor Hysteresis
Voltage
Drain-Source monitor
Vthds
Threshold Voltage
Vdshy
Drain-Source monitor
Hysteresis Voltage
FLT Output Saturation
at FLT, output sink
Vsft
Voltage
current: 2mA
Min.
Typ.
Max.
Unit
0
-
5.5
V
30
50
75
µA
4.00
4.25
4.35
V
50
100
150
mV
9.0
9.5
10.0
V
400
500
600
mV
-
-
VM+6
V
-
-
200
mV
-
6
V
-
-
200
mV
0.7
1
1.3
V
-200
-
-
mV
-
0.15
0.5
V
SVCC
(VM,
External gate voltage,
External Drain-Source voltage)
Vshy
(Vmhy,Vughy,Vlghy,Vdshy)
Vths
(Vthm,Vthug,Vthlg,Vthds)
5V
FLT
0V
Fig.2 Supply Voltage Monitor Time Definition
Rev.1.0, Sep.16.2003, page 10 of 40
M63155FP
Electrical characteristics
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
Limits
Symbol
Parameter
Conditions
CURRENT CONTROL (RSS, REF, CTL, TCL, CCFB)
Current Control
Vcti
at CTL
Input Voltage Range
Icti
Current Control
at CTL,
Input Current
CTL=RSS=0V
Current Control Off
Vtcl
at TCL
Time
Threshold Voltage
at TCL
Vtclhy
Current Control Off
Time
Hysteresis Voltage
Off Time Input
at TCL, output sink
Vstl
current: 2mA
Saturation Voltage
RSS>CTL
Vcpi1
Current comparator
at CCFB,
Output Current
RSS<CTL
Current comparator
at CCFB,
Vcpi2
Output Current
RSS>CTL
Vcpv1
Current comparator
at CCFB,
Saturation Voltage
sink current 1mA
Current comparator
at CCFB,
Vcpv2
Saturation Voltage
source current 1mA
HALL SIGNAL (HU, HV, HW, FG)
Hall High-State Input
Vhah
Voltage
Vhal
Hall Low-State Input
Voltage
Hall High-State Input
Ihah
Vha= 5V
Current
Ihal
Hall Low-State Input
Vha = 0V
Current
FG Output Saturation
at FG, output sink
Vsfg
Voltage
current : 2mA
Rev.1.0, Sep.16.2003, page 11 of 40
Min.
Typ.
Max.
Unit
0
-
3.3
V
-2.0
-0.4
-
µA
2.4
2.5
2.6
V
1.15
1.22
1.29
V
-
0.15
0.5
V
-1
-
-
mA
-
-
1
mA
0.5
-
-
V
-
-
VCC1
-0.5
V
2.0
-
-
V
-
-
1.0
V
-
0
1.0
µA
-1.0
0
-
µA
-
0.15
0.5
V
M63155FP
Electrical characteristics
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.0
-
-
V
-
-
1.0
V
Vlg= 5V
-
100
150
µA
Vlg= 0V
-1.0
0
-
µA
3.2
-
-
V
-
-
2.8
V
-
0
1
µA
Ilsl
Logic Low-State
Vls=0V
GATE DRIVE OUTPUTS (UT, VT, WT, UB, VB, WB)
Top Side Gate Drive
Vtoh=VGT-UT, VGT-VT,
Vtoh
VGT-WT
High State Voltage
Iload = -10 mA , Rg=0 Ω
Vtol
Top Side Gate Drive
Vtol=UT-U, VT-V, WTLow State Voltage
W
Iload = 10 mA , Rg=0 Ω
Bottom Side Gate Drive Vboh=VGB-UB, VGBVboh
VB, VGB-WB
High State Voltage
Iload = -10 mA , Rg=0 Ω
Vbol
Bottom Side Gate Drive Vbol=UB-RS, VB-RS,
Low State Voltage
WB-RS
Iload = 10 mA , Rg=0 Ω
-1
0
-
µA
-
0.7
1.2
V
-
0.25
0.40
V
-
0.7
1.2
V
-
0.25
0.40
V
Ton
Toff
-
150
100
-
nsec
nsec
-
200
-
nsec
-
80
-
nsec
-
200
-
nsec
-
80
-
nsec
LOGIC INPUT (DS, FR, BRS, BRK)
Logic High-State
Vlgh
Input Voltage
Vlgl
Logic Low-State
Input Voltage
Logic High-State
Ilgh
Input Current
Ilgl
Logic Low-State
LOGIC INPUT[Level shift] (PWM)
Vlsh
Logic High-State
Input Voltage
Logic Low-State
Vlsl
Input Voltage
Ilsh
Logic High-State
Input Current
Ttr
Ttf
Tbr
Tbf
Turn-on Delay
Turn-off Delay
Top Side Switching
Rise Time
Top Side Switching
Fall Time
Bottom Side Switching
Rise Time
Bottom Side Switching
Fall Time
Rev.1.0, Sep.16.2003, page 12 of 40
Conditions
Vls=11.5V
*Refer to the Fig.3.
*Refer to the Fig.3.
CL =1200pF, Rg=0 Ω
*Refer to the Fig.3.
CL=1200pF, Rg=0Ω
*Refer to the Fig.3.
M63155FP
Electrical characteristics
(Unless otherwise noted Ta=25°C, VM=12V, VCC1=VCC2=5V)
5V
50%
50%
PWM
0V
VA(*Note3)
90%
Vout(*Note2)
10%
0V
Ton
Tr
Toff
Tf
Fig.3 Gate Drive Output Time Characteristics Definition
* Note2 : Vout is the external Nch MOS FET 's gate-source voltage. The definition is, UT-U, VT-V, WT-W, and
U=V=W=VM=12V, Capacitor Load CL=1200pF. UB-RS, VB-RS, WB-RS, and RS=0V, Capacitor Load
CL=1200pF.
* Note3 : VA is the power supply voltage of the gate drive output. The definition is, VGT-VM=10.8V for UT-U, VTV, WT-W. VGB=12.2V for UB-RS, VB-RS, WB-RS.
* Note4 : The waveform above-mentioned is one of the switching timing, because an gate drive output state is due to
Hall sensor Amp. inputs. Please refer to the "Hall Signal Inputs and Motor Outputs Timing Diagram".
Rev.1.0, Sep.16.2003, page 13 of 40
M63155FP
Function Explanation
1. VM terminal (VM)
The power supply for the M63155FP is connected between this terminal and GND.
2. VCC terminals (VCC1, VCC2)
The 5V power supply for the M63155FP is connected between these terminals and GND.
The VCC1 supplies small signal 5V, and the VCC2 supplies big signal 5V (for Charge Pump).
*Notes: In order to ensure proper coast/braking operation even after detecting power loss, it is necessary to make
the VCC1 supplies maintain externally.
The state of the fault latch and the guaranteed function of other shutdown circuits is maintained by the charge
held on Cvcc1. Therefore, the length of this extended operation is determined by the value of Cvcc1.
The calculation method of a minimum value for Cvcc1, given a minimum hold-up time requirement (t).
Coarse hold-up calculation
Cvcc1(min) = t x iss / [Vcc1(nom) - Vcc1(min)]
for C in farads:
t = hold-up time (sec)
iss = steady-state Vcc1 node current in fault mode (A)
V = delta V from nominal to minimum (volts)
3. Hall Input Terminals (HU, HV, HW)
These terminals are connected to the Hall effect commutation IC’s output of the brushless motor, which have opencollector outputs.
4. Output Terminals (UT, VT, WT, U, V, W, UB, VB, WB)
These terminals are the gate drive outputs for the external MOS FETs. UT, VT and WT are the gate drive outputs
for the top side external MOS FETs. U, V and W are connected to the motor output terminals and the source
terminals of the top side external MOS FETs. UB, VB and WB are the gate drive outputs for the bottom side
external MOS FETs.
Rev.1.0, Sep.16.2003, page 14 of 40
M63155FP
Function Explanation
5. Oscillator (OSC1, OSC2, SGND)
The oscillation frequency (Fosc) of the oscillator is determined by the external capacitor and resistor which are
connected to these terminals. The capacitor is connected between OSC2 and SGND, and the resistor is connected
between OSC1 and OSC2.
SGND is the common terminal of the oscillator circuit. So it is connected to the root of the board GND due to
getting the high accurate performance. The oscillation frequency theoretical value is given by:
(Fosc)
1
- 2 Rosc Cosc ln( 1 )
2
Rosc : External resistance for oscillator
Cosc : External condenser for oscillator
However, the actual oscillation frequency is different by influence of response of the oscillator circuit.
The characteristic of the theoretical oscillation Frequency – the actual oscillation frequency is as follows (Fig.4).
Fosc [kHz]
1600
1400
theoretical value
measurment value
1200
1000
800
TBD
600
400
200
0
1
1
0
Rosc [kohm]
100
Fig.4 The characteristic of oscillation frequency (Cosc=180pF)
Rev.1.0, Sep.16.2003, page 15 of 40
M63155FP
6. Charge Pump (CP1, CP2, VCP / CP3, CP4, VGB / CP5, CP6, VGT )
The charge pump consists of an internal circuit and two external capacitors. One capacitor should be connected
between the CP1 (CP3/CP5) terminal and the CP2 (CP4/CP6) terminal, and the other capacitor should be connected
between the VCP (VGB/VGT) terminal and GND.
The VGB (VGT) (the output of the charge pump circuit) is connected internally to the source of the bottom side Pchannel pre-driver transistors. (the source of the top side P-channel pre-driver transistors.) So the bottom side gate
drive transistors are powered by VGB and top side by VGT.
The explanation of the charge pump function is as follows (Fig.5). And the characteristic of the PWM Input
Frequency – the VGB(VGT) is as follows (Fig.6).
VCC2
(VCP/VGB)
1/Fosc
VCP
(VGB/VGT)
1/4*1/Fosc
Q1
Oscillator
VCC2
(CP2/VM)
D1
OFF
ON
CP2
CP1
(CP3/CP5) (CP4/CP6)
D2
1/4 Counter
Ccp
(Cgb, Cgt)
Cp1
(Cp2/Cp3)
Q2
ON
OFF
inverter
Fig.5 Charge Pump Circuit
(1) Q1=OFF, Q2=ON
The voltage of the CP2 terminal
(Vcp2) is given by: Vcp2 = VCC2 - VF
VF is the threshold voltage of the diodesD1, D2.
At this time, a capacitor connected between the CP1 terminal and the CP2 terminal is charged up.
(2) Q1=ON, Q2=OFF
Then the Q1 and Q2 are switched (the Q1 is turned on and the Q2 is turned off).
The Vcp2 is given by: Vcp2 = (VCC2 - VF) + VCC2
And the charge-pump voltage is given by: VCP = (VCC2 - VF) + VCC2 - VF = 2VCC2-2VF
In case of VCC2=5V and VF=0.7V, VCP is 10-1.4=8.6V.
(3) VGB, VGT
Likewise VCP mentioned above, VGB and VGT voltage is given by:
VGB = (CP2 - VF) + VCP - VF = CP2+VCP-2VF
VGT = (VM - VF) + VGB - VF = VM+VGB-2VF
M63155FP Fpwm - VGT characteristic
at VM=12V
M63155FP Fpwm - VGB characteristic
15.6
15.4
VGT (V)
VGB (V)
15.2
15
14.8
Cgs=470pF
Cgs=1000pF
Cgs=1500pF
14.6
14.4
14.2
1
1 0
Fpwm (kHz)
100
25.8
25.6
25.4
25.2
25
24.8
24.6
24.4
24.2
24
23.8
Cgs=470pF
Cgs=1000pF
Cgs=1500pF
1
10
Fpwm (kHz)
Fig.6 PWM Input Frequency (Fpwm) – VGB(VGT) characteristic
Rev.1.0, Sep.16.2003, page 16 of 40
100
M63155FP
In case of VCC1=VCC2=5V, VM=12V, RST=PWM=FR=BRK=HV=5V, DS=BRS=HU=HW=0V,Cp1~3=470nF,
Ccp=Cgt= 4.7µF, Cgb=33µF, Fosc=8MHz
7. 5V Regulator (REGE, REGB, REGC, REGR, REGL)
The 5V regulator with the external PNP Tr. included the internal gain resistors. It has the output current limit
function which needs the external current sensing resistor .
The explanation of the 5V Regulator function is as follows (Fig.7).
VM
[V]
REGC
(5V)
RSR
REGE
REGB
+
-
REGL
REGR
5V
REGC
0
+
Ilim
[A]
The limit current value is given by:
+
-
(Limit Current)
Vlim
RSR
Vlim : 5V Regulator Rs threshold voltage (typ; 1.0V)
RSR : 5V Regulator current sensing resistor value
Fig. 7 5V Regulator application circuit and characteristics
Rev.1.0, Sep.16.2003, page 17 of 40
M63155FP
8. Current Control (RSS, RSM, CTL, TCL)
RSS is the sensing input of the motor current. A filter resistor(Rnf) should be connected between this terminal and
the RSM terminal. A sensing resistor(RS) should be connected between the RSM and motor ground. The current
control circuit compares the voltage of the sensing resistor(RS) with the CTL terminal input voltage.
When the motor current reaches the threshold voltage (the CTL terminal input voltage), the current control circuit
shuts down the motor current with turning off the external FETs during the constant period determined by the
external elements on the TCL terminal. This function acts independent of the PWM input signal.
If the motor current is controlled by the only PWM input signal, this current control circuit acts as a motor current
limit protection circuit. In this case, the motor current limit value could be determined by the CTL input voltage.
(1) Current control function
Vctl /Rs
Motor Current
Toff Constant
(Tcl)
zero
5V typ.
12V typ.
VM
M
(Control Current)
CTL
Rcin
Rcl Ccl ln(
VCC1 Vtcl
)
VCC1
The motor control current value is given by:
Rcl
Vctl
from MCU
(Off Time)
Rcl : Current control Off Time Resistance
Ccl : Current control Off Time Condenser
Vtcl : Current control Off Time Threshold Voltage
(typ; 2.5V)
- M63155FP -
VCC1
/VCC2
The motor current is controlled by the CTL input voltage.
When the motor current reaches the threshold voltage,
the motor current is shut down while the constant period.
The period of the motor shutting down is given by:
TCL
RSM
RSS
Ccl
Cnf
Rnf
RS
Vctl
Rs
Vctl : CTL terminal input voltage (from MCU)
Rs : Motor current sensing resistor value
The CTL input resistor(Rcin) sets the same value of the
limit sensing low pass filter resistor(Rnf) to compensate
the input impedance of current comparator.
(2) Current limit function
The Current control circuit could be acted as the current
limit protection circuit. In this case, the motor current is
controlled by the PWM input duty.
The value of the motor current limit is given by:
PWM Input
Motor Current
5V typ.
(Limit Current) Vref
12V typ.
- M63155FP -
VCC1
/VCC2
Rcl
Rct1
Vref : output voltage (ex.; VCC1=5V)
Rct1, Rct2 : VCC1 into CTL dividing resistor value
Rs : Motor current sensing resistor value
VM
M
CTL
Ccl
Rct2
Rcin
TCL
RSM
RSS
Cnf
Rct2
1
Rct1 Rct2 Rs
Rnf
RS
When the motor current reaches the limit current value,
the motor current is shut down while the constant period
like as above mentioned in “(1) Current control function”.
The CTL input resistor(Rcin) sets the below equation
value to compensate the input impedance of current
comparator.
Rcin (Rct1//Rct2) Rnf
Rct1, Rct2 : VCC1 into CTL dividing resistor value
Rnf : Limit sensing low pass filter resistor value
Fig. 8 Motor Current Control Function
Rev.1.0, Sep.16.2003, page 18 of 40
M63155FP
9. Current Decay Method (DS)
The current decay method is determined by the input into the DS terminal. In slow-decay mode, only the high side
MOS FET is switched open during a PWM OFF (Low) cycle. The fast-decay mode switches both the high and low
side MOS FETs.
Table 1. gives the DS selection truth table.
TABLE 1.
DS Selection Truth Table
DS
Function Mode
High
Slow-Decay
Low
Fast-Decay
The output MOS FETs are controlled by PWM signal as follows.
D3
Q1
I1
Q3
Q5
D2
Q2
VM
I2
Q4
Q6
Q1
I1
Q3
D2
Q5
VM
Q4
Q2
Q6
I2
RS
(1)Condition: Q1 is ON and Q4 is ON.
(PWM ON period)
The motor current I1 goes to RS through the
transistors Q1 and Q4.
(2)Condition: Q4 is ON and Q2, Q1 are OFF.
(PWM ON -> OFF switching period)
The discharge current I2 goes through the
diode D2. This diode is a parasitic diode of the
output power FET.
(3)Condition: Q4 is ON and Q2, Q1 are OFF.
(PWM OFF period)
The discharge current I2 keeps going through
the diode D2. Q2 keeps being OFF.
(4)Condition: Q4 is ON and Q2, Q1 are OFF.
(PWM OFF -> ON switching period)
Likewise state (3), the discharge current I2
keeps going through the diode D2. Q2 keeps
being OFF.
RS
(1)Condition: Q1 is ON and Q4 is ON
(PWM ON period)
The motor current I1 goes to RS through the
transistors Q1 and Q4.
(2)Condition: Q1, Q4, Q2 and Q3 are OFF.
(PWM ON -> OFF switching period)
The discharge current I2 goes through the
diode D2 and D3. This diode is a parasitic diode of
the output power FET.
(3)Condition: Q1, Q4, Q2 and Q3 are OFF.
(PWM OFF period)
The discharge current I2 keeps going through
the diode D2 and D3.
(4)Condition: Q1, Q4, Q2 and Q3 are OFF.
(PWM OFF -> ON switching period)
Likewise state (2), the discharge current I2 goes
through the diode D2 and D3.
* When all the output power FETs are OFF, for example as
the phase change, the discharge current goes to VM through
these parasitic diodes.
a) Slow-Decay Function
b) Fast-Decay Function
Fig. 9 Current Decay Method at the MOS FETs Control with PWM Signal
Rev.1.0, Sep.16.2003, page 19 of 40
M63155FP
10. Braking Mode Enable (BRK)
In the normal motor rotation, the motor is able to be braked optionally by external control signal put into the BRK
terminal. The braking mode, either coast (free-run) or brake (short-brake) is selected by the BRS terminal (cf. 12.
Brake Mode Selection -1)).
Table 2. gives the BRK selection truth table.
TABLE 2.
BRK Selection Truth Table
BRK
Function Mode
High
Normal Control Mode
Low
Brake Mode
11. Voltage Monitor (VM, SVCC, FLT)
If either the motor power supply (VM) or the 5V (SVCC) or both drops below the threshold, FLT is “Low”. At this
time, the BRS state (cf. 12. Braking Mode Selection) is latched by this FLT “L” signal and keeps its state. (a
detailed explanation is given under item “18. Protection circuit” on page 23.)
Then, the return of the FLT is decided by conditions of the Voltage Monitor comparator output and Reset input
(RST).
(normal)
SVcc or VM
(normal)
SVcc or VM
(fault)
H
H
RST
H
L
H
FLT
L
RST:L
FLT:Low latch
H
H
RST
L
H
FLT
(fault)
FLT:latch cancel
H
L
L
RST:L
RST:H and Voltage fault keeps
FLT:High
FLT:latch cancel
Fig.10 Voltage Monitor Circuit & Timing Chart
Rev.1.0, Sep.16.2003, page 20 of 40
M63155FP
12. Braking Mode Selection (BRS)
1) In the normal mode (FLT output is “H”)
The braking mode whether coast (free-run) or brake (short-brake) is selected by the BRS terminal. In the coast
(free-run) mode, all of the output terminals are floating. On the other side, in the brake (short-brake) mode, all of
the top side MOS FETs are turned off and all of the bottom side MOS FETs are turned on. This Braking Mode
provides a braking torque which depends on the motor speed.
2) In the fault mode (FLT output is “L”)
In this case, the braking mode whether coast or brake is selected by the PWM signal irrelevant to the BRK
signal and the Current Control (RSS, CTL, TCL) function. The BRS state is latched by the FLT “L” signal. In
the BRS “L” state the coast mode is selected, while in the BRS “H” state the PWM signal determines the brake
mode.
And at this time, the positive power supply for the gate of the bottom side MOS FETs is provided by the chargepump external capacitor (Cgb; cf. Application circuit).
If gate drive to the bottom side MOS FETs is chopped via external control of the PWM pin, the minimum value
for Cgb is given in the following formula.
Coarse Cgb calculation
Cgb(min)= t x f x 3q(gate) / [Vcgb(initial) - Vcgb(final)]
for C in farads:
t = soft braking time (sec)
f = a chop frequency for PWM pin (Hz)
q(gate) = a electric charge stored in MOS FET gate (C)
q(gate) : refer to the data sheet of selected MOS FET
* In brake mode, the three bottom side MOS FETs(UB,VB,WB) turns on simultaneously. So, it is needed
by 3q(gate).
Vcgb = delta V from initial to final (volts)
Table 3. gives the BRS selection truth table.
TABLE 3.
BRS Selection Truth Table
normal mode (FLT;H)
fault mode (FLT;L)
BRS
BRK; H
BRK; L
PWM; H
PWM; L
High
Low
Normal
Normal
Brake
Coast
Brake
Coast
Coast
13. Reset input (RST)
This input used to enable the device. The “H” input allows the gate drive output to follow “Motor I/O truth table”.
The “L” input forces all gate drive output to 0V, coast(free-run) mode, and overrides the BRK state. And this “L”
input also resets the BRS state latched by the FLT “L” signal.
Table 4. gives the RST selection truth table.
TABLE 4.
RST Selection Truth Table
RST
Function Mode
High
Enable the device
Low
Disable the device (Reset the BRS and FLT state)
Rev.1.0, Sep.16.2003, page 21 of 40
M63155FP
14. Motor Rotation Direction (FR)
With the FR input at logic "High", the circuits are allowed to follow the commutation sequence for the motor
rotation in the forward direction. With the FR input at logic "Low", the internal switching matrix logic is inverted to
drive the motor in the reverse rotation.
Table 5. gives the FR selection truth table.
TABLE 5.
FR Selection Truth Table
FR
Function Mode
High
Forward Rotation
Low
Reverse Rotation
The relationship of the Hall sensors and the rotor of the motor is as follows.
Hall sensors
Outer rotor
U
V
W
V
W
U
U
V
REVERSE
W
FORWARD
Fig. 11 Motor Rotation Direction
15. Motor Rotation Speed Signal (FG)
The FG terminal is connected to the output of the internal tachometer which generates 3 pulse signal per electrical
revolution from the Hall sensor inputs. The relationship between the motor rotation speed and FG output signal
frequency is given by;
(Motor speed [rpm])
fFG ×60
1
Np× 2× 3
fFG : FG output signal frequency [Hz]
Np : Motor pole number
16. PWM Input (PWM)
In the normal mode (FLT is “H”), the PWM signal is applied to this terminal to control the motor speed. The motor
speed is due to the duty of the PWM input signal. On the other side, in the case of the FLT “L” state and the BRS
“H” state, the PWM signal determines the brake mode. (cf. 11. Voltage Monitor (VM, SVCC, FLT)).
Table 6. gives the PWM selection truth table.
TABLE 6.
PWM Selection Truth Table
PWM
Function Mode
High
Normal circulate current
Low
Recirculate current
17. Disable FET Voltage Monitors Input (FCE)
Usually, FCE is set “L”.
When fail of external FETs gate voltage or D-S voltage is detected, the FCE can be set “H” to disable the external
voltage check.
Detail explanation is shown in 5)D-S voltage monitor and 6)External FETs gate voltage monitor on page 23.
Rev.1.0, Sep.16.2003, page 22 of 40
M63155FP
18. Protection circuit
1) VM voltage monitor (VM: Motor supply voltage)
If VM drops below the Vthm, FLT is "L". Then the return of the FLT is decided by Vthm+Vmhy and RST
toggled(H-L-H) .
Detail drawing are in Fig.10 on page 20 and in Fig.24,25 on page 27.
2) SVCC voltage monitor (SVCC: External 5V power supply)
If SVCC drops below the Vths,FLT is "L". Then,the return of the FLT is decided by Vths+Vshy and RST
toggled(H-L-H).
Detail drawing are in Fig.10 on page 20 and in Fig.24,25 on page 27.
For relationships between protection and FLT output refer to Fig.18 on page 24.
3) TSD (Thermal shut down)
This function is for thermal protection. The Thermal Shut Down (TSD) circuit has a thermal sensor for the
junction temperature of the device. If the temperature goes above the TSD function start temperature, the TSD
circuit shut down the high-side Motor Pre-drive circuit and sets the fault latch.
Once the TSD circuit start the shut down function, it continues to the TSD function stop temperature.
The Table 7. gives the TSD function start / stop temperatures.
TABLE 7.
Thermal Shut Down Truth Table
Parameter
Typical Value
Units
Function Start temperature
140
degrees centigrade
Function Stop Temperature
110
degrees centigrade
* Note5:
These TSD temperature are the target temperatures for circuit design, not the guaranteed value.
4) HALL code check
If all halls are "H" or "L", FLT is "L". Then,the return of the FLT is decided by RST toggled (H-L-H).
Detail drawing are in Fig.10 on page 18 and in Fig.24,25 on page 27.
5) D-S voltage monitor (Drain-source voltage monitor of Top side External FETs)
In case of Fig.20 on page 25, FLT is “L”.
The timing to check the Drain-source voltage refer to Fig.21 on page 25.
Then, the return of the FLT is decided by RST toggled (H-L-H).
Detail drawing are in Fig.10 on page 20 and in Fig.24,25 on page 27.
The protection circuit is disable by setting a FCE pin to “H”.
Detail drawing are in Fig.22 on page 26.
6) External FETs gate voltage monitor (Voltage of the hi-side FETs gate x3, Voltage of the low-side FETs gate x3)
The timing that each External FET is ON,If each gate voltage does’nt come to threshold,FLT is “L”.
The timing to check each gate voltage refer to Fig.19 on page 24 .
Then, the return of the FLT is decided by RST toggled (H-L-H).
Detail drawing are in Fig.10 on page 20 and in Fig.24,25 on page 27.
The protection circuit is disable by setting a FCE pin to “H”.
Detail drawing are in Fig.23 on page 26.
Rev.1.0, Sep.16.2003, page 23 of 40
M63155FP
Motor supply voltage
VM
+
Vthm
External 5V power supply SVCC
(or REGC; the 5V Regulator output)
Drain-Source voltage monitor
VDSM-U
of Top side External FET.
TSD
+
c
FLT
-
open drain output
d
HALL
+
l
m
n
b
-
Vtht
Invalid HALL Cords
*Note:This function is guaranteed during
Absolute Maximam Rating on page 3.
+
Vths
Voltage by temperature
a
-
e
M1
Vthds
mask1
UT
Voltage of the hi-side FETs gate
VT
WT
L
M
N
UVWT
Vthug
+
f
-
M2
mask2
Voltage of the low-side FET gate
+
UB
g
Voltage of the low-side FET gate
M3
mask3
+
VB
h
Voltage of the low-side FET gate
M4
mask4
+
WB
Vthlg
i
-
M5
mask5
FCE
Reset input
RST
Fig.18 relations between each protections and FLT output
PWM is off.
Voltage of Phase U
Voltage of Phase V
Voltage of Phase W
Selecting switch point
for Hi-side FETs gate
M
L
L
N
M2 (mask signal)
Monitoring timing
M3 (mask signal)
M4 (mask signal)
M5 (mask signal)
1.54 - 2.5uS
moving
Fig.19 Timing chart of gate voltage monitor in Fast Decay
Rev.1.0, Sep.16.2003, page 24 of 40
Braking
M63155FP
For example:
If point-B is shorted GND, voltage(point-A) between external drain and source voltage reach to more than 1V
during turn-on.
So Drain-Source voltage monitor circuit senses voltage of point-A.
But this circuit can’t do perfect detecting shorted winding coil to GND.
VM
Drain-Source voltage monitor
At Point-e in Fig.22 on page 22
Off
Q5
A
On
Q3
More than 1V
l
Q1
+
Off
To FLT
Vthds
m
M1
>
n
Phase W
Phase V
Q4
Q6
Off
Phase U
Q2
Refer to Fig.21 on page 23
B
Off
On
RS
Over load current
Fig.20 Drain-Source voltage monitor of external FETs
PWM is off
Voltage of Phase U
Voltage of Phase V
Voltage of Phase W
Selecting switch point
for Hi-side FETs gate
l
m
n
l
M1 (mask signal)
Monitoring timing
1.54 - 2.5uS
moving
Fig.21 Timing of drain-source voltage monitor
Rev.1.0, Sep.16.2003, page 25 of 40
Braking
M63155FP
PWM is off.
Voltage of Phase U
Voltage of Phase V
Voltage of Phase W
Selecting switch point
for Hi-side FETs gate
M
L
L
N
M2 (mask signal)
Monitoring timing
M3 (mask signal)
M4 (mask signal)
M5 (mask signal)
moving
1.54 - 2.5uS
FCE(pin22)
Braking
Disabled
Fig.22 Timing chart of gate voltage monitor in Fast Decay
PWM is off
Voltage of Phase U
Voltage of Phase V
Voltage of Phase W
Selecting switch point
for Hi-side FETs gate
l
m
l
n
M1 (mask signal)
Monitoring timing
1.54 - 2.5uS
moving
FCE(pin22)
Braking
Disabled
Fig.23 Timing of drain-source voltage monitor
Rev.1.0, Sep.16.2003, page 26 of 40
M63155FP
Function Explanation
5V
4.35V
4.25V
4.35V
4.25V
SVCC
4V
0V
(normal)
A*
(fault)
(fault)
H
RST L
H
L
H
L
H
FLT
H
H
L
L
H
L
BRS latch timing
Condition:
L
No latching
Latching BRS=“L”
BRS=“L”,PWM=“H”
Ex. FETs condition
Coast
Active
Coast
Active
Coast
Fig.24 Timing chart in power on and off (Pattern A)
5V
4.35V
4.25V
4.35V
4.25V
SVCC
4V
0V
(normal)
A*
(fault)
(fault)
H
RST L
FLT
BRS latch timing
Condition:
L
H
H
L
L
H
H
H
H
L
L
H
L
H
L
L L
Latching BRS=“H”
No latching
BRS=“H”,PWM=“H”
Ex. FETs condition
Coast
Active
Coast
Fig.25 Timing chart in power on and off (Pattern B)
A*: VM, TSD, HALL, VDSM-U, UT, VT, WT, UB, VB and WB in Fig. 18 on page 24
Rev.1.0, Sep.16.2003, page 27 of 40
Active
Brake
M63155FP
19. Power Loss Brake
In Power Loss Brake, calculation of capacitor value is show by Fig.26, and Block diagram of VGB line is Show by
Fig.27.
When mode is Power Loss Brake, low side pre. calculation of VGB capacitor value is as follows.
Condition
PWM
Function Time
VGB voltage
External FET capacity
Supplying Current to pre driver.
A=(122 x 2) pC (At once PWM)
B=14 µA (At Constant current)
D=47 µA (Max. current)
Capacity of External FET
C=740 pF ( External FET capacity)
:50 cycles
:500mS
:8.5V -> 6.8V
:740pF
Refer to fig.1 about A, B, C and D
For example calculation of PWM for 3 phases
Charge value for A (3 phase), B (3 phase), D(1 ch)
A x 50 x 3 + B x 500mS x 3 + D x 500mS = 36.6 nC + 21 µC + 23.5 µA
= 44.54 µC
Charge value for C (3 phase)
(740pF x 50) x (8.5 + 6.8) x 3 / 2 = 849.3 nC
C = 849.3 nC
Capacity value for A,B,C (3 phase)
(A + B + C + D) / (8.5V - 6.8V) = 45.39 µC / 1.7V
= 26.7 µF
Fig.26 Calculation of VGB current at Power Loss Brake
When mode is Power Loss Brake, low side pre. driver circuit was driven by current of VGB capacitor.
VM
Soft braking
VGT
M63155FP
VM
UT
Pre. Driver
for Top side FET
(Top-side-MOS)
Off
U
Phase-U
VGB
D
I/F
27uF
B
Pre. Driver
for Bottom side FET
A
8.5V
UB
RSM
On
C 740pF
Fig.27 Block diagram of Pre Driver
Rev.1.0, Sep.16.2003, page 28 of 40
One time
6.8V
Off
On
(Bottom-side-MOS)
M63155FP
Motor Input/Output Truth Table
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Input
DS FR BRK BRS PWM
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
H H/L H
H
H
H H/L L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
H
L
H H/L H
H
L
H H/L L
HU HV HW UT UB VT
H
H
H
L
L
L
H
H
H
L
L
L
H
L
H
L
H
H
H
L
H
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
H
H
L
L
L
H
H
L
L
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
H
L
L
H
L
H
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
H
L
H
L
L
H
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
H
H
H
L
L
L
H
H
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
L
H
H
L
L
H
L
H
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
H
H
L
L
L
H
H
H
L
L
L
L
L
H
L
L
H
H
L
H
L
L
H
L
L
H
H
L
H
L
L
H
H
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Rev.1.0, Sep.16.2003, page 29 of 40
Output
VB WT WB FG
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
H
H
L
L
H
L
L
L
H
L
L
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
H
L
L
H
H
L
L
H
L
L
L
H
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
H
H
L
H
H
L
L
H
L
L
L
L
L
L
L
L
Condition
Regular mode
*Rotate Direction ; Forward
*Current Decay MODE ; Slow Decay
*non-Brake-state
Regular mode
*Rotate Direction ; Forward
*Current Decay MODE ; Slow Decay
*Short-Brake-State
Regular mode
*Rotate Direction ; Forward
*Current Decay MODE ; Slow Decay
*Free-Run-State
Regular mode
*Rotate Direction ; Reverse
*Current Decay MODE ; Slow Decay
*non-Brake-state
M63155FP
Motor Input/Output Truth Table
No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Input
DS FR BRK BRS PWM
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
L
L
L
L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
H H/L H
L
H
H H/L L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
L
HU HV HW UT UB VT
H
H
H
L
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
H
L
L
H
L
H
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
H
L
H
L
L
H
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
H
H
H
L
L
L
H
H
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
L
H
L
H
H
H
L
H
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
H
H
L
L
L
H
H
L
L
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
H
L
L
H
L
H
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
H
L
H
L
L
H
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
Rev.1.0, Sep.16.2003, page 30 of 40
Output
VB WT WB FG
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
H
H
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
L
L
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
Condition
Regular mode
*Rotate Direction ; Reverse
*Current Decay MODE ; Slow Decay
*Short-Brake-state
Regular mode
*Rotate Direction ; Reverse
*Current Decay MODE ; Slow Decay
*Free-Run-state
Regular mode
*Rotate Direction ; Forward
*Current Decay MODE ; Fast Decay
*non-Brake-state
Regular mode
*Rotate Direction ; Forward
*Current Decay MODE ; Fast Decay
*Short-Brake-state
M63155FP
Motor Input/Output Truth Table
No.
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
Input
DS FR BRK BRS PWM
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
L
L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
H H/L H
L
L
H H/L L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
Output
HU HV HW UT UB VT VB WT WB FG
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
H
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
L
L
H
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
H
H
L
H
L
L
H
L
L
L
H
H
l
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
H
L
H
H
H
H
H
L
H
L
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
H
H
L
L
L
H
L
H
L
H
H
H
H
L
L
H
L
H
L
H
L
H
H
L
L
H
L
H
L
H
L
L
H
L
L
H
L
H
L
H
H
L
H
L
L
H
L
H
L
H
H
L
H
H
L
H
L
H
L
H
L
L
H
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
H
L
L
H
L
H
L
H
L
H
H
L
L
L
L
H
L
H
L
H
L
L
L
L
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
H
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Rev.1.0, Sep.16.2003, page 31 of 40
Condition
Regular mode
*Rotate Direction ; Forward
*Current Decay MODE ; Fast Decay
*Free-Run-state
Regular mode
*Rotate Direction ; Reverse
*Current Decay MODE ; Fast Decay
*non-Brake-state
Regular mode
*Rotate Direction ; Reverse
*Current Decay MODE ; Fast Decay
*Short-Brake-state
Regular mode
*Rotate Direction ; Reverse
*Current Decay MODE ; Fast Decay
*Free-Run-state
M63155FP
I/O Circuit
< VM, VCC2, CP1, CP2, VCP, CP3, CP4, VGB, CP5, CP6, VGT >
< UT, U, VT, V, WT, W >
VM
VCC2
VGT
VGB
VCP
CP4
CP2
UT, VT, WT
VM
CP1
VGT
CP5
CP3
CP6
U, V, W
< REGC >
< UB, VB, WB, RSM >
< REGE >
< REGR >
VM
VM
VM
VGB
REGR
UB, VB, WB
19K
RSM
< REGB >
REGE
800
REGC
2K
17K
< TCL >
< CTL >
< REGL >
< RSS >
VM
VM
VCC1
VCC1
VM
VCC1
50K
REGB
REGL
CTL
1K
< OSC1 >
< OSC2 >
RSS
2K
< SGND >
VCC1
VCC1
TCL
2K
2K
< BRK, BRS, DS, FR, RST, FCE >
VCC1
VCC1
60K
OSC1
OSC2
BRK,BRS, DS,
FR,RST, FCE
30K
5K
2K
90K
Rev.1.0, Sep.16.2003, page 32 of 40
SGND
48K
M63155FP
I/O Circuit
< SVCC >
< FLT, FG >
< HU, HV, HW >
VCC1
VCC1
VCC1
SVCC
HU, HV, HW
FLT, FG
2K
74.4K
25.6K
<CCFB>
<PWM>
VGB
VCC1
200K
CCFB
PWM
2K
Rev.1.0, Sep.16.2003, page 33 of 40
M63155FP
Hall Inputs and Motor Outputs Timing Chart
HU
Hall Input
(120 deg.)
HV
HW
PWM
PWM
U
Motor Output
Voltage
V
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
W
PWM
PWM
PWM
PWM
U
Motor Output
Voltage
(PWM Duty 100%) V
W
0
180
360
540
720
Electrical Revolution angle [degree]
* Note6 : These are the timing chart of the Hall commutation sensor outputs and the motor outputs,
and the motor output voltage waveforms only show the High/Low/Middle state in each period.
In details, these output voltage waveforms are different from the real waveforms of the actual
motor outputs under rotation.
Rev.1.0, Sep.16.2003, page 34 of 40
M63155FP
Application Circuit 1
• Motor current is controlled by D/A signal input level
VM(10~40V)
5V
Cregc
Cvcc1
VCC2
OSC1
VCC1
SVCC
REGL REGR REGC REGB
5V
Regulator
TSD Monitor
VGT Monitor
A
B
Hall Monitor
C
D-S Monitor
D
VGB Monitor
SGND
Cvm
Creg1 Creg2
5V Monitor
OSC2 Oscillator
Rosc
+
+
RSR
+
+
Cvcc2
Bandgap
Reference
REGE
VM Monitor
+
Cgt
VGT
VM
CP6
ZD4
Cp3
CP5
VGB
Cgb
B
UT
Rg1
U
SD1
D
charge pump
for
upper gate
ZD1
FET1
Ro1 Rgs1
A UB
+
FET2
ZD5
CP4
Rg2
B
CP3
Rpwm
120 / 60 degree Switching Matrix / Pre-Driver
Cp2
charge pump
for
lower gate 2
VCP
Ccp
+
CP2
Cp1
CP1
charge pump
for
lower gate 1
Rflt
MCU
Input Logic Circuit (latched BRS)
FLT
Voltage monitor error
BRS reset
RST
PWM Duty
PWM
Enable Coast /
Brake
BRK
Select Coast or
Brake
BRS
Rotation Polarity
FR
Decay Mode Select
DS
FG output
FG
Rg3
V
SD2
D
M
FET4
Rg4
B
WT
Rg5
W
SD3
ZD3
FET5
D
Rgs3
Ro3
A
WB
RSM
RSS
FET6
Rg6
Ri
Rnf
RS
Cnf
C
C
C
FCE
Hall Inputs
HU
HV
HW
Rh1
Hall IC
Rh2
Hall IC
Rh3
Hall IC
CTL
Motor current control
+
Rcl
Toff
circuit
PWM off time control
Current
Control
Ccl
GND
CCFB
Rfb
GND
Rev.1.0, Sep.16.2003, page 35 of 40
FET3
Rgs2
Ro2
FG
(Tacho Meter)
TCL
ZD2
A VB
Rfg
Rcin
VT
M63155FP
Application Circuit 2
• Soft brake in power loss.
5V
VM(10~40V)
0V
0V
Cregc
Cvcc1
VCC2
OSC1
VCC1
SVCC
REGL REGR REGC REGB
5V
Regulator
TSD Monitor
VGT Monitor
A
B
Hall Monitor
C
D-S Monitor
D
VGB Monitor
SGND
Cvm
Creg1 Creg2
5V Monitor
OSC2 Oscillator
Rosc
+
+
RSR
+
+
Cvcc2
Bandgap
Reference
REGE
VM Monitor
+
Cgt
VGT
VM
CP6
ZD4
Cp3
CP5
VGB
Cgb
B
UT
Rg1
U
SD1
D
charge pump
for
upper gate
ZD1
FET1
Ro1 Rgs1
A UB
+
FET2
ZD5
CP4
Rg2
B
CP3
Rpwm
120 / 60 degree Switching Matrix / Pre-Driver
Cp2
charge pump
for
lower gate 2
VCP
Ccp
+
CP2
MCU
Cp1
CP1
charge pump
for
lower gate 1
MCU
Input Logic Circuit (latched BRS)
FLT
Rflt
Voltage monitor error
BRS reset
RST
PWM Duty
PWM
Enable Coast /
Brake
BRK
Select Coast or
Brake
BRS
Rotation Polarity
FR
Decay Mode Select
DS
FG output
FG
Rg3
V
SD2
D
M
FET4
Rg4
B
WT
Rg5
W
SD3
ZD3
FET5
D
Rgs3
Ro3
A
WB
RSM
RSS
FET6
Rg6
Ri
Rnf
RS
Cnf
C
C
C
FCE
Hall Inputs
HU
HV
HW
Rh1
Hall IC
Rh2
Hall IC
Rh3
Hall IC
CTL
Motor current control
+
Rcl
Toff
circuit
PWM off time control
Current
Control
Ccl
GND
CCFB
Rfb
GND
Rev.1.0, Sep.16.2003, page 36 of 40
FET3
Rgs2
Ro2
FG
(Tacho Meter)
TCL
ZD2
A VB
Rfg
Rcin
VT
M63155FP
Application Circuit 3
• Motor current is controlled by PWM pulse input duty
5V
VM(10~40V)
Cregc
Cvcc1
VCC2
OSC1
VCC1
SVCC
REGL REGR REGC REGB
5V
Regulator
TSD Monitor
VGT Monitor
A
B
Hall Monitor
C
D-S Monitor
D
VGB Monitor
SGND
Cvm
Creg1 Creg2
5V Monitor
OSC2 Oscillator
Rosc
+
+
RSR
+
+
Cvcc2
Bandgap
Reference
REGE
VM Monitor
+
Cgt
VGT
VM
CP6
ZD4
Cp3
CP5
VGB
B
Rg1
U
SD1
D
charge pump
for
upper gate
ZD1
FET1
Ro1 Rgs1
A UB
+
Cgb
UT
FET2
ZD5
CP4
Rg2
B
CP3
120 / 60 degree Switching Matrix / Pre-Driver
Cp2
charge pump
for
lower gate 2
VCP
Ccp
+
CP2
Cp1
CP1
charge pump
for
lower gate 1
MCU
Input Logic Circuit (latched BRS)
FLT
Rflt
Voltage monitor error
BRS reset
RST
PWM Duty
PWM
Enable Coast /
Brake
BRK
Select Coast or
Brake
BRS
Rotation Polarity
FR
Decay Mode Select
DS
FG output
FG
Rg3
V
SD2
D
M
FET4
Rg4
B
WT
Rg5
W
SD3
ZD3
FET5
D
Rgs3
Ro3
A
WB
RSM
RSS
FET6
Rg6
Ri
Rnf
RS
Cnf
C
C
C
FCE
Hall Inputs
HU
HV
HW
Rh1
Hall IC
Rh2
Hall IC
Rh3
Hall IC
Rct1
CTL
Motor current control
+
Rcl
Rct2
Toff
circuit
PWM off time control
Current
Control
Ccl
GND
CCFB
Rfb
GND
Rev.1.0, Sep.16.2003, page 37 of 40
FET3
Rgs2
Ro2
FG
(Tacho Meter)
TCL
ZD2
A VB
Rfg
Rcin
VT
M63155FP
Reference Values of the External Parts
Value
External Parts Name
Notes
Symbol
Min.
Typ.
Cvm
Bypass Condenser for VM
Cvm
-
10
-
µF
FET1~FET6
Nch Power MOS FET
Ciss
-
1200
-
pF
Rg1~Rg6
Ro1~Ro3
Gate Resistances of FETs
Output Resistances for
Motor Coils
Gate-Source Resistances
of FETs
Schottky Diode
Rg
Ro
-
10
10
-
Ω
Ω
Rgs
-
100
-
kΩ
Rgs1~Rgs3
SD1~SD4
ZD1~ZD5
RS
Rnf
Cnf
Rh1~Rh3
Ccp, Cgt
Cgb
Cp1~3
Rosc
PNP
RSR
Creg1
Creg2
Cvcc1
Cvcc2
Cregc
Rfg, Rflt
Rct1
Rct2
Rcl
Rcin
Max.
Units
VF
-
-
0.5
V
Zener Diode
Motor Current Sensing
Resister
RS terminal Filtering
Resister
RS terminal Filtering
Condenser
Vak
RS
-
13
0.4
-
V
Ω
Rnf
-
430
-
Ω
Cnf
-
180
-
pF
Hall Input Pull-up Resister
Bypass Condenser for
Charge-pump Voltage
Bypass Condenser for
Charge-pump Voltage
(Power Loss Hold up of
500mS.)
Charge-pump Condenser
External Resistance for
Oscillator
External PNP Tr. for 5V
Regulator
5V Regulator Current
Sensing Resistance
Phase Compensation
Condenser for 5V Reg. 1
Phase Compensation
Condenser for 5V Reg. 2
Bypass Condenser for
VCC1
Bypass Condenser for
VCC2
Bypass Condenser for
REGC
FG, FLT Output Pull- Up
Resistances
Current Control input Gain
Resistances 1
Current Control input Gain
Resistances 2
Current Control Off Time
Resistance
Current Control input
Impedance Compensation
Rh
Ccp1
-
10
4.7
-
kΩ
µF
Ccp2
-
33
-
µF
Cp
-
470
-
nF
Rosc
-
15
-
kΩ
hfe
100
-
-
-
RSR
-
10
-
Ω
Creg1
-
1
-
nF
Creg2
-
1
-
nF
Cvcc1
-
10
-
µF
Cvcc2
-
10
-
µF
10
-
µF
Rev.1.0, Sep.16.2003, page 38 of 40
Cregc
Rd
-
100
-
kΩ
Rct1
-
2
-
kΩ
Rct2
-
0.5
-
kΩ
Rcl
2.5
-
-
kΩ
Rci
-
0.03
-
kΩ
M63155FP
Value
External Parts Name
Notes
Symbol
Min.
Typ.
Max.
Units
Ccl
Current Control Off Time
Condenser
Ccl
-
440
-
pF
Rpwm
PWM Input Pull-resistance
Rpwm
-
100
-
kΩ
*Note 10: This parameters are calculated values.
Rev.1.0, Sep.16.2003, page 39 of 40
M63155FP
Package Outline
52P9Y-K
MMP
EIAJ Package Code
HSSOP52-P-450-0.65
Plastic 52pin 450mil HSSOP
Weight(g)
–
JEDEC Code
–
Lead Material
Cu Alloy
TOP VIEW
e
b2
BOTTOM VIEW
I2
27
E
HE
e1
52
F
Recommended Mount Pad
1
Symbol
26
A
SIDE VIEW
G
D
A2
b
x
A1
M
L1
y
L
e
C
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
z
Z1
Detail G
Rev.1.0, Sep.16.2003, page 40 of 40
Detail F
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
–
–
2.2
0.2
0
0.1
–
2.0
–
0.22
0.27
0.32
0.23
0.25
0.3
17.3
17.5
17.7
8.2
8.4
8.6
–
0.65
–
11.63
11.93
12.23
0.3
0.5
0.7
–
1.765
–
–
–
0.625
0.775
–
–
0.12
–
–
–
–
0.1
0°
–
10°
–
0.5
–
–
11.43
–
1.27
–
–
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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