IDT ICS83023AMILF

DATA SHEET
DUAL, 1-TO-1Integrated
DIFFERENTIAL-TOCircuit
Systems, Inc.
LVCMOS TRANSLATOR/BUFFER
ICS83023I
ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
GENERAL DESCRIPTION
Features
The ICS83023I is a dual, 1-to-1 Differential-toICS
LVCMOS Translator/Fanout Buffer and a memHiPerClockS™
ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The differential inputs can accept most differential signal
types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and
translate into two single-ended LVCMOS outputs. The small
8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
• Two LVCMOS / LVTTL outputs
• Two differential CLKx, nCLKx input pairs
• CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 350MHz (typical)
• Output skew: 60ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.14ps (typical)
• Small 8 lead SOIC package saves board space
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK0
nCLK0
Q0
CLK1
nCLK1
Q1
CLK0
nCLK0
nCLK1
CLK1
1
2
3
4
8
7
6
5
VDD
Q0
Q1
GND
ICS83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
83023AMI
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
1
1
REV. B JANUARY 18, 2006
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
CLK0
Input
Type
Description
Pulldown Non-inver ting differential clock input.
2
nCLK0
Input
Pullup
Inver ting differential clock input.
3
nCLK1
Input
Pullup
Inver ting differential clock input.
4
CLK1
Input
5
GND
Power
Power supply ground.
6
Q1
Output
Single clock output. LVCMOS / LVTTL interface levels.
7
Q0
Output
Single clock output. LVCMOS / LVTTL interface levels.
8
VDD
Power
Positive supply pin.
Pulldown Non-inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
7
Ω
CPD
83023AMI
VDD = 3.6V
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4
pF
23
pF
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
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ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Positive Supply Voltage
Test Conditions
IDD
Positive Supply Current
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
20
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Minimum
Typical
Maximum
2.6
Units
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Maximum
Units
nCLK0, nCLK1
Test Conditions
VIN = VDD = 3.6V
Minimum
Typical
5
µA
CLK0, CLK1
VIN = VDD = 3.6V
150
µA
nCLK0, nCLK1
VIN = 0V, VDD = 3.6V
-150
µA
CLK0, CLK1
VIN = 0V, VDD = 3.6V
-5
µA
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
GND + 0.5
VCMR
NOTE 1, 2
NOTE 1: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
83023AMI
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1.3
V
VDD - 0.85
V
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
3
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Maximum Output Frequency
Test Conditions
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
t sk(pp)
tR
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise Time
tF
Output Fall Time
odc
Output Duty Cycle
Typical
1.8
2.1
Units
MHz
2.4
ns
60
ps
500
ps
100MHz, Integration Range
(637kHz-10MHz)
0.8V to 2V
100
25 0
400
ps
0.8V to 2V
100
250
400
ps
f ≤ 166MHz
45
50
55
%
57
%
0.14
f > 166MHz
43
50
All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information.
NOTE 1: Measured from the differential input crossing point to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2. Input clocks are phase aligned.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83023AMI
Maximum
350
t sk(o)
t ji t
Minimum
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ps
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
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ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
ADDITIVE PHASE JITTER
ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
0
-10
Additive Phase Jitter @ 100MHz
-20
(12kHz to 20MHz)
= 0.14ps typical
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
83023AMI
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
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REV. B JANUARY 18, 2006
5
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
5
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V ± 0.15V
VDD
SCOPE
VDD
nCLK
Qx
LVCMOS
V
V
Cross Points
PP
CMR
CLK
GND
GND
-1.65V ± 0.15V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
V
DD
Qx
Qx
2
V
PART 2
DD
Qy
Qy
2
tsk(o)
V
DD
2
V
DD
2
tsk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0, nCLK1
V
DD
2
Q0, Q1
CLK0, CLK1
t PW
Q0, Q1
t
VDD
2
t
PD
odc =
PERIOD
t PW
x 100%
t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
2V
Clock
Outputs
2V
0.8V
0.8V
tR
tF
OUTPUT RISE/FALL TIME
83023AMI
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REV. B JANUARY 18, 2006
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
6
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and VDD = 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
83023AMI
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
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REV. B JANUARY 18, 2006
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
7
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both VSWING and VOH must
meet the VPP and VCMR input requirements. Figures 2A to 2E
show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input inter-
faces suggested here are examples only. Please consult with
the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
83023AMI
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
8
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
200
500
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83023I is: 416
Pin-to-pin compatible with MC100EPT23
83023AMI
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REV. B JANUARY 18, 2006
9
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
9
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUN
N
MAXIMUM
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
e
H
4.00
1.27 BASIC
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
83023AMI
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10
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
10
ICS83023I
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
Systems, Inc.
TABLE 7. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS83023AMI
83021AMI
8 lead SOIC
tube
-40°C to 85°C
ICS83023AMIT
83021AMI
8 lead SOIC
2500 tape & reel
-40°C to 85°C
ICS83023AMILF
83023AIL
8 lead "Lead-Free" SOIC
tube
-40°C to 85°C
ICS83023AMILFT
83023AIL
8 lead "Lead-Free" SOIC
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industiral applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83023AMI
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11
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
11
ICS83023I
Integrated
ICS83023I
Circuit
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Systems, Inc.
ICS83023I
DUAL, 1-TO-1TSD
DIFFERENTIAL-TO-LVCMOS TRANSLATOR /BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
A
7
11
T7
1
2
4
5
7
8
11
T7
11
T2
T4
B
B
83023AMI
Description of Change
Ordering Information Table - corrected Par t/Order Number for Tape & Reel to
read ICS83023AMIT from ICS83023AMI.
Features Section - added Additive Phase Jitter and Lead-Free bullets.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
AC Characteristics Table - added Additive Phase Jitter row.
Added Additive Phase Jitter Plot.
Added Recommendations for Unused Input and Output Pins.
Added Differential Clock Input Interface.
Ordering Information Table - added Lead-Free Par t Number and Note.
Update datasheet format.
Ordering information Table - added Lead-Free marking.
www.icst.com/products/hiperclocks.html
Date
09/09/02
12/12/05
1/18/08
REV. B JANUARY 18, 2006
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IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
12
ICS83023I
ICS83023I
ICS252
DUAL,
1-TO-1 DIFFERENTIAL-TO-LVCMOS
FIELD PROGRAMMABLE
DUAL OUTPUT SSTRANSLATOR/BUFFER
VERSACLOCK SYNTHESIZER
TSD
TSD
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