ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85301 is a high performance 2:1 Differential-to-LVPECL Multiplexer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85301 can also perform differential translation because the differential inputs accept LVPECL, CML as well as LVDS levels. The ICS85301 is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use on space constrained boards. • 2:1 LVPECL MUX ICS • One LVPECL output • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 3GHz • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLK0, nPCLK0 • Propagation delay: 490ps (maximum) • Part-to-part skew: 150ps (maximum) • Additive phase jitter, RMS: 0.009ps (typical) • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages PCLK0 nPCLK0 PCLK1 nPCLK1 0 Q nQ 1 VCC VEE VEE PIN ASSIGNMENT nc BLOCK DIAGRAM PCLK0 1 16 15 14 13 12 nPCLK0 2 11 Q PCLK1 3 10 nQ 9 VEE 7 nc V BB 8 VCC 6 VBB CLK_SEL 5 CLK_SEL nPCLK1 4 VEE ICS85301 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View PCLK0 nPCLK0 PCLK1 nPCLK1 VBB CLK_SEL nc VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc VEE VEE VCC VEE Q nQ VEE ICS85301 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View 85301AK www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 PCLK0 Input Type 2 nPCLK0 Input 3 PCLK1 Input 4 nPCLK1 Input Description Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. 5 VBB Output Bias voltage. 7, 16 nc Unused 6 CLK_SEL Input 8, 13 VCC Power No connect. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Positive supply pins. Pulldown 9, 12, 14, 15 VEE Power Negative supply pins. 10, 11 nQ, Q Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 1 pF RPULLUP Input Pullup Resistor 37 kΩ RPULLDOWN Input Pulldown Resistor 37 kΩ TABLE 3. CONTROL INPUT FUNCTION TABLE Input Input Selected CLK_SEL PCLK 0 PCLK0, nPCLK0 1 PCLK1, nPCLK1 85301AK www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 16 VFQFN 16 TSSOP 51.5°C/W (0 lfpm) 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 26 mA Units TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum 2.375 2.5 2.625 V 24 mA Maximum Units TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V ± 5% OR 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage CLK_SEL 2 VCC + 0.3 V VIL Input Low Voltage CLK_SEL -0.3 0.8 V IIH Input High Current CLK_SEL VCC = VIN = 3.465V or 2.625V IIL Input Low Current CLK_SEL VCC = 3.465V or 2.625V, VIN = 0V 150 -150 µA µA NOTE: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information, "Output Load Test Circuit". TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 150 µA PCLK0, nPCLK0, PCLK1, nPCLK1 PCLK0, PCLK1 VCC = 3.465V, VIN = 0V -10 µA nPCLK0, nPCLK1 VCC = 3.465V, VIN = 0V -150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCC = VIN = 3.465 150 1200 mV VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 3. 3 V VOH Output High Voltage; NOTE 3 2.01 2.535 V VOL Output Low Voltage; NOTE 3 1.24 1.845 V VBB Bias Voltage 1.695 2.145 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. . 85301AK www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Input High IIH Current Test Conditions Minimum Typical Maximum Units 150 µA PCLK0, nPCLK0, PCLK1, nPCLK1 PCLK0, PCLK1 VCC = 2.625V, VIN = 0V -10 µA nPCLK0, nPCLK1 VCC = 2.625V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage VCC = VIN = 2.625V 150 1200 mV VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 2.5 V VOH Output High Voltage; NOTE 3 1.25 1.705 V VOL Output Low Voltage; NOTE 3 0.48 1.005 V VBB Bias Voltage 0.935 1.305 V Maximum Units 3 GHz NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. . TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions tPD Propagation Delay; NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tsk(i) tR / tF Input Skew Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time odc Output Duty Cycle MUX_ISOL MUX Isolation tjit Minimum Typical 240 622MHz (Integration Range: 12KHz - 20MHz) 20% to 80% 490 ps 150 ps 25 ps 0.009 ps 100 200 ps 48 52 % f = 622MHz -55 dBm All parameters measured at f ≤ 1.7GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions tPD Propagation Delay; NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tsk(i) Input Skew Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time t j it tR / tF odc Output Duty Cycle MUX_ISOL MUX Isolation Minimum Typical 240 622MHz (Integration Range: 12KHz - 20MHz) 20% to 80% Units 3 GHz 490 ps 150 ps 25 ps 0.009 100 ps 200 47 f = 622MHz Maximum 53 -55 ps % dBm For notes, see Table 5A above. 85301AK www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter -20 3.3V or 2.5V @ 622MHz (12KHz to 20MHz) = 0.009ps typical -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 85301AK vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 2V 2V VCC Qx SCOPE VCC Qx SCOPE LVPECL LVPECL nQx nQx VEE VEE -0.5V ± 0.125V -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT VCC nQx PART 1 Q0x nPCLK0, nPCLK1 V Cross Points PP V nQy CMR PART 2 Qy nPCLK0, nPCLK1 tsk(pp) V EE PART-TO-PART SKEW DIFFERENTIAL INPUT LEVEL nQ nPCLK0, nPCLK1 Q t PW PCLK0, PCLK1 t PERIOD nQ odc = Q x 100% t PERIOD tPD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY 85301AK t PW www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER nPCLK0 80% 80% PCLK0 VOD Clock Outputs nPCLK1 20% 20% tR tF PCLK1 nQ Q tPD2 tPD1 tsk(i) tsk(i) = |tPD1 - tPD2| INPUT SKEW 85301AK OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 1B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level V BB generated from the device is connected to the negative input. VCC(or VDD) CLK_IN PCLK VBB nPCLK FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 85301AK www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER LVPECL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK R1 100 Zo = 50 Ohm nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER PCLK FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 VBB nPCLK HiPerClockS Input PC L K/n PC LK R5 100 - 200 R2 84 FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 50 R2 50 FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK PC L K/n PC L K R1 1K R2 120 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 85301AK VBB C2 FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 9 R2 1K REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched imped- 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 85301AK FIN 50Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 85301AK www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER APPLICATION SCHEMATIC EXAMPLE Figure 5 shows an example of ICS85401 application schematic. This device can accept different types of input signal. In this example, the input is driven by a LVDS driver. The decoupling capacitor should be located as close as possible to the power pin. 3.3V C1 0.1u 16 15 14 13 3.3V R2 100 Zo = 50 1 2 3 4 LVDS 3.3V CLK0 nCLK0 CLK1 nCLK1 U1 nc CLK_SEL nc VDD nc GND GND VDD Zo = 50 GND Q nQ GND 12 11 10 9 Zo = 50 + R1 Zo = 50 100 - ICS85401 5 6 7 8 Zo = 50 R3 100 Zo = 50 R4 1K 3.3V C2 0.1u LVDS FIGURE 5. ICS85401 APPLICATION SCHEMATIC EXAMPLE 85301AK www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85301. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85301 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 26mA = 90.09mW Power (outputs)MAX = 27.83mW/Loaded Output pair Total Power_MAX (3.465, with all outputs switching) = 90.09mW + 27.83mW = 117.92mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.118W * 51.5°C/W = 91.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6A. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION θJA at 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards TABLE 6B. THERMAL RESISTANCE θJA FOR FOR 51.5°C/W 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85301AK www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX – 1.005V ) = 1.005 For logic low, VOUT = V (V =V =V CC_MAX – 1.78V ) = 1.78V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1.005V)/50Ω] * 1.005V = 20mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.78V)/50Ω] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW 85301AK www.icst.com/products/hiperclocks.html 14 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA at 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards TABLE 7B. θJAVS. AIR FLOW TABLE FOR 51.5°C/W 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85301 is: 137 85301AK www.icst.com/products/hiperclocks.html 15 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER 16 LEAD VFQFN TABLE 8A. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 85301AK www.icst.com/products/hiperclocks.html 16 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER 16 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 85301AK www.icst.com/products/hiperclocks.html 17 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS85301AK 301A 16 Lead VFQFN Tray -40°C to 85°C ICS85301AKT 301A 16 Lead VFQFN 2500 Tape & Reel -40°C to 85°C ICS85301AKLF 01AL 16 Lead "Lead-Free" VFQFN Tray -40°C to 85°C ICS85301AKLFT 01AL 16 Lead "Lead-Free" VFQFN 2500 Tape & Reel -40°C to 85°C ICS85301AG 85301AG 16 Lead TSSOP tube -40°C to 85°C ICS85301AGT 85301AG 16 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS85301AGLF 85301AGL 16 Lead "Lead-Free" TSSOP Tube -40°C to 85°C ICS85301AGLFT 85301AGL 16 Lead "Lead-Free" TSSOP 2500 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85301AK www.icst.com/products/hiperclocks.html 18 REV. A JANUARY 16, 2006 ICS85301 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER REVISION HISTORY SHEET Rev Table Page A T9 17 Ordering Information Table - corrected count. 11/17/04 T9 Added 16 Lead TSSOP package throughout the datasheet. Added Recommendations for Unused Input Pins. Ordering Information Table - added lead-free marking to ICS85301AGLF par t number. 5/23/05 10 18 A A 85301AK Description of Change www.icst.com/products/hiperclocks.html 19 Date 1/16/06 REV. A JANUARY 16, 2006