Quad, 12-Bit, 170 MSPS/210 MSPS Serial Output 1.8 V ADC AD9639 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9639 VIN + A VIN – A BUF SHA BUF SHA BUF SHA BUF SHA DOUT + A PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC 12 VCM A VIN + B VIN – B VCM B VIN + C VIN – C VCM C VIN + D VIN – D DATA SERIALIZER, ENCODER, AND CML DRIVERS CHANNEL A DOUT – A DOUT + B CHANNEL B DOUT – B DOUT + C CHANNEL C DOUT – C DOUT + D CHANNEL D DOUT – D VCM D PGM3 REFERENCE PGM2 RBIAS DATA RATE MULTIPLIER SERIAL PORT TEMPOUT PGM1 PGM0 RESET APPLICATIONS SCLK Communication receivers Cable head end equipment/M-CMTS Broadband radios Wireless infrastructure transceivers Radar/military-aerospace subsystems Test equipment SDI/ SDIO SDO CSB CLK+ CLK– 07973-001 4 ADCs in one package JESD204 coded serial digital outputs On-chip temperature sensor −95 dB channel-to-channel crosstalk SNR: 65 dBFS with AIN = 85 MHz at 210 MSPS SFDR: 77 dBc with AIN = 85 MHz at 210 MSPS Excellent linearity DNL: ±0.28 LSB (typical) INL: ±0.7 LSB (typical) 780 MHz full power analog bandwidth Power dissipation: 325 mW per channel at 210 MSPS 1.25 V p-p input voltage range, adjustable up to 1.5 V p-p 1.8 V supply operation Clock duty cycle stabilizer Serial port interface features Power-down modes Digital test pattern enable Programmable header Programmable pin functions (PGMx, PDWN) Figure 1. GENERAL DESCRIPTION The AD9639 is a quad, 12-bit, 210 MSPS analog-to-digital converter (ADC) with an on-chip temperature sensor and a high speed serial interface. It is designed to support the digitizing of high frequency, wide dynamic range signals with an input bandwidth of up to 780 MHz. The output data is serialized and presented in packet format, consisting of channel-specific information, coded samples, and error code correction. The ADC requires a single 1.8 V power supply. The input clock can be driven differentially with a sine wave, LVPECL, CMOS, or LVDS. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. The on-chip reference eliminates the need for external decoupling and can be adjusted by means of SPI control. Various power-down and standby modes are supported. The ADC typically consumes 150 mW per channel with the digital link still in operation when standby operation is enabled. Rev. B Fabricated on an advanced CMOS process, the AD9639 is available in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Four ADCs are contained in a small, space-saving package. An on-chip PLL allows users to provide a single ADC sampling clock; the PLL distributes and multiplies up to produce the corresponding data rate clock. The JESD204 coded data rate supports up to 4.2 Gbps per channel. The AD9639 operates from a single 1.8 V power supply. Flexible synchronization schemes and programmable mode pins are available. An on-chip temperature sensor is included. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com AD9639 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Analog Input Considerations ................................................... 17 Functional Block Diagram .............................................................. 1 Clock Input Considerations ...................................................... 19 General Description ......................................................................... 1 Digital Outputs ........................................................................... 21 Product Highlights ........................................................................... 1 Serial Port Interface (SPI) .............................................................. 29 Revision History ............................................................................... 2 Hardware Interface..................................................................... 29 Specifications..................................................................................... 3 Memory Map .................................................................................. 31 AC Specifications.......................................................................... 4 Reading the Memory Map Table .............................................. 31 Digital Specifications ................................................................... 5 Reserved Locations .................................................................... 31 Switching Specifications .............................................................. 6 Default Values ............................................................................. 31 Timing Diagram ........................................................................... 7 Logic Levels ................................................................................. 31 Absolute Maximum Ratings............................................................ 8 Applications Information .............................................................. 35 Thermal Resistance ...................................................................... 8 Power and Ground Recommendations ................................... 35 ESD Caution .................................................................................. 8 Exposed Paddle Thermal Heat Slug Recommendations ...... 35 Pin Configuration and Function Descriptions ............................. 9 Outline Dimensions ....................................................................... 36 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 36 Equivalent Circuits ......................................................................... 15 REVISION HISTORY 7/13—Rev. A to Rev. B Change to Current Drive Parameter, Table 1 ................................ 3 Updated Outline Dimensions ....................................................... 36 2/10—Rev. 0 to Rev. A Changes to Differential Input Voltage Range Parameter, Table 1 ................................................................................................ 3 Changes to Table 7 ............................................................................ 9 Changes to Digital Outputs and Timing Section ....................... 25 Change to Addr. (Hex) 0x01, Table 15 ......................................... 32 5/09—Revision 0: Initial Version Rev. B | Page 2 of 36 Data Sheet AD9639 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ANALOG INPUTS Differential Input Voltage Range 2 Common-Mode Voltage Input Capacitance Input Resistance Analog Bandwidth, Full Power Voltage Common Mode (VCM x Pins) Voltage Output Current Drive TEMPERATURE SENSOR OUTPUT Voltage Output Current Drive POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation2 CROSSTALK Overrange Condition 3 Temp Full 25°C 25°C 25°C 25°C Full Full Min 12 −2.8 AD9639BCPZ-170 Typ Max Guaranteed −2 4 +1 0.9 ±0.28 ±0.45 ±12 12 +4.7 2.7 ±0.6 ±0.9 Min 12 −2.8 AD9639BCPZ-210 Typ Max Guaranteed −2 4 +1 0.9 ±0.28 ±0.7 Unit Bits ±12 12 +4.7 2.7 ±0.6 ±1.3 mV mV % FS % FS LSB LSB Full Full 25°C Full Full 1.0 1.25 1.4 2 4.3 780 1.5 1.0 1.25 1.4 2 4.3 780 1.5 V p-p V pF kΩ MHz Full Full 1.4 1.44 1 −1.12 739 50 1.5 1.4 1.44 1 −1.12 737 50 1.5 V mA mV/°C mV µA 1.7 1.7 1.8 1.8 535 98 1.139 1.9 1.9 570 105 1.215 1.7 1.7 1.8 1.8 610 111 1.298 1.9 1.9 650 120 1.386 V V mA mA W Full Full Full Full Full Full Full Full Full Full Full 3 152 −95 −90 3 173 −95 −90 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. AVDD/DRVDD, with link established. 3 Overrange condition is specified as 6 dB above the full-scale input range. 1 2 Rev. B | Page 3 of 36 mW mW dB dB AD9639 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 84.3 MHz fIN = 240.3 MHz SIGNAL-TO-(NOISE + DISTORTION) (SINAD) RATIO fIN = 84.3 MHz fIN = 240.3 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 84.3 MHz fIN = 240.3 MHz WORST HARMONIC (SECOND) fIN = 84.3 MHz fIN = 240.3 MHz WORST HARMONIC (THIRD) fIN = 84.3 MHz fIN = 240.3 MHz WORST OTHER (EXCLUDING SECOND OR THIRD) fIN = 84.3 MHz fIN = 240.3 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fIN1 = 140.2 MHz, fIN2 = 141.3 MHz, AIN1 and AIN2 = −7.0 dBFS fIN1 = 170.2 MHz, fIN2 = 171.3 MHz, AIN1 and AIN2 = −7.0 dBFS 2 1 2 AD9639BCPZ-170 Typ Max Min AD9639BCPZ-210 Typ Max Temp Min Unit Full 25°C 63.5 64.5 64.1 63.2 64.2 63.2 dB dB Full 25°C 63.3 64.4 63.9 62.8 63.9 63 dB dB Full 25°C 10.2 10.4 10.3 10.1 10.3 10.2 Bits Bits Full 25°C 87.5 82 78.6 86 80 77 dBc dBc Full 25°C 79 84 74 76 77 72.6 dBc dBc Full 25°C 96 88 86 90 88 83.7 dBc dBc 25°C 78 25°C 77 dBc 77 dBc See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. Tested at 170 MSPS and 210 MSPS. Rev. B | Page 4 of 36 Data Sheet AD9639 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Voltage Range Temp Internal Common-Mode Bias Input Common-Mode Voltage High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Differential Input Resistance Input Capacitance LOGIC INPUTS (PDWN, CSB, SDI/SDIO, SCLK, RESET, PGMx) 2 Logic 1 Voltage Full Full Full Full Full Full 25°C 25°C Logic 0 Voltage Full Full Full Full Min 0.2 AVDD − 0.3 1.1 1.2 0 −10 −10 16 AD9639BCPZ-170 Typ Max LVPECL/LVDS/CMOS 6 AVDD + 1.6 1.2 AVDD 3.6 0.8 +10 +10 20 24 4 0.8 × AVDD Min 0.2 AVDD − 0.3 1.1 1.2 0 −10 −10 16 AD9639BCPZ-210 Typ Max LVPECL/LVDS/CMOS 6 AVDD + 1.6 1.2 AVDD 3.6 0.8 +10 +10 20 24 4 V p-p V V V V µA µA kΩ pF V 0.8 × AVDD Full Unit 0.2 × AVDD 0.2 × AVDD V Logic 1 Input Current (CSB) Logic 0 Input Current (CSB) Logic 1 Input Current (PDWN, SDI/SDIO, SCLK, RESET, PGMx) Logic 0 Input Current (PDWN, SDI/SDIO, SCLK, RESET, PGMx) Input Resistance Input Capacitance LOGIC OUTPUT (SDO) Logic 1 Voltage Full Full Full 0 −60 55 0 −60 55 µA µA µA Full 0 0 µA 25°C 25°C 30 4 30 4 kΩ pF Full 1.2 Logic 0 Voltage DIGITAL OUTPUTS (DOUT + x, DOUT − x) Logic Compliance Differential Output Voltage Common-Mode Voltage Full 0 1 2 Full Full AVDD + 0.3 0.3 CML 0.8 DRVDD/2 1.2 AVDD + 0.3 0.3 0 CML 0.8 DRVDD/2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. Specified for 13 SDI/SDIO pins on the same SPI bus. Rev. B | Page 5 of 36 V V V V AD9639 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 4. Parameter 1 CLOCK Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) DATA OUTPUT PARAMETERS Data Output Period or UI (DOUT + x, DOUT − x) Data Output Duty Cycle Data Valid Time PLL Lock Time (tLOCK) Wake-Up Time (Standby) Wake-Up Time (Power-Down) 2 Pipeline Latency Data Rate per Channel (NRZ) Deterministic Jitter Random Jitter Channel-to-Channel Bit Skew Channel-to-Channel Packet Skew 3 Output Rise/Fall Time TERMINATION CHARACTERISTICS Differential Termination Resistance APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) OUT-OF-RANGE RECOVERY TIME Temp Min Full Full Full 100 2.65 2.65 AD9639BCPZ-170 Typ Max 170 2.9 2.9 Min 100 2.15 2.15 AD9639BCPZ-210 Typ Max 210 Unit 2.4 2.4 MSPS ns ns Full 1/(20 × fCLK) 1/(20 × fCLK) Seconds 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 50 0.8 4 250 50 50 0.8 4 250 50 3.4 10 6 0 ±1 50 4.2 10 6 0 ±1 50 % UI µs ns μs CLK cycles Gbps ps ps rms Seconds CLK cycles ps 25°C 100 100 Ω 25°C 25°C 25°C 1.2 0.2 1 1.2 0.2 1 ns ps rms CLK cycles 40 40 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. Receiver dependent. 3 See the Serial Data Frame section. 1 2 Rev. B | Page 6 of 36 Data Sheet AD9639 TIMING DIAGRAM SAMPLE N+1 N N – 40 ANALOG INPUT SIGNAL N – 39 N – 38 N – 37 SAMPLE RATE CLOCK ... ... SERIAL CODED SAMPLES: N – 40, N – 39, N – 38, N – 37 ... SERIAL DATA OUTPUT ... ... ... Figure 2. Timing Diagram Rev. B | Page 7 of 36 ... ... ... 07973-002 SAMPLE RATE CLOCK AD9639 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD DOUT + x/DOUT − x to DRGND SDO, SDI/SDIO, CLK±, VIN ± x, VCM x, TEMPOUT, RBIAS to AGND SCLK, CSB, PGMx, RESET, PDWN to AGND Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to DRVDD + 0.3 V −0.3 V to AVDD + 0.3 V The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the printed circuit board (PCB) increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Thermal Resistance Package Type 72-Lead LFCSP (CP-72-3) θJA 16.2 θJB 7.9 θJC 0.6 Unit °C/W −0.3 V to AVDD + 0.3 V Typical θJA, θJB, and θJC values are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces θJA. −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 8 of 36 Data Sheet AD9639 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 NC AVDD VCM C AVDD VIN – C VIN + C AVDD AVDD AVDD NC AVDD AVDD AVDD VIN + B VIN – B AVDD VCM B AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR PIN 0 = EPAD = AGND AD9639 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 NC PGM0 PGM1 PGM2 PGM3 NC AVDD VCM A AVDD VIN – A VIN + A AVDD AVDD AVDD CSB SCLK SDI/SDIO SDO NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE. 07973-004 NC AVDD AVDD RESET DRGND DRVDD DOUT + D DOUT – D DOUT + C DOUT – C DOUT + B DOUT – B DOUT + A DOUT – A DRVDD DRGND PDWN NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC TEMPOUT RBIAS AVDD NC NC AVDD VCM D AVDD VIN – D VIN + D AVDD AVDD AVDD AVDD CLK– CLK+ AVDD Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 0 Mnemonic AGND 1, 5, 6, 19, 36, 49, 54, 63, 72 2 3 4, 7, 9, 12, 13, 14, 15, 18, 20, 21, 41, 42, 43, 46, 48, 55, 57, 60, 61, 62, 64, 65, 66, 69, 71 8 10 11 16 17 22 23, 34 24, 33 25 26 27 28 29 30 NC Description Analog Ground (Exposed Paddle). The exposed paddle must be soldered to the ground plane. Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package. No Connection. TEMPOUT RBIAS AVDD Output Voltage to Monitor Temperature. External Resistor to Set the Internal ADC Core Bias Current. 1.8 V Analog Supply. VCM D VIN − D VIN + D CLK− CLK+ RESET DRGND DRVDD DOUT + D DOUT − D DOUT + C DOUT − C DOUT + B DOUT − B Common-Mode Output Voltage Reference. ADC D Analog Input Complement. ADC D Analog Input True. Clock Input Complement. Clock Input True. Reset Enable Pin. Resets the digital output timing. Digital Output Driver Ground. 1.8 V Digital Output Driver Supply. ADC D Digital Output True. ADC D Digital Output Complement. ADC C Digital Output True. ADC C Digital Output Complement. ADC B Digital Output True. ADC B Digital Output Complement. Rev. B | Page 9 of 36 AD9639 Pin No. 31 32 35 37 38 39 40 44 45 47 50, 51, 52, 53 56 58 59 67 68 70 Data Sheet Mnemonic DOUT + A DOUT − A PDWN SDO SDI/SDIO SCLK CSB VIN + A VIN − A VCM A PGM3, PGM2, PGM1, PGM0 VCM B VIN − B VIN + B VIN + C VIN − C VCM C Description ADC A Digital Output True. ADC A Digital Output Complement. Power-Down. Serial Data Output for 4-Wire SPI Interface. Serial Data Input/Serial Data Input/Output for 3-Wire SPI Interface. Serial Clock. Chip Select Bar. ADC A Analog Input True. ADC A Analog Input Complement. Common-Mode Output Voltage Reference. Optional Pins to be Programmed by Customer. Common-Mode Output Voltage Reference. ADC B Analog Input Complement. ADC B Analog Input True. ADC C Analog Input True. ADC C Analog Input Complement. Common-Mode Output Voltage Reference. Rev. B | Page 10 of 36 Data Sheet AD9639 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –1.0dBFS SNR = 64.88dB ENOB = 10.49 BITS SFDR = 77.57dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –60 –80 –100 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 –120 07973-059 –120 0 Figure 4. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 170 MSPS 20 40 60 FREQUENCY (MHz) 80 100 Figure 7. Single-Tone 32k FFT with fIN = 240.3 MHz, fSAMPLE = 210 MSPS 70 0 AIN = –1.0dBFS SNR = 63.95dB ENOB = 10.33 BITS SFDR = 78.90dBc –20 69 68 67 –40 SNR (dBFS) AMPLITUDE (dBFS) –40 07973-062 AMPLITUDE (dBFS) –20 AIN = –1.0dBFS SNR = 63.13dB ENOB = 10.19 BITS SFDR = 76.07dBc –60 66 65 64 170MSPS –80 210MSPS 63 62 –100 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 60 50 07973-060 –120 70 Figure 5. Single-Tone 32k FFT with fIN = 240.3 MHz, fSAMPLE = 170 MSPS 110 130 150 170 ENCODE (MSPS) 190 210 230 250 230 250 Figure 8. SNR vs. Encode, fIN = 84.3 MHz 90 0 AIN = –1.0dBFS SNR = 64.65dB ENOB = 10.44 BITS SFDR = 77.54dBc –20 88 86 84 –40 SFDR (dBFS) AMPLITUDE (dBFS) 90 07973-067 61 –60 –80 82 170MSPS 80 78 76 74 210MSPS –100 0 20 40 60 FREQUENCY (MHz) 80 100 70 50 07973-061 –120 Figure 6. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 210 MSPS 70 90 110 130 150 170 ENCODE (MSPS) 190 210 Figure 9. SFDR vs. Encode, fIN = 84.3 MHz Rev. B | Page 11 of 36 07973-068 72 AD9639 Data Sheet 0 100 AIN1 AND AIN2 = –7.0dBFS SFDR = 75.44dBc IMD2 = –78.34dBc IMD3 = –75.44dBc 90 SFDR (dBFS) –20 80 SNR/SFDR (dB) AMPLITUDE (dBFS) SNR (dBFS) 70 60 50 SFDR (dB) 40 30 –40 –60 –80 SNR (dB) 20 –100 –80 –70 –60 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 –120 07973-069 0 –90 0 Figure 10. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, fSAMPLE = 170 MSPS 40 60 FREQUENCY (MHz) 80 100 Figure 13. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz, fSAMPLE = 210 MSPS 0 100 90 SFDR (dBFS) 70 AIN1 AND AIN2 = –7.0dBFS SFDR = 76.88dBc IMD2 = –78.75dBc IMD3 = –78.68dBc –20 80 SNR (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dB) 20 07973-073 10 60 50 SFDR (dB) 40 30 –40 –60 –80 SNR (dB) 20 –100 –80 –70 –60 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 –120 07973-070 0 –90 0 Figure 11. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, fSAMPLE = 210 MSPS 40 60 FREQUENCY (MHz) 80 100 Figure 14. Two-Tone 32k FFT with fIN1 = 170.2 MHz and fIN2 = 171.3 MHz, fSAMPLE = 210 MSPS 0 95 AIN1 AND AIN2 = –7.0dBFS SFDR = 77.26dBc IMD2 = –86.55dBc IMD3 = –77.26dBc 90 85 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 20 07973-074 10 –40 –60 –80 80 SFDR (dB) 75 70 65 SNR (dB) 60 55 –100 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 45 07973-072 0 0 Figure 12. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz, fSAMPLE = 170 MSPS 50 100 150 200 250 300 350 AIN FREQUENCY (MHz) 400 450 500 07973-077 50 –120 Figure 15. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 170 MSPS Rev. B | Page 12 of 36 Data Sheet AD9639 95 0.8 90 0.6 85 SFDR (dB) 0.2 75 INL (LSB) AMPLITUDE (dBFS) 0.4 80 70 65 0 –0.2 SNR (dB) 60 –0.4 55 0 50 100 150 200 250 300 350 AIN FREQUENCY (MHz) 400 450 500 –0.8 07973-078 45 0 Figure 16. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 210 MSPS 500 1000 1500 2000 2500 CODE 3000 3500 4000 4500 07973-119 –0.6 50 Figure 19. INL, fIN = 9.7 MHz, fSAMPLE = 210 MSPS 70 0.4 69 0.2 68 0 67 –0.2 SNR, 210MSPS 66 DNL (LSB) SNR (dB) SNR, 170MSPS 65 64 –0.4 –0.6 63 –0.8 62 –20 0 20 40 TEMPERATURE (°C) 60 80 –1.2 07973-080 60 –40 0 Figure 17. SNR vs. Temperature, fIN = 84.3 MHz 500 1000 1500 2000 2500 CODE 3000 3500 4000 4500 07973-120 –1.0 61 Figure 20. DNL, fIN = 9.7 MHz, fSAMPLE = 210 MSPS 90 40,000 INPUT REFERRED NOISE: 0.72 LSB 35,000 85 30,000 NUMBER OF HITS SFDR, 210MSPS 75 SFDR, 170MSPS 70 25,000 20,000 15,000 10,000 65 –20 0 20 40 TEMPERATURE (°C) 60 80 0 N–3 N–2 N–1 N N+1 N+2 N+3 MORE BIN Figure 18. SFDR vs. Temperature, fIN = 84.3 MHz Figure 21. Input-Referred Noise Histogram, fSAMPLE = 170 MSPS Rev. B | Page 13 of 36 07973-106 60 –40 5000 07973-081 SFDR (dB) 80 AD9639 Data Sheet 40,000 90 INPUT REFERRED NOISE: 0.70 LSB 85 35,000 80 75 SNR/SFDR (dB) NUMBER OF HITS 30,000 25,000 20,000 15,000 SFDR 70 65 SNR 60 55 10,000 50 5000 N–2 N–1 N N+1 N+2 N+3 MORE BIN 40 1.0 07973-107 N–3 Figure 22. Input-Referred Noise Histogram, fSAMPLE = 210 MSPS 1.8 Figure 24. SNR/SFDR vs. Analog Input Common-Mode Voltage, fIN = 84.3 MHz, fSAMPLE = 210 MSPS 0 0 –20 AMPLITUDE (dBFS) –5 –40 –60 –80 –10 –15 –120 0 20 40 60 80 FREQUENCY (Hz) 100 Figure 23. Noise Power Ratio (NPR), fSAMPLE = 210 MSPS 120 –25 1M 10M 100M AIN FREQUENCY (Hz) 1G 07973-125 –20 –100 07973-123 AMPLITUDE (dBFS) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 ANALOG INPUT COMMON-MODE VOLTAGE (V) 07973-124 45 0 Figure 25. Full-Power Bandwidth Amplitude vs. AIN Frequency, fSAMPLE = 210 MSPS Rev. B | Page 14 of 36 Data Sheet AD9639 EQUIVALENT CIRCUITS AVDD AVDD AVDD 1.2V 10kΩ CLK+ 10kΩ 250Ω CLK– SDI/SDIO 07973-005 07973-009 30kΩ Figure 26. CLK± Inputs Figure 30. Equivalent SDI/SDIO Input Circuit AVDD VIN + x AVDD BUF 2kΩ AVDD AVDD BUF ~1.4V 2kΩ TEMPOUT VIN – x 07973-010 07973-006 BUF Figure 27. Analog Inputs Figure 31. Equivalent TEMPOUT Output Circuit 100Ω 175Ω RBIAS 175Ω 30kΩ 07973-011 07973-007 SCLK, PDWN, PGMx, RESET Figure 32. Equivalent RBIAS Input/Output Circuit Figure 28. Equivalent SCLK, RESET, PDWN, PGMx Input Circuit AVDD VCM x 26kΩ 175Ω 1kΩ 07973-008 07973-012 CSB Figure 33. Equivalent VCM x Output Circuit Figure 29. Equivalent CSB Input Circuit Rev. B | Page 15 of 36 AD9639 Data Sheet AVDD SDO DRVDD RTERM VCM DOUT + x DOUT – x 345Ω 4mA 07973-089 4mA AVDD 4mA 07973-030 4mA Figure 35. Equivalent SDO Output Circuit Figure 34. Equivalent Digital Output Circuit Rev. B | Page 16 of 36 Data Sheet AD9639 THEORY OF OPERATION with each input can help to reduce the peak transient current injected from the output stage of the driving source. The AD9639 architecture consists of a differential input buffer and a front-end sample-and-hold amplifier (SHA) followed by a pipelined switched-capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. The use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-827 Application Note and the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, Number 2, April 2005) for more information on this subject. In general, the precise values depend on the application. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended mode. The output of the pipeline ADC is put into its final serial format by the data serializer, encoder, and CML drivers block. The data rate multiplier creates the clock used to output the high speed serial data at the CML outputs. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9639, the default input span is 1.25 V p-p. To configure the ADC for a different input span, see the VREF register (Address 0x18). For the best performance, an input span of 1.25 V p-p or greater should be used (see Table 15 for details). ANALOG INPUT CONSIDERATIONS Differential Input Configurations The analog input to the AD9639 is a differential buffer. This input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades if the analog input is driven with a single-ended signal. The AD9639 can be driven actively or passively; in either case, optimum performance is achieved by driving the analog input differentially. For example, using the ADA4937 differential amplifier to drive the AD9639 provides excellent performance and a flexible interface to the ADC for baseband and second Nyquist (~100 MHz IF) applications (see Figure 36 and Figure 37). In either application, use 1% resistors for good gain matching. Note that the dc-coupled configuration shows some degradation in spurious performance. For more information, consult the ADA4937 data sheet. For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. A small resistor in series 3.3V 1.8V 1.8V AVDD DRVDD 205Ω 200Ω 62Ω SIGNAL GENERATOR 10kΩ 10kΩ 0.1µF 1.65V VOCM 24Ω ADA4937 C R –VS 24Ω 27Ω VIN + x OPTIONAL C G = UNITY 200Ω 33Ω +VS 0.1µF 33Ω AD9639 ADC INPUT IMPEDANCE VIN – x 07973-090 1.25V p-p 0.1µF 205Ω Figure 36. Differential Amplifier Configuration for AC-Coupled Baseband Applications 3.3V 205Ω 62Ω 0.1µF 33Ω VIN + x 1.8V AVDD DRVDD +VS VOCM 200Ω ADA4937 G = UNITY AD9639 OPTIONAL C R –VS 24Ω 27Ω 33Ω VIN – x C ADC INPUT IMPEDANCE VCM x 205Ω 1.4V Figure 37. Differential Amplifier Configuration for DC-Coupled Baseband Applications Rev. B | Page 17 of 36 07973-091 SIGNAL GENERATOR 24Ω 200Ω 1.25V p-p 1.8V AD9639 Data Sheet For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration to achieve the true performance of the AD9639 (see Figure 38 to Figure 40). 1.25V p-p BALUN 1:1 Z 66Ω 0.1µF 0.1μF *CDIFF VIN – x 07973-013 L 33Ω VIN + x 65Ω 07973-017 Single-Ended Input Configuration AGND C ADT1-1WT 1:1 Z RATIO 250Ω L 2.2pF 33Ω ADC AD9639 A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance can degrade due to input common-mode swing mismatch. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched to achieve the best possible performance. A full-scale input of 1.25 V p-p can be applied to the VIN + x pin of the AD9639 while the VIN − x pin is terminated. Figure 42 shows a typical single-ended input configuration. VIN – x C 07973-014 0.1μF 33Ω 1.25V p-p Figure 39. Differential Transformer-Coupled Configuration for Wideband IF Applications 49.9Ω 1.25V p-p 0.1μF VIN + x 0.1µF *CDIFF 25Ω ADT1-1WT 1:1 Z RATIO VIN – x Figure 41. Differential Balun-Coupled Configuration for Wideband IF Applications ADC AD9639 Figure 38. Differential Transformer-Coupled Configuration for Baseband Applications L 33Ω ADC AD9639 BALUN 1:1 Z VIN + x *CDIFF IS OPTIONAL 1.25V p-p 4.7pF C 33Ω 0.1μF VIN + x 0.1µF 33Ω ADC AD9639 VIN – x C 33Ω VIN + x L 33Ω *CDIFF IS OPTIONAL ADC AD9639 Figure 42. Single-Ended Input Configuration VIN – x 0.1μF 07973-015 250Ω Figure 40. Differential Transformer-Coupled Configuration for Narrow-Band IF Applications Rev. B | Page 18 of 36 07973-016 50Ω 1.25V p-p 0.1µF 33Ω 33Ω 0.1µF Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. ADT1-1WT 1:1 Z RATIO 0.1µF Data Sheet AD9639 0.1µF CLK+ Figure 43 shows a preferred method for clocking the AD9639. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-toback Schottky diodes across the secondary transformer limit clock excursions into the AD9639 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD9639, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. CLK+ XFMR 50Ω CLK 50Ω* CMOS DRIVER 0.1µF Figure 46. Single-Ended 1.8 V CMOS Sample Clock CMOS DRIVER CLK 07973-018 0.1µF CLK+ 100Ω PECL DRIVER 0.1µF CLK– 0.1µF CLK– CLK 240Ω 50Ω* ADC AD9639 240Ω 07973-019 50Ω* 0.1µF CLK *50Ω RESISTORS ARE OPTIONAL. Figure 44. Differential PECL Sample Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ AD9516/AD9518 0.1µF CLK+ 0.1µF CLK+ CLK 0.1µF CLK– LVDS DRIVER 100Ω 0.1µF CLK ADC AD9639 CLK– 50Ω* *50Ω RESISTORS ARE OPTIONAL. 07973-020 50Ω* ADC AD9639 *50Ω RESISTOR IS OPTIONAL. Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 44. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9518 family of clock drivers offers excellent jitter performance. 0.1µF 0.1µF CLK+ CLK– Figure 43. Transformer-Coupled Differential Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ AD9516/AD9518 OPTIONAL 100Ω 0.1µF CLK– CLK+ AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ AD9516/AD9518 CLK 50Ω* ADC AD9639 SCHOTTKY DIODES: HSMS-2812 39kΩ *50Ω RESISTOR IS OPTIONAL. CLK+ 0.1µF ADC AD9639 CLK– 0.1µF CLK+ 0.1µF CLK+ CLK 0.1µF 0.1µF OPTIONAL 100Ω 0.1µF ADT1-1WT, 1:1Z 0.1µF AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ AD9516/AD9518 07973-021 For optimum performance, the AD9639 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally to 1.2 V and require no additional biasing. CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V and, therefore, offers several selections for the drive logic voltage. Figure 45. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 46). Although the 07973-022 CLOCK INPUT CONSIDERATIONS Figure 47. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9639 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9639. When the DCS is on (default), noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance may be affected when operated in this mode. See the Memory Map section for more details on using this feature. Jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 50 MHz nominal. It is not recommended that this ADC clock be dynamic in nature. Moving the clock around dynamically requires long wait times for the back end serial capture to retime and resynchronize to the receiving logic. This long time constant far exceeds the time that it takes for the DCS and the PLL to lock and stabilize. Only in rare applications would it be necessary to disable the DCS circuitry in the clock register (see Address 0x09 in Table 15). Keeping the DCS circuit enabled is recommended to maximize ac performance. Rev. B | Page 19 of 36 AD9639 Data Sheet Clock Jitter Considerations Power Dissipation High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated as follows: As shown in Figure 49 and Figure 50, the power dissipated by the AD9639 is proportional to its clock rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the digital output drivers. Refer to the AN-501 Application Note, the AN-756 Application Note, and the Analog Dialogue article, “Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective” (Volume 42, Number 2, February 2008) for in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). 0.7 1.6 IAVDD 0.5 1.2 POWER 1.0 0.4 0.8 0.3 0.6 0.2 0.4 IDRVDD 0.2 0 50 70 90 0.1 110 130 ENCODE (MSPS) 150 2.0 120 1.8 110 1.6 16 BITS 1.4 90 14 BITS 1.2 POWER (W) 100 12 BITS 70 0 170 Figure 49. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 170 MSPS RMS CLOCK JITTER REQUIREMENT 80 CURRENT (mA) 0.6 1.4 0.8 0.7 IAVDD 0.6 0.5 POWER 1.0 0.4 0.8 0.3 10 BITS 60 0.6 0.125 ps 0.25 ps 0.5 ps 1.0 ps 2.0 ps 40 0.2 0.4 IDRVDD 30 1 10 100 ANALOG INPUT FREQUENCY (MHz) Figure 48. Ideal SNR vs. Input Frequency and Jitter 0.1 0.2 1000 0 50 70 90 110 130 150 ENCODE (MSPS) 170 190 0 210 07973-057 50 07973-024 SNR (dB) 130 0.8 1.8 07973-056 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9639. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock during the last step. 2.0 CURRENT (mA) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 48). POWER (W) SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) Figure 50. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 210 MSPS Rev. B | Page 20 of 36 Data Sheet AD9639 The two resulting octets are optionally scrambled and encoded into their corresponding 10-bit code. The scrambling function is controlled by the JESD204 register, Address 0x033[0]. Figure 51 shows how the 12-bit data is taken from the ADC, the tail bits are added, the two octets are scrambled, and the octets are encoded into two 10-bit symbols. Figure 52 illustrates the data format. DIGITAL OUTPUTS Serial Data Frame The AD9639 digital output complies with the JEDEC Standard No. 204 (JESD204), which describes a serial interface for data converters. JESD204 uses 8B/10B encoding as well as optional scrambling. K28.5 and K28.7 comma symbols are used for frame synchronization. The receiver is required to lock onto the serial data stream and recover the clock with the use of a PLL. (Refer to IEEE Std 802.3-2002, Section 3, for a complete 8B/10B and comma symbol description.) The scrambler uses a self-synchronizing polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver should be a self-synchronizing version of the scrambler polynomial. A 16-bit parallel implementation is shown in Figure 54. The 8B/10B encoding works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. In the AD9639, the 12-bit converter word is broken into two octets. Bit 11 through Bit 4 are in the first octet. The second octet contains Bit 3 through Bit 0 and four tail bits. The MSB of the tail bits can also be used to indicate an out-of-range condition. The tail bits are configured using the JESD204 register, Address 0x033[3]. FRAME ASSEMBLER (ADD TAIL BITS) SCRAMBLER 1 + x14 + x15 8B/10B ENCODER TO RECEIVER 07973-201 DATA FROM ADC Refer to JEDEC Standard No. 204-April 2006, Section 5.1, for complete transport layer and data format details and Section 5.2 for a complete explanation of scrambling and descrambling. Figure 51. ADC Data Output Path WORD 0[11:4] SYMBOL 0[9:0] WORD 0[3:0],TAIL BITS[3:0] SYMBOL 1[9:0] WORD 1[11:4] SYMBOL 2[9:0] WORD 1[3:0], TAIL BITS[3:0] SYMBOL 3[9:0] FRAME 0 TIME 07973-200 FRAME 1 FROM TRANSMITTER 8B/10B DECODER DESCRAMBLER 1 + x14 + x15 FRAME ALIGNMENT Figure 53. Required Receiver Data Path Rev. B | Page 21 of 36 DATA OUT 07973-202 Figure 52. 12-Bit Data Transmission with Tail Bits AD9639 Data Sheet S15 LSB D S31 Q CLK D31 LSB S14 D S30 Q CLK D30 S13 D S29 Q CLK SECOND OCTET OF FRAME S15 D29 S12 D S28 Q CLK S14 D28 S11 D S27 Q CLK S13 D27 S10 D S26 Q CLK S12 D26 S9 D S25 Q CLK S11 D25 S8 D S24 MSB Q CLK S10 D24 S7 LSB D S23 CLK = FRAME CLK Q CLK S9 D23 S6 D S22 Q CLK S8 D22 S5 D S21 Q CLK S7 D21 FIRST OCTET OF FRAME S4 D S20 Q CLK S6 D20 S3 D S19 Q CLK S5 D19 S2 D S18 Q CLK S4 D18 S1 D S17 Q CLK S3 S16 S2 D16 S1 Figure 54. Parallel Descrambler Required in Receiver Rev. B | Page 22 of 36 MSB 07973-203 MSB D17 Data Sheet AD9639 Initial Synchronization The serial interface must synchronize to the frame boundaries before data can be properly decoded. The JESD204 standard has a synchronization routine to identify the frame boundary. The PGMx pins are used as SYNC pins by default. When the SYNC pin is taken low for at least two clock cycles, the AD9639 enters the synchronization mode. The AD9639 transmits the K28.5 comma symbol until the receiver can identify the frame boundary. The receiver should then deassert the sync signal (take SYNC high) and the ADC begins transmitting real data. The first nonK28.5 symbol is the MSB symbol of the 12-bit data. ICOUNTER = ‘0’; VCOUNTER = ‘0’; SYNC_REQUEST = ‘1’; IF /K28.5/ AND /VALID/ THEN KCOUNTER = KCOUNTER + ‘1’; ELSE KCOUNTER = ‘0’; END IF; To minimize skew and time misalignment between each channel of the digital outputs, the following actions should be taken to ensure that each channel data frame is within ±1 clock cycle of the sample clock. For some receiver logic, this is not required. 1. 2. 3. Full power-down through external PDWN pin. Chip reset via external RESET pin. Power-up by releasing external PDWN pin. RESET INIT KCOUNTER < 4 ICOUNTER = 3 SYNC_REQUEST = ‘0’; KCOUNTER = ‘0’; IF /INVALID/ THEN ICOUNTER = ICOUNTER + ‘1’; VCOUNTER = ‘0’; ELSE IF /VALID/ THEN VCOUNTER = VCOUNTER + ‘1’; END IF; KCOUNTER = 4 ICOUNTER = ‘0’; VCOUNTER = ‘0’; VCOUNTER = 4 CHECK DATA /VALID/ VCOUNTER < 4 AND ICOUNTER < 3 07973-204 /INVALID/ Figure 55. Receiver State Machine Table 8. Variables Used in Receiver State Machine Variable ICOUNTER /INVALID/ /K28.5/ KCOUNTER SYNC_REQUEST /VALID/ VCOUNTER Description Counter used in the CHECK phase to count the number of invalid symbols. Asserted by receiver to indicate that the current symbol is an invalid symbol given the current running disparity. Asserted when the current symbol corresponds to the K28.5 control character. Counter used in the INIT phase to count the number of valid K28.5 symbols. Asserted by receiver when loss of code group synchronization is detected. Asserted by receiver to indicate that the current symbol is a valid symbol given the current running disparity. Counter used in the CHECK phase to count the number of successive valid symbols. Rev. B | Page 23 of 36 AD9639 Data Sheet Continuous Synchronization Continuous synchronization is part of the JESD204 specification. The 12-bit word requires two octets to transmit all the data. The two octets (MSB and LSB) are called a frame. When scrambling is disabled and the LSB octets of two consecutive frames are the same, the second LSB octet is replaced by a K28.7 comma symbol. The receiver is responsible for replacing the K28.7 comma symbol with the LSB octet of the previous frame. When scrambling is enabled, any D28.7 symbols found in the LSB octet of a frame are replaced with K28.7 comma symbols. The receiver is responsible for replacing the K28.7 comma symbols with D28.7 symbols when in this mode. By looking for K28.7 symbols, the receiver can ensure that it is still synchronized to the frame boundary. 07973-205 IF /K28.7/ /REPLACE_K28.7/ IF (OCOUNTER == PREVIOUS_POSITION) AND /VALID/ /RESET_OCTET_COUNTER/ END IF; IF /VALID/ | (OCOUNTER == N-1) PREVIOUS_POSITION = OCOUNTER END IF; END IF; Figure 56. Pseudocode for Data Dependent Frame Synchronization in Receiver Table 9. Variables and Functions in Data Dependent Frame Synchronization Variable N /K28.7/ OCOUNTER PREVIOUS_POSITION /REPLACE_K28.7/ /RESET_OCTET_COUNTER/ /VALID/ Description Number of octets in frame (octet indexing starts from 0). Asserted when the current symbol corresponds to the K28.7 control character. Counter used to mark the position of the current octet in the frame. Variable that stores the position in the frame of a K28.7 symbol. Replace K28.7 at the decoder output as follows. When scrambling is disabled, replace K28.7 with the LSB octet that was decoded at the same position in the previous frame; when scrambling is enabled, replace K28.7 at the decoder output with D28.7. Reset octet counter to 0 at reception of next octet. Asserted by receiver to indicate that the current symbol is a valid symbol given the current running disparity. Rev. B | Page 24 of 36 Data Sheet AD9639 A 100 Ω differential termination resistor should be placed at each receiver input to result in a nominal 400 mV peak-to-peak swing at the receiver. Alternatively, single-ended 50 Ω termination can be used. When single-ended termination is used, the termination voltage should be DRVDD/2; otherwise, ac coupling capacitors can be used to terminate to any single-ended voltage. The AD9639 digital outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close to the receiver logic as possible. The common mode of the digital output automatically biases itself to half the supply of DRVDD if dc-coupled connecting is used. For receiver logic that is not within the bounds of the DRVDD supply, an ac-coupled connection should be used. Simply place a 0.1 μF capacitor on each output pin and derive a 100 Ω differential termination close to the receiver side. Rev. B | Page 25 of 36 100Ω DIFFERENTIAL TRACE PAIR DRVDD DOUT + x RECEIVER 100Ω DOUT – x VCM = DRVDD/2 OUTPUT SWING = 400mV p-p 07973-092 The AD9639 has differential digital outputs that power up by default. The driver current is derived on chip and sets the output current at each output equal to a nominal 4 mA. Each output presents a 100 Ω dynamic internal termination to reduce unwanted reflections. If there is no far-end receiver termination or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 6 inches and that the differential output traces be close together and at equal lengths. Figure 57. DC-Coupled Digital Output Termination Example VRXCM DRVDD 100Ω DIFFERENTIAL TRACE PAIR 0.1µF DOUT + x 100Ω DOUT – x OR RECEIVER 0.1µF OUTPUT SWING = 400mV p-p VCM = Rx VCM Figure 58. AC-Coupled Digital Output Termination Example 07973-093 Digital Outputs and Timing AD9639 Data Sheet HEIGHT1: EYE DIAGRAM 600 TIE1: HISTOGRAM (y1) –375.023m (y2) +409.847m (∆y) +784.671m 600 1 100 2 + + 3 + 10–2 500 400 TJ@BERI: BATHTUB –200 200 –400 –600 300 10–10 100 EYE: ALL BITS OFFSET: 0.015 ULS: 5000: 40044, TOTAL: 12000: 80091 –200 –100 0 100 TIME (ps) 0 200 10–8 10–12 –30 –10 10 TIME (ps) 10–14 –0.5 30 0 ULS 07973-094 0 BER 10–6 HITS VOLTAGE (mV) 10–4 400 200 0.5 Figure 59. Digital Outputs Data Eye with Trace Lengths Less Than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver HEIGHT1: EYE DIAGRAM 600 TIE1: HISTOGRAM (y1) –402.016m (y2) +398.373m (∆y) +800.389m 300 1 100 2 + + 3 + 10–2 250 400 TJ@BERI: BATHTUB –200 100 –400 –600 10–6 150 10–10 50 EYE: ALL BITS OFFSET: 0.015 ULS: 5000: 40044, TOTAL 8000: 40044 –200 –100 0 100 TIME (ps) 200 0 10–8 10–12 –50 0 TIME (ps) 50 10–14 –0.5 0 ULS 0.5 07973-095 0 BER HITS VOLTAGE (mV) 10–4 200 200 Figure 60. Digital Outputs Data Eye with Trace Lengths Greater Than 12 Inches on Standard FR-4, External 100 Ω Terminations at Receiver Figure 59 shows an example of the digital output (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 6 inches on standard FR-4 material. Figure 60 shows an example of trace lengths exceeding 12 inches on standard FR-4 material. Note that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user’s responsibility to determine whether the waveforms meet the timing budget of the design when the trace lengths exceed 6 inches. Additional SPI options allow the user to further increase the output driver voltage swing of all four outputs to drive longer trace lengths (see Address 0x15 in Table 15). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. See the Memory Map section for more details. The format of the output data is offset binary by default. Table 10 provides an example of this output coding format. To change the output data format to twos complement or gray code, see the Memory Map section (Address 0x14 in Table 15). Table 10. Digital Output Coding Code 4095 2048 2047 0 (VIN + x) − (VIN − x), Input Span = 1.25 V p-p (V) +0.625 0.00 −0.000305 −0.625 Digital Output Offset Binary ([D11:D0]) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 The lowest typical clock rate is 100 MSPS. For clock rates slower than 100 MSPS, the user can set Bit 3 to 0 in the serial control register (Address 0x21 in Table 15). This option allows the user to adjust the PLL loop bandwidth to use clock rates as low as 50 MSPS. Rev. B | Page 26 of 36 Data Sheet AD9639 Setting Bit 2 in the output mode register (Address 0x14) allows the user to invert the digital outputs from their nominal state. This is not to be confused with inverting the serial stream to an LSB first mode. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this order can be inverted so that the LSB is first in the data output serial stream. There are eight digital output test pattern options available that can be initiated through the SPI (see Table 12 for the output bit sequencing options). This feature is useful when validating receiver capture and timing. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern selected. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the user pattern registers (Address 0x19 through Address 0x20). The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 (511) bits. A description of the PN sequence short and how it is generated can be found in Section 5.1 of the ITU-T O.150 (05/96) recommendation. The only difference is that the starting value must be a specific value instead of all 1s (see Table 11 for the initial values). The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 (8,388,607) bits. A description of the PN sequence long and how it is generated can be found in Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 11 for the initial values) and that the AD9639 inverts the bit stream with relation to the ITU-T standard. Table 11. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x0DF 0x29B80A First Three Output Samples (MSB First) 0xDF9, 0x353, 0x301 0x591, 0xFD7, 0x0A3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Table 12. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard PN sequence long 1 PN sequence short1 One-/zero-word toggle Digital Output Word 1 N/A 1000 0000 0000 1111 1111 1111 0000 0000 0000 1010 1010 1010 N/A N/A 1111 1111 1111 Digital Output Word 2 N/A Same Same Same 0101 0101 0101 N/A N/A 0000 0000 0000 Subject to Data Format Select Yes Yes Yes Yes No Yes Yes No All test mode options except PN sequence long and PN sequence short can support 8- to 14-bit word lengths to verify data capture to the receiver. Rev. B | Page 27 of 36 AD9639 Data Sheet TEMPOUT Pin The TEMPOUT pin can be used as a coarse temperature sensor to monitor the internal die temperature of the device. This pin typically has a 737 mV output with a clock rate of 210 MSPS and a negative going temperature coefficient of −1.12 mV/°C. The voltage response of this pin is characterized in Figure 61. SDO Pin 0.79 The SDO pin is for use in applications that require a 4-wire SPI mode operation. For normal operation, it should be tied low to AGND through a 10 kΩ resistor. Alternatively, the device pin can be left open, and the 345 Ω internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. 0.77 SDI/SDIO Pin 0.85 0.83 TEMPOUT PIN VOLTAGE (V) the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset. The AD9639 returns to normal operating mode when the PDWN pin is pulled low. This pin is only 1.8 V tolerant. 0.81 The SDI/SDIO pin is for use in applications that require either a 4- or 3-wire SPI mode operation. For normal operation, it should be tied low to AGND through a 10 kΩ resistor. Alternatively, the device pin can be left open, and the 30 kΩ internal pulldown resistor pulls this pin low. This pin is only 1.8 V tolerant. 0.75 0.73 0.71 0.69 0.67 SCLK Pin 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 07973-055 0.65 –40 –30 –20 –10 For normal operation, the SCLK pin should be tied to AGND through a 10 kΩ resistor. Alternatively, the device pin can be left open, and the 30 kΩ internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. Figure 61. TEMPOUT Pin Voltage vs. Temperature RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 kΩ) between ground and the RBIAS pin. The resistor current is derived on chip and sets the AVDD current of the ADC to a nominal 610 mA at 210 MSPS. Therefore, it is imperative that a 1% or less tolerance on this resistor be used to achieve consistent performance. VCM x Pins The common-mode output pins can be enabled through the SPI to provide an external reference bias voltage of 1.4 V for driving the VIN + x/VIN − x analog inputs. The VCM x pins may be required when connecting external devices, such as an amplifier or transformer, to interface to the analog inputs. RESET Pin The RESET pin resets the datapath and sets all SPI registers to their default values. To use this pin, the user must resynchronize the digital outputs. This pin is only 1.8 V tolerant. PDWN Pin When asserted high, the PDWN pin turns off all ADC channels, including the output drivers. This function can be changed to a standby function (see Address 0x08 in Table 15). This feature allows the user to place all channels into standby mode. The output drivers transmit pseudorandom data until the outputs are disabled using the output mode register (Address 0x14). CSB Pin For normal operation, the CSB pin should be tied high to AVDD through a 10 kΩ resistor. Alternatively, the device pin can be left open, and the 26 kΩ internal pull-up resistor pulls this pin high. Tying the CSB pin to AVDD causes all information on the SCLK and SDI/SDIO pins to be ignored. Tying the CSB pin low causes all information on the SDO and SDI/SDIO pins to be written to the device. This feature allows the user to reduce the number of traces to the device if necessary. This pin is only 1.8 V tolerant. PGMx Pins All PGMx pins are automatically initialized as synchronization pins by default. These pins are used to lock the FPGA timing and data capture during initial startup. These pins are respective to each channel (PGM3 = Channel A, PGM2 = Channel B, and so on). The sync (PGMx) pin should be pulled high until this pin receives a low signal input from the receiver, during which time the ADC outputs K28.5 comma symbols to indicate the frame boundary. When the receiver finds the frame boundary, the sync identification is deasserted low and the ADC outputs the valid data on the next packet boundary. When steady state operation for the device is achieved, these pins can be assigned as a standby option using the PGM mode register (Address 0x53 in Table 15). All other PGMx pins become global synchronization pins. This pin is only 1.8 V tolerant. When the PDWN pin is asserted high, the AD9639 is placed into power-down mode, shutting down the reference, reference buffer, PLL, and biasing networks. In this state, the ADC typically dissipates 3 mW. If any of the SPI features are changed before Rev. B | Page 28 of 36 Data Sheet AD9639 SERIAL PORT INTERFACE (SPI) The AD9639 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. The SPI can provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Four pins define the SPI: SCLK, SDI/SDIO, SDO, and CSB (see Table 13). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDI/SDIO pin is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The SDO pin is used in 4-wire mode to read back data from the part. The CSB pin is an active low control that enables or disables the read and write cycles. Table 13. Serial Port Pins Pin SCLK SDI/SDIO SDO CSB Function Serial clock. Serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. Dual-purpose pin that typically serves as an input or an output, depending on the SPI wire mode, the instruction sent, and the relative position in the timing frame. Serial data output. Used only in 4-wire SPI mode. When set, the SDO pin becomes active. When cleared, the SDO pin remains in three-state and all read data is routed to the SDI/SDIO pin. Chip select bar (active low). This control gates the read and write cycles. The falling edge of CSB in conjunction with the rising edge of SCLK determines the start of the framing sequence. During the instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 63 and Table 14. During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDI/SDIO to execute instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port configuration influences how the AD9639 operates. For applications that do not require a control port, the CSB line can be tied high. This places the SDI/SDIO pin into its secondary mode, as defined in the SDI/SDIO Pin section. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDI/SDIO are the only pins required for communication. Although the device is synchronized during power-up, the user should ensure that the serial port remains synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDI/SDIO pin to change from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first or LSB first mode. MSB first mode is the default at power-up and can be changed by adjusting the configuration register (Address 0x00). For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the user’s programming device and the serial port of the AD9639. The SCLK and CSB pins function as inputs when using the SPI. The SDI/SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDI/SDIO pins share a common connection, ensure that proper VOH levels are met. Assuming the same load for each AD9639, Figure 62 shows the number of SDI/SDIO pins that can be connected together and the resulting VOH level. This interface is flexible enough to be controlled by either serial PROMs or PIC microcontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). For users who wish to operate the ADC without using the SPI, remove any connections from the CSB, SCLK, SDO, and SDI/SDIO pins. By disconnecting these pins from the control bus, the ADC can function in its most basic operation. Each of these pins has an internal termination that floats to its respective level. Rev. B | Page 29 of 36 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDI/SDIO PINS CONNECTED TOGETHER 07973-104 Data Sheet VOH (V) AD9639 Figure 62. SDI/SDIO Pin Loading tDS tS tHIGH tCLK tH tDH tLOW CSB DON’T CARE SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 07973-028 SDI/ SDIO Figure 63. Serial Timing Details Table 14. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHIGH tLOW tEN_SDI/SDIO Timing (ns min) 5 2 40 5 2 16 16 10 tDIS_SDI/SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDI/SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 63) Minimum time for the SDI/SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 63) Rev. B | Page 30 of 36 Data Sheet AD9639 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 15) has eight bit locations. The memory map is divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02), the device index and transfer registers (Address 0x05 and Address 0xFF), and the ADC function registers (Address 0x08 to Address 0x53). Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Blank cells in Table 15 should be considered reserved bits and have a 0 written into their registers during power-up. The leftmost column of the memory map indicates the register address; the default value is shown in the second rightmost column. The Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address, followed by 0x01 in the device update register (Address 0xFF[0], the transfer bit), the duty cycle stabilizer is turned off. It is important to follow each write sequence with a transfer bit to update the SPI registers. For more information about this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. DEFAULT VALUES When the AD9639 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 15. LOGIC LEVELS In Table 15, “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “bit is cleared” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. B | Page 31 of 36 AD9639 Data Sheet Table 15. Memory Map Register Addr. Register (MSB) (Hex) Name Bit 7 Chip Configuration Registers 0x00 chip_port_ SDO active (not config (local, master) required, ignored if not used) 0x01 chip_id (global) 0x02 chip_grade (global) Bit 6 Bit 5 LSB first Soft reset Bit 4 ADC A device_ update (local, master) ADC Function Registers 0x08 Modes (local) 0x09 Clock (global) 0x0D test_io (local) 0x0E test_bist (local) 0x0F adc_input (local) Bit 2 Bit 1 External PDWN pin function 00 = full power-down (default) 01 = standby Reset PN sequence long gen 1 = on 0 = off (default) Reset PN sequence short gen 1 = on 0 = off (default) Rev. B | Page 32 of 36 Default Value (Hex) Comments 0x18 16-bit address (default mode for ADCs) 8-bit chip ID, Bits[2:0] 0x29: AD9639, 12-bit quad Speed grade 010 = 170 MSPS 100 = 210 MSPS Device Index and Transfer Registers 0x05 device_ index_A (global) 0xFF Bit 3 (LSB) Bit 0 Read only. Read only. ADC B ADC C ADC D 0x0F SW transfer 1 = on 0 = off (default) 0x00 Power-down mode 00 = chip run (default) 01 = full power-down 10 = standby 11 = reset Duty cycle stabilize 1 = on (default) 0 = off Flexible output test mode 0000 = off (normal operation) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1/0 word toggle BIST init BIST 1 = on enable 0 = off 1 = on (default) 0 = off (default) VCM Analog disconnect enable 1 = on enable 0 = off 1 = on (default) 0 = off (default) 0x00 Determines generic modes of chip operation. 0x01 Turns the internal duty cycle stabilizer on and off. 0x00 When set, the test data is placed on the output pins in place of normal data. 0x00 When Bit 0 is set, the built-in selftest function is initiated. 0x00 Bits are set to determine which device on chip receives the next write command. The default is all devices on chip. Synchronously transfers data from the master shift register to the slave. Data Sheet Addr. (Hex) 0x10 Register Name Offset (local) 0x14 output_mode (local/global) 0x15 output_adjust (global) 0x18 VREF (global) 0x19 user_ patt1_lsb (local) user_ patt1_msb (local) user_ patt2_lsb (local) user_ patt2_msb (local) user_ patt3_lsb (local) user_ patt3_msb (local) user_ patt4_lsb (local) user_ patt4_msb (local) 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 AD9639 (MSB) Bit 7 Bit 6 Bit 5 (LSB) Bit 0 Bit 4 Default Value (Hex) 0x00 B7 B6 B5 Bit 3 Bit 2 Bit 1 6-bit device offset adjustment[5:0] 011111 = +31 LSB 011110 = +30 LSB 011101 = +29 LSB … 000010 = +2 LSB 000001 = +1 LSB 000000 = 0 LSB 111111 = −1 LSB 111110 = −2 LSB 111101 = −3 LSB … 100001 = −31 LSB 100000 = −32 LSB Data format select Output Output (global) invert enable bar 00 = offset binary enable (local) (default) (global) 1 = off 01 = twos 1 = on 0 = on complement 0 = off (default) 10 = gray code (default) Output driver current[1:0] 00 = 400 mV (default) 01 = 500 mV 10 = 440 mV 11 = 320 mV Ref_Vfs[4:0] Reference full-scale adjust 10000 = 0.98 V p-p 10001 = 1.00 V p-p 10010 = 1.02 V p-p 10011 = 1.04 V p-p … 11111 = 1.23 V p-p 00000 = 1.25 V p-p 00001 = 1.27 V p-p … 01110 = 1.48 V p-p 01111 = 1.5 V p-p B4 B3 B2 B1 B0 B15 B14 B13 B12 B11 B10 B9 B8 0xAA B7 B6 B5 B4 B3 B2 B1 B0 0xAA B15 B14 B13 B12 B11 B10 B9 B8 0xAA B7 B6 B5 B4 B3 B2 B1 B0 0xAA B15 B14 B13 B12 B11 B10 B9 B8 0xAA B7 B6 B5 B4 B3 B2 B1 B0 0xAA B15 B14 B13 B12 B11 B10 B9 B8 0xCC Rev. B | Page 33 of 36 Comments Device offset trim. 0x00 Configures the outputs and the format of the data. 0x00 VCM output adjustments. 0x00 Select adjustments for VREF. 0xAA User-Defined Pattern 1 LSB. User-Defined Pattern 1 MSB. User-Defined Pattern 2 LSB. User-Defined Pattern 2 MSB. User-Defined Pattern 3 LSB. User-Defined Pattern 3 MSB. User-Defined Pattern 4 LSB. User-Defined Pattern 4 MSB. AD9639 Data Sheet Addr. (Hex) 0x21 Register Name serial_control (global) (MSB) Bit 7 Bit 6 Bit 5 Bit 4 0x24 misr_lsb (local) B7 B6 B5 0x25 misr_msb (local) B15 B14 B13 0x33 JESD204 (global) 0x50 coarse_ gain_adj (local) 0x51 fine_ gain_adj (local) 0x52 gain_cal_ctl 0x53 Dynamic pgm pins (global) Gain adjust enable 1 = on 0 = off (default) Temperature sensor enable 1 = on 0 = off (default) pgm_3 00 = sync 01 = Standby A 10 = Standby A and Standby D 11 = Standby A and Standby B Default Value (Hex) 0x08 Bit 2 Bit 1 B4 Bit 3 PLL high encode rate mode (global) 0 = low rate 1 = high rate (default) B3 (LSB) Bit 0 B2 B1 B0 0x00 B12 B11 B10 B9 B8 0x00 ScramOverbling range in enable LSB of 0 = scramtail bits bling 0 = overdisabled range (default) disabled 1 = scram(default) bling 1 = overenabled range enabled Coarse gain adjust[5:0] = output[63:0] 000000 = 0000…0001 000001 = 0000…0011 000010 = 0000…0111 … 111101 = 0011…1111 111110 = 0111…1111 111111 = 1111…1111 Fine gain adjust[3:0] = output[15:0] 0000 = 0000000000000001 0001 = 0000000000000010 0010 = 0000000000000100 … 1101 = 0010000000000000 1110 = 0100000000000000 1111 = 1000000000000000 Gain cal Gain cal Gain enable resetb quarter 1 = on 1 = on LSB 0 = off (default) 1 = on (default) 0 = off 0 = off (default) pgm_0 pgm_1 pgm_2 00 = sync 00 = sync 00 = sync 01 = Standby D 01 = Standby C 01 = Standby B 10 = Standby D and 10 = Standby C and 10 = Standby B and Standby A Standby B Standby C 11 = Standby D and 11 = Standby C and 11 = Standby B and Standby C Standby D Standby A Rev. B | Page 34 of 36 Comments Serial stream control. Least significant byte of MISR. Read only. Most significant byte of MISR. Read only. 0x00 0x00 0x00 0x02 0x00 Standby = ADC core off, PN23 enabled, serial channel enabled. Data Sheet AD9639 APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9639, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD pin first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD pin. Several different decoupling capacitors can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the parts, with minimal trace lengths. A single PCB ground plane should be sufficient when using the AD9639. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the PCB, optimum performance can easily be achieved. EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9639. An exposed continuous copper plane on the PCB should mate to the AD9639 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane into several uniform sections by overlaying a silkscreen on the PCB. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions guarantees only one tie point. See Figure 64 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. 07973-029 SILKSCREEN PARTITION PIN 1 INDICATOR Figure 64. Typical PCB Layout Rev. B | Page 35 of 36 AD9639 Data Sheet OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 72 55 54 PIN 1 INDICATOR 1 PIN 1 INDICATOR 9.85 9.75 SQ 9.65 0.50 BSC 0.50 0.40 0.30 18 37 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012-A 1.00 0.85 0.80 19 36 TOP VIEW 12° MAX 8.35 8.20 SQ 8.05 EXPOSED PAD Figure 65. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9639BCPZ-170 AD9639BCPZRL-170 AD9639BCPZ-210 AD9639BCPZRL-210 AD9639-210KITZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07973-0-7/13(B) Rev. B | Page 36 of 36 Package Option CP-72-3 CP-72-3 CP-72-3 CP-72-3