TMS320C80 Digital Signal Processor Data Sheet 1997 Digital Signal Processing Solutions Printed in U.S.A., October 1997 SPRS023B Book Type Data Sheet TMS320C80 DSP 1997 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data (MIMD) DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set Computing (RISC) Processor – IEEE-754 Floating-Point Capability – 4K-Byte Instruction Cache – 4K-Byte Data Cache Four Parallel Processors (PP) – 32-Bit Advanced DSPs – 64-Bit Opcode Provides Many Parallel Operations per Cycle – 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP Transfer Controller ( TC) – 64-Bit Data Transfers – Up to 480M-Byte / s Transfer Rate – 32-Bit Addressing – Direct DRAM / VRAM Interface With Dynamic Bus Sizing – Intelligent Queuing and Cycle Prioritization Video Controller ( VC) – Provides Video Timing and VRAM Control – Dual-Frame Timers for Two Simultaneous Image-Capture and / or Display Systems Big- or Little-Endian Operation 50K-Byte On-Chip RAM 4G-Byte Address Space 16.6-ns Cycle Time 3.3-V Operation IEEE Standard 1149.1† Test Access Port (JTAG) GF PACKAGE ( BOTTOM VIEW ) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 AR AP AN AM AL AK AH AF AJ AG AD AB Y V T P M K H F D B AE AC AA W U R N L J G E C A GGP PACKAGE ( BOTTOM VIEW ) 26 24 22 20 18 16 14 12 10 8 6 4 2 5 25 23 21 19 17 15 13 11 9 7 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 description The TMS320C80 is a single chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 120-MFLOP IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 480M-byte/s off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications applications. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GF Terminal Assignments – Numerical Listing NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME A5 CT1 C21 HSYNC0 L5 VDD HACK C23 VDD W E33 A7 E35 TCK L31 VSS VSS C25 DBEN F2 L33 TRST C27 L35 XPT1 C29 VSS CAREA0 F4 A13 VSS CAS / DQM7 VDD VSS M2 A15 CAS / DQM5 C31 CBLNK0 / VBLNK0 F10 VDD VSS VDD VSS A17 D2 RETRY F12 D4 F14 A21 RAS D6 VDD VSS VDD PS0 M32 A19 VDD VSS DSF D8 AS0 F18 VSS CT2 N1 A23 A25 VSS SCLK1 D10 UTIME F20 N5 D12 F22 N31 VSS VSS D14 TMS D16 REQ0 F26 VDD VSS N33 A31 VDD EINT1 VSS RESET VDD VSS N35 B2 No Connect D18 F28 VDD A4 BS1 D20 VDD VSS P2 B4 VSS CAS / DQM0 P4 A9 B6 VDD PS1 D22 FCLK1 F34 TDO D24 G1 P34 XPT0 B10 REQ1 D26 VSS CAREA1 VDD VDD P32 B8 G3 A2 R1 B12 D28 SCLK0 G5 A1 R3 VSS VDD B14 VDD CAS / DQM6 D30 G31 EINT2 R5 B16 CAS / DQM3 D32 VSS VDD G33 CBLNK1 / VBLNK1 R31 B18 D34 VSYNC0 G35 E1 AS1 H2 VDD STATUS0 R33 B20 VDD CAS / DQM1 R35 VDD VSS B22 TRG / CAS E3 FAULT H4 A3 T2 A5 B24 E5 CSYNC1 / HBLNK1 T4 A13 E7 VSS STATUS2 H32 B26 VDD DDIN H34 TDI T32 D62 B28 FCLK0 E9 READY J1 STATUS1 T34 EMU0 B30 VDD CSYNC0 / HBLNK0 E11 BS0 J3 U1 E13 J5 U3 VDD A10 E15 PS3 E17 CAS / DQM4 J33 VDD VSS U5 C5 VSS STATUS3 VSS HREQ VSS VDD U31 FF1 C7 AS2 E19 RL J35 EMU1 U33 D61 C9 E21 STATUS5 K2 STATUS4 U35 C11 VSS CT0 E23 K4 A6 V2 C13 PS2 E25 VSS CLKOUT VDD VDD K32 VSYNC1 V4 C15 VDD CLKIN E27 LINT4 K34 HSYNC1 V32 C17 E29 EINT3 L1 A0 V34 C19 CAS / DQM2 E31 VSS L3 A7 W1 A9 A11 A27 A29 B32 C3 POST OFFICE BOX 1443 F8 F16 F24 F32 J31 • HOUSTON, TEXAS 77251–1443 M4 M34 N3 VSS VDD VDD A8 VDD VDD VSS VSS VDD A11 3 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GF Terminal Assignments – Numerical Listing (Continued) NO. NO. TERMINAL NAME TERMINAL NO. TERMINAL NAME NO. NAME W3 A18 AG1 A16 AL17 D20 AN29 D35 W5 AG3 VSS VDD AL19 D21 AN31 D45 W31 VSS VSS AL21 D24 AN33 W33 D59 AG31 AL23 D63 AG33 AL25 VSS D29 AP4 W35 VDD VSS VDD A27 Y2 A12 AG35 D57 AL27 D32 AP8 VDD D5 Y4 A19 AH2 A20 AL29 D38 AP10 D8 Y32 XPT2 AH4 A30 AL31 AP12 Y34 D56 AH32 D44 AL33 VSS D48 AP14 VDD D13 AA1 VSS VDD AH34 D54 AL35 D53 AP16 D17 AJ1 AM2 A24 AP18 VDD VDD AJ3 VDD A31 AM4 AP20 AM6 AP22 D34 AJ31 AM8 D2 AP24 AA35 VDD VSS VSS VSS VDD VSS VDD D26 AJ33 D42 AM10 D6 AP26 VDD D39 AB2 A14 AJ35 AM12 D41 A21 AK2 AM14 VSS D14 AP28 AB4 VDD VDD AP30 AB32 D55 AK4 AM16 D19 AP32 VDD D47 AB34 D60 AK8 VSS VDD AM18 D0 VDD A22 AK10 VSS VDD AM20 VSS D23 AR5 AC1 AR7 AM22 D25 AR9 VDD D7 VSS VSS AK14 AM26 VSS D31 AR11 AK16 VSS VDD AM24 AC31 AR13 VSS D11 AC33 D52 AK18 FF2 AM28 D33 AR15 D15 AC35 VDD VDD AK20 VSS D27 AM30 AR17 AM32 VSS VDD AR19 VSS VDD VSS VSS AK24 VDD VSS AM34 D50 AR21 D30 AN5 A29 AR23 D36 AK28 VDD VSS AN7 D1 AR25 AE1 VDD A15 AN9 AR27 AE3 A26 AK34 AN11 AE5 AL1 AN13 D12 AR31 AE31 VSS VSS VDD A23 VSS D9 VSS D40 AL3 A25 AN15 AE33 D51 AL5 AN17 AE35 D58 AL7 VSS D3 VDD D18 AN19 D22 AF2 A17 AL9 D4 AN21 AF4 A28 AL11 D10 AN23 VDD D28 AF32 D46 AL13 AN25 D37 AF34 D49 AL15 VSS D16 AN27 VSS AA3 AA5 AA31 AA33 AC3 AC5 AD2 AD4 AD32 AD34 4 TERMINAL NAME AG5 AJ5 AK12 AK22 AK26 AK32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 AP6 AR29 VDD D43 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GF Terminal Assignments – Alphabetical Listing TERMINAL NAME NO. TERMINAL NAME TERMINAL NAME NO. NO. TERMINAL NAME NO. A0 L1 CAS/DQM0 D20 D22 AN19 D61 U33 A1 G5 CAS/DQM1 B20 D23 AM20 D62 T32 A2 G3 CAS/DQM2 C19 D24 AL21 D63 W35 A3 H4 CAS/DQM3 B16 D25 AM22 DBEN C25 A4 P2 CAS/DQM4 E17 D26 AP20 DDIN B26 A5 T2 CAS/DQM5 A15 D27 AK22 DSF A23 A6 K4 CAS/DQM6 B14 D28 AN23 EINT1 A31 A7 L3 CAS/DQM7 A13 D29 AL25 EINT2 G31 A8 N3 CBLNK0/VBLNK0 C31 D30 AR21 EINT3 E29 A9 P4 CBLNK1/VBLNK1 G33 D31 AM26 EMU0 T34 A10 U3 CLKIN C17 D32 AL27 EMU1 J35 A11 W1 CLKOUT E25 D33 AM28 FAULT E3 A12 Y2 CSYNC0/HBLNK0 B32 D34 AP22 FCLK0 B28 A13 T4 CSYNC1/HBLNK1 H32 D35 AN29 FCLK1 D22 A14 AB2 CT0 C11 D36 AR23 FF1 U31 A15 AE1 CT1 A5 D37 AN25 FF2 AK18 A16 AG1 CT2 F18 D38 AL29 HACK A9 A17 AF2 D0 AR5 D39 AP26 HREQ E15 A18 W3 D1 AN7 D40 AR27 HSYNC0 E33 A19 Y4 D2 AM8 D41 AP28 HSYNC1 K34 A20 AH2 D3 AL7 D42 AJ33 LINT4 E27 A21 AB4 D4 AL9 D43 AR31 PS0 F14 A22 AC3 D5 AP8 D44 AH32 PS1 B8 A23 AL1 D6 AM10 D45 AN31 PS2 C13 A24 AM2 D7 AR9 D46 AF32 PS3 U5 A25 AL3 D8 AP10 D47 AP32 RAS A21 A26 AE3 D9 AN11 D48 AL33 READY E9 A27 AP4 D10 AL11 D49 AF34 REQ0 D16 A28 AF4 D11 AR13 D50 AM34 REQ1 B10 A29 AN5 D12 AN13 D51 AE33 RESET D14 A30 AH4 D13 AP14 D52 AC33 RETRY D2 A31 AJ3 D14 AM14 D53 AL35 RL E19 AS0 D8 D15 AR15 D54 AH34 SCLK0 D28 AS1 E1 D16 AL15 D55 AB32 SCLK1 A27 AS2 C7 D17 AP16 D56 Y34 STATUS0 H2 BS0 E11 D18 AN17 D57 AG35 STATUS1 J1 BS1 B4 D19 AM16 D58 AE35 STATUS2 E7 CAREA0 C29 D20 AL17 D59 W33 STATUS3 C5 CAREA1 D26 D21 AL19 D60 AB34 STATUS4 K2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GF Terminal Assignments – Alphabetical Listing (Continued) TERMINAL NAME NO. STATUS5 E21 TCK E35 TDI H34 TDO P32 TMS N33 TRG/CAS B22 TRST L33 UTIME D10 VDD VDD A17 A7 VDD VDD A29 VDD VDD B12 VDD VDD B24 VDD VDD C15 VDD VDD B6 B18 B30 C21 D4 D32 VDD VDD F2 VDD VDD F12 VDD VDD F24 VDD VDD F34 VDD VDD G35 VDD VDD J31 VDD VDD M34 VDD VDD N35 VDD 6 F8 F20 F28 G1 J5 M2 TERMINAL NAME NO. VDD VDD R31 VDD VDD U1 VDD VDD R33 U35 V2 V34 VDD VDD AA3 VDD VDD AA31 VDD VDD AC1 VDD VDD AA5 AA33 AC35 AD2 AD34 VDD VDD AG5 AG31 VDD VDD AJ35 AJ1 VDD VDD AK2 VDD VDD AK12 VDD VDD AK24 VDD VDD AK34 VDD VDD AM32 VDD VDD AN21 VDD VDD AP6 AK8 AK16 AK28 AM4 AN15 AN33 AP12 VDD VDD AP18 VDD VDD AP30 R3 R5 VDD N1 TERMINAL NAME NO. VDD VSS AR29 VSS VSS A19 VSS VSS C3 VSS VSS C27 VSS VSS D12 VSS VSS D24 VSS VSS E5 VSS VSS VSS VSS A11 A25 C9 D6 D18 D30 E13 E23 E31 F4 F10 VSS VSS F16 VSS VSS F26 VSS VSS J3 F22 F32 J33 VSS VSS L31 VSS VSS M32 VSS VSS VSS VSS L5 M4 N5 N31 R1 VSS VSS AC31 VSS VSS AD32 VSS VSS AE31 VSS VSS AG33 VSS VSS AJ31 VSS VSS AK10 VSS VSS AK20 VSS VSS AK32 VSS VSS AL13 VSS VSS AL31 VSS VSS AM12 VSS VSS AM24 VSS VSS VSS VSS AC5 AD4 AE5 AG3 AJ5 AK4 AK14 AK26 AL5 AL23 AM6 AM18 AM30 AN9 AN27 AR11 AR17 V4 VSYNC1 K32 V32 W C23 W5 XPT0 P34 W31 XPT1 L35 XPT2 Y32 VSS VSS AR19 VSS AA1 • HOUSTON, TEXAS 77251–1443 AA35 R35 AR7 POST OFFICE BOX 1443 VSS VSS VSS VSYNC0 VSS VSS AP24 TERMINAL NAME NO. AR25 D34 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GGP Terminal Assignments – Numerical Listing NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME A1 No Connect B1 No Connect C1 No Connect D1 A0 A2 No Connect B2 No Connect C2 No Connect D2 A3 No Connect B3 No Connect C3 No Connect D3 VDD STATUS4 A4 STATUS1 B4 STATUS2 C4 STATUS3 AS1 B5 AS2 C5 VSS STATUS0 D4 A5 D5 A6 RETRY B6 READY C6 FAULT D6 VDD AS0 A7 CT1 B7 BS0 C7 BS1 D7 UTIME A8 PS0 B8 PS1 C8 PS2 D8 CT0 A9 VDD VSS B9 HACK C9 HREQ D9 RESET B10 C10 REQ1 B11 C11 VSS VDD D10 D11 REQ0 B12 CAS / DQM7 C12 CLKIN D12 A13 VSS VDD No Connect VSS VDD VDD CAS / DQM6 No Connect B14 C14 VSS CAS / DQM5 D13 A14 No Connect VSS C13 A15 B15 CAS / DQM4 C15 CAS / DQM3 D15 A16 VDD CAS / DQM2 B16 CAS / DQM1 D16 CAS / DQM0 B17 VSS RL C16 A17 C17 D17 VDD VSS A18 VSS FCLK1 B18 RAS C18 VSS VDD D18 TRG / CAS B19 W D19 STATUS5 B20 VDD DSF C19 VDD VDD C20 D20 DBEN B21 DDIN C21 VSS CLKOUT D21 CAREA1 VSS VSS B22 SCLK1 C22 FCLK0 B23 SCLK0 C23 VDD VDD D22 A23 D23 CAREA0 A24 No Connect B24 No Connect C24 No Connect D24 LINT4 A25 No Connect B25 No Connect C25 No Connect D25 EINT3 A26 No Connect B26 No Connect C26 No Connect D26 EINT2 A10 A11 A12 A19 A20 A21 A22 B13 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D14 VDD CT2 7 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GGP Terminal Assignments – Numerical Listing (Continued) NO. NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME E1 A3 J23 HSYNC0 P1 No Connect V23 D52 E2 A2 J24 TRST P2 No Connect V24 E3 J25 TCK P3 J26 TMS P4 VSS VSS V25 E4 VSS A1 VSS VSS V26 D53 E23 EINT1 K1 A12 P23 W1 A24 E24 CBLNK1 / VBLNK1 K2 P24 W2 E25 CBLNK0 / VBLNK0 K3 VDD A11 VSS D59 W3 VSS VSS E26 VSS A4 K4 P26 K23 VSS TDI VDD No Connect W23 VDD VDD K24 TDO R2 VSS A17 VSS D49 W24 D50 K25 EMU1 R3 A18 W25 D51 VDD VSS K26 XPT0 R4 L1 R23 Y1 VDD A25 F24 CSYNC1 / HBLNK1 L2 VDD A13 VSS XPT2 W26 F23 R24 D57 Y2 A26 F25 VDD CSYNC0 / HBLNK0 L3 R25 VDD D58 Y3 A27 L4 VSS VSS Y4 VSS VSS L23 XPT1 T1 A19 Y23 VDD VDD L24 T2 D48 A5 L25 T3 VDD VDD Y24 G3 VSS VSS Y25 G4 L26 EMU0 T4 A20 Y26 VSS VSS G23 VSS VSYNC1 M1 T23 VSYNC0 M2 T24 VDD VDD AA1 G24 VDD A15 AA2 VDD VDD G25 VSS VSS M3 PS3 T25 D56 AA3 A28 M4 A14 T26 A8 M23 U1 AA23 VSS D45 H2 M24 D46 M25 D62 U3 VSS A21 AA24 H3 VDD A7 VDD D63 VSS VSS AA4 H1 AA25 D47 H4 A6 M26 D61 U4 AA26 H23 HSYNC1 N1 No Connect U23 VDD VDD AB1 VDD VSS H24 VDD VDD N2 A16 U24 D54 AB2 A29 N3 U25 A30 N4 U26 VSS D55 AB3 VDD A10 VDD VDD AB4 V1 A22 AB23 N24 V2 A23 AB24 VSS VDD D44 J3 VDD A9 VSS D60 N25 No Connect V3 VSS N26 No Connect V4 VDD VDD AB25 J4 F1 F2 F3 F4 F26 G1 G2 G26 H25 H26 J1 J2 8 TERMINAL NAME N23 POST OFFICE BOX 1443 P25 R1 R26 U2 • HOUSTON, TEXAS 77251–1443 W4 AB26 VSS VSS TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GGP Terminal Assignments – Numerical Listing (Continued) NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME AC1 A31 AD1 No Connect AE1 No Connect AF1 No Connect AC2 AD2 No Connect AE2 No Connect AF2 No Connect AC3 VDD VDD AD3 No Connect AE3 No Connect AF3 No Connect AC4 D0 AD4 D1 AF4 D2 D3 AD5 AE5 D4 AF5 AC6 VSS VDD D9 AD6 VSS VDD D5 AE4 AC5 AE6 D6 AF6 VSS D7 VDD D10 AE7 D8 AF7 AE8 D11 AF8 AC9 D12 AD9 D13 AF9 AD10 AE10 D15 AF10 AC11 VDD D16 VSS VDD VSS AE9 AC10 AE11 AF11 AC12 D18 AD12 D19 AE12 VSS VDD AC13 D20 AD13 AE13 VDD No Connect AD14 AE14 AF14 No Connect AC15 VDD D24 VSS No Connect AF13 AC14 VSS D21 AE15 D23 AF15 D22 AC16 D27 AD16 VDD D26 AE16 D25 AF16 AC17 VSS D31 AD17 VSS D30 AE17 D28 AF17 VSS VDD AE18 AF18 D29 AD19 VDD D34 AE19 AF19 AC20 VDD D35 VDD D32 AE20 D33 AF20 VSS VSS AC21 D37 AD21 AE21 D36 AF21 AC22 D40 AD22 VSS VDD AE22 D39 AF22 AC23 D42 AD23 D41 AE23 AF23 AC24 D43 AD24 No Connect AE24 VSS No Connect AF24 VSS No Connect AC25 VDD VDD AD25 No Connect AE25 No Connect AF25 No Connect AD26 No Connect AE26 No Connect AF26 No Connect AC7 AC8 AC18 AC19 AC26 AD7 AD8 AD11 AD15 AD18 AD20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 AF12 VSS VDD D14 VSS D17 VDD D38 9 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GGP Terminal Assignments – Alphabetical Listing TERMINAL NAME 10 NO. TERMINAL NAME TERMINAL NAME NO. NO. TERMINAL NAME NO. A0 D1 CAS / DQM0 A17 D22 AF15 D61 M26 A1 E4 CAS / DQM1 C16 D23 AE15 D62 M25 A2 E2 CAS / DQM2 A16 D24 AC15 D63 M24 A3 E1 CAS / DQM3 C15 D25 AE16 DBEN D20 A4 F1 CAS / DQM4 B15 D26 AD16 DDIN B21 A5 G3 CAS / DQM5 C14 D27 AC16 DSF B20 A6 H4 CAS / DQM6 D13 D28 AE17 EINT1 E23 A7 H3 CAS / DQM7 B12 D29 AF18 EINT2 D26 A8 H1 CBLNK0 / VBLNK0 E25 D30 AD18 EINT3 D25 A9 J3 CBLNK1 / VBLNK1 E24 D31 AC18 EMU0 L26 A10 J1 CLKIN C12 D32 AE19 EMU1 K25 A11 K3 CLKOUT C21 D33 AE20 FAULT C6 A12 K1 CSYNC0 / HBLNK0 F26 D34 AD20 FCLK0 D22 A13 L2 CSYNC1 / HBLNK1 F24 D35 AC20 FCLK1 A19 A14 M4 CT0 D8 D36 AE21 HACK B9 A15 M2 CT1 A7 D37 AC21 HREQ C9 A16 N2 CT2 D15 D38 AF22 HSYNC0 J23 A17 R2 D0 AC4 D39 AE22 HSYNC1 H23 A18 R3 D1 AE4 D40 AC22 LINT4 D24 A19 T1 D2 AF4 D41 AD23 PS0 A8 A20 T4 D3 AC5 D42 AC23 PS1 B8 A21 U3 D4 AE5 D43 AC24 PS2 C8 A22 V1 D5 AD6 D44 AB24 PS3 M3 A23 V2 D6 AE6 D45 AA23 RAS B18 A24 W1 D7 AF6 D46 AA24 READY B6 A25 Y1 D8 AE7 D47 AA25 REQ0 D11 A26 Y2 D9 AC8 D48 Y24 REQ1 D10 A27 Y3 D10 AD8 D49 W23 RESET D9 A28 AA3 D11 AE8 D50 W24 RETRY A6 A29 AB2 D12 AC9 D51 W25 RL B17 A30 AB3 D13 AE9 D52 V23 SCLK0 B23 A31 AC1 D14 AF9 D53 V26 SCLK1 B22 AS0 D6 D15 AE10 D54 U24 STATUS0 C5 AS1 A5 D16 AC11 D55 U26 STATUS1 A4 AS2 B5 D17 AF11 D56 T25 STATUS2 B4 BS0 B7 D18 AC12 D57 R24 STATUS3 D4 BS1 C7 D19 AD12 D58 R26 STATUS4 D3 CAREA0 D23 D20 AC13 D59 P24 STATUS5 D19 CAREA1 D21 D21 AD14 D60 N24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GGP Terminal Assignments – Alphabetical Listing (Continued) TERMINAL NAME NO. TERMINAL NAME TERMINAL NAME NO. NO. TERMINAL NAME NO. TCK J25 A11 VSS VSS U25 R25 VSS VSS A10 K23 VDD VDD P25 TDI TDO K24 VDD T2 VSS A18 VSS V25 VDD VDD T3 VSS VSS A22 VSS VSS W2 VDD VDD T24 VSS VSS B10 VSS VSS W4 VDD VDD U23 VSS VSS B16 VSS VSS Y26 VDD VDD V4 VSS VSS C10 VSS VSS AB1 VDD VDD Y4 VSS VSS C17 VSS VSS AB25 VDD VDD AA1 VSS VSS D17 VSS VSS AC6 VDD VDD AA26 VSS VSS E26 VSS VSS AD4 VDD VDD AC2 VSS VSS G1 VSS VSS AD11 VDD VDD AC7 VSS VSS G4 VSS VSS AD17 VDD VDD AC14 VSS VSS G26 VSS VSS AE11 VDD VDD AC25 VSS VSS K4 VSS VSS AE23 VDD VDD AD5 VSS VSS L4 VSS VSS AF7 VDD VDD AD10 VSS VSS L25 VSS VSS AF16 VDD VDD AD19 VSS VSS P3 AF20 P4 VSS VSS VDD VDD AE12 VSS VSS P23 VSYNC0 G24 R1 VSYNC1 G23 VDD VDD AF8 VSS VSS R4 W C19 T26 XPT0 K26 VDD VDD AF17 VSS VSS U1 XPT1 L23 U2 XPT2 R23 TMS J26 TRG / CAS D18 TRST J24 UTIME D7 VDD VDD A9 VDD VDD A15 VDD VDD A21 VDD VDD B19 VDD VDD C18 VDD VDD C23 VDD VDD D5 VDD VDD D14 VDD VDD F2 VDD VDD F4 VDD VDD H2 VDD VDD H25 VDD VDD J2 VDD VDD L1 VDD VDD M23 VDD N4 A12 A20 B11 C11 C22 D2 D12 D16 F3 F25 H24 H26 K2 M1 N3 T23 U4 V3 W26 Y23 AA2 AB23 AC3 AC10 AC19 AC26 AD7 AD15 AD22 AE18 AF12 AF21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 A23 B14 C4 C13 C20 E3 F23 G2 G25 J4 L3 L24 N23 V24 W3 Y25 AA4 AB4 AB26 AC17 AD9 AD13 AD21 AE13 AF5 AF10 AF19 AF23 11 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 Terminal Functions TERMINAL NAME DESCRIPTION TYPE† LOCAL MEMORY INTERFACE A31 – A0 O Address bus. A31 – A0 output the 32-bit byte address of the external memory cycle. The address can be multiplexed for DRAM accesses. AS2 – AS0 I Address-shift selection. AS2 – AS0 determine how the column address appears on the address bus. Eight shift values are supported, including zero. BS1 – BS0 I Bus-size selection. BS1 – BS0 indicate the bus size of the memory or other device being accessed, allowing dynamic bus sizing for data buses less than 64-bits wide. I Cycle-timing selection. CT2 – CT0 signals determine the timing of the current memory access. CT2 – CT0 D63 – D0 I/O Data bus. D63 – D0 transfer up to 64 bits of data per memory cycle into or out of the ’C80. DBEN O Data-buffer enable. DBEN drives the active-low output-enables of bi-directional transceivers that can be used to buffer input and output data on D63 – D0. DDIN O Data-direction indicator. DDIN indicates the direction of the data that passes through the transceivers. When DDIN is low, the transfer is from external memory into the ’C80. FAULT I Fault. FAULT is driven low by external circuitry to inform the ’C80 that a fault has occurred on the current memory row-access. PS3 – PS0 I Page-size indication. PS3 – PS0 indicate the page size of the memory device(s) being accessed by the current cycle. The ’C80 uses this information to determine when to begin a new row-access. READY I Ready. READY indicates that the external device is ready to complete the memory cycle. READY is driven low by external circuitry to insert wait states into a memory cycle. RL O Row latch. The high-to-low transition of RL can be used to latch the valid 32-bit byte address that is present on A31 – A0. RETRY I Retry. RETRY is driven low by external circuitry to indicate that the addressed memory is busy. The ’C80 memory cycle is rescheduled. STATUS5 – STATUS0 O Status code. At row time, STATUS5 – STATUS0 indicate the type of cycle being performed. At column time, they identify the processor and type of request that initiated the cycle. UTIME I User-timing selection. UTIME causes the timing of RAS and CAS / DQM7 – CAS / DQM0 to be modified so that custom memory timings can be generated. During reset, UTIME selects the endian mode in which the ’C80 operates. DRAM, VRAM, AND SDRAM CONTROL CAS / DQM7 – CAS / DQM0 O Column-address strobes. CAS / DQM7 – CAS / DQM0 drive the CAS inputs of DRAMs and VRAMs, or the DQM input of SDRAMs. The eight strobes provide byte-write access to memory. DSF O Special function. DSF selects special VRAM functions such as block-write, load color register, split-register transfer, and SGRAM block write. RAS O Row-address strobe. RAS drives the RAS inputs of DRAMs, VRAMs, and SDRAMs. TRG / CAS O Transfer / output enable or column-address strobe. TRG / CAS is used as an output-enable for DRAMs and VRAMs, and also as a transfer-enable for VRAMs. TRG / CAS also drives the CAS inputs of SDRAMs. W O Write enable. W is driven low before CAS during write cycles. W controls the direction of the transfer during VRAM transfer cycles. † I = input, O = output, Z = high impedance 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION O Host acknowledge. The ’C80 drives HACK output low following an active HREQ to indicate that it has driven the local-memory-bus signals to the high-impedance state and is relinquishing the bus. HACK is driven high asynchronously following HREQ being detected inactive, and then the ’C80 resumes driving the bus. HREQ I Host request. An external device drives HREQ low to request ownership of the local-memory bus. When HREQ is high, the ’C80 owns and drives the bus. HREQ is synchronized internally to the ’C80’s internal clock. Also, HREQ is used at reset to determine the power-up state of the MP. If HREQ is low at the rising edge of RESET, the MP comes up running. If HREQ is high, the MP remains halted until the first interrupt occurrence on EINT3. REQ1, REQ0 O Internal cycle request. REQ1 and REQ0 provide a two-bit code indicating the highest-priority memory-cycle request that is being received by the TC. External logic can monitor REQ1 and REQ0 to determine if it is necessary to relinquish the local-memory bus to the ’C80. HOST INTERFACE HACK SYSTEM CONTROL CLKIN I Input clock. CLKIN generates the internal ’C80 clocks to which all processor functions (except the frame timers) are synchronous. CLKOUT O Local output clock. CLKOUT provides a way to synchronize external circuitry to internal timings. All ’C80 output signals (except the VC signals) are synchronous to this clock. EINT1, EINT2, EINT3 I Edge-triggered interrupts. EINT1, EINT2 and EINT3 allow external devices to interrupt the master processor (MP) on one of three interrupt levels (EINT1 is the highest priority). The interrupts are rising-edge triggered. EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on EINT3 causes the MP to unhalt and fetch its reset vector (the EINT3 interrupt-pending bit is not set in this case). LINT4 I Level-triggered interrupt. LINT4 provides an active-low level-triggered interrupt to the MP. Its priority falls below that of the edge-triggered interrupts. Any interrupt request should remain low until it is recognized by the ’C80. RESET I Reset. RESET is driven low to reset the ’C80 (all processors). During reset, all internal registers are set to their initial state and all outputs are driven to their inactive or high-impedance levels. During the rising edge of RESET, the MP reset mode and the ’C80’s operating endian mode are determined by the levels of HREQ and UTIME pins, respectively. XPT2 – XPT0 I External packet transfer. XPT2 – XPT0 are used by external devices to request a high-priority XPT by the TC. EMULATION CONTROL I/O Emulation pins. EMU0 and EMU1 are used to support emulation host interrupts, special functions targeted at a single processor, and multiprocessor halt-event communications. I Test clock. TCK provides the clock for the ’C80 IEEE-1149.1 logic, allowing it to be compatible with other IEEE-1149.1 devices, controllers, and test equipment designed for different clock rates. TDI‡ I Test data input. TDI provides input data for all IEEE-1149.1 instructions and data scans of the ’C80. TDO TMS‡ O Test data output. TDO provides output data for all IEEE-1149.1 instructions and data scans of the ’C80. I Test-mode select. TMS controls the IEEE-1149.1 state machine. TRST§ I Test reset. TRST resets the ’C80 IEEE-1149.1 module. When low, all boundary-scan logic is disabled, allowing normal ’C80 operation. EMU0, EMU1‡ TCK‡ † I = input, O = output, Z = high impedance ‡ This pin has an internal pullup and can be left unconnnected during normal operation. § This pin has an internal pulldown and can be left unconnnected during normal operation. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION O Composite area. CAREA0 and CAREA1 define a special area such as an overscan boundary. This area represents the logical OR of the internal horizontal and vertical area signals. VIDEO INTERFACE CAREA0, CAREA1 Composite blanking / vertical blanking. Each of CBLNK0 / VBLNK0 and VBLNK1 provides one of two blanking functions, depending on the configuration of the CSYNC / HBLNK pin: CBLNK0 / VBLNK0, CBLNK1 / VBLNK1 O Composite blanking disables pixel display /capture during both horizontal and vertical retrace periods and is enabled when CSYNC is selected for composite sync video systems. Vertical blanking disables pixel display /capture during vertical retrace periods and is enabled when HBLNK is selected for separate-sync video systems. Following reset, CBLNK0 / VBLNK0 and CBLNK1 / VBLNK1 are configured as CBLNK0 and CBLNK1, respectively. Composite sync / horizontal blanking. CSYNC0 / HBLNK0 and CSYNC1 / HBLNK1 can be programmed for one of two functions: CSYNC0 / HBLNK0, CSYNC1 / HBLNK1 I/O/Z Composite sync is for use on composite-sync video systems and can be programmed as an input, output, or high-impedance signal. As an input, the ’C80 extracts horizontal and vertical sync information from externally generated active-low sync pulses. As an output, the active-low composite sync pulses are generated from either external HSYNC and VSYNC signals or the ’C80’s internal video timers. In the high-impedance state, the pin is neither driven nor allowed to drive circuitry. Horizontal blank disables pixel display / capture during horizontal retrace periods in separate-sync video systems and can be used as an output only. Immediately following reset, CSYNC0 / HBLNK0 and CSYNC1 / HBLNK1 are configured as high-impedance CSYNC0 and CSYNC1, respectively. FCLK0, FCLK1 HSYNC0, HSYNC1 SCLK0, SCLK1 VSYNC0, VSYNC1 I Frame clock. FCLK0 and FCLK1 are derived from the external video system’s dotclock and are used to drive the ’C80 video logic for frame timer 0 and frame timer 1. I/O/Z Horizontal sync. HSYNC0 and HSYNC1 control the video system. They can be programmed as input, output, or high impedance signals. As an input, HSYNC synchronizes the video timer to externally generated horizontal sync pulses. As an output, HSYNC is an active-low horizontal sync pulse generated by the ’C80 on-chip frame timer. In the high-impedance state, the pin is not driven, and no internal synchronization is allowed to occur. Immediately following reset, HSYNC0 and HSYNC1 are in the high-impedance state. I Serial-data clock. SCLK0 and SCLK1 are used by the ’C80 SRT controller to track the VRAM tap point when using midline reload. SCLK0 and SCLK1 should be the same signals that clock the serial register on the VRAMs controlled by frame timer 0 and frame timer 1, respectively. I/O/Z Vertical sync. VSYNC0 and VSYNC1 control the video system. They can be programmed as inputs, outputs, or high-impedance signals. As inputs, VSYNCx synchronizes the frame timer to externally generated vertical-sync pulses. As outputs, VSYNCx are active-low vertical-sync pulses generated by the ’C80 on-chip frame timer. In the high-impedance state, the pin is not driven and no internal synchronization is allowed to occur. Immediately following reset, VSYNCx is in the high-impedance state. POWER VSS‡ VDD‡ I Ground. Electrical ground inputs I Power. Nominal 3.3-V power supply inputs MISCELLANEOUS No Connect No connect serves as an alignment key and must be left unconnected. FF2 – FF1 FF2 – FF1 (GF package only) are reserved for factory use and should be left unconnected. † I = input, O = output, Z = high-impedance ‡ For proper operation, all VDD and VSS pins must be connected externally. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 architecture Figure 1 shows the major components of the ’C80: the master processor (MP), the parallel digital signal processors (PPs), the transfer controller ( TC), the video controller ( VC), and the IEEE-1149.1 emulation interface. Shared access to on-chip RAM is achieved through the crossbar. Crossbar connections are represented by . Each PP can perform three accesses per cycle through its local ( L ), global ( G ), and instruction ( I ) ports. The MP can access two RAMs per cycle through its crossbar/data ( C/ D) and instruction ( I ) ports, and the TC can access one RAM through its crossbar interface. Up to 15 simultaneous accesses are supported in each cycle. Addresses can be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In addition to the crossbar, a 32-bit datapath exists between the MP and the TC and VC. This allows the MP to access TC and VC on-chip registers that are memory mapped into the MP memory space. The ’C80 has a 4G-byte address space as shown in Figure 2. The lower 32M bytes are used to address internal RAM and memory-mapped registers. PP3 PP2 PP1 PP0 MP VC OCR L G I 32 64 L G I 32 64 32 L G I 32 64 32 L G I 32 C/D I 64 32 32 32 IEEE1149.1 (JTAG) 32 64 64 Instruction Cache Data RAM0 Data RAM1 Data RAM2 Parameter RAM Data RAM0 Instruction Cache Data RAM1 Data RAM2 Parameter RAM Instruction Cache Data RAM0 Data RAM1 Data RAM2 Parameter RAM Data RAM0 Instruction Cache Data RAM1 Data RAM2 Parameter RAM Data RAM0 Instruction Cache Data RAM1 Data RAM2 Parameter RAM 64 TC Figure 1. Block Diagram Showing Datapaths POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 architecture (continued) PP0 Data RAM0 (2K Bytes) PP0 Data RAM1 (2K Bytes) PP1 Data RAM0 (2K Bytes) PP1 Data RAM1 (2K Bytes) PP2 Data RAM0 (2K Bytes) PP2 Data RAM1 (2K Bytes) PP3 Data RAM0 (2K Bytes) PP3 Data RAM1 (2K Bytes) Reserved (16K Bytes) PP0 Data RAM2 (2K Bytes) Reserved (2K Bytes) PP1 Data RAM2 (2K Bytes) Reserved (2K Bytes) PP2 Data RAM2 (2K Bytes) Reserved (2K Bytes) PP3 Data RAM2 (2K Bytes) Reserved (16 730 112 Bytes) PP0 Parameter RAM (2K Bytes) Reserved (2K Bytes) PP1 Parameter RAM (2K Bytes) Reserved (2K Bytes) PP2 Parameter RAM (2K Bytes) Reserved (2K Bytes) PP3 Parameter RAM (2K Bytes) 0x01003800 0x00000000 Reserved (51 200 Bytes) 0x000007FF 0x00000800 0x00000FFF 0x00001000 MP Parameter RAM (2K Bytes) 0x000017FF 0x00001800 PP0 Instruction Cache (2K Bytes) 0x00002FFF 0x00003000 0x000037FF 0x00003800 Reserved (6K Bytes) PP1 Instruction Cache (2K Bytes) 0x00003FFF 0x00004000 0x00007FFF 0x00008000 Reserved (6K Bytes) PP2 Instruction Cache (2K Bytes) 0x000087FF 0x00008800 Reserved (6K Bytes) 0x00008FFF 0x00009000 PP3 Instruction Cache (2K Bytes) 0x000097FF 0x00009800 Reserved (32K Bytes) 0x00009FFF 0x0000A000 MP Data Cache (4K Bytes) 0x0000A7FF 0x0000A800 Reserved (28K Bytes) 0x0000AFFF 0x0000B000 MP Instruction Cache (4K Bytes) 0x0000B7FF 0x0000B800 0x00FFFFFF 0x01000000 0x010007FF 0x01000800 Reserved (28K Bytes) Memory-Mapped TC Registers (512 Bytes) Memory-Mapped VC Registers (512 Bytes) 0x01000FFF 0x01001000 0x010017FF 0x01001800 Reserved (8 327 168 Bytes) 0x018017FF 0x01801800 0x01801FFF 0x01802000 0x018037FF 0x01803800 0x01803FFF 0x01804000 0x018057FF 0x01805800 0x01805FFF 0x01806000 0x018077FF 0x01807800 0x01807FFF 0x01808000 0x0180FFFF 0x01810000 0x01810FFF 0x01811000 0x01817FFF 0x01818000 0x01818FFF 0x01819000 0x0181FFFF 0x01820000 0x018201FF 0x01820200 0x018203FF 0x01820400 0x01FFFFFF 0x02000000 0x01001FFF 0x01002000 External Memory (4 064M Bytes) 0x010027FF 0x01002800 0x01002FFF 0x01003000 0x010037FF 0xFFFFFFFF Figure 2. Memory Map 16 0x010107FF 0x01010800 Reserved (8 327 168 Bytes) 0x00001FFF 0x00002000 0x000027FF 0x00002800 0x0100FFFF 0x01010000 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 master processor (MP) architecture The master processor (MP) is a 32-bit RISC processor with an integral IEEE-754 floating-point unit. The MP is designed for effective execution of C code and is capable of performing at well over 130K dhrystones/s. Major tasks which the MP typically performs are: D D D Task control and user interface Information processing and analysis IEEE-754 floating point (including graphics transforms) MP functional block diagram Figure 3 shows a block diagram of the master processor. Key features of the MP include: D D D D D D D D D D D 32-bit RISC processor – Load/store architecture – Three operand arithmetic and logical instructions 4K-byte instruction cache and 4K-byte data cache – Four-way set associative – LRU replacement – Data writeback 2K-byte non-cached parameter RAM Thirty-one 32-bit general-purpose registers Register and accumulator scoreboard 15-bit or 32-bit immediate constants 32-bit byte addressing Scalable timer Leftmost-one and rightmost-one logic IEEE-754 floating-point hardware – Four double-precision floating-point vector accumulators – Vector floating-point instructions Floating-point operation and parallel load or store Multiply and accumulate High performance – 60 million instructions per second (MIPS) – 120 million floating-point operations per second (MFLOPS) – Over 130K dhrystones/s POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP functional block diagram (continued) Register File (Thirty-One 32-Bit Registers) Scoreboard Barrel Rotator Mask Generator Double-Precision Floating-Point Multiplier (Single-Precision Core) Zero Comparator Integer ALU Leftmost / Rightmost One Double-Precision Floating-Point Accumulators Timer Control Registers Double-Precision Floating-Point Adder Instruction Register Program Counters PC Incrementer Emulation Logic Endian Multiplexers Instruction Cache Controller Data/Cache Controller Crossbar Interface Figure 3. MP Block Diagram MP general-purpose registers The MP contains 31 32-bit general-purpose registers, R1 – R31. Register R0 always reads as zero and writes to it are discarded. Double precision values are always stored in an even-odd register pair with the higher numbered register always holding the sign bit and exponent. The R0/R1 pair is not available for this use. A scoreboard keeps track of which registers are awaiting loads or the result of a previous instruction and stalls the instruction pipeline until the register contains valid data. As a recommended software convention, typically R1 is used as a stack pointer and R31 as a return-address link register. Figure 4 shows the MP general-purpose registers. 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP general-purpose registers (continued) Zero/Discard Not Available R1 R2 R2 R3 R2, R3 R4 R4 R5 R4, R5 ••• ••• R30 R30 R31 R30, R31 32-Bit Registers 64-Bit Register Pairs Figure 4. MP General-Purpose Registers The 32-bit registers can contain signed-integer, unsigned-integer, or single precision floating-point values. Signed and unsigned bytes and halfwords are sign extended or zero-filled. Doublewords may be stored in a 64-bit even/odd register pair. Double-precision floating-point values are referenced using the even register number or the register pair. Figure 5 through Figure 7 show the register data formats. 31 Si Single l P Precision i i Floating Point 22 0 S E E E E E E E E M M M M M M M M M M M M M M M M M M M M M M M MS LS 31 Si d 32 bit Signed 32-bit Integer S 0 I I I I I I I I I I I I I I I I I I I I MS I I I I I I I I I I LS 31 Unsigned 32-Bit 32 Bit Integer I 0 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U MS LS Figure 5. MP Register 32-Bit Data Formats POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP general-purpose registers (continued) 31 Signed Byte 7 S S S S S S S S S S S S S S S S S S S S S S S S S 0 I I I I I I MS 31 Unsigned Byte 0 LS 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U U U U U U U U MS 31 Signed Halfword 0 I I I I I I I MS 31 Unsigned Halfword 0 LS 15 S S S S S S S S S S S S S S S S S 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I I I I I I I I I LS 0 U U U U U U U U U U U U U U U U MS LS Figure 6. MP Register 8-Bit and 16-Bit Data 31 Odd Register 0 Most Significant 32-Bit Word MS 31 Even Register 0 Least Significant 32-Bit Word LS 19 0 Double Precision 31 Double-Precision S E E E E E E E E E E E M M M M M M M M M M M M M M M M M M M M Floating-Point Odd Register MS 0 Double-Precision Double Precision 31 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M Floating-Point Even Register LS Figure 7. MP Register 64-Bit Data MP double-precision floating-point accumulators There are four double-precision floating-point registers (see Figure 8) to accumulate intermediate floating-point results. 64 0 a0 Accumulator 0 a1 Accumulator 1 a2 Accumulator 2 a3 Accumulator 3 MSB LSB Figure 8. Double-Precision Floating-Point Accumulators 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP control registers In addition to the general-purpose registers, there are a number of control registers that are used to represent the state of the processor. Table 1 shows the control register numbers of the accessible registers. Table 1. Control Register Numbers NO. NAME DESCRIPTION NO. NAME 0x0000 EPC Exception Program Counter 0x0015–0x001F — 0x0001 EIP Exception Instruction Pointer 0x0020 SYSSTK System Stack Pointer 0x0002 CONFIG Configuration 0x0021 SYSTMP System Temporary Register 0x0003 — 0x0004 INTPEN 0x0005 Reserved DESCRIPTION Reserved 0x0022–0x002F — Interrupt Pending 0x0030 MPC Emulator Exception Program Cntr — Reserved 0x0031 MIP Emulator Exception Instruction Ptr 0x0006 IE Interrupt Enable 0x0032 — 0x0007 — Reserved 0x0033 ECOMCNTL 0x0008 FPST 0x0009 — 0x000A PPERROR Floating-Point Status Reserved Reserved Reserved Emulator Communication Control 0x0034 ANASTAT 0x0035–0x0038 — 0x0039 BRK1 Emulation Breakpoint 1 Reg. Emulation Breakpoint 2 Reg. PP Error Indicators Emulation Analysis Status Reg Reserved 0x000B — Reserved 0x003A BRK2 0x000C — Reserved 0x003B–0x01FF — 0x000D PKTREQ Packet Request Register 0x0200 – 0x020F ITAG0 – 15 Instruction Cache Tags 0 to 15 0x000E TCOUNT Current Counter Value 0x0300 ILRU Instruction Cache LRU Register 0x000F TSCALE Counter Reload Value 0x0400–0x040F DTAG0 – 15 Data Cache Tags 0 to 15 Reserved 0x0010 FLTOP Faulting Operation 0x0500 DLRU Data Cache LRU Register 0x0011 FLTADR Faulting Address 0x4000 IN0P Vector Load Pointer 0 0x0012 FLTTAG Faulting Tag 0x4001 IN1P Vector Load Pointer 1 0x0013 FLTDTL Faulting Data (low) 0x4002 OUTP Vector Store Pointer 0x0014 FLTDTH Faulting Date (high) MP pipeline registers The MP uses a three-stage fetch, execute, access (FEA) pipeline. The primary pipeline registers are manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and emulation pipeline registers are user accessible as control registers. All pipeline registers are 32 bits. Program Execution Mode Normal Exception Emulation PC EPC MPC Instruction Pointer IP EIP MIP Instruction Register IR Program Counter • • • Instruction register (IR) contains the instruction being executed. Instruction pointer (IP) points to the instruction being executed. Program counter (PC) points to the instruction being fetched. • • Exception/emulator instruction pointer (EIP/MIP) points to the instruction that would have been executed had the exception / emulation trap not occurred. Exception/emulator program counter (EPC/MPC) points to the instruction to be fetched on returning from the exception/emulation trap. Figure 9. MP FEA Pipeline Registers POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 configuration (CONFIG) register (0x0002) The CONFIG register controls or reflects the state of certain options as shown in Figure 10. 31 30 29 28 27 E R T H X E R T H X Type Release 26 25 24 23 22 21 20 19 18 17 16 15 Reserved 14 13 12 11 Type 10 9 8 7 Reserved 6 5 4 3 Release 2 1 0 Reserved Endian mode; 0 = big-endian, 1 = little-endian, read only PPData RAM round robin; 0 = fixed, 1 = variable, read / write TC PT round robin; 0 = variable, 1 = fixed, read / write. High priority MP events; 0 = disabled, 1 = enabled, read / write Externally initiated packet transfers; 0 = disabled, 1 = enabled, read / write Number of PPs in device, read only TMS320C80 version number Figure 10. CONFIG Register interrupt-enable (IE) register (0x0006) The IE register contains enable bits for each of the interrupts/traps as shown in Figure 11. The global-interrupt-enable (ie) bit and the appropriate individual interrupt-enable bit must be set in order for an interrupt to occur. 31 30 29 28 27 26 25 pe x4 x3 bp pb pc mi pe x4 x3 bp pb pc mi p3 24 23 22 21 20 19 18 17 16 15 14 p3 p2 p1 p0 io mf p2 p1 p0 io mf x2 x1 ti PP error External interrupt 4 (LINT4) External interrupt 3 (EINT3) Bad packet transfer Packet transfer busy Packet transfer complete Message (MP self) interrupt PP3 message interrupt 13 12 11 10 9 8 7 6 5 x2 x1 ti f1 f0 fx fu fo PP2 message interrupt PP1message interrupt PP0 message interrupt Integer overflow Memory fault External interrupt 2 (EINT2) External interrupt 1 (EINT1) MP timer interrupt f1 f0 fx fu fo fz fi ie 4 3 2 fz fi 1 0 ie Frame-timer 1 interrupt Frame-timer 0 interrupt Floating-point inexact Floating-point underflow Floating-point overflow Floating-point divide-by-zero Floating-point invalid Global-interrupt enable Figure 11. IE Register interrupt-pending (INTPEN) register (0x0004) The bits in INTPEN register show the current state of each interrupt/trap. Pending interrupts do not occur unless the ie bit and corresponding interrupt-enable bit are set. Software must write a 1 to the appropriate INTPEN bit to clear an interrupt. Figure 12 shows the INTPEN register locations. 31 30 29 28 27 26 25 pe x4 x3 bp pb pc mi 24 23 22 21 20 19 18 17 16 15 14 p3 p2 p1 p0 io mf 13 12 11 10 9 8 7 6 5 x2 x1 ti f1 f0 fx fu fo Figure 12. INTPEN Register 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 4 3 2 fz fi 1 0 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 floating-point status register (FPST) (0x0008) FPST contains status and control information for the FPU as shown in Figure 13. Bits 17–21 are read/write floating-point unit (FPU) control bits. Bits 22 – 26 are read/write accumulated status bits. All other bits show the status of the last FPU instruction to complete and are read only. 31 30 29 28 27 destination dest ai az ao au ax sm fs vm drm opcode e1 26 25 24 23 22 21 20 19 ai az ao au ax sm fs vm 18 17 16 drm 15 14 13 opcode 11 e0 10 9 8 pd 7 6 rm The ninth MSB of exponent Destination precision 00 – single float 01 – double float Rounding mode 00 – nearest 01 – zero Int multiply overflow Invalid Divide-by-zero Overflow Underflow Inexact e0 pd Destination register value Accumulated value invalid Accumulated divide-by-zero Accumulated overflow Accumulated underflow Accumulated inexact Sequential mode select Floating-point stall Vector fast mode Rounding mode 00 – nearest 10 – positive ∞ 01 – zero 11 – negative ∞ Last opcode The tenth MSB of exponent 12 e1 rm mo i z o u x 5 4 3 2 1 0 mo i z o u x 10 – signed int 11 – unsigned int 10 – positive ∞ 11 – negative ∞ Figure 13. FPSTS Register PP error register (PPERROR) (0x000A) The bits in the PPERROR register reflect parallel processor errors (see Figure 14). The MP can use these when a PP error interrupt occurs to determine the cause of the error. 31 30 29 28 27 26 25 24 23 22 21 20 Reserved PP# h – PP halted 19 18 17 16 h h h h 3 2 1 0 15 14 13 12 11 10 9 8 i i i i 3 2 1 0 Reserved PP# i – PP illegal instruction 7 6 5 4 Reserved PP# 3 2 1 0 f f f f 3 2 1 0 f – PP fault type; 0 = icache, 1 = DEA Figure 14. PPERROR Register packet-transfer request register (PKTREQ) (0x000D) PKTREQ controls the submission and priority of packet-transfer requests as shown in Figure 15. It also indicates that a packet transfer is currently active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved I – Immediate (urgent) priority selected F – High (foreground) priority selected S – Suspend packet transfer Q – Packet transfer queued; read only 9 8 7 6 5 4 3 2 1 0 I F S Q P P – Submit packet-transfer request Figure 15. PKTREQ Register POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 memory-fault registers The five read-only memory-fault registers contain information about memory address exceptions, as shown in Figure 16. FLTOP (0x0010) FLTTAG (0x0012) 31 30 29 28 27 26 25 24 Dest 31 30 29 23 22 21 20 19 18 17 Reserved 28 27 26 25 24 23 22 21 16 15 K 20 19 18 17 14 13 SZ 16 15 14 13 12 11 10 9 i d x R 12 11 10 22-Bit Cache Tag Address 8 7 6 5 4 3 2 Reserved 9 8 7 6 5 4 3 2 P D P D P D P D 3 2 1 0 Block 1 1 0 0 Sub-Block 31 0 FLTADR (0x0011) Faulting Address Accessed by the Instruction FLTDTH (0x0013) Faulting Write Most-Significant-Data Word FLTDTL (0x0014) Faulting Write Least-Significant-Data Word Dest K SZ Destination Register Number Kind of Operation: 00 – load 01 – unsigned load 10 – store 11 – cache flush/clean Size of Data: 00 – 8-bit 01 – 16-bit 10 – 32-bit 11 – 64-bit i d x R Block P D MP icache fault MP dcache fault DEA Fault Modified return sequence Faulting block number Sub-block is present. Dirty bit set Figure 16. Memory-Fault Registers 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP cache registers The ILRU and DLRU registers track least-recently-used (LRU) information for the sixteen instruction-cache and sixteen data-cache blocks. The ITAGxx registers contain block addresses and the present flags for each sub-block. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each sub-block. Figure 17 shows the cache registers. ILRU (0x0300) DLRU (0x0500) 31 30 mru 29 28 nmru 27 26 25 nlru 24 lru 23 22 mru 21 20 nmru 19 18 17 nlru 16 lru 15 14 mru 13 Set 2 Set 3 12 nmru 11 10 9 nlru 8 7 lru 6 mru 5 4 nmru Set 1 3 2 1 nlru 0 lru Set 0 ITAG0 –ITAG15 (0x0200 – 0x020F) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22-Bit Cache Tag Address 9 8 P 7 6 P 3 5 4 P 2 3 2 1 0 1 0 P 1 0 Sub-Block DTAG0 – DTAG15 (0x0400 – 0x040F) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22-Bit Cache Tag Address 9 8 7 6 5 4 3 2 P D P D P D P D 3 2 1 0 Sub-Block mru nmru nlru Most-recently-used block Next most-recently-used block Next least-recently-used block lru P D Least-recently-used block Sub-block present Sub-block dirty mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set. Figure 17. Cache Registers POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP cache architecture The MP contains two four-way set-associative, 4K caches for instructions and data. Each cache is divided into four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and is aligned to a 256-byte address boundary. Each block is partitioned into four sub-blocks that each contain sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one sub-block to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19 shows how addresses map into the cache using the cache tags and address bits. Block 0 Tag Reg 0 (Block 0) Block 1 Tag Reg 1 (Block 1) LRU in SET 0 Sub-Blocks NLRU in SET 0 NMRU in SET 0 Set 0 Block 2 Tag Reg 2 (Block 2) Block 3 Tag Reg 3 (Block 3) MRU in SET 0 LRU Stack for SET 0 Figure 18. MP Cache Architecture (x4 Sets) 32-Bit Logical Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 T T T T T T T T T T T T T T T T T T T T T T S S s s 5 4 3 2 W W W W 1 0 B B On-Chip MP 2K Cache RAMS Bank 0 Bank 1 Set 0 Set 2 Set 1 Set 3 11 10 9 8 7 6 5 4 3 2 1 0 S S A A s s W W W W B B Address in On-Chip Cache Bank T – Tag Address Bits s – Sub-Block (within block) Select (0 – 3) B – Byte (within word) Select (0 – 3) S – Set Select Bits (0 – 3) W – Word (within sub-block) Select (0 – 15) A – Block Select (which tag matched) (0 – 3) Figure 19. MP Cache Addressing 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP parameter RAM The parameter RAM is a noncachable, 2K-byte, on-chip RAM which contains MP-interrupt vectors, MP-requested TC task buffers, and a general-purpose area. Figure 20 shows the parameter RAM address map. 0x01010000– 0x0101007F Suspended PT Parameters (128 Bytes) 0x01010080– 0x010100DF Reserved (96 Bytes) 0x010100E0– 0x010100FB XPT7 / SOF0 Linked List Start Add. 0x010100E0 XPT6 / SAM0 Linked List Start Add. 0x010100E4 XPT5 / SOF1 Linked List Start Add. XPT Linked List Start Addresses (28 Bytes) 0x010100FC – 0x010100FF MP Linked List Start Address 0x01010100– 0x0101017F Off-Chip to Off-Chip PT Buffer (128 Bytes) 0x01010180– 0x0101021F Interrupt and Trap Vectors (160 Bytes) 0x01010220– 0x0101029F XPT Off-Chip to Off-Chip PT Buffer (128 Bytes) 0x010102A0– 0x010107FF General-Purpose RAM (1376 Bytes) 0x010100E8 XPT4 / SAM1 Linked List Start Add. 0x010100EC XPT3 Linked List Start Add. 0x010100F0 XPT2 Linked List Start Add. 0x010100F4 XPT1 Linked List Start Add. 0x010100F8 Figure 20. MP Parameter RAM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP interrupt vectors Table 2 and Table 3 show the MP interrupts and traps and their vector addresses. Table 2. Maskable Interrupts IE BIT (TRAP#) NAME VECTOR ADDRESS 0 ie 0x01010180 2 fi 0x01010188 Floating-point invalid 3 fz 0x0101018C Floating-point divide-by-zero 5 fo 0x01010194 Floating-point overflow 6 fu 0x01010198 Floating-point underflow 7 fx 0x0101019C Floating-point inexact 8 f0 0x010101A0 Frame timer 0 9 f1 0x010101A4 Frame timer 1 MASKABLE INTERRUPT 10 ti 0x010101A8 MP timer 11 x1 0x010101AC External interrupt 1 (EINT1) 12 x2 0x010101B0 External interrupt 2 (EINT2) 14 mf 0x010101B8 Memory fault 15 io 0x010101BC Integer overflow 16 p0 0x010101C0 PP0 message 17 p1 0x010101C4 PP1 message 18 p2 0x010101C8 PP2 message 19 p3 0x010101CC PP3 message 25 mi 0x010101E4 MP message 26 pc 0x010101E8 Packet transfer complete 27 pb 0x010101EC Packet transfer busy 28 bp 0x010101F0 Bad packet transfer 29 x3 0x010101F4 External interrupt 3 (EINT3) 30 x4 0x010101F8 External interrupt 4 (LINT4) 31 pe 0x010101FC PP error Table 3. Nonmaskable Traps TRAP NO. NAME VECTOR ADDRESS 32 e1 0x01010200 Emulator trap1 (reserved) 33 e2 0x01010204 Emulator trap2 (reserved) 34 e3 0x01010208 Emulator trap3 (reserved) 35 e4 0x0101020C Emulator trap4 (reserved) 36 fe 0x01010210 Floating-point error 0x01010214 Reserved 0x01010218 Illegal MP instruction 39 0x0101021C Reserved 72 to 415 0x010102A0 to 0x010107FC 37 38 28 er POST OFFICE BOX 1443 NONMASKABLE TRAP System or user defined • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP opcode formats The three basic classes of MP instruction opcodes are; short immediate, three register, and long immediate. Figure 21 shows the opcode structure for each class of instruction. 31 Short Immediate 27 26 Dest 31 Three Register Dest Source 2 1 1 15-Bit Immediate 13 12 11 1 Opcode 22 21 20 19 Source 2 0 Opcode 22 21 20 19 27 26 Dest 15 14 Source 2 27 26 31 Long immediate 22 21 0 5 4 Options 13 12 11 1 Opcode 1 0 Source 1 5 4 Options 0 Source 1 32-Bit Long Immediate Figure 21. MP Opcode Formats POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP opcode summary Table 4 through Table 6 show the opcode formats for the MP. Table 7 summarizes the master processor instruction set. Table 4. Short-Immediate Opcodes 31 30 29 illop0 28 27 26 25 24 23 22 Source Dest 21 20 19 18 17 16 15 0 0 0 0 0 0 0 14 13 12 11 10 Unsigned Immediate 9 8 7 6 5 4 3 2 trap – – – – E – – – – – 0 0 0 0 0 0 1 Unsigned Trap Number cmnd – – – – – – – – – – 0 0 0 0 0 1 0 Unsigned Immediate – – – – – 0 0 0 0 1 0 0 Unsigned Control Register Number 0 0 0 0 1 0 1 Unsigned Control Register Number 0 0 0 0 1 1 0 Unsigned Control Register Number rdcr Dest swcr Dest brcr – – – Source – – – – – – – shift.dz Dest Source 0 0 0 1 0 0 0 – – – i n Endmask Rotate shift.dm Dest Source 0 0 0 1 0 0 1 – – – i n Endmask Rotate shift.ds Dest Source 0 0 0 1 0 1 0 – – – i n Endmask Rotate shift.ez Dest Source 0 0 0 1 0 1 1 – – – i n Endmask Rotate shift.em Dest Source 0 0 0 1 1 0 0 – – – i n Endmask Rotate shift.es Dest Source 0 0 0 1 1 0 1 – – – i n Endmask Rotate shift.iz Dest Source 0 0 0 1 1 1 0 – – – i n Endmask Rotate shift.im Dest Source 0 0 0 1 1 1 1 – – – i n Endmask Rotate and.tt Dest Source2 0 0 1 0 0 0 1 Unsigned Immediate and.tf Dest Source2 0 0 1 0 0 1 0 Unsigned Immediate and.ft Dest Source2 0 0 1 0 1 0 0 Unsigned Immediate xor Dest Source2 0 0 1 0 1 1 0 Unsigned Immediate or.tt Dest Source2 0 0 1 0 1 1 1 Unsigned Immediate and.ff Dest Source2 0 0 1 1 0 0 0 Unsigned Immediate xnor Dest Source2 0 0 1 1 0 0 1 Unsigned Immediate or.tf Dest Source2 0 0 1 1 0 1 1 Unsigned Immediate or.ft Dest Source2 0 0 1 1 1 0 1 Unsigned Immediate or.ff Dest Source2 0 0 1 1 1 1 0 Unsigned Immediate ld Dest Base 0 1 0 0 M SZ Signed Offset ld.u Dest Base 0 1 0 1 M SZ Signed Offset Base 0 1 1 0 M SZ Signed Offset Source2 0 1 1 1 M 0 0 Signed Offset 1 0 0 0 0 0 A Signed Offset st dcache bsr – A E F i 30 Source – – – – Link F – – – – – jsr Link Base 1 0 0 0 1 0 A Signed Offset bbz BITNUM Source 1 0 0 1 0 0 A Signed Offset bbo BITNUM Source 1 0 0 1 0 1 A Signed Offset bcnd Cond Source 1 0 0 1 1 0 A Signed Offset cmp Dest Source2 1 0 1 0 0 0 0 Signed Immediate add Dest Source2 1 0 1 1 0 0 U Signed Immediate sub Dest Source2 1 0 1 1 0 1 U Signed Immediate Reserved bit (code as 0) Annul delay slot instruction if branch taken Emulation trap bit Clear present flags Invert endmask POST OFFICE BOX 1443 M n SZ U 1 0 Modify, write modified address back to register Rotate sense for shifting Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword) Unsigned form • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP opcode summary (continued) Table 5. Long-Immediate and Three-Register Opcodes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 trap – – – – E – – – – – 1 1 0 0 0 0 0 0 1 I – – – – – – – IND TR cmnd – – – – – – – – – – 1 1 0 0 0 0 0 1 0 I – – – – – – – Source1 – – – – – 1 1 0 0 0 0 1 0 0 I – – – – – – – IND CR 1 1 0 0 0 0 1 0 1 I – – – – – – – IND CR 1 1 0 0 0 0 1 1 0 I – – – – – – – IND CR rdcr Dest swcr Dest brcr – – – Source – – – – – – – 4 3 2 shift.dz Dest Source 1 1 0 0 0 1 0 0 0 0 i n Endmask Rotate shift.dm Dest Source 1 1 0 0 0 1 0 0 1 0 i n Endmask Rotate shift.ds Dest Source 1 1 0 0 0 1 0 1 0 0 i n Endmask Rotate shift.ez Dest Source 1 1 0 0 0 1 0 1 1 0 i n Endmask Rotate shift.em Dest Source 1 1 0 0 0 1 1 0 0 0 i n Endmask Rotate shift.es Dest Source 1 1 0 0 0 1 1 0 1 0 i n Endmask Rotate shift.iz Dest Source 1 1 0 0 0 1 1 1 0 0 i n Endmask Rotate shift.im Dest Source 1 1 0 0 0 1 1 1 1 0 i n and.tt Dest Source2 1 1 0 0 1 0 0 0 1 I – – – Endmask – – – – Source1 and.tf Dest Source2 1 1 0 0 1 0 0 1 0 I – – – – – – – Source1 and.ft Dest Source2 1 1 0 0 1 0 1 0 0 I – – – – – – – Source1 xor Dest Source2 1 1 0 0 1 0 1 1 0 I – – – – – – – Source1 or.tt Dest Source2 1 1 0 0 1 0 1 1 1 I – – – – – – – Source1 Dest Source2 1 1 0 0 1 1 0 0 0 I – – – – – – – Source1 xnor Dest Source2 1 1 0 0 1 1 0 0 1 I – – – – – – – Source1 or.tf Dest Source2 1 1 0 0 1 1 0 1 1 I – – – – – – – Source1 or.ft Dest Source2 1 1 0 0 1 1 1 0 1 I – – – – – – – Source1 or.ff Dest Source2 1 1 0 0 1 1 1 1 0 I – – – – – – – Source1 ld Dest Base 1 1 0 1 0 0 M SZ I S D – – – – – Offset ld.u Dest Base 1 1 0 1 0 1 M SZ I S D – – – – – Offset Base 1 1 0 1 1 0 M SZ I S D – – – – – Offset Source2 1 1 0 1 1 1 M 0 0 I 0 0 – – – – – Source1 1 1 1 0 0 0 0 0 A I – – – – – – – Offset st bsr – D E F i Source – – – – F Link – – – – – jsr Link Base 1 1 1 0 0 0 1 0 A I – – – – – – – Offset bbz BITNUM Source 1 1 1 0 0 1 0 0 A I – – – – – – – Target Target bbo BITNUM Source 1 1 1 0 0 1 0 1 A I – – – – – – – bcnd Cond Source 1 1 1 0 0 1 1 0 A I – – – – – – – Target cmp Dest Source2 1 1 1 0 1 0 0 0 0 I – – – – – – – Source1 add Dest Source2 1 1 1 0 1 1 0 0 U I – – – – – – – Source1 sub Dest Source2 1 1 1 0 1 1 0 1 U I – – – – – – – Source1 Reserved bit (code as 0) Direct external access bit Emulation trap bit Clear present flags Invert endmask l M n S SZ POST OFFICE BOX 1443 0 Rotate and.ff dcache 1 Long immediate Modify, write modified address back to register Rotate sense for shifting Scale offset by data size Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword • HOUSTON, TEXAS 77251–1443 31 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP opcode summary (continued) Table 6. Miscellaneous Instruction Opcodes 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 vadd 31 Mem Src / Dst 30 29 28 27 26 Source2 / Dest 25 24 23 22 1 1 1 1 0 – 0 0 0 I – m P – d m s 4 3 Source1 2 1 vsub Mem Src / Dst Source2 / Dest 1 1 1 1 0 – 0 0 1 I – m P – d m s Source1 vmpy Mem Src / Dst Source2 / Dest 1 1 1 1 0 – 0 1 0 I – m P – d m s Source1 vmsub Mem Src / Dst Dest 1 1 1 1 0 a 0 1 1 I a m P Z – m – Source1 vrnd(FP) Mem Src / Dst Dest 1 1 1 1 0 a 1 0 0 I a m P m s Source1 PD 0 vrnd(Int) Mem Src / Dst Dest 1 1 1 1 0 – 1 0 1 I – m P – d m s Source1 vmac Mem Src / Dst Source2 1 1 1 1 0 a 1 1 0 I a m P Z – m – Source1 vmsc Mem Src / Dst Source2 1 1 1 1 0 a 1 1 1 I a m P Z – m – Source1 fadd Dest Source2 1 1 1 1 1 0 0 0 0 I – PD P2 P1 Source1 fsub Dest Source2 1 1 1 1 1 0 0 0 1 I – PD P2 P1 Source1 fmpy Dest Source2 1 1 1 1 1 0 0 1 0 I – PD P2 P1 Source1 fdiv Dest Source2 1 1 1 1 1 0 0 1 1 I – PD P2 P1 Source1 frndx Dest 1 1 1 1 1 0 1 0 0 I – PD RM P1 Source1 fcmp Dest 1 1 1 1 1 0 1 0 1 I – P2 P1 Source1 fsqrt Dest 1 1 1 1 1 0 1 1 1 I – P1 Source1 lmo Dest Source 1 1 1 1 1 1 0 0 0 – – – – – – – – – – – – – rmo Dest Source 1 1 1 1 1 1 0 0 1 – – – – – – – – – – – – – – – – – Source2 – – – – – – – PD – – estop – – – – – – – – – – 1 1 1 1 1 1 1 1 0 – – – – – – – – – – – – – illopF – – – – – – – – – – 1 1 1 1 1 1 1 1 1 C – – – – – – – – – – – – – a C d l m Mem Src / Dst Dest 32 – Reserved bit (code as 0) Floating-point accumulator select Constant operands rather than register Destination precision for vector (0 = sp, 1 = dp) Long immediate 32-bit data Parallel memory operation specifier Vector store or load source / dst register Destination register POST OFFICE BOX 1443 P P1 P2 PD RM s Z Dest precision for parallel load / store (0 = single, 1 = double) Precision of source1 operand Precision of source2 operand Precision of destination result Rounding Mode (0 = N, 1 = Z, 2 = P, 3 = M) Scale offset by data size Use 0 rather than accumulator • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MP opcode summary (continued) Table 7. Summary of MP Opcodes INSTRUCTION add DESCRIPTION INSTRUCTION DESCRIPTION Signed integer add or.ff Bitwise OR with 1s complement and.tt Bitwise AND or.ft Bitwise OR with 1s complement and.ff Bitwise AND with 1s complement or.tf Bitwise OR with 1s complement and.ft Bitwise AND with 1s complement rdcr Read control register and.tf Bitwise AND with 1s complement rmo Rightmost one bbo Branch bit one shift.dz Shift, disable mask, zero extend bbz Branch bit zero shift.dm Shift, disable mask, merge bcnd Branch conditional shift.ds Shift, disable mask, sign extend Branch always shift.ez Shift, enable mask, zero extend brcr br Branch control register shift.em Shift, enable mask, merge bsr Branch and save return shift.es Shift, enable mask, sign extend cmnd Send command shift.iz Shift, invert mask, zero extend cmp Integer compare shift.im Shift, invert mask, merge dcache Flush data cache sub-block st Store register into memory estop Emulation stop sub Signed integer subtract fadd Floating-point add swcr Swap control register fcmp Floating-point compare trap Trap Floating-point divide vadd Vector floating-point add fmpy Floating-point multiply vmac Vector floating-point multiply and add to accumulator frndx Floating-point convert/round vmpy Vector floating-point multiply fsqrt Floating-point square root vmsc Vector floating-point multiply and subtract from accumulator fsub FLoating-point subtract vmsub Vector floating-point subtract accumulator from source illop fdiv Illegal operation vrnd(FP) Vector round with floating-point input jsr Jump and save return vrnd(Int) Vector round with integer input ld Load signed into register vsub Vector floating-point subtract ld.u Load unsigned into register xnor Bitwise exclusive NOR lmo Leftmost one xor Bitwise exclusive OR or.tt Bitwise OR POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP architecture The parallel processor (PP) is a 32-bit integer DSP optimized for imaging and graphics applications. Each PP can execute in parallel; a multiply, ALU operation, and two memory accesses within a single instruction. This internal parallelism allows a single PP to achieve over 500 million operations per second for certain algorithms. The PP has a three-input ALU that supports all 256 three input Boolean combinations and many combinations of arithmetic and Boolean functions. Data-merging and bit-to-byte, bit-to-word, and bit-to-halfword translations are supported by hardware in the input data path to the ALU. Typical tasks performed by a PP include: D D D D D 34 Pixel-intensive processing – Motion estimation – Convolution – PixBLTs – Warp – Histogram – Mean square error Domain transforms – DCT – FFT – Hough Core graphics functions – Line – Circle – Shaded fills – Fonts Image Analysis – Segmentation – Feature extraction Bit-stream encoding/decoding – Data merging – Table look-ups POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP functional block diagram Figure 22 shows a block diagram of a parallel processor. Key features of the PP include: D D D D D D D 64-bit instruction word (supports multiple parallel operations) Three-stage pipeline for fast instruction cycle Numerous registers – 8 data, 10 address, 6 index registers – 20 other user-visible registers Data Unit – 16x16 integer multiplier (optional dual 8x8) – Splittable 3-input ALU – 32-bit barrel rotator – Mask generator – Multiple-status flag expander for translations to/from 1 bit-per-pixel space. – Conditional assignment of data unit results – Conditional source selection – Special processing hardware Leftmost one / rightmost one Leftmost bit change / rightmost bit change Memory addressing – Two address units (global & local) provide up to two 32-bit accesses in parallel with data unit operation. – 12 addressing modes (immediate and indexed) – Byte, halfword, and word addressability – Scaled indexed addressing – Conditional assignment for loads – Conditional source selection for stores Program flow – Three hardware loop controllers Zero overhead looping / branching Nested loops Multiple loop endpoints – Instruction cache management – PC mapped to register file – Interrupts for messages and context switching Algebraic assembly language POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP functional block diagram (continued) Data Unit ALU Data Path Multiplier Data Path d0 – d7 Expander Mask Generator Barrel Rotator Three-Input ALU mf & sr Registers Local Address Unit Global Destination Global Source Local Destination / Source a0 – a4, a7 x0 – x2 Global Address Unit a8 – a12, a15 sp = a6 = a14 Local Data Path x8 – x10 Global Data Path Program Flow Control Unit Three Zero-Overhead Loop / Branch Controllers Repl Instruction and Cache Control Repl 32 A/S A/S 64 Local Data Port Instruction Port Global Data Port Repl Replicate hardware A/S Align/sign extend hardware IAP Instruction address port LAP Local address port GAP Global address port Figure 22. PP Block Diagram 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 32 IAP LAP GAP TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP registers The PP contains many general-purpose registers, status registers, and configuration registers. All PP registers are 32-bit registers. Figure 23 shows the accessible registers of the PP blocks. Data-Unit Registers Data Registers Multiple Flags Status d0 / EALU Operation mf sr d1 d2 d3 d4 d5 d6 d7 Address-Unit Registers Global-address Unit Address Registers Index Flags Local-Address Unit Address Registers Index Flags a8 x8 a0 x0 a9 x9 a1 x1 a10 x10 a2 x2 a11 a3 a12 a14 / sp a15 = 0 PFC-Unit Registers PC-Related Registers a4 Stack Pointer Same Physical Register a6/ sp a7 = 0 Loop Addresses Loop Counts Communications pc (br, call) ls0 lr0 comm iprs ls1 lr1 Interrupts ipa (read only) ls2 lr2 lntflg ipe (read only) le0 lc0 inten Cache Tags le1 lc1 tag0 (read only) le2 lc2 tag1 (read only) tag2 (read only) Loop Control tag3 (read only) lctl Figure 23. PP Registers POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP data-unit registers The data unit contains eight 32-bit general-purpose data registers (d0–d7) referred to as the D registers. The d0 register also acts as the control register for EALU operations. d0 register Figure 24 shows the format when d0 is used as the EALU control register. 31 30 29 28 FMOD FMOD A C I S N 27 26 A 25 24 23 22 21 20 19 EALU Function Code 18 17 16 15 14 13 12 11 10 9 C I S N E F – – – DMS E F DMS M R DBR Function modifiers Arithmetic enable EALU carry-In Invert-carry-In Sign extend Nonmultiple mask 8 7 6 M R 5 4 3 – 2 1 0 DBR Explicit multiple carry-In Expanded mf Default multiply shift amount Split multiply Rounded multiply Default barrel rotate amount Figure 24. d0 Format for EALU Operations multiple flags (mf) register The mf register records status information from each split ALU segment for multiple arithmetic operations. The mf register may be expanded to generate a mask for the ALU. Figure 25 shows the mf register format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 3 2 1 0 1 0 Figure 25. mf Register Format status register (sr) The sr contains status and control bits for the PP ALU. Figure 26 shows the sr register format. 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 N C V 30 Z LV – – – – – – – – – – – – – – – – – – MSS N C V Z LV R MSS Negative status bit Carry status bit Overflow status bit Zero status bit Latched overflow Rotation bit Msize Asize 7 6 R 5 4 Msize Asize mf Status selection 00 – set by zero 10 – set by extended result 01 – set by sign 11 – reserved Expander data size Split ALU data size Figure 26. sr Format PP address-unit registers address registers The address unit contains ten 32-bit address registers which contain the base address for address computations or which can be used for general-purpose data. The registers a0 – a4 are used for local address computations and registers a8–a12 are used for global-address computations. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 index registers The six 32-bit index registers contain index values for use with the address registers in address computations or they can be used for general-purpose data. Registers x0 – x2 are used by the local-address unit and registers x8 – x10 are used by the global-address unit. stack pointer (sp) The sp contains the address of the bottom of the PP’s system stack. The stack pointer is addressed as a6 by the local-address unit and as a14 by the global-address unit. Figure 27 shows the sp register format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Word-Aligned Address 1 0 0 0 Figure 27. sp Register Format zero register The zero registers are read-as-zero address registers for the local address unit (a7) and global-address unit (a15). Writes to the registers are ignored and can be specified when operational results are to be discarded. Figure 28 shows the zero register format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28. zero Registers PP program flow control (PFC) unit registers loop registers The loop registers control three levels of zero-overhead loops. The 32-bit loop start registers (ls0 – ls2) and loop-end registers (le0 – le2) contain the starting and ending addresses for the loops. The loop-counter registers (lc0 – lc2) contain the number of repetitions remaining in their associated loops. The lr0 – lr2 registers are loop reload registers used to support nested loops. The format for the loop-control (lctl) register is shown in Figure 29. There are also six special write-only mappings of the loop-reload registers. The lrs0 – lrs2 codes are used for fast initialization of lsn, lrn, and lcn registers for multi-instruction loops while the lrse0 – lrse2 codes are used for single instruction-loop fast initialization. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 – – – – – – – – – – – – – – – – – – – – E E LCDn 10 Loop End Enable Loop Counter Designator 000 – None 010 – lc1 001 – lc0 011 – lc2 1xx – reserved 9 LCD2 le2 8 7 E 6 5 LCD1 le1 4 3 E 2 1 0 LCD0 le0 Figure 29. lctl Register pipeline registers The PFC unit contains a pointer to each stage of the PP pipeline. The pc contains the program counter which points to the instruction being fetched. The ipa points to the instruction in the address stage of the pipeline and the ipe points to the instruction in the execute stage of the pipeline. The instruction pointer return-from-subroutine (iprs) register contains the return address for a subroutine call. Figure 30 shows the variable pipeline register format. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 pipeline registers (continued) 31 30 29 28 27 26 25 24 23 22 21 pc 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 PC (29-Bit Doubleword Address) 31 30 29 28 27 26 25 24 23 22 21 20 19 1 0 – G L G – Global Interrupt Enable ipa 2 L – Loop Inhibit 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32-Bit Copy of the Previous pc Register Value 31 30 29 28 27 26 25 24 23 22 ipe 21 20 19 18 17 16 15 14 13 12 11 10 32-Bit Copy of the Previous ipa Register Value 31 30 29 28 27 26 25 24 23 22 iprs 21 20 19 18 17 16 15 14 13 12 11 10 29-Bit Doubleword Return Address 2 1 0 – – – Figure 30. Pipeline Registers interrupt registers The interrupt-enable (inten) register allows individual interrupts to be enabled and configures the interrupt flag (intflg) register operation. The intflg register contains the interrupt flag bits. Interrupt priority increases moving from left to right on intflg. Figure 31 shows the PP-interrupt register format. inten intflg 31 30 29 28 r r r r 27 26 25 24 23 22 21 E E E E – – – P P P P 3 2 M M S S G G P P 1 M S G P P 0 M S G 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 E E E E – – E – – – – – – – – – – – – – W M P M S G P T E N D P T E R R P T Q T A S K 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r I I I I – – – I I I I – – I – – – – – – – – – – – – – – r E W PPnMSG Reserved (write as 0) Enable Interrupt Write Mode 0 – writing 1 clears intflg 1 – writing 1 sets intflg PPn message Interrupt MPMSG PTEND PTERR PTQ TASK MP Message Interrupt Packet Transfer Complete Packet-Transfer Error Packet Transfer Queued MP Task Interrupt Figure 31. PP-Interrupt Registers 40 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 communication (comm) register The comm register contains the packet-transfer handshake bits and PP indicator bits. Figure 32 shows the comm register format. 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 H S Q P 30 29 – – – – – – – – – – – – – – – – – – – – – – – – – MAREV PP# High-priority packet transfer Packet-transfer suspend Packet transfer queued Submit packet transfer request Major revision # Minor revision # 00 – 320C80 10 – 320C82 H S Q P MAREV MIREV DEV Device MIREV 2 1 0 PP# DEV pp Number (read only) 000 – pp0 010 – pp2 001 – pp1 011 – pp3 1xx – not implemented Figure 32. comm Register cache-tag registers The tag0 – tag3 registers contain the tag address and sub-block present bits for each cache block. Figure 33 shows the cache tag registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23-Bit Tag Address P LRU Present bit Least-recently-used code 00 – mru 10 – next lru 01 – next mru 11 – lru Sub-Block # 8 7 6 5 4 3 2 1 0 P P P P – – – LRU 3 2 1 0 Figure 33. Cache Tag Registers PP cache architecture Each PP has its own 2K-byte instruction cache. Each cache is divided into four blocks and each block is divided into four sub-blocks containing 16 64-bit instructions each. Cache misses cause one sub-block to be loaded into cache. Figure 34 shows the cache architecture for one of the four sets in each cache. Figure 35 shows how addresses map into the cache using the cache tags and address bits. Block 0 tag 0 (Block 0) Block 1 tag 1 (Block 1) Block 2 tag 2 (Block 2) Block 3 tag 3 (Block 3) LRU Sub-Blocks NLRU NMRU MRU LRU Stack Figure 34. PP Cache Architecture 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23-Bit Tag Value 8 7 sub 6 5 4 instruction 3 2 1 0 ignored sub – sub-block Figure 35. pc Register Cache-Address Mapping POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP parameter RAM The parameter RAM is a, 2K-byte, on-chip RAM which contains PP-interrupt vectors, PP-requested TC task buffers, and a general-purpose area. The parameter RAM does not use the cache memory. Figure 36 shows the parameter RAM address map. Suspended PT Parameters (128 Bytes) 0x0100#000– 0x0100#07F Reserved (96 Bytes) 0x0100#080– 0x0100#0DF Restricted for Operating System Use (24 Bytes) 0x0100#0E0– 0x0100#0F7 Cache Fault Address 0x0100#0F8– 0x0100#0FB PP-Linked List Start Address 0x0100#0FC – 0x0100#0FF Off-Chip to Off-Chip PT Buffer (128 Bytes) 0x0100#100– 0x0100#17F Interrupt Vectors (128 Bytes) 0x0100#180– 0x0100#1FF General-Purpose RAM (1524 Bytes Less Stack Size) 0x0100#200 Application-Dependent Boundary Stack 0x0100#7F0 Stack State Information After Reset (12 Bytes) Stack Pointer After Reset 0x0100#7F4– 0x0100#7FF # – PP Number Figure 36. PP Parameter RAM PP interrupt vectors The PP interrupts and their vector addresses are shown in Table 8. ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Table 8. PP-Interrupt Vectors NAME 42 VECTOR ADDRESS INTERRUPT TASK 0x0100#1B8 Task Interrupt PTQ 0x0100#1C4 Packet Transfer Queued PTERR 0x0100#1C8 Packet-Transfer Error PTEND 0x0100#1CC Packet-Transfer End MPMSG 0x0100#1D0 MP Message PP0MSG 0x0100#1E0 PP0 Message PP1MSG 0x0100#1E4 PP1 Message PP2MSG 0x0100#1E8 PP2 Message PP3MSG 0x0100#1EC PP3 Message POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP data-unit architecture The data unit has independent data paths for the ALU and the multiplier, each with its own set of hardware functions. The multiplier data path includes a 16 × 16 multiplier, a halfword swapper, and rounding hardware. The ALU data path includes a 32-bit three-input ALU, a barrel rotator, mask generator, mf expander, left/rightmost one and left/rightmost bit-change logic, and several multiplexers. Figure 37 shows the data-unit block diagram. src1 / src2 / dstc / 0 dst2 src3 src4 src4 / src2 0 src1 / 0x1 d0 Rotate Amount Multiplexer mf dst / dst1 Mask Generator Multiplexer Expander LMO, RMO, LMBC, RMBC Barrel Rotator Mask Generator C Port Multiplexer Multiplier (Splittable) Barrel Rotator Input Sign Bit Scale Round A B Three-Input ALU (Splittable) Swap / Merge C ALU Function Code Logic N, C, V, Z, LV mf Legend: src1 scr2 scr3 scr4 dst/dst1 Any register, D reg only for l/rmo, l/rmbc hardware D reg or sometimes 15/32-bit immediate D reg only D reg only Any register dst2 dstc 0x1 0 d0 D reg only D reg only (destination companion reg source) Constant Constant 5 LSBs of d0 Figure 37. Data Unit Block Diagram The PP’s ALU can be split into one 32-bit ALU, two 16-bit ALUs, or four 8-bit ALUs. Figure 38 shows the multiple arithmetic data flow for the case of a four 8-bit split of the ALU (called multiple-byte arithmetic). The ALU operates as independent parallel ALUs where each ALU receives the same function code. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP data-unit architecture (continued) 32 Rotate Clear mf Register 4 Expander (Replicate) 8 8 8 8 sr(C) A B C C-Out A C-IN 8 B C C-Out C-IN Logic A C-IN 8 C, Z, S, or E C, Z, S, or E B C C-Out C-IN Logic C-IN A 8 C, Z, S, or E B C C-Out C-IN Logic C-IN C-IN Logic 8 C, Z, S, or E Figure 38. Multiple-Byte Arithmetic Data Flow PP multiplier The PP’s hardware multiplier can perform one 16x16 multiply with a 32-bit result or two 8x8 multiplies with two 16-bit results in a single cycle. A 16x16 multiply can use signed or unsigned operands as shown in Figure 39. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 X X X X X X X X X X X X X X X X S 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 S S 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Signed Input 14 13 12 11 10 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 Signed × Signed Result 15 14 13 12 Unsigned Input 15 14 13 12 11 10 9 8 7 6 Unsigned × Unsigned Result Figure 39. 16 x 16 Multiplier Data Formats When performing two simultaneous 8x8 split multiplies, the first input word contains unsigned byte operands and the second input word contains signed or unsigned byte operands. These formats are shown in Figure 40 and Figure 41. 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP multiplier (continued) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 X X X X X X X X X X X X X X X X S 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1b × 2b Signed Result S 15 14 13 12 11 10 9 8 7 6 Unsigned Input 1b 14 13 12 11 10 9 13 12 11 10 9 4 3 2 1 0 Unsigned Input 1a 8 Signed Input 2b 14 5 7 6 S 8 7 5 4 3 2 1 0 Signed Input 2a 6 5 4 3 2 1 0 4 3 2 1 0 1a × 2a Signed Result S Figure 40. Signed Split Multiply Data Formats 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Unsigned Input 1b 15 14 13 12 11 10 9 8 7 6 Unsigned Input 2b 15 14 13 12 11 1b × 2b Unsigned Result 10 9 5 Unsigned Input 1a 5 4 3 2 1 0 Unsigned Input 2a 8 7 6 5 4 3 2 1 0 1a × 2a Unsigned Result Figure 41. Unsigned Split Multiply Data Formats PP program-flow-control unit architecture The PP has a three-stage fetch, address, execute (FAE) pipeline as shown in Figure 42. The pc, ipa, and ipe registers point to the address of the instruction in each stage of the pipeline. On each cycle in which the pipeline advances, ipa is copied into ipe, pc is copied into ipa, and the pc is incremented by one instruction (8 bytes). The program-flow-control (pfc) unit performs instruction fetching and decoding, loop control, and handshaking with the transfer controller. The pfc unit architecture is shown in Figure 43. pc Instruction One Two Three T1 T2 T3 T4 Fetch Address Execute Fetch Address Execute Fetch Address T5 ipa Execute ipe Figure 42. FAE-Instruction Pipeline POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP program-flow-control unit architecture (continued) pc lprs incrementer Cache Controller ipa Tag Comparators ipe Tag Registers Present Bits LRU Stack Loop Controller 0 ls0 le0 lctl Comparator Instruction Decode lr0 FAE Pipeline Control decr. Control Signal Generation lc0 zero Loop Control Loop Controller 1 Instruction Control Signal Instruction Address Loop Controller 2 Figure 43. Program-Flow-Control Unit Block Diagram PP address-unit architecture The PP has both a local- and global-address unit which operate independently of each other. The address units support twelve different addressing modes. In place of performing a memory access, either or both of the address units can perform an address computation that is written directly to a PP register instead of being used for a memory access. This address-unit arithmetic provides additional arithmetic operation to supplement the data unit during compute-intensive algorithms. Figure 44 shows the address-out architecture. 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP address-unit architecture (continued) From Global Destination Bus Offset To Global Source Bus From Global Destination Bus Offset To Global Source Bus sp = a6 (local) sp = a14 (global) a0 – a4 (a7 = 0) a8 – a12 (a15 = 0) x0 – x2 pba dba PP-Relative Multiplexer pba, dba Index Multiplexer Index Scaler Scale Data Size 32-Bit Adder / Subtracter Unit Preindex / Postindex Multiplexer x8 – x10 Preindex / Postindex PP-Relative Multiplexer Index Multiplexer Index Scaler Scale Data Size 32-Bit Adder / Subtracter Unit Preindex / Postindex Multiplexer Preindex / Postindex Global-Address Port Local-Address Port Figure 44. Address-Unit Architecture PP instruction set PP instructions are represented by algebraic expressions for the operations performed in parallel by the multiplier, ALU, global-address unit, and local-address unit. The expressions use the || symbol to indicate operations that are to be performed in parallel. The PP ALU operator syntax is shown in Table 9. The data unit operations (multiplier and ALU) are summarized in Table 10 and the parallel transfers (global and local) are summarized in Table 11. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP instruction set (continued) Table 9. PP Operators by Precedence OPERATOR 48 FUNCTION src1 [n] src1–1 Select odd (n=true) or even (n=false) register of D register pair based on negative condition code () Subexpression delimiters @mf Expander operator % Mask generator %% Nonmultiple mask generator (EALU only) %! Modified mask generator (0xFFFFFFFF output for 0 input) %%! Nonmultiple shift right mask generator (EALU only) \\ Rotate left << Shift left (pseudo-op for rotate and mask) >>u Unsigned shift right >> or >>s Signed shift right & Bitwise AND ^ Bitwise XOR | Bitwise OR + Addition – Subtraction =[cond] Conditional assignment =[cond.pro] Conditional assignment with status protection = Equate POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP instruction set (continued) Table 10. Summary of Data-Unit Operations Operation Base set ALUs Description Perform an ALU operation specifying ALU function, 2 src and 1 dest operand, and operand routing. ALU function is one of 256 three-input Boolean operations or one of 17 arithmetic operations combined with one of 15 function modifiers. Syntax dst = [fmod] [ [[cond [.pro] ]] ] ALU_EXPRESSION Examples d6 = (d6 ^ d4) & d2 d3 = [nn.nv] d1 –1 Operation EALU || ROTATE Description Perform an extended ALU (EALU) operation (specified in d0) with one of two data routings to the ALU and optionally write the barrel rotator output to a second dest register. ALU Function is one of 256 Boolean or 256 arithmetic. Syntax dst1 = [ [[cond [.pro] ]] ] ealu (src2, [dst2 = ] [ [[cond]] src1 [[[n]] src1–1] \\ src3, [%] src4) dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label:EALU_EXPRESSION [ || dst2 = [[cond]] src1 [ [[n]] src1–1] \\ src3]) Examples d7 = [nn] ealu(d2, d6 = [nn] d3\\d1, %d4) d3 = mzc ealu(mylabel: d4 + (d5\\d6 & %d7) || d1 = d5\\d6) Operation MPY || ADD Description Perform a 16x16 multiply with optional parallel add or subtract. Condition code applies to both multiply and add. Syntax dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 + src1 [ [[n]] src1 –1] ] dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 – src1 [ [[n]] src1 –1] ] Example d7 = u d6 * d5 || d5 = d4 – d1 Operation MPY || SADD Description Perform a 16x16 multiply with a parallel right-shift and add or subtract. Condition code applies to multiply, shift, and add. Syntax dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 + src1 [ [[n]] src1 –1] >> –d0 dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 – src1 [ [[n]] src1 –1] >> –d0 Examples d7 = u d6 * d5 || d5 = d4 – d1 >> –d0 Operation MPY || EALU Description Perform a multiply and an optional parallel EALU. Multiply can use rounding, scaling, or splitting features. Syntax Generic Form: dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[cond [.pro] ]] ] ealu[f] (src2, src1 [ [[n]] src1 –1] \\ d0, %d0) dst2 = [sign] [ [[cond]] ] src3 * src4 || ealu() Explicit Form: dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label: EALU_EXPRESSION) dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || ealu (label) Examples d7 = [p] d5 * d3 || d2 = [p] ealu(d1, d6\\d0, %d0) d2 = m d4 * d7 || d3 = ealu (mylabel: d3 + d2 >> 9) Operation divi Description Perform one iteration of unsigned divide algorithm. Generates one quotient bit per execution using iterative subtraction. Syntax dst1 = [ [[cond [.pro] ]] ] divi (src2, dst2 = [[cond]] src1 [ [[n]] src1 –1]) Examples d3 = divi (d1, d2 = d2) d3 = divi (d1, d2 = d3[n]d2) Legend: [] [[ ]] pro f Optional parameter extension Square brackets ([ ]) must be used Protect status bits Use 1s compliment of d0 cond fmod dms sign POST OFFICE BOX 1443 ; generic form ; explicit form Condition code Function modifier Default multiply shift amount u = unsigned, s = signed • HOUSTON, TEXAS 77251–1443 49 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP instruction set (continued) Table 10. Summary of Data-Unit Operations (Continued) Misc. Operations dint; eint; nop; dloop; eloop; qwait Description Globally disable interrupts; globally enable interrupts; do nothing in the data unit; globally enable looping; globally disable looping; wait until comm register Q bit is zero. Syntax dint dloop eint eloop nop qwait Legend: [] [[ ]] pro f 50 Optional parameter extension Square brackets ([ ]) must be used Protect status bits Use 1s compliment of d0 POST OFFICE BOX 1443 cond fmod dms sign Condition code Function modifier Default multiply shift amount u = unsigned, s = signed • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP instruction set (continued) Table 11. Summary of Parallel Transfers Operation Load Description Transfer from memory into PP register Syntax dst = [sign] [size] [ [[cond]] ]* addrexp dst = [sign] [size] [ [[cond]] ]* an.element Examples d3 = uh[n]* (a9++=[2]) d1 = * a2.sMY_ELEMENT Operation Store Description Transfer from PP register into memory Syntax * addrexp = [size] src [ [[n]] src–1] * an.element = [size] src [ [[n]] src–1] Examples *––a2 = d3 *a9.sMY_ELEMENT = a3 Operation Address unit arithmetic Description Compute address and store in PP register Syntax dst = [size] [ [[cond]] ] & * addrexp dst = [size] [ [[cond]] ] & * an.element Examples d2 = &*(a3 + x0) a1 = &*a9.sMY_ELEMENT Operation Move Description Transfer from PP register to PP register Syntax dst = [g] [ [[cond]] ] src Examples x2 = mf d1 = g d3 Operation Field extract move Description Transfer from PP register to PP register extracting and right-aligning one byte or halfword Syntax dst = [sign] [size item] Example d3 = ub2 d1 Operation Field replicate move Description Transfer from PP register to PP register replicating the LSbyte or LShalfword to 32 bits Syntax dst = r [size] [[cond]] src Example d7 = rh d3 Legend: [] [[ ]] g item Optional parameter extension Square brackets ([ ]) must be used Use global unit 0 = byte0/halfword0, 1 = byte1/halfword1, 2 = byte2, 3 = byte3 POST OFFICE BOX 1443 cond sign size Condition code u = unsigned, s = signed b = byte, h = halfword, w = word (default) • HOUSTON, TEXAS 77251–1443 51 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP opcode formats A PP instruction uses a 64-bit opcode. The opcode is divided essentially into a data unit portion and a parallel transfer portion. There are five data unit opcode formats comprising bits 38–63 of the opcode. Bits 0–38 of the opcode specify one of 10 parallel transfer formats. An alphabetical list of the mnemonics used in Figure 45 for the data unit and parallel transfer portions of the opcode are shown in Table 12 and Table 13, respectively. Data Unit Formats 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 0 1 1 oper dst1 src1 1 class A ALU Operation dst src1 0 1 class A ALU Operation dst src1 1 0 – 1 class A ALU Operation dst src1 1 1 src3 dst2 src4 1 0 0 0 1 – 0 – 0 – 0 – 0 – – – – – – 0 0 0 3 2 1 0 src2 Parallel Transfers A. Six-Operand (MPYIIADD, etc.) imm. src2 Parallel Transfers B. Base Set ALU (5-Bit Immediate) Parallel Transfers C. Base Set ALU (Register src2) src2 dstbank s1bnk cond Operation 32-Bit Immediate Parallel Transfers D. Base Set ALU (32-Bit Immediate) E. Miscellaneous Reserved 0 1 0 Reserved Transfer Formats 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 0 9 8 7 6 5 4 3 2 1 0 0 Lmode d e size s La Gim/X reg e size s Ga Lim/X 1. Double Parallel Lmode d e size s La 0 Lrm dstbank L 0 0 0 0 src srcbank dst Lim/X 2. Move II Local Lmode d e size s La 0 Lrm dstbank L 0 0 0 1 src e size D dst Lim/X 3. Field Move II Local Lmode reg e size s La 1 Lrm bank L 0 0 bank L 0 0 Lmode Global Long Offset /X d e size s La 0 Lrm L 0bank Gmode Local Long Offset / X Gmode reg e size s Ga 4. Local (Long Offset) 0 L 0 0 1 – – – – As1bank – – – cond c r g N C V Z 0 – – dstbank – 0 0 0 0 src srcbank dst – 0 0 – cond c r g N C V Z 0 dstbank – 0 0 0 1 src e size D dst 0 0 – cond c r g N C V Z Gim/X bank L reg e size s Ga 0 0 – cond c r – N C V Z 0 – – Adstbank itm Adstbank L 0 0 – Gmode – 0 0 1 – – – – As1bank POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Grm Lim/X 5. Global (Long Offset) 6. Non-D DU II Local – – 7. Conditional DU II Conditional Mode – – – 8. Conditional DU II Conditional Field Move 1 Grm – – – – Figure 45. PP Opcode Formats 52 1 – 9. Conditional DU II Conditional Global – 10. Conditional Non-D DU TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP opcode formats (continued) Table 12. Data Unit Mnemonics MNEMONIC FUNCTION A A = 1 selects arithmetic operations, A = 0 selects Boolean operations ALU Operation For Boolean operation (A = 0) select the 8 ALU function signals. For arithmetic operation (A = 1), odd bits specify the ALU function and even bits define the ALU function modifiers. class Operation class, determines routing of ALU operands cond condition code dst D register destination or lower 3 bits of non-D register code dst1 ALU dest. for MPY||ADD, MPY||EALU, or EALU||ROTATE operation. D register or lower 3 bits of non-D register code dst2 Multiply dest. for MPY||ADD or MPY||EALU operation or rotate dest. for EALU||ROTATE operation. D register dstbank ALU register bank imm.src2 5-bit immediate for src2 of ALU operation 32-Bit Immediate 32-bit immediate for src2 of ALU operation oper Six-operand data unit operation (MPY||ADD, MPY||SADD, MPY||EALU, EALU||ROTATE, divi) Operation Miscellaneous operation src1 ALU source 1 register code (D register unless srcbank or s1bank is used) src2 D register used as ALU source 2 src3 D register for multiplier source (MPY||ADD or MPY||EALU) or rotate amount (EALU||ROTATE) src4 D reg for ALU C port operand or EALU||ROTATE mask generator input or multiplier source 2 for MPY||ADD, MPY||EALU s1bnk Bits 5-3 of src1 register code (bit 6 assumed to be 0) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP opcode formats (continued) Table 13. Parallel Transfer Mnemonics MNEMONIC FUNCTION 0bank Bits 5–3 of global transfer source/destination register code (bit 6 assumed to be 0) Adstbnk Bits 6–3 of ALU destination register code As1bank Bits 6–3 of ALU source 1 register code bank Bits 6–3 of global (or local) store source or load destination c Conditional choice of D register for src1 operand of the ALU C Protect status register’s carry bit cond Condition code d D register or lower 3 bits of register code for local transfer source/destination D Duplicate least significant data during moves dst The three lowest bits of the register code for move or field move destination dstbank Bits 6–3 of move destination register code e Sign extend local (bit 31), sign extend global (bit 9) g Conditional global transfer Ga Global address register for load, store, or address unit arithmetic Gim / X Global address unit immediate offset or index register Gmode Global unit addressing mode Grm Global PP-relative addressing mode itm Number of item selected for field extract move L L = 1 selects load operation, L = 0 selects store / address unit arithmetic operation La Local address register for load, store, or address unit arithmetic Lim / X Local address unit immediate offset or index register Lmode Local unit addressing mode Lrm Local PP-relative addressing mode N Protect status register’s negative bit r Conditional write of ALU result reg Register number used with bank or 0bank for global load, store, or address unit arithmetic s Enable index scaling. Additional index bit for byte accesses or arithmetic operations (bit 28, local; bit 6, global) size Size of data transfer (bits 30 – 29, local; bits 8 – 7, global) src Three lowest bits of register code for register-register move source or non-field moves. D register source for field move srcbank Bits 6–3 of register code for register-register move source V Protect status register’s overflow bit Z Protect status register’s zero bit – Unused bit (fill with 0) 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP opcode formats (continued) Table 14 summarizes the supported parallel-transfer formats, their formats, and whether the transfers are local or global. It also lists the allowed ALU operations and states whether conditions and status protection are supported. Table 14. Parallel-Transfer Format Summary FORMAT GLOBAL TRANSFER ALU OPERANDS Move LOCAL TRANSFER Load / Store / AUA Load / Store / AUA dst1 src1 Cond Status Protection Double parallel D D No No Move || Local D D No No Field move || Local D D No No Global (long offset) D D No No — Any X/long Yes — src → dst s/d Index Rel s/d Index Rel Port — Lower X/short No D X/short No Local Any Any — — — D X/short Yes Local — — — D X/short No Local — — — D ³ ³Any Local (long offset) D D No No — — — — Any X/long Yes Global Non-D DU || Local Any Any No No — — — — D X/short Yes Global Conditional move D D Yes Yes Any Any — — — — — — — Conditional field move D D Yes Yes — — — — — — — Conditional global D D Yes Yes — Any X/short Yes — — — — — — — — — — — — Conditional non-D DU Any Any Yes Yes 32-bit imm. base ALU Any Lower Yes No Legend: DU AUA s/d Rel D ³ ³Any — Data unit Address unit arithmetic Source/destination register Relative addressing support POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PP opcode formats (continued) Table 15 shows the encoding used in the opcodes to specify particular PP registers. A 3-bit register field contains the three LSBs. The register codes are used for the src, src1, src2, src3, src4, dst, dst1, dst2, d, reg, Ga, La, Gim/X, and Lim/X opcode fields. The four MSBs specify the register bank which is concatenated to the register field for the full 7-bit code. The register bank codes are used for the dstbank, s1bnk, srcbank, 0bank, bank, Adstbnk, and As1bank opcode fields. When no associated bank is specified for a register field in the opcode, the D register bank is assumed. When the MSB of the bank code is not specified in the opcode (as in 0bank and s1bnk) it is assumed to be 0, indicating a lower register. Table 15. PP Register Codes LOWER REGISTERS (MSB OF BANK = 0) CODING BANK REG 0000 000 0000 0000 REGISTER CODING BANK REG a0 0100 000 001 a1 0100 010 a2 0100 0000 011 a3 0000 100 0000 101 0000 110 0000 111 0001 000 0001 0001 UPPER REGISTERS (MSB OF BANK = 1) REGISTER CODING BANK REG d0 1000 000 001 d1 1000 010 d2 1000 0100 011 d3 a4 0100 100 reserved 0100 101 a6 (sp) 0100 a7 (zero) 0100 a8 001 010 CODING REGISTER BANK REG reserved 1100 000 lc0 001 reserved 1100 001 lc1 010 reserved 1100 010 lc2 1000 011 reserved 1100 011 reserved d4 1000 100 reserved 1100 100 lr0 d5 1000 101 reserved 1100 101 lr1 110 d6 1000 110 reserved 1100 110 lr2 111 d7 1000 111 reserved 1100 111 reserved 0101 000 reserved 1001 000 reserved 1101 000 lrse0 a9 0101 001 sr 1001 001 reserved 1101 001 lrse1 a10 0101 010 mf 1001 010 reserved 1101 010 lrse2 0001 011 a11 0101 011 reserved 1001 011 reserved 1101 011 reserved 0001 100 a12 0101 100 reserved 1001 100 reserved 1101 100 lrs0 0001 101 reserved 0101 101 reserved 1001 101 reserved 1101 101 lrs1 0001 110 a14 (sp) 0101 110 reserved 1001 110 reserved 1101 110 lrs2 0001 111 a15 (zero) 0101 111 reserved 1001 111 reserved 1101 111 reserved 0010 000 x0 0110 000 reserved 1010 000 reserved 1110 000 ls0 0010 001 x1 0110 001 reserved 1010 001 reserved 1110 001 ls1 0010 010 x2 0110 010 reserved 1010 010 reserved 1110 010 ls2 0010 011 reserved 0110 011 reserved 1010 011 reserved 1110 011 reserved 0010 100 reserved 0110 100 reserved 1010 100 reserved 1110 100 le0 0010 101 reserved 0110 101 reserved 1010 101 reserved 1110 101 le1 0010 110 reserved 0110 110 reserved 1010 110 reserved 1110 110 le2 0010 111 reserved 0110 111 reserved 1010 111 reserved 1110 111 reserved 0011 000 x8 0111 000 pc/call 1011 000 reserved 1111 000 reserved 0011 001 x9 0111 001 ipa/br 1011 001 reserved 1111 001 reserved 0011 010 x10 0111 010 ipe # 1011 010 reserved 1111 010 reserved 0011 011 reserved 0111 011 iprs 1011 011 reserved 1111 011 reserved 0011 100 reserved 0111 100 inten 1011 100 reserved 1111 100 tag0 # 0011 101 reserved 0111 101 intflg 1011 101 reserved 1111 101 tag1 # 0011 110 reserved 0111 110 comm 1011 110 reserved 1111 110 tag2 # 0011 111 reserved 0111 111 lctl 1011 111 reserved 1111 111 tag3 # # Read only 56 REGISTER POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 data unit operation code For data unit opcode format A, a 4-bit operation code specifies one of 16 six-operand operations and an associated data path, as shown in Table 16. Table 16. Six Operand Format Operation Codes oper FIELD BIT 60 59 58 57 OPERATION TYPE 0 u 0 s MPY || ADD 0 u 1 f MPYU || EALU 1 0 f k EALU || ROTATE 1 0 1 0 divi 1 1 u s MPY || SADD Legend: u Unsigned f 1s complement EALU function code s Subtract k Use mask or mf expander operation class code The base set ALU opcodes (formats B, C, D) use an operation class code to specify one of eight different routings to the A, B, and C ports of the ALU, as shown in Table 17. Table 17. Base Set ALU Class Summary CLASS DESTINATION A PORT 000 dst src2 src1 001 dst dstc src1 010 dst dstc src1 011 dst dstc src1 \\ src2 100 dst src2 src1 \\ d0 %d0 101 dst src2 src1 \\ d0 @mf 110 dst dstc src1 111 dst src1 1 \\ src2 Legend: \\ @mf % dstc dst src2 srd1 B PORT C PORT @mf \\ d0 src2 %src2 %src2 src2 src2 Rotate left Expand function Mask generation Companion D reg Destination Dreg or any reg if dstbank or Adstbnk is used with destination. Source D reg or immediate Source D reg or any if As1bank is used or any lower reg if s1bnk is used POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 ALU-operation code For base-set ALU Boolean opcodes (A=0), the ALU function is formed by a sum of Boolean products selected by the ALU operation opcode bits as shown in Table 18. For base-set arithmetic opcodes (A=1), the four odd ALU operation bits specify an arithmetic operation as described in Table 19 while the four even bits specify one of the ALU function modifiers as shown in Table 20. Table 18. Base-Set ALU Boolean Function Codes ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ OPCODE BIT PRODUCT TERM 58 A&B&C 57 ~A & B & C 56 A & ~B & C 55 ~A & ~B & C 54 A & B & ~C 53 ~A & B & ~C 52 A & ~B & ~C 51 ~A & ~B & ~C Table 19. Base-Set Arithmetics OPCODE BITS CARRY IN ALGEBRAIC DESCRIPTION NATURAL FUNCTION MODIFIED FUNCTION (IF DIFFERENT FROM NATURAL FUNCTION) 57 55 53 51 0 0 0 0 x 0 0 0 1 1 A – (B | C) A – B <1< 0 0 1 0 0 A + (B & ~C) A + B <0< 0 0 1 1 1 A–C A–C 0 1 0 0 1 A – (B | ~C) A – B >1> 0 1 0 1 1 A–B A–B 0 1 1 0 C(n) A – (B & @mf | –B & ~@mf) A+B/A–B if class 0 or 5 1/0 A + |B| A+B/A–B if class 1–4 or 6–7, A–B if sign=1 0 1 1 1 1 A – (B & C) A – B>0> 1 0 0 0 0 A + (B & C) A + B>0> 1 0 0 1 ~C(n) A + (B & @mf | –B & ~@mf) A–B/A+B if class 0 or 5 0/1 A – |B| A–B/A+B if class 1–4 or 6–7, A+B if sign=1 1 0 1 0 0 A+B A+B 1 0 1 1 0 A + (B | ~C) A + B >1> 1 1 0 0 0 A+C A+C 1 1 0 1 1 A – (B & ~C) A – B <0< 1 1 1 0 0 A + (B | C) A + B <1< 1 1 1 1 0 (A & C) + (B & C) field A + B Legend: C(n) >0> <0< >1> <1< 58 (A – (B & C)) if sign=0 LSB of each part of C port register Zero-extend shift right Zero-extend shift left One-extend shift right One-extend shift left POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 (A + (B & C)) if sign=0 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 ALU-operation code (continued) Table 20. Function Modifier Codes FUNCTION MODIFIER BITS MODIFICATION PERFORMED 58 56 54 52 0 0 0 0 Normal operation 0 0 0 1 cin 0 0 1 0 %! if maskgen instruction, lmo if not maskgen 0 0 1 1 %! and cin if maskgen instruction, rmo if not maskgen 0 1 0 0 A port = 0 0 1 0 1 A port = 0 and cin 0 1 1 0 A port = 0 and %! if maskgen, lmbc if not maskgen 0 1 1 1 A port = 0, %! and cin if maskgen, rmbc if not maskgen 1 0 0 0 mf bit(s) set by carry out(s). (mc) 1 0 0 1 mf bit(s) set based on status register MSS field. (me) 1 0 1 0 Rotate mf by Asize, mf bit(s) set by carry out(s). (mrc) 1 0 1 1 Rotate mf by Asize, mf bit(s) set based on status register MSS field. (mre) 1 1 0 0 Clear mf, mf bit(s) set by carry out(s). (mzc) 1 1 0 1 Clear mf, mf bit(s) set based on status register MSS field. (mze) 1 1 1 0 No setting of bits in mf register. (mx) 1 1 1 1 Reserved Legend: cin lmbc lmo Carry in from sr(C) Leftmost-bit change Leftmost one %! rmbc rmo Modified mask generator Rightmost-bit change Rightmost one miscellaneous operation code For data-unit opcode format E, the operation field selects one of the miscellaneous operations codes as shown in Table 21. Table 21. Miscellaneous Operation Codes OPCODE BITS MNEMONIC OPERATION 0 nop No data-unit operation. Status not modified 0 1 qwait 1 0 eint Global-interrupt enable 0 1 1 dint Global-interrupt disable 0 1 0 0 eloop Global loop enable 0 1 0 1 dloop Global loop disable 0 0 1 1 x reserved 0 1 x x x reserved 1 x x x x reserved 43 42 41 40 39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POST OFFICE BOX 1443 Wait until comm Q bit is clear • HOUSTON, TEXAS 77251–1443 59 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 addressing-mode codes The Lmode (bits 35–38) and Gmode (bits 13–16) of the opcode specify the local and global transfer for various parallel transfer opcode formats (Lmode in formats 1, 2, 3, 4, and 6 and Gmode in formats 1, 5, and 9). Table 22 shows the coding for the addressing-mode fields. Table 22. Addressing-Mode Codes CODING EXPRESSION DESCRIPTION 00xx Legend: an imm xm Nop (nonaddressing mode operation) 0100 *(an ++= xm) Postaddition of index register, with modify 0101 *(an – – = xm) Postsubtraction of index register, with modify 0110 *(an ++= imm) Postaddition of immediate, with modify Postsubtraction of immediate, with modify 0111 *(an – – = imm) 1000 *(an + xm) Preaddition of index register 1001 *(an – xm) Presubtraction of index register 1010 *(an + imm) Preaddition of immediate 1011 *(an – imm) Presubtraction of immediate 1100 *(an += xm) Preaddition of index register, with modify 1101 *(an – = xm) Presubtraction of index register, with modify 1110 *(an += imm) Preaddition of immediate, with modify 1111 *(an – = imm) Presubtraction of immediate, with modify Address register in l/g address unit Immediate offset Index register in same unit as an register L, e codes The L and e bits combine to specify the type of parallel transfer performed, as shown in Table 23. For the local transfer, L and e are bits 21 and 31, respectively. For the global transfer, L and e are bits 17 and 9, respectively. Table 23. Parallel Transfer Type L e 1 0 Zero-extend load PARALLEL TRANSFER 1 1 Sign-extend load 0 0 Store 0 1 Address unit arithmetic size codes The size code specifies the data transfer size. For field moves (parallel transfer format 3), only byte and halfword data sizes are valid, as shown in Table 24. ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ Table 24. Transfer Data Size CODING 60 DATA SIZE 00 Byte (8 bits) 01 Halfword (16 bits) 10 Word (32 bits) 11 Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 relative-addressing mode codes The Lrm and Grm opcode fields allow the local-address or global-address units, respectively, to select PP-relative addressing as shown in Table 25. ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Table 25. Relative-Addressing Mode Codes CODING RELATIVE-ADDRESSING MODE 00 Normal (absolute addressing) 01 Reserved 10 PP-relative dba 11 PP-relative pba Legend: dba – Data RAM 0 base is base address pba – Paramater RAM base is base address condition codes In the four conditional parallel transfer opcodes (formats 7–10), the condition code field specifies one of 16 condition codes to be applied to the data-unit operation source, data-unit result, or global transfer based on the setting of the c, r, and g bits, respectively. Table 26 shows the condition codes. For the 32-bit immediate data unit opcode (format D), the condition applies to the data-unit result only. Table 26. Condition Codes CONDITION BITS MNEMONIC DESCRIPTION STATUS BIT COMBINATION 35 34 33 32 0 0 0 0 u Unconditional (default) None 0 0 0 1 p Positive ~N & ~Z 0 0 1 0 ls Lower than or same ~C | Z 0 0 1 1 hi Higher than C & ~Z 0 1 0 0 lt Less than (N & ~V) | (~N & V) 0 1 0 1 le Less than or equal (N & ~V) | (~N & V) | Z 0 1 1 0 ge Greater than or equal (N & V) | (~N & ~V) 0 1 1 1 gt Greater than (N & V & ~Z) | (~N & ~V & ~Z) 1 0 0 0 hs, c Higher than or same, carry C 1 0 0 1 lo, nc Lower than, no carry ~C 1 0 1 0 eq, z Equal, zero Z 1 0 1 1 ne, nz Not equal, not zero ~Z 1 1 0 0 v Overflow V 1 1 0 1 nv No overflow ~V 1 1 1 0 n Negative N 1 1 1 1 nn Nonnegative ~N EALU operations Extended ALU (EALU) operations allow the execution of more advanced ALU functions than those specified in the base set ALU opcodes. The opcode for EALU instructions contains the operands for the operation while the d0 register extends the opcode by specifying the EALU operation to be performed. The format of d0 for EALU operations is shown in Figure 24. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 EALU Boolean functions EALU operations support all 256 Boolean ALU functions plus the flexibility to add 1 or a carry-in to Boolean sum. The Boolean function performed by the ALU are shown below and in Table 27. (F0 & (~A & ~B & ~C)) | (F1 & (A & ~B & ~C)) | (F2 & (~A & B & ~C)) | (F3 & (A & B & ~C)) | (F4 & (~A & ~B & C)) | (F5 & (A & ~B & C)) | (F6 & (~A & B & C)) | (F7 & (A & B & C)) [+1 | +cin] Table 27. EALU Boolean Function Codes d0 BIT ALU FUNCTION SIGNAL 26 F7 PRODUCT TERM A&B&C 25 F6 ~A & B & C 24 F5 A & ~B & C 23 F4 ~A & ~B & C 22 F3 A & B & ~C 21 F2 ~A & B & ~C 20 F1 A & ~B & ~C 19 F0 ~A & ~B & ~C EALU arithmetic functions EALU operations support all 256 arithmetic functions provided by the three-input ALU plus the flexibility to add 1 or a carry-in to the result. The arithmetic function performed by the ALU is: f(A,B,C) = A & f1(B,C) + f2(B,C) [+1 | cin] f1(B,C) and f2(B,C) are independent Boolean combinations of the B and C ALU inputs. The ALU function is specified by selecting the desired f1 and f2 subfunction and then XORing the f1 and f2 code from Table 28 to create the ALU function code for bits 19–26 of d0. Additional operations such as absolute values and signed shifts can be performed using d0 bits which control the ALU function based on the sign of one of the inputs. Table 28. ALU f1(B,C) and f2(B,C) Subfunctions 62 f1 CODE f2 CODE 00 00 0 Zero the term AA FF –1 –1 (All 1s) 88 CC B B SUBFUNCTION COMMON USAGE 22 33 –B –1 Negate B A0 F0 C C 0A 0F –C –1 Negate C 80 C0 B&C Force bits in B to 0 where bits in C are 0 2A 3F –(B & C) – 1 Force bits in B to 0 where bits in C are 0 and negate A8 FC B|C Force bits in B to 1 where bits in C are 1 02 03 –(B | C) – 1 Force bits in B to 1 where bits in C are 1 and negate 08 0C B & ~C Force bits in B to 0 where bits in C are 1 A2 F3 –(B & ~C) –1 Force bits in B to 0 where bits in C are 1 and negate 8A CF B | ~C Force bits in B to 1 where bits in C are 0 20 30 –(B | ~C) –1 Force bits in B to 1 where bits in C are 0 and negate 28 3C (B & ~C) | ((–B – 1) & C) Choose B if C = all 0s and –B if C = all 1s 82 C3 (B & C) | ((–B – 1) & ~C) Choose B if C = all 1s and –B if C = all 0s POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 video controller architecture The video controller (VC) provides a method for handling the video or graphics capture, or display portions of a TMS320C80 system. It provides simultaneous control over two independent capture or display systems and frame grabber or frame buffer image storage. VC functional block diagram Figure 46 shows a functional block diagram of the video controller. Key features of the VC include: D D D Dual-frame timers – Independent or locked operation – Programmable horizontal and vertical timing – Separate or composite sync and blanking control – Synchronization to external timing signals – Interlaced or noninterlaced frame control – Virtually limitless screen resolutions Programmable timing and control registers Programmable line interrupt to MP Shift register transfer (SRT) controller – Generates VRAM serial register transfer requests to the TC – Tracks VRAM tap point and schedules midline reloads – Generates packet-transfer requests for DRAM-based buffer updates – Supports two display or capture buffers On-Chip Register Bus (MP) 32 VC Register Interface HSYNC0 FT0 Events Frame Timer 0 VC Request (to TC) VSYNC0 CSYNC0 / HBLNK0 CBLNK0 / VBLNK0 CAREA0 SRT Controller MUX D HSYNC1 Frame Timer 1 FT1 Events SCLK1 SCLK0 VSYNC1 CSYNC1 / HBLNK1 CBLNK1 / VBLNK1 CAREA1 FCLK1 FCLK0 Figure 46. VC Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 frame-timer registers Each frame timer has twenty-one 16-bit registers to control its horizontal and vertical timing signals. The registers are on-chip memory-mapped registers accessible by the MP only. Each horizontal / vertical register pair can be accessed as a single 32-bit quantity. The register map for Frame-Timer 0 is shown in Figure 47. The Frame-Timer 1 register map is shown in Figure 48. Address Address FTCTL0 0x01820200 SETVCT0 0x01820206 SETHCT0 0x01820204 VFTINT0 0x0182020A HESERR0 0x01820208 VESYNC0 0x0182020E HESYNC0 0x0182020C VEBLNK0 0x01820212 HEBLNK0 0x01820210 VSAREA0 0x01820216 HSAREA0 0x01820214 VEAREA0 0x0182021A HEAREA0 0x01820218 VSBLNK0 0x0182021E HSBLNK0 0x0182021C VTOTAL0 0x01820222 HTOTAL0 0x01820220 HALINE0 0x01820224 HBLINE0 0x01820228 HCOUNT0 0x0182023C VCOUNT0 0x0182023E Figure 47. Frame-Timer 0 Register Map Address Address FTCTL1 0x01820240 SETVCT1 0x01820246 SETHCT1 0x01820244 VFTINT1 0x0182024A HESERR1 0x01820248 VESYNC1 0x0182024E HESYNC1 0x0182024C VEBLNK1 0x01820252 HEBLNK1 0x01820250 VSAREA1 0x01820256 HSAREA1 0x01820254 VEAREA1 0x0182025A HEAREA1 0x01820258 VSBLNK1 0x0182025E HSBLNK1 0x0182025C VTOTAL1 0x01820262 HTOTAL1 0x01820260 HALINE1 0x01820264 HBLINE1 0x01820268 HCOUNT1 0x0182027C VCOUNT1 0x0182027E Figure 48. Frame-Timer 1 Register Map frame-timer register programming The register format for the frame-timer control registers is shown in Figure 49. All other registers are 16-bit values. For programming details, see the TMS320C80 Video Controller User’s Guide (literature number SPRU111). 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 frame-timer control (FTCTLx) register The FTCTLx register contains mode bits to determine frame-timer behavior. 15 14 13 FTE IFD IIM FTE IFD IIM SSE FLE CPM 12 11 10 9 8 SSE FLE 7 6 5 4 3 CPM Frame-timer enable Interlaced frame disable Interlace interrupt mode Set synchronization enable Frame lock enable CSYNC / HBLNK pin mode 00 – CSYNC Hi-Z 10 – CSYNC output 11 – HBLNK output 01 – CSYNC input VPM HPM 2 1 VPM VSYNC Pin Mode 00 – Hi-Z 01 – Input HSYNC Pin Mode 00 – Hi-Z 01 – Input 0 HPM 10 – Output 11 – Reserved 10 – Output 11 – Reserved Figure 49. FTCTLx Register SRT controller registers The SRT controller has two sets of 32-bit registers, one for each of the supported frame memory regions. The location of these registers in on-chip memory-mapped register space is shown in Figure 50. Address Address FMEMCTL0 0x01820300 FMEMCTL1 0x01820340 F1STADR0 0x01820304 F1STADR1 0x01820344 F0STADR0 0x01820308 F0STADR1 0x01820348 LINEINC0 0x0182030C LINEINC1 0x0182034C SAMMASK0 0x01820310 SAMMASK1 0x01820350 NEXTADR0 0x01820314 NEXTADR1 0x01820354 CRNTADR0 0x0182033C CRNTADR1 0x0182037C Figure 50. SRT Controller Register Map SRT controller register programming The register format for the frame memory control registers is shown in Figure 51. All other registers are 32-bit values. For programming details, see the TMS320C80 Video Controller User’s Guide (literature number SPRU111). FMEMCTLx Register The frame memory control (FMEMCTLx) register contains mode bits to determine operation of the associated frame memory. 31 30 29 HSS ILR PTS TMS 28 27 26 25 24 23 Half-SAM select Interlaced line repeat Packet transfer select Transfer mode select 00 – Display 01 – Reserved 22 21 20 19 18 17 16 15 14 13 12 H S S I L R P T S EMS 10 – Capture 11 – Merge capture UED FTS 11 10 9 8 TMS 7 6 5 EMS 4 3 U E D 2 1 0 FTS Event mode select 00 – sof, line, sam 10 – sof, line 01 – sof, eof, sam 11 – none Unblanked event disable Frame timer sequencer 00 – ft0 / disabled 10 – ft1 / disabled 01 – ft0 / enabled 11 – ft1 / enabled Figure 51. FMEMCTLx Register POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 TC architecture The transfer controller (TC) is a combined memory controller and DMA (direct memory access) machine. It handles the movement of data within the ’C80 system as requested by the master processor, parallel processors, video controller, and external devices. The transfer controller performs the following data movement and memory control functions: D D D D D D D D D MP and PP instruction cache fills MP data cache fills and dirty block write-back MP and PP direct external accesses (DEAs) MP and PP packet transfers Externally initiated packet transfers (XPTs) VC packet transfers (VCPTs) VC shift register transfers (SRTs) DRAM/ SDRAM refresh Host bus request TC functional block diagram Figure 52 shows a functional block diagram of the transfer controller. Key features of the TC include: D D Crossbar interface – 64-bit data path – Single-cycle access External memory interface – 4G-Byte address range – Dynamically configurable memory cycles 8-, 16-, 32-, or 64-bit bus size Selectable memory page size Selectable address multiplexing Selectable cycle timing – D D D 66 Big- or little-endian operation Cache, VRAM, refresh controller – Programmable refresh rate – VRAM block write support Independent Src and Dst addressing – Autonomous addressing based on packet-transfer parameters – Data read and write at different rates – Numerous data merging and alignment functions performed during transfer Intelligent request prioritization POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 TC functional block diagram (continued) Packet Transfer FIFO Src MUX and Alignment Dst MUX and Alignment Cache Buffer 64 Crossbar Interface External Memory Interface 64 64 Src Controller 64 Dst Controller Cache, VRAM, and Refresh Controller Src Control Registers Dst Control Registers Request Queuing and Prioritization MP Requests PP Requests VC Requests XPT Requests Host Requests Figure 52. TC Block Diagram TC registers The TC contains four on-chip memory-mapped registers accessible by the MP. TC registers are shown in Figure 53. refresh control (REFCNTL) register (0x01820000) The REFCNTL register controls refresh cycles. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RPARLD RPARLD 8 7 6 5 4 3 2 1 0 REFRATE Refresh Pseudo-Address Reload Value REFRATE Refresh Interval (in clock cycles) Figure 53. REFCNTL Register packet-transfer minimum (PTMIN) register (0x01820004) The PTMIN register determines the minimum number of cycles that a packet transfer executes before being suspended by a higher priority packet transfer. Figure 54 shows the PTMIN register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTMIN Figure 54. PTMIN Register POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PT maximum (PTMAX) register (0x01820008) The PTMAX register determines the maximum number of cycles after PTMIN has elapsed that a packet transfer executes before timing out. Figure 55 showns the format of the PTMAX register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTMAX Figure 55. PTMAX Register fault status (FLTSTS) register (0x0182000C) The FLTSTS register indicates the cause of a memory access fault. Fault status bits are cleared by writing a 1 to the appropriate bit. Figure 56 shows the format of the fault status (FLTSTS) register. 31 30 29 28 PP # PC PP 27 26 25 24 P C P C P C P C 3 2 1 0 23 22 21 20 PP# 19 18 17 16 P P P P P P P P 3 2 1 0 PPx Cache / DEA Fault PPx Packet-Transfer Fault 15 14 13 12 11 10 9 8 7 6 XPT XPT M 5 4 3 2 1 0 M Faulting XPT MP Packet-Transfer Fault Figure 56. FLTSTS Register packet-transfer parameters The most efficient method for data movement in a TMS320C80 system is through the use of packet transfers (PTs). Packet transfers allow the TC to move blocks of data autonomously between a specified src and dst memory region. Requests for the TC to execute a packet transfer may be made by the MP, PPs, VC, or external devices. A packet-transfer parameter table describing the data packet and how it is to be transferred must be programmed in on-chip memory before the transfer is requested. The parameter table formats for long-form and short-form packet transfers are shown in Figure 57. 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 packet-transfer parameters (continued) Byte Address PT Long-Form Parameter Table 31 0 Word Number Byte Address Short-Form Parameter Table 31 0 Next Entry Address 0 PT PT+4 PT Options 1 PT+4 PT+8 Src Start Address 0 PT+8 Src Start Address 0 Dst Start Address Dst Start Address 1 PT+12 Next Entry Address Word Number PT Options Count 0 1 1 PT+12 PT+16 Src B Count Src A Count 0 PT+20 Dst B Count Dst A Count 1 PT - 16-byte aligned on-chip starting address of parameter table. PT+24 Src C Count 0 PT+28 Dst C Count 1 PT+32 Src B Pitch 0 PT+36 Dst B Pitch 1 PT+40 Src C Pitch 0 PT+44 Dst C Pitch 1 †PT+48 Transparency/Color Word 0 0† †PT+52 Transparency/Color Word 1 1† PT+56 Don’t Care 0 PT+60 Don’t Care 1 PT - 64-byte aligned on-chip starting address of parameter table. † These words are swapped in big-endian mode. Figure 57. Packet-Transfer Parameter Table POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PT-options field The PT-options field of the parameter table controls the type of src and dst transfer that the TC performs. The formats of the options field for long-form and short-form packet transfers are shown in Figure 58. 3 1 S 30 29 PTS S PTS I RDC RDB RA RSC RSB SF X ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 28 I 27 26 Long-Form PT Options 25 24 23 22 21 20 19 R D C R D B R A R S C R S B S F X 18 17 16 PAM ÉÉ ÉÉ ÉÉ ÉÉ 15 14 13 STM PAM Stop Bit PT Status 00 – Active 10 – Fault on Src 01 – Suspended 11 – Fault on Dst Stop Bit Reverse Dst C Addressing Reverse Dst B Addressing Reverse A Addressing Reverse Src C Addressing Reverse Src B Addressing Short Form Exchange Src and Dst Parameters 12 STM / DTM SUM / DTM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 11 10 9 8 SUM ÉÉ ÉÉ ÉÉ ÉÉ 7 6 5 4 DTM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 3 2 1 0 DUM PT Access Mode 000 – Normal 100 – 8-Bit Transparency 001 – PDT 101 – 16-Bit Transparency 010 – Block Write 110 – 32-Bit Transparency 011 – SRT 111 – 64-Bit Transparency Src / Dst Transfer Mode 000 – Dimensioned 100 – Variable, Delta-Guided 001 – Fill (Src Only) 101 – Variable, Offset-Guided 010 – Reserved 110 – Fixed, Delta-Guided 011 – LUT (Src Only) 111 – Fixed, Offset-Guided Src / Dst Update Mode 00 – None 01 – Add C Pitch 01 – Add B Pitch 11 – Add C Pitch / Reverse Short-Form PT Options 3 1 S 30 29 PTS S PTS I RA 28 I ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ 27 26 25 24 Stop Bit PT Status 00 – Active 01 – Suspended Stop Bit Reverse Addressing 23 R A 22 21 20 19 S F X 18 17 16 15 14 13 12 11 PAM 10 – Fault on Src 11 – Fault on Dst POST OFFICE BOX 1443 9 8 7 6 5 4 3 Count RA X PAM Reverse Addressing Exchange Src & Dst Parameters PT Access Mode 000 – Normal 100 – Reserved 001 – PDT 101 – Reserved 010 – Reserved 110 – Reserved 011 – SRT 111 – Reserved Figure 58. PT-Options Field 70 10 • HOUSTON, TEXAS 77251–1443 2 1 0 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 LOCAL MEMORY INTERFACE status codes Status codes are output on STATUS[5:0] to describe the cycle being performed. During row time, the STATUS[5:0] pins indicate the type of cycle being performed. The cycle type can be latched using RL or RAS and used by external logic to perform memory bank decoding or to enable special hardware features. During column time, the STATUS[5:0] pins indicate the requesting processor or special column information. See Table 29 for a listing of the Row-time status codes and Table 30 for a listing of column-time status codes. Table 29. Row-Time Status Codes STATUS[5:0] CYCLE TYPE STATUS[5:0] CYCLE TYPE 0 0 0 0 0 0 Normal Read 1 0 0 0 0 0 Reserved 0 0 0 0 0 1 Normal Write 1 0 0 0 0 1 Reserved 0 0 0 0 1 0 Refresh 1 0 0 0 1 0 Reserved 0 0 0 0 1 1 SDRAM DCAB 1 0 0 0 1 1 Reserved 0 0 0 1 0 0 Peripheral Device PT Read 1 0 0 1 0 0 XPT1 Read 0 0 0 1 0 1 Peripheral Device PT Write 1 0 0 1 0 1 XPT1 Write 0 0 0 1 1 0 Reserved 1 0 0 1 1 0 XPT1 PDPT Read 0 0 0 1 1 1 Reserved 1 0 0 1 1 1 XPT1 PDPT Write 0 0 1 0 0 0 Reserved 1 0 1 0 0 0 XPT2 Read 0 0 1 0 0 1 Block Write PT 1 0 1 0 0 1 XPT2 Write 0 0 1 0 1 0 Reserved 1 0 1 0 1 0 XPT2 PDPT Read 0 0 1 0 1 1 Reserved 1 0 1 0 1 1 XPT2 PDPT Write 0 0 1 1 0 0 SDRAM MRS 1 0 1 1 0 0 XPT3 Read 0 0 1 1 0 1 Load Color Register 1 0 1 1 0 1 XPT3 Write 0 0 1 1 1 0 Reserved 1 0 1 1 1 0 XPT3 PDPT Read 0 0 1 1 1 1 Reserved 1 0 1 1 1 1 XPT3 PDPT Write 0 1 0 0 0 0 Frame 0 Read Transfer 1 1 0 0 0 0 XPT4 / SAM1 Read 0 1 0 0 0 1 Frame 0 Write Transfer 1 1 0 0 0 1 XPT4 / SAM1 Write 0 1 0 0 1 0 Frame 0 Split Read Transfer 1 1 0 0 1 0 XPT4 / SAM1 PDPT Read 0 1 0 0 1 1 Frame 0 Split Write Transfer 1 1 0 0 1 1 XPT4 / SAM1 PDPT Write 0 1 0 1 0 0 Frame 1 Read Transfer 1 1 0 1 0 0 XPT5 / SOF1 Read 0 1 0 1 0 1 Frame 1 Write Transfer 1 1 0 1 0 1 XPT5 / SOF1 Write 0 1 0 1 1 0 Frame 1 Split Read Transfer 1 1 0 1 1 0 XPT5 / SOF1 PDPT Read 0 1 0 1 1 1 Frame 1 Split Write Transfer 1 1 0 1 1 1 XPT5 / SOF1 PDPT Write 0 1 1 0 0 0 Reserved 1 1 1 0 0 0 XPT6 / SAM0 Read 0 1 1 0 0 1 Reserved 1 1 1 0 0 1 XPT6 / SAM0 Write 0 1 1 0 1 0 Reserved 1 1 1 0 1 0 XPT6 / SAM0 PDPT Read 0 1 1 0 1 1 Reserved 1 1 1 0 1 1 XPT6 / SAM0 PDPT Write 0 1 1 1 0 0 PT Read Transfer 1 1 1 1 0 0 XPT7 / SOF0 Read 0 1 1 1 0 1 PT Write Transfer 1 1 1 1 0 1 XPT7 / SOF0 Write 0 1 1 1 1 0 Reserved 1 1 1 1 1 0 XPT7 / SOF0 PDPT Read 0 1 1 1 1 1 Idle 1 1 1 1 1 1 XPT7 / SOF0 PDPT Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 status codes (continued) Table 30. Column-Time Status Codes STATUS[5:0] CYCLE TYPE 0 0 0 0 0 0 PP0 Low Priority Packet Transfer 1 0 0 0 0 STATUS[5:0] 0 Reserved 0 0 0 0 0 1 PP0 High Priority Packet Transfer 1 0 0 0 0 1 Reserved 0 0 0 0 1 0 PP0 Instruction Cache 1 0 0 0 1 0 Reserved 0 0 0 0 1 1 PP0 DEA 1 0 0 0 1 1 Reserved 0 0 0 1 0 0 PP1 Low Priority Packet Transfer 1 0 0 1 0 0 Reserved 0 0 0 1 0 1 PP1 High Priority Packet Transfer 1 0 0 1 0 1 Reserved 0 0 0 1 1 0 PP1 Instruction Cache 1 0 0 1 1 0 Reserved 0 0 0 1 1 1 PP1 DEA 1 0 0 1 1 1 Reserved 0 0 1 0 0 0 PP2 Low Priority Packet Transfer 1 0 1 0 0 0 Reserved 0 0 1 0 0 1 PP2 High Priority Packet Transfer 1 0 1 0 0 1 Reserved 0 0 1 0 1 0 PP2 Instruction Cache 1 0 1 0 1 0 Reserved 0 0 1 0 1 1 PP2 DEA 1 0 1 0 1 1 Reserved 0 0 1 1 0 0 PP3 Low Priority Packet Transfer 1 0 1 1 0 0 Reserved 0 0 1 1 0 1 PP3 High Priority Packet Transfer 1 0 1 1 0 1 Reserved 0 0 1 1 1 0 PP3 Instruction Cache 1 0 1 1 1 0 Reserved 0 0 1 1 1 1 PP3 DEA 1 0 1 1 1 1 Reserved 0 1 0 0 0 0 MP Low Priority Packet Transfer 1 1 0 0 0 0 Reserved 0 1 0 0 0 1 MP High Priority Packet Transfer 1 1 0 0 0 1 Reserved 0 1 0 0 1 0 MP Urgent Packet Transfer (Low) 1 1 0 0 1 0 Reserved 0 1 0 0 1 1 MP Urgent Packet Transfer (High) 1 1 0 0 1 1 Reserved 0 1 0 1 0 0 XPT / VCPT in Progress 1 1 0 1 0 0 Reserved 0 1 0 1 0 1 XPT / VCPT Complete 1 1 0 1 0 1 Reserved 0 1 0 1 1 0 MP Instruction Cache (Low) 1 1 0 1 1 0 Reserved 0 1 0 1 1 1 MP Instruction Cache (High) 1 1 0 1 1 1 Reserved 0 1 1 0 0 0 MP DEA (Low) 1 1 1 0 0 0 Reserved 0 1 1 0 0 1 MP DEA (High) 1 1 1 0 0 1 Reserved 0 1 1 0 1 0 MP Data Cache (Low) 1 1 1 0 1 0 Reserved 0 1 1 0 1 1 MP Data Cache (High) 1 1 1 0 1 1 Reserved 0 1 1 1 0 0 Frame 0 1 1 1 1 0 0 Reserved 0 1 1 1 0 1 Frame 1 1 1 1 1 0 1 Reserved 0 1 1 1 1 0 Refresh 1 1 1 1 1 0 Reserved 0 1 1 1 1 1 Idle 1 1 1 1 1 1 Write Drain / SDRAM DCAB Low – MP operating in low (normal) priority mode High – MP operating in high priority mode 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CYCLE TYPE TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 address multiplexing To support various RAM devices, the TMS320C80 can provide multiplexed row and column addresses on its address bus. A full 32-bit address is always output at row time. The alignment of column addresses is configured by the value input on the AS[2:0] pins at row time (see Figure 59). A[31:0] Pins 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row Time A[31:0] Pins AS [2:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 001 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x 2 1 0 010 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x 2 1 0 011 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x 2 1 0 100 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x 2 1 0 101 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x 2 1 0 110 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x 2 1 0 111 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x 2 1 0 Column Time Figure 59. Address Multiplexing dynamic bus sizing The ’C80 supports data bus sizes of 8, 16, 32, or 64 bits as shown in Table 31. The value input on the BS[1:0] pins at row time indicates the bus size of the addressed memory. This determines the maximum number of bytes which the ’C80 can transfer during each column access. If the number of bytes to be transferred exceeds the bus size, multiple accesses are performed automatically to complete the transfer. Table 31. Bus Size Selection BS[1:0] BUS SIZE 00 8 bits 01 16 bits 10 32 bits 11 64 bits The selected bus size also determines which portion of the data bus is used for the transfer. For 64-bit memory, the entire data bus is used. For 32-bit memory, D[31:0] are used in little-endian mode and D[63:32] are used in big-endian mode. 16-bit buses use D[15:0] and D[63:48] and 8-bit buses use D[7:0] and D[63:56] for littleand big-endian modes, respectively. The ’C80 always aligns data to the proper portion of the bus and activates the appropriate CAS / DQM strobes to ensure that only valid bytes are transferred. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 cycle time selection The ’C80 supports eight basic sets of memory timings to support various memory types directly. The cycle timing is selected by the value input on the CT[2:0] and UTIME pins at row time. The selected timing remains in effect until the next row access. See Table 32 for Cycle-timing selections. Table 32. Cycle-Timing Selection UTIME CT[2:0] MEMORY TIMING 0 0 0 0 Reserved 0 0 0 1 SDRAM: burst length 1, read latency 4 0 0 1 0 Reserved 0 0 1 1 SDRAM: burst length 2, read latency 4 0 1 0 0 User timed DRAM: pipelined 1 cycle / column 0 1 0 1 User timed DRAM: 1 cycle / column 0 1 1 0 User timed DRAM: 2 cycle / column 0 1 1 1 User timed DRAM: 3 cycle / column 1 0 0 0 SDRAM: burst length 1, read latency 2 1 0 0 1 SDRAM: burst length 1, read latency 3 1 0 1 0 SDRAM: burst length 2, read latency 2 1 0 1 1 SDRAM: burst length 2, read latency 3 1 1 0 0 DRAM: pipelined 1 cycle / column 1 1 0 1 DRAM: 1 cycle / column 1 1 1 0 DRAM: 2 cycle / column 1 1 1 1 DRAM: 3 cycle / column page sizing Whenever an external memory access occurs, the TC records the 26 most significant bits of the address in its internal LASTPAGE register. The address of each subsequent (column) access is compared to this value. The page size value input on the PS[3:0] pins determines which bits of LASTPAGE are used for this comparison. If a difference exists between the enabled LASTPAGE bits and the corresponding bits of the next access then the page has changed and the next memory access begins with a new row-address cycle (see Table 33). 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 page sizing (continued) Table 33. Page-Size Selection PS[3:0] ADDRESS BITS COMPARED PAGE SIZE (BYTES) 0 0 0 0 A(31:6) 64 0 0 0 1 A(31:7) 128 0 0 1 0 A(31:8) 256 0 0 1 1 A(31:9) 512 0 1 0 0 A(31:10) 1K 0 1 0 1 A(31:18) 256K 0 1 1 0 A(31:19) 512K 0 1 1 1 A(31:20) 1 0 0 0 A(31:0) 1M 1–8† 1 0 0 1 A(31:11) 2K 1 0 1 0 A(31:12) 4K 1 0 1 1 A(31:13) 8K 1 1 0 0 A(31:14) 16K 1 1 0 1 A(31:15) 32K 1 1 1 0 A(31:16) 64K 1 1 1 1 A(31:17) 128K † PS[3:0] = 1000 disables page-mode cycles so that the effective page size is the same as the bus size block write support The TMS320C80 supports three modes of VRAM block write. The block-write mode is dynamically selectable so that software may specify block writes without knowing what type of block write the addressed memory supports. Block writes are supported only for 64-bit buses. During block-write and load-color-register cycles, the BS[1:0] inputs determine which block mode will be used (see Table 34). Table 34. Block-Write Selection BS[1:0] BLOCK-WRITE MODE 0 0 Simulated 0 1 Reserved 1 0 4x 1 1 8x SDRAM support The TMS320C80 provides direct support for synchronous DRAM (SDRAM), VRAM (SVRAM), and graphics RAM (SGRAM). During ’C80 power-up refresh cycles, the external system must signal the presence of these memories by inputting a CT2 value of 0. This causes the ’C80 to perform special deactivate (DCAB) and mode register set (MRS) commands to initialize the synchronous RAMs. Figure 60 shows the MRS value generated by the ’C80. Note that read latency 4 timing programs the mode register for a read latency of 3. See Figure 60 for a listing of MRS values. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 75 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM support (continued) SDRAM Mode Register Bit 11 10 Meaning Value 0 0 9 8 7 WB 0 0 0 0 0 6 5 4 3 Read Latency !(UTIME) UTIME 2 S/I UTIME&CT0 0 1 0 Burst Length 0 0 CT1 UTIME, CT0, CT1 values as input at the start of the MRS cycle Figure 60. MRS Value Because the MRS register is programmed through the SDRAM address inputs, the alignment of the MRS data to the ’C80 logical-address bits is adjusted for the bus size (see Figure 61). The appearance of the MRS bits on the ’C80 physical-address bus is dependent on the address multiplexing as selected by the AS[2:0] inputs. ’C80 LOGICAL ADDRESS BITS BS[1:0] A15 A14 A13 0 0 X X X 0 1 X X X 1 0 X X 11 1 1 X 11 10 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 X 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 X 10 9 8 7 6 5 4 3 2 1 0 X X 9 8 7 6 5 4 3 2 1 0 X X X Figure 61. MRS Value Alignment memory cycles TMS320C80 external memory cycles are generated by the TC’s external memory controller. The controller’s state machine generates a sequence of states which define the transition of the memory interface signals. The state sequence is dependent on the cycle timing selected for the memory access being performed as shown in Figure 62. Memory cycles consist of row states and the column pipeline (see Figure 62). 76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 memory cycles (continued) rhiz bus release idle or abort bus request r1 r2 any cycle r8 wait always r5 new page & CT = 100 & write r4 or (CT = 0xx & !SRS) CT = 110 CT = 111 CT = 10x or (0xx & SRS) refresh & CT = 10x or 0xx refresh & CT = 110 r7 refresh & CT = 111 dw MRS or DCAB dcab new page & CT = 0xx r3 new page always always always r9 always any cycle fault, retry, or abort always !MRS & !DCAB spin spin r6 col access rspin wait col access Column Pipeline Figure 62. Memory Cycle State Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 77 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 row states The row states make up the row time of each memory access. They occur when each new page access begins. The transition indicators determine the conditions that cause transitions to another state. See Table 35 and Table 36. Table 35. Row States STATE DESCRIPTION r1 Beginning state for all memory accesses. Outputs row address (A[31:0]) and cycle type (STATUS[5:0]) and drives control signals to their inactive state r2 Common to all memory accesses. Asserts RL and drives DDIN according to the data transfer direction. AS[2:0], BS[1:0], CT[2:0], PS[3:0] and UTIME inputs are sampled r3 Common to all memory accesses. DBEN is driven to its active level. For non-SDRAM, W, TRG / CAS, and DSF are driven to their active levels and for non-SDRAM refreshes, all CAS / DQM strobes are activated. FAULT, READY, and RETRY inputs are sampled. r4 Inserted for 3 cycle / column accesses (CT=111) only. No signal transitions occur. RETRY input is sampled. r5 Common to SDRAM and 2 or 3 cycle / column accesses (CT=0xx or 11x). RAS is driven low. W is driven low for DCAB and MRS cycles and TRG / CAS is driven low for MRS and SDRAM refresh cycles. r6 Common to all memory accesses. For SDRAM cycles, RAS, TRG / CAS, and W are driven high. For non-SDRAM, RAS is driven low (if not already) and W, TRG / CAS, and DSF are driven to their appropriate levels. DBEN is driven low and READY and RETRY are sampled. rspin Additional state to allow TC column time pipeline to load. No signal transitions occur. RETRY is sampled. The rspin state can, on occasion, repeat multiple times. r7 Common to 2 and 3 cycle / column refreshes (CT=11x). Processor activity code is output on STATUS[5:0]. RETRY input is sampled. r8 For 3 cycle / column refreshes only (CT=111). No signal transitions occur. RETRY input is sampled. r9 Common to all refresh cycles. Processor activity code is output on STATUS[5:0] and RETRY input is sampled. dw Occurs for pipelined 1 cycle / column writes only. All CAS / DQM strobes are activated. dcab Occurs for SDRAM cycles (CT = 0xx). RAS and W are activated to perform a DCAB command. rhiz High impedance state. Occurs during host requests and repeats until bus is released by the host Table 36. State Transition Indicators INDICATOR any cycle CT=xxx DESCRIPTION Continuation of current cycle State change occurs for indicated CT[2:0] value (as latched in r2 state) abort Current cycle aborted by TC in favor of higher priority cycle fault FAULT input sampled low (in r3 state), memory access faulted retry RETRY input sampled low (in r3 state), row-time retry wait READY input sampled low (in r3, r6, or last column state) repeat current state spin Internally generated wait state to allow TC pipeline to load new page The next access requires a page change (new row access). external memory timing examples The following sections contain descriptions of the ’C80 memory cycles and illustrate the signal transitions for those cycles. Memory cycles may be separated into two basic categories; DRAM-type cycles for use with DRAM-like devices, SRAM, and peripherals, and SDRAM-type cycles for use with SDRAM-like devices. 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 DRAM-type cycles The DRAM-type cycles are page-mode accesses consisting of a row access followed by one or more column accesses. Column accesses may be one, two, or three clock cycles in length with two and three cycle accesses allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column accesses have completed or between column accesses due to “bubbles” in the TC data-flow pipeline. The pipeline diagrams in Figure 63 show the pipeline stages for each access type and when the CAS / DQM signal corresponding to the column access is activated. CAS / DQM - / A A / B B / C C / Col A c1 Col B CAS / DQM Col A c2 c3 c1 c2 c3 c1 c2 c3 ci ci Col C Idle A B C c1 Col B c1 Col C c1 Idle ci ci Pipelined 1 cycle / column (CT = 100) Pipelined 1 cycle / column (CT = 100) reads, read transfers, split read transfers writes, LCRs, block writes, write transfers, split write transfers CAS / DQM A B Col A c1 c2 Col B c1 Col C C - CAS / DQM Col A c2 c1 B Col B ci C c1 Col C c2 ci Idle A c1 c1 ci Idle Nonpipelined 1 cycle / column (CT = 101) Nonpipelined 1 cycle / column (CT = 101) reads, read transfers, split read transfers writes, LCRs, block writes, write transfers, split write transfers A CAS / DQM Col A c1 Col B B CAS / DQM C Col A c2 c1 A A c2 c3 - - c2 - Col C c1 Col B c1 - - c1 c2 c3 - - ci B ci C C - c2 - Idle B Col C - - c1 c2 c3 - - - - - - ci ci Idle 2 cycle / column (CT = 110) 3 cycle / column (CT = 111) all cycles (except refresh) all cycles (except refresh) ci Figure 63. DRAM Cycle Column Pipelines read cycles Read cycles transfer data or instructions from external memory to the ’C80. The cycles can occur as a result of a packet transfer, cache request, or DEA request. During the cycle, W is held high, TRG / CAS is driven low after RAS to enable memory output drivers and DDIN is low so that data transceivers drive into the ’C80. The TC places D[63:0] in high impedance allowing it to be driven by the memory and latches input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. During peripheral device packet transfers, DBEN remains high. Read cycles are shown in Figure 64 through Figure 67. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 79 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 read cycles (continued) State Col A Col B Col C Col D r1 r2 r3 r6 col c1 col c2 c1 col c3 c2 c1 col col col c3 c2 c1 c3 c2 c3 CLKOUT CT[2:0] 4 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC PAC PAC Row Col A Col B Col C Col D Idle RL A[31:0] RAS –/A B/C A/B C/D D/– CAS / DQM[7:0] DSF TRG / CAS W D[63:0] A DBEN B C 0 For Normal Reads, 1 For PDPT Reads DDIN For user-modified timing: UTIME RAS –/A CAS / DQM[7:0] A/B B/C C/D D/– Figure 64. Pipelined 1 Cycle / Column Read-Cycle Timing 80 D POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 read cycles (continued) State r1 r2 r3 Col A r6 col col c1 c2 Col B col c1 col r1 c2 Col C c1 c2 Idle CLKOUT CT[2:0] 5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC PAC Row Col A Col B Col C A B C RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] A B C 0 For Normal Reads, 1 For PDPT Reads DBEN DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B C Figure 65. Nonpipelined 1 Cycle / Column Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 81 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 read cycles (continued) State r1 r2 r3 r5 r6 Col A col col c1 c2 Col B col col† col c1 c2 c2 ci‡ Col C col col c1 c2 CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row Col A PAC Idle PAC RL A[31:0] Col B Col C RAS A CAS / DQM[7:0] B C DSF TRG / CAS W A D[63:0] B C 0 For Normal Reads, 1 For PDPT Reads DBEN DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Figure 66. 2 Cycles / Column Read-Cycle Timing 82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 C r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 read cycles (continued) State r1 r2 r3 r4 Col A r5 r6 col col col c1 c2 c3 Col B col col col† col c1 c2 c3 c3 ci‡ Col C col col col c1 c2 c3 r1 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Idle PAC RL A[31:0] Row Column A Column B Column C A B C RAS CAS / DQM[7:0] DSF TRG / CAS W A D[63:0] DBEN B C 0 For Normal Reads, 1 For PDPT Reads DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B C † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Figure 67. 3 Cycles / Column Read-Cycle Timing write cycles Write cycles transfer data from the ’C80 to external memory. These cycles can occur as a result of a packet transfer, a DEA request, or an MP data cache write-back. During the cycle TRG/ CAS is held high, W is driven low after the fall of RAS to enable early-write cycles, and DDIN is high so that data transceivers drive toward memory. The TC drives data out on D[63:0] and indicates valid bytes by activating the appropriate CAS/ DQM strobes. During peripheral device packet transfers, DBEN remains high and D[63:0] is placed in high impedance so that the peripheral device can drive data into the memory. Write cycles are shown in Figure 68 through Figure 71. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 83 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 write cycles (continued) State Col A Col B Col C r1 r2 r3 r6 rspin rspin col col ci† col drn c1 c1 c1 CLKOUT CT[2:0] 4 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Idle PAC Col A Col B Col C A B C Drain RL Row A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W A D[63:0] B C 0 For Normal Write, 1 For PDPT Write DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] A B † Internally generated pipeline bubble (example) Figure 68. Pipelined 1 Cycle / Column Write-Cycle Timing 84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 C r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 write cycles (continued) State Col A Col B Col C r1 r2 r3 r6 rspin rspin col c1 col ci† col r1 c1 c1 CLKOUT CT[2:0] 5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Idle Row Col A Col B Col C A B C PAC RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] A B C 0 For Normal Write, 1 For PDPT Write DBEN DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B C † Internally generated pipeline bubble (example) Figure 69. Nonpipelined 1 Cycle / Column Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 85 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 write cycles (continued) State r1 r2 r3 r5 r6 rspin Col A col col c1 c2 Col B col col† col c1 c2 c2 ci‡ Col C col col c1 c2 CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] PAC PAC Col A Col B Col C B C Idle PAC RL Row A[31:0] RAS A CAS / DQM[7:0] DSF TRG / CAS W A D[63:0] B C 0 For Normal Write, 1 For PDPT Write DBEN DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Figure 70. 2 Cycles / Column Write-Cycle Timing 86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 C r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 write cycles (continued) State r1 r2 r3 r4 r5 Col A r6 col col col c1 c2 c3 Col B col col col† col c1 c2 c3 c3 ci‡ col col col c1 c2 c3 Col C r1 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Row Col A Col B Idle PAC RL A[31:0] Col C RAS A CAS / DQM[7:0] B C DSF TRG / CAS W A D[63:0] B C 0 For Normal Write, 1 For PDPT Write DBEN DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B C † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Figure 71. 3 Cycles / Column Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 87 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 load-color-register cycles Load-color-register (LCR) cycles are used to load a VRAM’s color register prior to performing a block write. LCR cycles are supported only on 64-bit data buses. An LCR cycle closely resembles a normal write cycle because it writes into a VRAM. The difference is that the DSF output is high at both the fall of RAS and the fall of CAS/ DQM. Also, because the VRAM color register is a single location, only one column access occurs. The row address that is output by the TC is used for bank decode only. Normally all VRAM banks should be selected during an LCR cycle because another LCR cycle will not occur when a block-write memory page change occurs. The column address that is output during an LCR is likewise irrelevant because the VRAM color register is the only location written. All CAS / DQM strobes are active during an LCR cycle. The RETRY input is sampled during LCR column states and must be valid high or low. Asserting RETRY at column time has no effect, however, because only one column access is performed. If the BS[1:0] inputs indicate that the addressed memory supports only simulated block writes, the LCR cycle will be changed into a normal write cycle at the start of the simulated block write. Load color register cycles timing is shown in Figure 72 through Figure 75. 88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 load-color-register cycles (continued) State r1 r2 r3 r6 rspin rspin c1 drn PAC Drain r1 CLKOUT CT[2:0] 4 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] RL Row A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W Color D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 72. Pipelined 1 Cycle / Column Load-Color-Register-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 89 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 load-color-register cycles (continued) State r1 r2 r3 r6 rspin rspin c1 r1 CLKOUT CT[2:0] 5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] PAC RL A[31:0] Row RAS CAS / DQM[7:0] DSF TRG / CAS W Color D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 73. Nonpipelined 1 Cycle / Column Load-Color-Register-Cycle Timing 90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 load-color-register cycles (continued) State r1 r2 r3 r5 r6 rspin c1 c2 r1 CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL Row A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W Color Value D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 74. 2 Cycles / Column Load-Color-Register-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 91 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 load-color-register cycles (continued) State r1 r2 r3 r4 r5 r6 c1 c2 c3 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] PAC RL Row A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W Color Value D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 75. 3 Cycles / Column Load-Color-Register-Cycle Timing 92 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 block-write cycles Block-write cycles cause the data stored in the VRAM color registers to be written to the memory locations enabled by the appropriate data bits output on the D[63:0] bus. This allows up to a total of 64 bytes (depending on the type of block write being used) to be written in a single-column access. This cycle is identical to a standard write cycle with the following exceptions: D D D D D DSF is active (high) at the fall of CAS, enabling the block-write function within the VRAMs. Only 64-bit bus sizes are supported during block write; therefore, BS[1:0] inputs are used to indicate the type of block write that is supported by the addressed VRAMs, rather than the bus size. The two or three LSBs (depending on the type of block write) of the column address are ignored by the VRAMs because these column locations are specified by the data inputs. The values output by the TC on D[63:0] represent the column locations to be written to, using the color-register value. Depending on the type of block write supported by the VRAM, all of the data bits are not necessarily used by the VRAMs. Block writes always begin with a row access. Upon completion of a block write, the memory interface returns to state r1 to await the next access. See Figure 76 through Figure 79 for block-write cycle timing. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 93 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 block-write cycles (continued) State Col A Col B Col C r1 r2 r3 r6 rspin rspin col c1 ci† col col drn c1 c1 CLKOUT CT[2:0] 4 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Row Col A Col B Col C A B C Sel A Sel B Sel C A B C Idle PAC RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] † Internally generated pipline bubble (example) Figure 76. Pipelined 1 Cycle / Column Block-Write-Cycle Timing 94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Drain r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 block-write cycles (continued) State Col A Col B Col C r1 r2 r3 r6 rspin rspin col c1 col ci† col r1 c1 c1 CLKOUT CT[2:0] 5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Row Col A Col B Col C A B C Sel A Sel B Sel C A B C Idle PAC RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] † Internally generated pipline bubble (example) Figure 77. Nonpipelined 1 Cycle / Column Block-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 95 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 block-write cycles (continued) State r1 r2 r3 r5 r6 rspin Col A Col B Col C col col c1 c2 col c1 col† col c2 c2 ci‡ col col c1 c2 CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Col A Col B Idle PAC RL Row A[31:0] Col C RAS A CAS / DQM[7:0] B C DSF TRG / CAS W Col Sel A D[63:0] Col Sel B Col Sel C DBEN DDIN For user-modified timing: UTIME RAS A CAS / DQM[7:0] B † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Figure 78. 2 Cycles / Column Block-Write-Cycle Timing 96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 C r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 block-write cycles (continued) State Col A Col B Col C r1 r2 r3 r4 r5 r6 col col col c1 c2 c3 col col col col† c1 c2 c3 c3 ci‡ col col col c1 c2 c3 r1 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC Row Col A Col B Idle PAC RL A[31:0] Col C RAS A CAS / DQM[7:0] C B DSF TRG / CAS W D[63:0] Col Sel A Col Sel B Col Sel C DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] A B C † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Figure 79. 3 Cycles / Column Block-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 97 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles Read-transfer (memory-to-register) cycles transfer a row from the VRAM memory array into the VRAM shift register (SAM). This causes the entire SAM (both halves of the split SAM) to be loaded with the array data. Split-register read-transfer (memory-to-split-register) cycles also transfer data from a row in the memory array to the SAM. However, these transfers cause only half of the SAM to be written. Split-register read transfers allow the inactive half of the SAM to be loaded with the new data while the other active half continues to shift data in or out. Write-transfer (register-to-memory) cycles transfer data from the SAM into a row of the VRAM array. This transfer causes the entire SAM (both halves of the split SAM) to be written into the array. Split-register write-transfer (split-register-to-memory) cycles also transfer data from the SAM to a row in the memory array. However, these transfers write only half of the SAM into the array. Split-register write transfers allow the inactive half of the SAM to be transferred into memory while the other (active) half continues to shift serial data in or out. Read and split-read transfers resemble a standard read cycle. Write and split-write transfers resemble a standard write cycle. The TRG / CAS output is driven low prior to the fall of RAS to indicate a transfer cycle. Only a single column access is performed so RETRY, while required to be at a valid level, has no effect if asserted at column time. The value output on A[31:0] at column time represents the SAM tap point (see Figure 80 through Figure 86 for transfer cycle timing. 98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r6 c1 c2 c3 r1 CLKOUT CT[2:0] 4 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Idle RL A[31:0] Row Tap Point RAS CAS / DQM[7:0] DSF 0 for Full Transfer, 1 for Split Transfer TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 80. Pipelined 1 Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 99 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 c1 c2 PAC Idle r6 r1 CLKOUT CT[2:0] 5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type RL A[31:0] Row Tap Point RAS CAS / DQM[7:0] DSF 0 for Full Transfer, 1 for Split Transfer TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 81. Nonpipelined 1 Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r5 r6 c1 c2 r1 CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL A[31:0] Row Tap Point RAS CAS / DQM[7:0] 0 for Full Transfer, 1 for Split Transfer DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 82. 2 Cycles/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 101 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r4 r5 r6 c1 c2 c3 r1 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] PAC RL Row A[31:0] Tap Point RAS CAS / DQM[7:0] DSF 0 for Full Transfer, 1 for Split Transfer TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 83. 3 Cycles/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing 102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r6 rspin rspin c1 drn PAC Drain r1 CLKOUT CT[2:0] 4 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type RL A[31:0] Row Tap Point RAS CAS / DQM[7:0] 0 for Full Transfer, 1 for Split Transfer DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 84. Pipelined 1 Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 103 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r6 rspin rspin c1 r1 CLKOUT CT[2:0] 5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL Row A[31:0] Tap Point RAS CAS / DQM[7:0] 0 for Full Transfer, 1 for Split Transfer DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 85. Nonpipelined 1 Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing 104 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r5 r6 rspin c1 c2 rl CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row Tap Point RL A[31:0] RAS CAS / DQM[7:0] 0 for Full Transfer, 1 for Split Transfer DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 86. 2 Cycles/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 105 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 transfer cycles (continued) State r1 r2 r3 r4 r5 r6 c1 c2 c3 r1 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row Tap Point RL A[31:0] RAS CAS / DQM[7:0] 0 for Full Transfer, 1 for Split Transfer DSF TRG / CAS W D[63:0] DBEN DDIN For user-modified timing: UTIME RAS CAS / DQM[7:0] Figure 87. 3 Cycles/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing 106 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 refresh cycles Refresh cycles are generated by the TC at the programmed refresh interval. They are characterized by the following signal activity: D D D D D D D D D CAS falls prior to RAS. All CAS pins ( CAS/ DQM[7:0]) are active. TRG, W, and DBEN all remain inactive (high) because no data transfer occurs. DSF remains inactive (low). The data bus is driven to the high-impedance state. The upper half of the address bus (A[31:16]) contains the refresh pseudo-address and the lower half (A[15:0]) is driven to all zeros. If RETRY is asserted at any sample point during the cycle, the cycle timing is not modified. Instead, the pseudo-address and backlog counters are simply not decremented. Selecting user-modified timing has no effect on the cycles. Upon completion of the refresh cycle, the memory interface returns to state r1 to await the next access. See Figure 88 through Figure 90 for refresh cycle timing. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 107 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 refresh cycles (continued) State r1 r2 r3 r6 r9 CLKOUT CT[2:0] 4/5 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL A[31:16] Refresh Pseudo Address A[15:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Figure 88. 1-Cycle/Column Refresh-Cycle Timing 108 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 refresh cycles (continued) State r1 r2 r3 r5 r6 r7 r9 r1 CLKOUT CT[2:0] 6 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL A[31:16] Refresh Pseudo Address A[15:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Figure 89. 2 Cycles/Column Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 109 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 refresh cycles (continued) State r1 r2 r3 r4 r5 r6 r7 r8 CLKOUT CT[2:0] 7 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL A[31:16] Refresh Pseudo Address A[15:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Figure 90. 3 Cycles/Column Refresh-Cycle Timing 110 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r9 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM type cycles The SDRAM type cycles support the use of SDRAM, SGRAM, or SVRAM devices for single-cycle memory accesses. While SDRAM cycles use the same state sequences as DRAM cycles, the memory-control signal transitions are modified to perform SDRAM command cycles. The supported SDRAM commands are: DCAB Deactivate (precharge) all banks ACTV Activate the selected bank and select the row READ Input starting column address and start read operation WRT Input starting column address and start write operation MRS Set SDRAM mode register REFR Auto-refresh cycle with internal address SRS Set special register (color register) BLW Block write SDRAM cycles begin with an activate (ACTV) command followed by the requested column accesses. When a memory-page change occurs, the selected bank is deactivated with a DCAB command. The TMS320C80 supports read latencies of 2, 3, or 4 cycles and burst lengths of 1 or 2. These are selected by the CT code and UTIME value input at the start of the access. The column pipelines for SDRAM accesses are shown in Figure 91. Idle cycles can occur after necessary column accesses have completed or between column accesses due to “bubbles” in the TC data flow pipeline. The pipeline diagrams show the pipeline stages for each access type and when the CAS/ DQM signal corresponding to the column access is activated. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 111 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM type cycles (continued) CAS / DQM Col A A B C CAS / DQM c1 c2 c3 Col A c1 c2 c3 c1 c2 c3 ci ci Col B Col C Idle Col B Col A c1 A B C c2 c3 c4 c1 Col B Col C c3 c4 c5 c2 c3 c4 ci C c4 c1 c2 c3 c4 c1 c2 c3 c4 ci ci ci CAS / DQM A (B) C Col A, B c1 c2 c3 - c5 ci ci Col C, D ci (D) - - c1 c2 - Col E, F Burst-length 1, 4 cycle latency reads, read transfers,split-read transfers. CAS / DQM A Col A c1 Col B B E (F) c3 - - c1 c2 c3 - - - ci ci Idle C ci Burst-length 2, 2 cycle latency reads, read transfers, split-read transfers c1 c1 Col C Idle ci CAS / DQM A (B) Col A, B c1 c2 - Burst-length 1 writes, block writes, SRSs, write transfers, split-write transfers Col C, D C (D) CAS / DQM c1 A (B) C c2 c3 c4 - - - - c1 c2 c3 Col C, D Col E, F (D) E E (F) c1 c2 - Col E, F Col A, B ci Burst-length 1, 3 cycle latency reads, read transfers, split-read transfers c5 c1 ci B c3 Idle ci c2 Idle A c2 Col C Burst-length 1, 2 cycle latency reads, read transfers, split-read transfers CAS / DQM c1 c1 (F) c2 - ci Burst-length 2, writes c4 - - - c1 c2 c3 c4 - - - - ci ci ci Idle ci Idle ci Burst-length 2, 3 cycle latency reads, read transfers, split-read transfers CAS / DQM Col A A B C CAS / DQM A (B) C (D) E Col A, B c1 c2 c3 c4 c5 c1 - Col B c1 Col C, D - - - - c1 c2 c3 c4 - - - - - c1 c2 c3 c4 c5 - - - - - ci ci ci ci Col C c1 Col E, F - Idle ci Burst-length 2, block writes, write transfers, split-write transfers Idle Burst-length 2, 4 cycle latency reads, read transfers,split-read transfers. Figure 91. SDRAM Column Pipelines 112 POST OFFICE BOX 1443 (F) • HOUSTON, TEXAS 77251–1443 c5 ci TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 special SDRAM cycles To initialize the SDRAM properly, the TMS320C80 performs two special SDRAM cycles after reset. The ’C80 first performs a deactivate cycle on all banks (DCAB) and then initializes the SDRAM mode register with a mode register set (MRS) cycle. The CT code input at the start of the MRS cycle determines the burst length and latency that is programmed into the SDRAM mode register (see Figure 92 and Figure 93). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 113 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 special SDRAM cycles (continued) State r1 r2 r3 r5 CLKOUT CT[2:0] 0xx AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Command DCAB Figure 92. SDRAM Power-Up Deactivate Cycle Timing 114 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 special SDRAM cycles (continued) State r1 r2 r3 r5 r1 CLKOUT CT[2:0] 0xx AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY Cycle Type STATUS[5:0] RL MRS A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Command MRS Figure 93. SDRAM Mode Register Set-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 115 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles Read cycles begin with an activate (ACTV) command to activate the bank and to select the row. The TC outputs the column address and activates the TRG/ CAS strobe for each read command. For burst length 1 accesses, a read command can occur on each cycle. For burst-length 2 accesses, a read command can occur every two cycles. The TC places D[63:0] into the high-impedance state, allowing it to be driven by the memory, and latches input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. The CAS/ DQM strobes are activated two cycles before input data is latched. If the second column in a burst is not required, then CAS/ DQM is not activated. During peripheral device packet transfers, DBEN remains high (see Figure 94 through Figure 99). 116 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles (continued) State r1 r2 r3 r5 Col Pipe r6 Col A Col B Col C Col D col c1 col c2 c1 col c3 c2 c1 col col c3 c2 c1 c3 c2 DCAB r1 c3 CLKOUT CT[2:0] 0 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC PAC PAC Row Col A Col B Col C Col D A B C D A B C D A B RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] C D 0 For Normal Read, 1 For PDPT read DBEN DDIN Command ACTV READ READ READ READ DCAB Figure 94. SDRAM Burst-Length 1, 2 Cycle Latency Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 117 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles (continued) State r1 r2 r3 r5 r6 Col A Col B Col C Col D Col Pipe col c1 col col col col col r1 c2 c1 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c4 c3 c4 PAC Idle DCAB CLKOUT CT[2:0] 1 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC PAC Row Col A Col B Col C A B C B C D RL A[31:0] Col D RAS CAS / DQM[7:0] D DSF A TRG / CAS W D[63:0] A B C 0 For Normal Read, 1 For PDPT Read DBEN DDIN Command ACTV READ READ READ READ Figure 95. SDRAM Burst-Length 1, 3 Cycle Latency Read-Cycle Timing 118 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DCAB D TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles (continued) State Col Pipe r1 r2 r3 r5 r6 Col A Col B Col C Col D col c1 col c2 c1 col c3 c2 c1 col c4 c3 c2 c1 col c5 c4 c3 c2 col col r1 c5 c4 c3 c5 c4 c5 CLKOUT CT[2:0] 1 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS [5:0] Cycle Type PAC PAC PAC PAC Row Col A Col B Col C A B C B C D DCAB Idle RL A[31:0] Col D RAS CAS / DQM [7:0] D DSF A TRG / CAS W D[63:0] A B C D 0 For Normal Read, 1 For PDPT Read DBEN DDIN Command ACTV READ READ READ READ DCAB Figure 96. SDRAM Burst-Length 1, 4 Cycle Latency Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 119 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles (continued) State r1 r2 r3 r5 Col Pipe r6 Col A Col B Col C Col D col col col c1 c2 c1 c3 c2 c1 col c3 c2 c1 col c3 c2 r1 c3 CLKOUT CT[2:0] 2 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC DCAB PAC RL A[31:0] Row Col A (Col B) Col C (Col D) A B C D RAS CAS / DQM[7:0] DSF A, B TRG / CAS C, D W D[63:0] A B C 0 For Normal Read, 1 For PDPT Read DBEN DDIN Command ACTV READ READ DCAB Figure 97. SDRAM Burst-Length 2, 2 Cycle Latency Read-Cycle Timing 120 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles (continued) State r1 r2 r3 r5 Col Pipe r6 Col A Col B Col C Col D col col col col col col r1 c1 c2 c1 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c4 c3 c4 Idle DCAB CLKOUT CT[2:0] 3 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC RL A[31:0] Row Col A (Col B) Col C A B (Col D) RAS CAS / DQM[7:0] C D A B DSF A, B TRG / CAS C, D W D[63:0] C D 0 For Normal Read, 1 For PDPT Read DBEN DDIN Command ACTV READ READ DCAB Figure 98. SDRAM Burst-Length 2, 3 Cycle Latency Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 121 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM read cycles (continued) State Col Pipe r1 r2 r3 r5 r6 Col A Col B Col C Col D col c1 col c2 c1 col c3 c2 c1 col c4 c3 c2 c1 col c5 c4 c3 c2 col col r1 c5 c4 c3 c5 c4 c5 CLKOUT CT[2:0] 3 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS [5:0] Cycle Type PAC PAC DCAB Idle RL A[31:0] Row Col A (Col B) Col C A B (Col D) RAS CAS / DQM [7:0] C D DSF A, B TRG / CAS C, D W D[63:0] A B C 0 For Normal Read, 1 For PDPT Read DBEN DDIN Command ACTV READ READ Figure 99. SDRAM Burst-Length 2, 4 Cycle Latency Read-Cycle Timing 122 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DCAB D TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM write cycles Write cycles begin with an activate (ACTV) command to activate the bank and select the row. The TC outputs the column address and activates the TRG / CAS and W strobes for each write command. For burst-length 1 accesses, a write command can occur on each cycle. For burst-length 2 accesses, a write command can occur every two cycles. The TC drives data out on D[63:0] during each cycle of an active-write command and indicates valid bytes by driving the appropriate CAS / DQM strobes low. During peripheral device packet transfers, DBEN remains high and D[63:0] are placed in the high-impedance state so that the peripheral can drive data into the memories. For SDRAM write cycles, see Figure 100 and Figure 101. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 123 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM write cycles (continued) State Col Pipe r1 r2 r3 r5 r6 rspin Col A Col B Col C Col D col c1 col col col col col Idle DCAB c1 c1 c1 CLKOUT CT[2:0] 0,1 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC PAC PAC Col A Col B Col C A B C D A B C D A B C D RL A[31:0] Row Col D RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] 0 For Normal Read, 1 For PDPT Read DBEN DDIN Command ACTV WRT WRT WRT WRT Figure 100. SDRAM Burst-Length 1 Write-Cycle Timing 124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DCAB r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM write cycles (continued) State Col Pipe r1 r2 r3 r5 r6 rspin Col A Col B Col C Col D col c1 col col col col col Idle DCAB r1 c1 c1 c1 CLKOUT CT[2:0] 2, 3 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY PAC Cycle Type STATUS[5:0] PAC RL Row A[31:0] Col A (Col B) Col C A B C (Col D) RAS CAS / DQM[7:0] D DSF A, B TRG / CAS C, D W D[63:0] A B C D DBEN DDIN ACTV Command WRT WRT DCAB Figure 101. SDRAM Burst-Length 2 Write-Cycle Timing special register set cycles Special register set (SRS) cycles are used to program control registers within an SVRAM or SGRAM. The ’C80 only supports programming of the color register for use with block writes. The cycle is similar to a single burst length 1 write cycle but DSF is driven high. The values output on the ’C80 address bits cause the color register to be selected as shown in Figure 102 (see Figure 103). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 125 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 special register set cycles (continued) SDRAM Address Pin BS A8 A7 A6 A5 A4 SDRAM Function 0 0 0 LC LM LS TMS320C80 Output Value 0 0 0 1 0 0 A3 A2 A1 A0 Stop Register 0 0 0 0 Figure 102. Special-Register-Set Value State r1 r2 r6 r3 rspin rspin col c1 Col Pipe CLKOUT CT[2:0] 0xx AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row SRS RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W Color D[63:0] DBEN DDIN SRS Command Figure 103. SDRAM SRS-Cycle Timing 126 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM block-write cycles Block-write cycles allow SVRAMs and SGRAMs to write a stored color value to multiple column locations in a single access. Block-write cycles are similar to write cycles except that DSF is driven high to indicate a block-write command. Because burst is not supported for block write, burst length 2 accesses generate a single block-write every other clock cycle (see Figure 104 and Figure 105). State Col Pipe r1 r2 r3 r5 r6 rspin Col A Col B Col C Col D col c1 col col col col col Idle DCAB r1 c1 c1 c1 CLKOUT CT[2:0] 0,1 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC PAC PAC PAC Col A Col B Col C A B C D A B C D Sel A Sel B Sel C Sel D BLKW BLKW BLKW BLKW RL A[31:0] Row Col D RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Command ACTV DCAB Figure 104. SDRAM Burst-Length 1 Block-Write Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 127 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM block-write cycles (continued) State Col Pipe r1 r2 r3 r5 r6 rspin ColA ColB col c1 col col col col col Idle DCAB r1 c1 CLKOUT CT[2:0] 2, 3 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] PAC Cycle Type PAC RL Row A[31:0] Col A Col B A B A B Sel A Sel B BLKW BLKW RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN ACTV Command DCAB Figure 105. SDRAM Burst-Length 2 Block-Write Cycle Timing SVRAM transfer cycles The SVRAM read- and write-transfer cycles transfer data between the SVRAM memory-array and the serial register (SAM). The TMS320C80 supports both normal and split transfers for SVRAMs. Read-and split-read transfers resemble a standard read cycle. Write-and split-write transfers resemble a standard write cycle. Because the ’C80’s TRG output is used as CAS, external logic must generate a TRG signal (by decoding STATUS) to enable the SVRAM transfer cycle. The value output on A[31:0] at column time represents the SAM tap point (see Figure 106 through Figure 113). 128 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r5 r3 r6 col c1 col c2 r1 c3 CLKOUT CT[2:0] 000 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row Tap Pt. DCAB RL A[31:0] RAS CAS / DQM[7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN ACTV Command RTR DCAB Figure 106. SVRAM Burst-Length 1, 2 Cycle Latency Read-Transfer Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 129 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r3 col c1 col c2 col c3 Cycle Type PAC Idle DCAB Row Tap Pt. r5 r6 CLKOUT CT[2:0] 001 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] RL A[31:0] RAS CAS / DQM[7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN ACTV Command RTR DCAB Figure 107. SVRAM Burst-Length 1, 3 Cycle Latency Read-Transfer Cycle Timing 130 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r3 r5 r6 col c1 col c2 col c3 col c4 r1 c5 CLKOUT CT[2:0] 001 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS [5:0] Cycle Type PAC Row Tap Pt. Idle DCAB RL A[31:0] RAS CAS / DQM [7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN Command ACTV RTR DCAB Figure 108. SVRAM Burst-Length 1, 4 Cycle Latency Read-Transfer Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 131 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r3 col c1 col c2 col c3 Cycle Type PAC Idle DCAB Row Tap Pt. r5 r6 CLKOUT CT[2:0] 010 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] RL A[31:0] RAS CAS / DQM[7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN ACTV Command RTR DCAB Figure 109. SVRAM Burst-Length 2, 2 Cycle Latency Read-Transfer Cycle Timing 132 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r3 r5 r6 col col c1 col c2 col c3 r1 CLKOUT CT[2:0] 011 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row Tap Pt. Idle DCAB RL A[31:0] RAS CAS / DQM[7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN Command ACTV RTR DCAB Figure 110. SVRAM Burst-Length 2, 3 Cycle Latency Read-Transfer Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 133 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r3 r5 r6 col c1 col c2 col c3 col c4 col c5 CLKOUT CT[2:0] 011 AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS [5:0] Cycle Type PAC Row Tap Pt. Idle DCAB RL A[31:0] RAS CAS / DQM [7:0] DSF 0 For Full, 1 For Split TRG / CAS W D[63:0] DBEN DDIN Command ACTV RTR DCAB Figure 111. SVRAM Burst-Length 2, 4 Cycle Latency Read-Transfer Cycle Timing 134 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 r1 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) State Col Pipe r1 r2 r3 col c1 col col Cycle Type PAC Idle DCAB Row Tap Pt. r5 r6 r1 CLKOUT CT[2:0] 00x AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] RL A[31:0] RAS CAS / DQM[7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN ACTV Command WTR DCAB Figure 112. SVRAM Burst-Length 1, Write-Transfer Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 135 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SVRAM transfer cycles (continued) r1 State Col Pipe r2 r3 r5 r6 col c1 col col col r1 CLKOUT 01x CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC Row Tap Pt. Idle DCAB RL A[31:0] RAS CAS / DQM[7:0] 0 For Full, 1 For Split DSF TRG / CAS W D[63:0] DBEN DDIN ACTV Command WTR DCAB Figure 113. SVRAM Burst-Length 2, Write-Transfer Cycle Timing SDRAM refresh cycle The SDRAM refresh cycle is performed when the TC receives an SDRAM-cycle timing input (CT=0xx) at the start of a refresh cycle. The RAS and TRG / CAS outputs are driven low for one cycle to strobe a refresh command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The ’C80 outputs a 16-bit pseudo-address (used for refresh bank decode) on A[31:16] and drives A[15:0] low (see Figure 114). 136 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 SDRAM refresh cycle (continued) State r1 r2 r3 r5 r6 r9 r1 CLKOUT CT[2:0] 0xx AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] Cycle Type PAC RL A[31:16] Refresh Pseudo-Address A[15:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN Command REFR Figure 114. SDRAM Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 137 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 host interface The ’C80 contains a simple four-pin mechanism by which a host or another device can gain control of the ’C80 local memory bus. The HREQ input can be driven low by the host to request the ’C80’s bus. Once the TC has completed the current memory access, it places the local bus (except CLKOUT) into a high-impedance state. It then drives the HACK output low to indicate that the host device owns the bus and can drive it. The REQ[1:0] outputs reflect the highest priority cycle request being received internally by the TC. The host can monitor these outputs to determine if it needs to relinquish the local bus back to the ’C80 (see Table 37). Table 37. TC Priority Cycles REQ[1:0] ASSOCIATED INTERNAL TC REQUEST 11 SRT, urgent refresh, XPT, or VCPT 10 Cache / DEA request, urgent packet transfer 01 High-priority packet transfer 00 Low-priority packet transfer, trickle refresh, idle device reset The TMS320C80 is reset when the RESET input is driven low. The ’C80 outputs immediately go into a high-impedance state with the exception of CLKOUT, HACK, and REQ[1:0]. While RESET is low, all internal registers are set to their default values and internal logic is reset. On the rising edge of RESET, the state of UTIME is sampled to determine if big-endian (UTIME = 0) or little-endian (UTIME = 1) operation is selected. Also on the rising edge of RESET, the state of HREQ is sampled to determine if the master processor comes up running (HREQ = 0) or halted (HREQ = 1). Once RESET is high, the ’C80 drives the high-impedance signals to their inactive values. The TC then performs 32 refresh cycles to initialize system memory. If, during initialization refresh, the TC receives an SDRAM cycle timing code (CT = 0xx), it performs an SDRAM DCAB cycle and a MRS cycle to initialize the SDRAM, and then continues the refresh cycles. After completing initialization refresh, if the MP is running, the TC performs its instruction-cache-fill request to fetch the cache block beginning at 0xFFFFFFC0. This block contains the starting MP instruction located at 0xFFFFFFF8. If the MP comes up halted, the instruction cache fill does not take place until the first occurrence of an EINT3 interrupt to unhalt the MP. 138 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 absolute maximum ratings over specified temperature ranges (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT 3.135 3.3 3.465 V VDD VSS Supply voltage IOH IOL High-level output current – 400 µA Low-level output current 2 mA Supply voltage (see Note 2) 0 V TC Operating case temperature 0 85 °C NOTE 2: In order to minimize noise on VSS, care should be taken to provide a minimum inductance path between the VSS pins and system ground. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) TEST CONDITIONS‡ PARAMETER VIH VIL High-level input voltage VOH VOL High-level output voltage Low-level input voltage – 0.3 VDD = MIN, VDD = MAX, Low-level output voltage Output current,, leakage g ((high g impedance)) (except EMU0 and EMU1) II Input current (except TCK, TDI, and TMS) Ci Supply current (see Note 3) TYP§ 2 IO IDD MIN IOH = MAX IOH = MIN 2.6 20 40 MHz 0.9# 10 V V – 20 50 MHz Input capacitance V 0.6 1.2# 1.0# 60 MHz UNIT ¶ VDD = MAX, VO = 2.8 V VDD = MAX, VO = 0.6 V VI = VSS to VDD VDD = MAX, VDD = MAX, VDD = MAX, MAX VDD + 0.3 0.8 V µA ± 20 2.5# µA 2.3# 1.9# A pF Co Output capacitance 10 pF ‡ For conditions shown as MIN / MAX, use the appropriate value specified under the recommended operating conditions. § All typical values are at VDD = 3.3 V, ambient air temperature = 25°C ¶ Typical steady-state VOH will not exceed VDD # Parameter value is representative of revision 4.x and higher devices. NOTE 3: Maximum supply current is derived from a test case that generates the theoretical maximum data flow using a worst case checkerboard data pattern on a sustained cycle by cycle basis. Actual maximum IDD varies in real applications based on internal and external data flow and transitions. Typical supply current is derived from a test case which attempts to emulate typical use conditions of the on-chip processors with random data. Typical IDD varies from application to application based on data flow and transitions and on-chip processor utilization. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 139 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω VLOAD Output Under Test CT IOH Where: IOL IOH VLOAD CT = = = = 2.0 mA (all outputs) 400 µA (all outputs) 1.5 V 60 pF typical load circuit capacitance Figure 115. Test Load Circuit signal transition levels TTL-output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Figure 116 shows the TTL-level outputs. 2.4 V 2V 0.8 V 0.6 V Figure 116. TTL-Level Outputs TTL-output transition times are specified as follows: D D For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level at which the output is said to be low is 0.8 V. For a low-to-high transition, the level at which the output is said to be no longer low is 0.8 V, and the level at which the output is said to be high is 2 V. Figure 117 shows the TTL-level inputs. 2V 0.8 V Figure 117. TTL-Level Inputs TTL-compatible input transition times are specified as follows: D D 140 For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 2 V, and the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.8 V, and the level at which the input is said to be high is 2 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A A[31 : 0] RDY READY CAS CAS / DQM[7 : 0] RST RESET CFG AS[2:0], BS[1:0], CT[2:0], PS[3:0], UTIME RTY RETRY CKI CLKIN REQ REQ[1:0] CKO CLKOUT RL RL CMP RETRY, READY, FAULT RR READY, RETRY D D[63:0] SCK SCLK0, SCLK1 EIN EINT1, EINT2, EINT3, or EINTx TCK TCK EMU EMU0, EMU1 TDI TDI FCK FCLK0, FCLK1 TDO TDO HAK HACK TMS TMS HRQ HREQ TRS TRST LIN LINT4 UTM UTIME MID A[31:0], STATUS[5:0] SI HSYNC0, VSYNC0, CSYNC0, HSYNC1, VSYNC1, or CSYNC1 OUT A[31:0], CAS / DQM[7 : 0], D[63:0], DBEN, DDIN, DSF, RAS, RL, STATUS[5:0], TRG / CAS, W SY HSYNC0, VSYNC0, CSYNC0 / HBLNK0, CBLNK0 / VBLNK0, HSYNC1, VSYNC1, CSYNC1 / HBLNK1, CBLNK1 / VBLNK1, CAREA0, or CAREA1 RAS RAS XPT XPT[2:0] OR XPTx Lowercase subscripts and their meanings are: The following letters and symbols and their meanings are: a access time H High c cycle time (period) L Low d delay time V Valid h hold time Z High impedance su setup time X Unknown, changing, or don’t care level t transition time w pulse duration (width) general notes on timing parameters The period of the output clock (CLKOUT) is twice the period of the input clock (CLKIN), or 2 × tc(CKI). The half cycle time (tH) that appears in the following tables is one-half of the output clock period, or equal to the input clock period, tc(CKI). All output signals from the ’C80 (including CLKOUT) are derived from an internal clock such that all output transitions for a given half cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 141 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 CLKIN timing requirements (see Figure 118) ’C80-40 NO NO. 1 2 3 4 MIN ’C80-50 MAX MIN ’C80-60 MAX MIN MAX UNIT tc(CKI) tw(CKIH) Period of CLKIN (tH) 12.5 10 8.3 ns Pulse duration of CLKIN high 4.8 4.2 3.9 ns tw(CKIL) tt(CKI) Pulse duration of CLKIN low Transition time of CLKIN† 4.8 4.2 3.9 1.5 ns 1.5 1.5 ns † This parameter is verified by computer simulation and is not tested. 1 4 2 4 CLKIN 3 Figure 118. CLKIN Timing local-bus switching characteristics over full operating range: CLKOUT‡(see Figure 119) NO NO. 5 6 7 ’C80-40 PARAMETER MIN ’C80-50 MAX MIN ’C80-60 MAX MIN Pulse duration of CLKOUT high 2tc(CKI)§ tH – 5.5 2tc(CKI) § tH – 4.5 2tc(CKI) § tH – 3.7 Pulse duration of CLKOUT low tH – 5.5 tH – 4.5 tH – 3.7 tc(CKO) tw(CKOH) Period of CLKOUT tw(CKOL) tt(CKO) 2¶ 2¶ MAX UNIT ns ns ns 2¶ 8 Transition time of CLKOUT ns ‡ The CLKOUT output has twice the period of CLKIN. No propagation delay or phase relationship to CLKIN is assured. Each state of a memory access begins on the falling edge of CLKOUT. § This is a functional minimum and is not tested. This parameter may also be specified as 2tH. ¶ This parameter is verified by computer simulation and is not tested. tH 5 tH tH tH 8 6 8 CLKOUT 7 Figure 119. CLKOUT Timing 142 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 device reset timing requirements (see Figure 120) NO. MIN Initial reset during power-up MAX UNIT 6th 6th ns ns 9 tw(RSTL) (RSTL) P lse d ration RESET low lo Pulse duration, 10 Setup time of HREQ low to RESET high to configure self-bootstrap mode 11 tsu(HRQL-RSTH) th(RSTH-HRQL) Hold time, HREQ low after RESET high to configure self-bootstrap mode 4th 0 12 tsu(UTML-RSTH) Setup time of UTIME low to RESET high to configure big-endian operation 4th ns 13 th(RSTH-UTML) Hold time, UTIME low after RESET high to configure big-endian operation 0 ns Reset during active operation ns ns 9 RESET 10 11 HREQ 13 12 UTIME Figure 120. Device-Reset Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 143 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 local bus timing requirements: cycle configuration inputs (see Figure 121) The cycle configuration inputs are sampled at the beginning of each row access during the r2 state. The inputs typically are generated by a static decode of the A[31:0] and STATUS[5:0] outputs. NO. 14 15 16 MIN tsu(CFGV-CKOH) th(CKOH-CFGV) ta(MIDV-CFGV) UNIT 8 ns Hold time, AS, BS, CT, PS, and UTIME valid after CLKOUT high 2 ns Access time, AS, BS, CT, PS, and UTIME valid after memory identification (A, STATUS) valid tH tH tH tH tH CLKOUT Cycle Type STATUS[5:0] Row Address A[31:0] 15 RL 16 14 AS[2:0] Valid BS[1:0] Valid CT[2:0] Valid PS[3:0] Valid UTIME Valid Figure 121. Local Bus Timing: Cycle Configuration Inputs 144 MAX Setup time, AS, BS, CT, PS, and UTIME valid to CLKOUT no longer low POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3tH – 10 tH ns TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 local bus timing: cycle completion inputs (see Figure 122 and Figure 123) The cycle completion inputs are sampled at the beginning of each row access at the start of the r3 state. The READY input is also sampled at the start of the r6 state and during each column access (2 and 3 cyc/col accesses only). The RETRY input is sampled on each CLKOUT falling edge following r3. The value n as used in the parameters represents the integral number of half cycles between the transitions of the two signals in question. ’C80-40 NO NO. MIN MAX ’C80-50 MIN MAX ’C80-60 MIN MAX UNIT 17 ta(MIDV-CMPV) Access time, RETRY, READY, FAULT valid after memory identification (A, STATUS) valid 18 tsu(CMPV-CKOL) Setup time, RETRY, READY, FAULT valid to CLKOUT no longer high 8.0 7.5 7.5 ns 19 th(CKOL-CMPV) Hold time, RETRY, READY, FAULT valid after CLKOUT low 1.2 1.2 1.2 ns 20 ta(RASL-RRV) Access time RETRY, READY valid from RAS low ntH–8 ntH–7.5 ntH–7.5 ns 21 ta(RLL-RRV) Access time, RETRY, READY valid from RL low ntH–8 ntH–7.5 ntH–7.5 ns ta(CASL-RRV) a(CASL RRV) Access time, READY valid from CAS low (non-usertime mode) 2 cyc/col accesses 22 tH–13.5 tH–12 tH–12 3 cyc/col accesses 2tH–9 2tH–8 2tH–7 POST OFFICE BOX 1443 ntH–9 • HOUSTON, TEXAS 77251–1443 ntH–8 ntH–7 ns ns 145 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 local bus timing: cycle completion inputs (continued) tH tH tH tH tH tH tH tH CLKOUT STATUS[5:0] A[31:0] RL RAS 17 18 21 19 20 RETRY READY FAULT Figure 122. Local Bus Timing: Row-Time Cycle Completion Inputs 146 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tH tH TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 local bus timing: cycle completion inputs (continued) tH tH tH tH tH tH tH tH tH tH CLKOUT STATUS[5:0] A[31:0] CAS/DQM[7:0] 18 22 19 17 READY RETRY Figure 123. Local Bus Timing: Column-Time Cycle Completion Inputs POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 147 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 general output signal characteristics over full range of operating conditions The following general timing parameters apply to all TMS320C80 output signals unless otherwise specifically given. The value n as used in the parameters represents the integral number of half cycles between the transitions of the two outputs in question. For timing purposes, outputs fall into one of three groups – the data bus (D[63:0]); the other output buses (A[31:0], STATUS[5:0], CAS/DQM[7:0]); and non-bus outputs (DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W). When measuring output to output, the named group refers to the first output to transition (output A), and the second output (output B) refers to any output group (see Figure 124). 148 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 general output signal characteristics over full range of operating conditions†(continued) NO NO. 23 24 ’C80-40 PARAMETER th(OUTV-CKOL) th(OUTV-CKOH) MIN Hold time, CLKOUT high after output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ’C80-50 MAX MIN ’C80-60 MAX MIN ntH–7 ntH–5.3 ntH–5.3 ntH–6.5 ntH–4.3 ntH–4.3 ntH–5.5 ntH–3.9 ntH–3.9 MAX UNIT ns Hold time, CLKOUT low after output valid D[63:0] A[31:0] STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–7 ntH–6.5 ntH–6.5 ntH–5.5 ntH–4.5 ntH–4.5 ntH–4 ntH–4 ntH–4.5 ntH–5.5 ntH–4.1 ntH–4.1 ns 25 th(CKOL-OUTV) Hold time, output valid after CLKOUT low ntH–5.5 ntH–5 ntH–5 ns 26 th(CKOH-OUTV) Hold time, output valid after CLKOUT high ntH–5.5 ntH–5 ntH–4 ns ntH–7 ntH–6.5 ntH–5.9 th(OUTV-OUTV) Hold time, output valid after output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–6.5 ntH–5.5 ntH–5.5 ntH–5.5 ntH–5 ntH–4.7 27 28 29 td(CKOH-OUTV) td(CKOL-OUTV) Delay time, CLKOUT no longer low to output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH+7 ntH+6.5 ntH+5.9 ntH+6.5 ntH+5.5 ntH+5.5 ntH+5.5 ntH+5 ntH+4.7 ntH+7 ntH+6.5 ntH+5.9 ns Delay time, CLKOUT no longer high to output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH+6.5 ntH+5.5 ntH+5.5 ntH+5.5 ntH+5 ntH+4.7 ntH+5.5 ntH+5 ntH+5 ns ntH+5.5 ntH+5 ntH+5 ns ntH+7 ntH+6.5 ntH+6.1 ntH+6.5 ntH+5.5 ntH+5.5 30 td(OUTV-CKOH) Delay time, output no longer valid to CLKOUT high 31 td(OUTV-CKOL) Delay time, output no longer valid to CLKOUT low td(OUTV-OUTV) Delay time, output no longer valid to output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W 32 ns ns ns ntH+5.5 ntH+5 ntH+5 † Tested across full voltage. Test temperature is selected by manufacturing test flow. Compliance across full temperature range is ensured by device characterization. ‡ Except for CAS/DQM[7:0] during non user-timed 2 cycle/column accesses POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 149 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 general output signal characteristics over full range of operating conditions† (continued) NO NO. 33 ’C80-40 PARAMETER MIN Pulse duration, output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W tw(OUTV) ’C80-50 MAX MIN ’C80-60 MAX MIN MAX ntH–7 ntH–6.5 ntH–6.1 ntH–6.5 ntH–5.5 ntH–5.5 UNIT ns ntH–5.5 ntH–5 ntH–5 † Tested across full voltage. Test temperature is selected by manufacturing test flow. Compliance across full temperature range is ensured by device characterization. ‡ Except for CAS/DQM[7:0] during non user-timed 2 cycle/column accesses tH tH tH tH tH tH tH tH tH tH tH CLKOUT 30 26 28 24 OutputA 25 31 32 23 27 29 OutputB 33 Figure 124. General Output-Signal Timing 150 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tH TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 data input timing The following general timing parameters apply to the D[63:0] inputs unless otherwise specifically given. The value n as used in the parameters represents the integral number of half cycles between the transitions of the output and input in question (see Figure 125). NO NO. ’C80-40 PARAMETER MIN ’C80-50 MAX MIN ’C80-60 MAX MIN MAX UNIT 34 ta(CKOH-DV) Access time, CLKOUT high to D[63:0] valid ntH–8 ntH–5.3 ntH–4.0 ns 35 ta(CKOL-DV) Access time, CLKOUT low to D[63:0] valid ntH–8 ntH–6.5 ntH–6.5 ns 36 tsu(DV-CKOH) Setup time, D[63:0] valid to CLKOUT no longer low 8 6.1 6.1 ns 37 tsu(DV-CKOL) Setup time, D[63:0] valid to CLKOUT no longer high 8 6.1 6.1 ns 38 th(CKOL-DV) Hold time, D[63:0] valid after CLKOUT low 2 2 2 ns 39 th(CKOH-DV) Hold time, D[63:0] valid after CLKOUT high 2 2 2 ns ta(OUTV-DV) Access time, output valid to D[63:0] inputs valid A[31:0], CAS/DQM[7:0]†, STATUS[5:0] DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W th(OUTV-DV)‡ Hold time, D[63:0] valid after output valid RAS, CAS/DQM[7:0] A[31:0] 40 41 ntH–9 ntH–7 ntH–7 ntH–8 ntH–6.5 ntH–6.5 2 3 2 3 ns 2 3 ns † Except CAS/DQM[7:0] during non user-timed 2 cycle/column accesses ‡ Applies to RAS, CAS/DQM[7:0], and A[31:0] transitions that occur on CLKOUT edge coincident with input data sampling tH tH tH tH tH tH tH tH tH tH tH tH CLKOUT 38 39 37 36 34 35 D[63:0] 41 40 Output Figure 125. Data-Input Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 151 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 local bus timing: 2 cycle/column CAS timing These timing parameters apply to the CAS/DQM[7:0] signals during 2 cycle per column memory accesses only. They should be used in place of the general output and data input timing parameters when the 2 cycle/column (non user-timed) cycle timing is selected (CT[2:0] inputs = 0b110). The value n as used in the parameters represents the integral number of half cycles between the transitions of the signals in question (see Figure 126). MIN 42 43 ’C80-50 ’C80-60 ’C80-40 NO. tw(CASH) tw(CASL) Pulse duration, CAS/DQM high MAX MIN tH–2 3tH–11 tH–2 3tH–9.5 Hold time, CAS/DQM high after output valid D[63:0] A[31:0], STATUS[5:0] DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–5 ntH–4.5 ntH–3.5 ntH–11 ntH–4.5 ntH–3.5 ntH–3 ntH–9.5 Pulse duration, CAS/DQM low 44 th(OUTV-CASL) 45 th(CASL-OUTV) ta(CASL-DV) Hold time, output valid after CAS/DQM low 46 47 th(CASH-DV) Hold time, data valid after CAS/DQM high Access time, data valid from CAS/DQM low tH tH tH tH 3tH–12 2 tH tH tH CLKOUT 42 43 CAS/DQM[7:0] 44 45 47 46 D[63:0] Figure 126. 2 Cycle / Column CAS Timing 152 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns ns ns ns 3tH–12 2 tH Output UNIT MAX tH ns ns tH TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 external-interrupt timing The following description defines the timing of the edge-triggered interrupts EINT1 – EINT3 and the level triggered interrupt LINT4 (see Note 4). See Figure 127. ’C80-40 NO. MIN 48 49 50 tw(EINL) tsu(EINH-CKOH) tw(EINH) tsu(LINL-CKOL) Pulse duration, EINTx low† Setup time, EINTx high before CLKOUT no longer low‡ Pulse duration, EINTx high† MAX ’C80-50 ’C80-60 MIN UNIT MAX 6 6 ns 11.5 9.5 ns 6 6 ns 8 ns Setup time, LINT4 low before CLKOUT no longer high‡ 51 10 † This parameter is assured by characterization and is not tested. ‡ This parameter must only be met to ensure that the interrupt is recognized on the indicated cycle. NOTE 4: In order to assure recognition, LINT4 must remain low until cleared by the interrupt service routine. Interrupt Recognized CLKOUT 49 50 EINTx 51 48 LINT4 Figure 127. External-Interrupt Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 153 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 XPT input timing The following description defines the sampling of the XPT[2:0] inputs. The value encoded on the XPT[2:0] inputs is synchronized over multiple cycles to ensure that a stable value is present (see Figure 128 and Figure 129). MIN 52 53 54 ’C80-50 ’C80-60 ’C80-40 NO. tw(XPTV) tsu(XPTV-CKOH) Pulse duration, XPTx valid† th(CKOH-XPTV) th(RLL-XPTV) Hold time, XPT[2:0] valid after CLKOUT high Hold time, XPT[2:0] valid after RL low§ Setup time, XPT[2:0] valid before CLKOUT no longer low‡ MAX MIN UNIT MAX 12tH 13.5 12tH 12 ns 5 5 ns ns 55 6tH 6tH ns † This parameter is a functional minimum assured by logic and is not tested. ‡ This parameter must only be met to ensure that the XPT input is recognized on the indicated cycle. § This parameter must be met to ensure that a second XPT request does nor occur. This parameter is a functional maximum assured by logic and is not tested. XPT Inputs Sampled XPT Inputs Recognized CLKOUT 53 54 52 XPT[2:0] Figure 128. XPT Input Timing – XPT Recognition CLKOUT STATUS[5:0] XPTn Row Status RL 55 XPT[2:0] XPTn XPTz Figure 129. XPT Input Timing – XPT Service 154 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 host-interface timing (see Figure 130) NO NO. ’C80-40 ’C80-50 MIN MIN MAX ’C80-60 MAX MIN MAX UNIT 56 tsu(REQV-CKOH) Setup time, REQ1 – REQ0 valid to CLKOUT no longer low tH – 7 tH – 7 tH – 5.5 ns 57 th(CKOH-REQV) Hold time, REQ1 – REQ0 valid after CLKOUT high tH – 7 tH – 7 tH – 5.5 ns 58 th(HRQL-HAKL) Hold time for HACK high after HREQ goes low† 4tH – 12 4tH – 12 4tH – 12 ns 59 60 td(HAKL OUTZ) d(HAKL-OUTZ) Delay time, HACK low to output out ut hi-Z‡ All signals except D[63:0] 0 0 0 D[63:0] 1 1 1 61 td(HRQH- HAKH) td(HAKH-OUTD) Delay time, HREQ high to HACK no longer low Delay time, HACK high to outputs driven† 62 tsu(HRQL-CKOH) Setup time, HREQ low to CLKOUT no longer low (see Note 5) 10 10 10 6tH 6tH 6tH 10.5 8.5 8.5 ns ns ns † This parameter is a functional minimum assured by logic and is not tested. ‡ This parameter is assured by characterization and is not tested. NOTE 5: Parameter must be met only to ensure HREQ recognition during the indicated clock cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 155 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 host-interface timing (see Figure 130) (continued) HREQ Sampled CLKOUT 56 57 REQ[1:0] HREQ 62 58 60 HACK 61 59 A[31:0] RL, TRG, WE, DSF, DSF2, DBEN RAS CAS[7:0] D[63:0] DDIN Figure 130. Host-Interface Timing 156 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 video interface timing: SCLK timing (see Figure 131) NO. 63 64 65 MIN tc(SCK) tw(SCKH) SCLK period tw(SCKL) tt(SCK) MAX UNIT 13 ns Pulse duration, SCLK high 5 ns Pulse duration, SCLK low 5 ns Transition time, SCLK (rise and fall)† 66 † This parameter is assured by simulation and is not tested. 2 ns 63 66 64 66 SCLK0 SCLK1 65 Figure 131. Video Interface Timing: SCLK Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 157 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 video interface timing: FCLK input and video outputs (see Note 6 and Figure 132) NO. 67 68 69 70 MIN tc(FCK) tw(FCKH) FCLK period tw(FCKL) tt(FCK) MAX UNIT 25 ns Pulse duration, FCLK high 8 ns Pulse duration, FCLK low 8 ns Transition time, FCLK (rise and fall)† 2 ns 71 th(FCKL-SYL) Hold time, HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK, or CAREA high after FCLK low 72 th(FCKL-SYH) Hold time, HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK, or CAREA low after FCLK low 73 td(FCKL-SYL) Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK, or CAREA low 20 ns 74 td(FCKL-SYH) Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK, or CAREA high 20 ns 0 ns 0 ns † This parameter is assured by simulation and is not tested. NOTE 6: Under certain circumstances these outputs also can transition asynchronously. These transitions occur when controller timing register values are modified by user programming. If the new register value forces the output to change states then this transition occurs without regard to FCLK inputs. 70 68 67 70 69 FCLK0 FCLK1 74 73 72 HSYNCn, VSYNCn, CSYNCn / HBLNKn CBLNKn / VBLNKn CAREAn 71 Figure 132. Video Interface Timing: FCLK Input and Video Outputs 158 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 video interface timing: external sync inputs When configured as inputs, the HSYNCn, VSYNCn, and CSYNCn signals may be driven asynchronously. The following parameters apply only when the inputs are being generated synchronous to FCLKn in order to ensure recognition on a particular FLCKn edge (see Figure 133). NO. 75 76 77 78 MIN MAX UNIT tsu(SIL-FCKH) th(FCKH-SIL) Setup time, HSYNC, VSYNC, or CSYNC low to FCLK no longer low† Hold time, HSYNC, VSYNC, or CSYNC high after FCLK high‡ 5 ns 7 ns tsu(SIH-FCKH) th(FCKH-SIH) Setup time, HSYNC, VSYNC, or CSYNC high to FCLK no longer low§ Hold time, HSYNC, VSYNC, or CSYNC low after FCLK high¶ 5 ns 7 ns † This parameter must be met only to ensure the input is recognized as low at FLCK edge B. ‡ This parameter must be met only to ensure the input is recognized as high at FLCK edge A. § This parameter must be met only to ensure the input is recognized as high at FLCK edge D. ¶ This parameter must be met only to ensure the input is recognized as low at FLCK edge C. A B C D FCLK0 FCLK1 76 77 78 HSYNC0, HSYNC1 VSYNC0, VSYNC1 CSYNC0, CSYNC1 (Inputs) 75 Figure 133. Video Interface Timing: External Sync Inputs POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 159 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 thermal resistance Figure 134 illustrates the maximum ambient temperature allowed for various air flow rates across the TMS320C80 to ensure that the case temperature is kept below the maximum operating temperature (85°C) (see Note A). Values for the GF package include integral heat sink. Values for the GGP package are with no heat sink. Max T A ( °C) Maximum Ambient Temperature Versus Airflow For GF and GGP Packages 85 40 MHz (GF) 80 50 MHz (GF) 75 60 MHz (GF) 40 MHz (GGP) 70 50 MHz (GGP) 65 60 MHz (GGP) 60 55 50 45 40 0 100 200 300 400 500 600 700 800 900 1000 Air Flow (Linear Ft / Min) NOTE A: TMS320C80 power consumption is based on the “typical” values of IDD measured at VDD = 3.3 V. Power consumption varies by application based on TMS320C80 processor activity and I/O pin loadings. User must ensure that the case temperature (TC) specifications are met when defining airflow and other thermal constraints of their system. Figure 134. Airflow Requirements 160 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 emulator interface connection The ’C80 supports emulation through a dedicated emulation port that is a superset of the IEEE Standard 1149.1 (JTAG) Standard. To support the ’C80 emulator, a target system must include a 14-pin header (2 rows of 7 pins) with the connections shown in Figure 135. TMS 2 TRST 3 4 GND PD(+3.3V) 5 6 No pin (key) TDO 7 8 GND TCKRET TDI 1 9 10 GND TCK 11 12 GND EMU0 13 14 EMU1 Pin Spacing: 0.100 in. (X,Y) Pin Width: 0.025 in, square post Pin Length: 0.235 in. nominal (see Table 38) Figure 135. Target System Header Table 38. Target Connectors XDS 510 SIGNAL XDS 510 STATE TARGET STATE TMS O I TDI O I Test-mode select† Test-data input† TDO I O Test-data output† TCK O I TRST O I Test clock – 10 MHz clock source from emulator. Can be used to drive system-test clock.† Test reset† EMU0 I I/O Emulation pin 0 EMU1 I I/O Emulation pin 1 PD (3.3 V) I O Presence detect. Indicates that the target is connected and powered up. Should be tied to + 3.3 V on target system. TCKRET I O Test clock return. Test clock input to the XDS 510 emulator. Can be buffered or unbuffered version of TCK.† DESCRIPTION † IEEE Standard 1149.1. For best results, the emulation header should be located as close as possible to the ’C80. If the distance exceeds six inches, the emulation signals should be buffered. See Figure 136. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 161 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 emulator-interface connection (continued) 3.3 V EMU0 EMU1 TRST TMS TDI TDO T34 (L26) 13 J35 (K25) 14 L33 (J24) 2 N33 (J26) 1 H34 (K23) 3 P32 (K24) 7 E35 (J25) 11 TCK ’C80 GF (GGP) Signal Pins 9 6 in. or less 3.3 V 3.3 V EMU0 3.3 V 5 PD EMU1 EMU0 EMU1 4 TRST GND TMS GND TDI GND TDO GND TCK GND TRST 6 TMS 8 TDI 10 TDO 12 T34 (L26) 13 J35 (K25) 14 L33 (J24) 2 N33 (J26) 1 H34 (K23) 3 P32 (K24) 7 E35 (J25) 11 TCK TCKRET Emulator Header 9 ’C80 GF (GGP) Signal Pins More than 6 in. 3.3 V 5 EMU0 PD EMU1 4 TRST GND TMS GND TDI GND TDO GND TCK GND 6 8 10 12 TCKRET Emulator Header Figure 136. Emulation Header Connections – Emulator Driven Test Clock The target system also can generate the test clock. This allows the user to: D D Set the test clock frequency to match the system requirements. (The emulator provides only a 10-MHz test clock.) Have other devices in the system that require a test clock when the emulator is not connected 3.3 V EMU0 EMU1 TRST TMS TDI TDO TCK 3.3 V T34 (L26) 13 J35 (K25) 14 L33 (J24) 2 N33 (J26) 1 H34 (K23) 3 P32 (K24) 7 E35 (J25) 11 9 ’C80 GF (GGP) Signal Pins System Test Clock PD EMU0 EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 3.3 V 5 4 6 8 10 12 TCKRET Emulator Header More than 6 in. Figure 137. Emulation Header Connections – System Driven Test Clock 162 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 emulator-interface connection (continued) For multiprocessor applications, the following conditions are recommended: D D D D To reduce timing skew, buffer TMS, TDI, TDO, and TCK through the same physical package. If buffering is used, 4.7 kΩ resistors are recommended for TMS, TDI, and TCK which should be pulled high (3.3 V). Buffering EMU0 and EMU1 is highly recommended to provide isolation. The buffers need not be in the same physical package as TMS, TCK, TDI, or TDO. Pullups to 3.3 V are required and should provide a signal rise time of less than 10 µs. A 4.7 kΩ resistor is suggested for most applications. To ensure high quality signals, special printed wire board (PWB) routing and use of termination resistors may be required. The emulator provides fixed series termination (33 Ω) on TMS and TDI and optional parallel terminators (180 Ω pullup and 270 Ω pulldown) on TCKRET and TDO. 3.3 V EMU0 EMU1 TRST TMS TDI TDO TCK 3.3 V T34 (L26) 13 J35 (K25) 14 L33 (J24) 2 N33 (J26) 1 H34 (K23) 3 P32 (K24) 7 E35 (J25) 11 9 EMU0 EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND EMU1 TRST TMS TDI TDO TCK 4 6 8 10 12 TCKRET ’C80 GF (GGP) Signal Pins EMU0 PD 3.3 V 5 Emulator Header T34 (L26) J35 (K25) L33 (J24) N33 (J26) H34 (K23) P32 (K24) E35 (J25) ’C80 GF (GGP) Signal Pins Figure 138. Emulation Header Connections – Multiprocessor Applications POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 163 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 GF package drawing AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31323334 35 Index Mark (Gold Plate) Index Pin M5 x 0.8 STUD 1.895 (48,13) DIA 1.905 (48,39) ÉÉÉ ÉÉÉ ÉÉÉ 0.279 (7,09) 0.299 (7,59) ~ 0.236 (6,00) NOTES: A. Pins are located within 0,13 (0.005) radius of the true position relative to each other at maximum material condition and within 0,457 (0.018) radius of the center of the ceramic. B. Dimensions do not include solder finish. Figure 139. Assembled Package Drawing Showing Integral Heatsink 164 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MECHANICAL DATA GF (S-CPGA-P305) CERAMIC PIN GRID ARRAY PACKAGE 1.717 (43,61) TYP 1.683 (42,75) 1.879 (47,73) SQ 1.841 (46,76) 0.100 (2,54) AR AN AL AJ AG AE AC AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Heatsink 0.050 (1,27) 0.060 (1,52) 0.040 (1,02) 0.019 (0,48) 0.014 (0,36) 0.026 (0,660) 0.006 (0,152) 0.045 (1,14) DIA 4 Places 0.040 (1,02) 0.190 (4,83) 0.170 (4,32) 0.150 (3,81) 0.180 (4,57) 0.110 (2,79) 0.140 (3,56) 4040035-3/E 03/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Package thickness of 0.150 (3,81) / 0.110 (2,79) includes package body and lid, but does not include integral heatsink or attached features. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 165 TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 MECHANICAL DATA GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE 31,75 SQ 35,20 SQ 34,80 1,27 26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Heat Slug 1,70 MAX 0,91 NOM Seating Plane 0,90 0,60 0,50 MIN 0,15 0,30 M 4073223/A 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Thermally enhanced die down plastic package with top surface metal heat slug. 166 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PACKAGE OPTION ADDENDUM www.ti.com 9-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TMS320C80GF OBSOLETE CPGA GF 305 TBD Call TI Call TI TMS320C80GF50 NRND CPGA GF 305 10 TBD Call TI Level-NC-NC-NC TMS320C80GF60 NRND CPGA GF 305 10 TBD Call TI Level-NC-NC-NC TMS320C80GGP50 NRND BGA GGP 352 24 TBD SNPB Level-4-220C-72HR TMS320C80GGP60 NRND BGA GGP 352 1 TBD SNPB Level-4-220C-72HR TMX320C80GF50 OBSOLETE CPGA GF 305 TBD Call TI Call TI TMX320C80GF60 OBSOLETE CPGA GF 305 TBD Call TI Call TI TMX320C80GGP OBSOLETE BGA GGP 352 TBD Call TI Call TI TMX320C80GGP50 OBSOLETE BGA GGP 352 TBD Call TI Call TI TMX320C80GGP60 OBSOLETE BGA GGP 352 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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