TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 N-Channel Controller for Dimmable LED Drives with Low-Side Current Sense Check for Samples: TPS92690 FEATURES DESCRIPTION • The TPS92690/90Q1 is a high voltage, low-side NFET controller with an adjustable output current sense resistor voltage. Ideal for LED drivers, it contains all of the features needed to implement current regulators based on boost, SEPIC, flyback, and Cuk topologies. 1 • • • • • • • • • • • • • TPS92690Q1 is an Automotive Grade Product that is AEC-Q100 Grade 1 Qualified (–40°C to 125°C Operating Junction Temperature) VIN Range from 4.5V to 75V Adjustable Current Sense (50mV – 500mV) Low-side Current Sensing 2-Ω MOSFET Gate Driver Input Under-Voltage Protection Output Over-Voltage Protection Cycle-by-Cycle Current Limit PWM Dmming Input Programmable Oscillator Frequency External Synchronization Capability Slope Compensation Programmable Soft-Start TSSOP-16 Exposed Pad Package Output current regulation is based on peak currentmode control supervised by a control loop. This methodology eases the design of loop compensation while providing inherent input voltage feed-forward compensation. The TPS92690/90Q1 includes a highvoltage start-up regulator that operates over a wide input range of 4.5V to 75V. The PWM controller is designed for high speed capability including an oscillator frequency range up to 2.0 MHz. The TPS92690/90Q1 includes an error amplifier, precision reference, cycle-by-cycle current limit, and thermal shutdown. The TPS92690Q1 is AEC-Q100 grade 1 qualified. APPLICATIONS • • LED Drivers Constant Current Regulator: Boost, Cuk, Flyback, and SEPIC TYPICAL APPLICATION DIAGRAM L1 D1 VIN RUV2 VOUT RUVH 1 ROV2 RUV1 nDIM TPS92690 VIN 16 VOUT CIN 2 VCC OVP 15 ROV1 CBYP 3 IS RT 14 RT ILED 4 CSS CCMP 5 6 7 SYNC GATE SS/SD PGND COMP CSP AGND CLIM RLIM 2 ILIM 11 10 RADJ 2 VREF CO Q1 12 DAP 8 RLIM 1 IADJ 13 RCS RADJ 1 9 CADJ CREF 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) GRADE PACKAGE (2) PINS PACKAGE DRAWING Commercial TSSOP EXP PAD 16 MXA16A AEC-Q100 Grade 1 qualified (3) TSSOP EXP PAD (1) (2) (3) 16 MXA16A ORDERABLE DEVICE NUMBER TRANSPORT MEDIA QUANTITY TPS92690PWP Tube 92 2500 TPS92690PWPR Tape and Reel TPS92690Q1PWP Tube 92 TPS92690Q1PWPR Tape and Reel 2500 For the most current package and ordering information; see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified with the letter Q. ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, –40°C < TJ = TA< 125°C, all currents are positive into and negative out of th specified terminal (unless otherwise noted) VALUE Supply voltage Input voltage range Output voltage range MIN MAX VIN –0.3 76 nDIM, OVP –0.3 76 IS (2) –0.3 76 CSP, IADJ, SS/SD, ILIM –0.3 6 VCC, GATE (3) –0.3 14 COMP, RT, VREF –0.3 6 IS Continuous input current Output current V –1 1 mA 1 VREF –1 mA 150 °C (4) TJ Tstg (2) (3) (4) V SYNC Storage temperature (1) V –1 GATE Junction temperature Electrostatic Discharge UNIT –65 (HBM) QSS 009-105 (JESD22-A114A) Field Induced Charged Device Model (FICDM) 150 °C 2 kV 750 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. IS can sustain -2V for 100ns without damage. GATE can sustain –2.5V for 100 ns, VCC +2.5V for 100 ns. Maximum junction temperature is internally limited. spacer 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 RECOMMENDED OPERATING CONDITIONS (1) unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA< 125°C MIN TYP MAX UNIT VIN Input voltage 4.5 12 75 V TJ Operating junction temperature –40 25 125 °C VIADJ(MAX) Maximum operating IADJ voltage 5 V (1) 0 Operating Ratings are conditions under which operation of the device is specified and do not imply specified performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics table. THERMAL INFORMATION TPS92690 THERMAL METRIC (1) TSSOP (16 PINS) θJA Junction-to-ambient thermal resistance (2) 38.9 θJCtop Junction-to-case (top) thermal resistance (3) 23.2 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 16.9 UNITS °C/W 0.6 16.7 (7) 1.8 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer ELECTRICAL CHARACTERISTICS unless otherwise specified –40°C < TJ = TA < 125°C, VIN = 14 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 7.45 V STARTUP REGULATOR (VCC) VCCREG VCC Regulation ICC = 0mA 6.35 6.9 ICCLIM VCC Current limit VCC = 0V –20 –30 IQ Quiescent current ISD Shutdown current VCCUV VCC UVLO threshold VCCHYS VCC UVLO hysteresis SS/SD = 0V VCC rising VCC falling 3.61 mA 2 3 mA 45 65 μA 4.1 4.50 4.01 83 V mV REFERENCE VOLTAGE OUTPUT VREF Reference voltage No Load 2.40 2.45 2.50 V –0.6 0 0.6 μA 17.1 28.5 39.9 μA –12.6 –16.8 –21 ERROR AMPLIFIER CSP Input bias current COMP sink current gm COMP source current IADJ = 5V Transconductance IADJ = 1V, 0V < VCSP < 0.8V Transconductance bandwidth –6dB IADJ input impedance VCSP Error Amp reference voltage Precise value implied in offset μA/V 1 MHz 1 MΩ VIADJ/10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 μA 33 V 3 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) unless otherwise specified –40°C < TJ = TA < 125°C, VIN = 14 V PARAMETER Error Amp input offset voltage TEST CONDITIONS MIN TYP MAX UNIT VCC = 4.5V, 1V < VCOMP < 1.4V, TA = 25°C –1.5 0 1.5 VCC > 6V, 1V < VCOMP < 3V, VIADJ ≤ 1.25V, TA = 25°C –1.8 0 1.8 VCC > 6V, 1V < VCOMP < 3V, VIADJ > 1.25V, TA = 25°C (% of VCSP) –1.44 0 1.44 % 90% 94.4% 950 1100 1250 mV mV PWM COMPARATOR and SLOPE COMPENSATION DMAX IOFF Maximum duty cycle Internal oscillator only IS to PWM offset voltage No slope added IS to PWM offset voltage D = DMAX (max slope added) IS source current No slope added IOFF + ISL D = DMAX (max slope added) 125 mV –11.9 μA –60 μA CURRENT LIMIT ILIM delay to output tON-MIN Leading edge blanking time Current limit off-timer 60 100 200 300 D = 50% ns μs 38 ILIM offset voltage ns –19 –5.6 5 mV 30 86 mV 24 mV –10.8 μA –1.1 μA LOW POWER SHUTDOWN and SOFTSTART VSD Shutdown threshold voltage VSDH Shutdown hysteresis ISS SS/SD falling VSS/SD > (VSD + VSDH) SS/SD current source VSS/SD < VSD OSCILLATOR and EXTERNAL SYNCHRONIZATION fSW Switching frequency RT = 121k 312 350 389 RT = 100k 372 418 464 RT = 84.5k 436 490 544 2.05 2.36 SYNC threshold voltage (Falling edge triggers Rising on-time) Falling SYNC Clamp Voltage 0.95 1.31 Positive 6.2 Negative –0.5 kHz V V OVER VOLTAGE PROTECTION OVP OVLO threshold OVP hysteresis source current Rising Falling OVP active (high) 1.23 1.282 1.144 1.19 –14 –21.5 -28 1.23 1.285 V μA PWM DIMMING INPUT and UVLO nDIM/UVLO threshold Rising Falling nDIM hysteresis current V 1.14 1.19 –14 –21.6 -28 μA GATE DRIVER GATE sourcing resistance GATE = High 2.4 6.0 Ω GATE sinking resistance GATE = Low 1.0 5.0 Ω Peak GATE current Source Sink –0.47 A 1.1 A 175 °C 25 °C THERMAL SHUTDOWN Thermal shutdown temperature Thermal shutdown hysteresis 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 DEVICE INFORMATION 16-Lead PWP Package (Top View) nDIM 1 16 VIN OVP 2 15 VCC RT 3 14 IS SYNC 4 13 GATE DAP SS/SD 12 PGND 5 COMP 6 11 CSP AGND 7 10 IADJ ILIM 8 9 VREF PIN DESCRIPTIONS PIN I/O DESCRIPTION nDIM I Connect resistor divider from VIN to set UVLO threshold and hysteresis. Connect through diode or MOSFET to PWM dim concurrently. 2 OVP I Connect resistor divider from output voltage to set OVP threshold and hysteresis. 3 RT O Connect resistor to AGND to set base switching frequency. 4 SYNC I Connect external PWM signal to set switching frequency. Must be higher than base frequency set at RT pin. Can also connect series resistor and capacitor to drain of main MOSFET and capacitor to AGND to implement zero-crossing detection for quasi-resonant topologies. In either case, a falling edge on SYNC triggers a new on-time at GATE. If tied to ground, internal oscillator is used. 5 SS/SD I Connect capacitor to AGND to set soft-start delay. Pull pin below 75mV for low power shutdown. 6 COMP 0 Connect ceramic capacitor to GND to set loop compensation. 7 AGND - Connect to PGND through DAP exposed thermal pad for proper ground return path. NUMBER NAME 1 8 ILIM I Connect resistor divider from VREF to set current limit threshold voltage at IS pin. 9 VREF O Connect to IADJ directly or through resistor divider. Bypass with 100nF ceramic capacitor to AGND. 10 IADJ I Connect resistor divider from VREF to set error amp reference voltage. 11 CSP I Connect to positive terminal of sense resistor in series with LED stack. 12 PGND - Connect to AGND through DAP exposed thermal pad for proper ground return path. 13 GATE - Connect to main N-channel MOSFET gate of switching converter. 14 IS I Connect to drain of main N-channel MOSFET or to source of MOSFET if sense resistor is used for improved accuracy. 15 VCC O Bypass with 2.2 µF ceramic capacitor to provide bias supply for controller. 16 VIN I Connect to input supply of converter. Bypass with 100nF ceramic capacitor to AGND as close to the device as possible. - DAP - Exposed thermal pad on the bottom of the package. Connect directly to PGND and AGND beneath the device. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 5 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM 6.9V LDO Regulator VIN VCC VCC UVLO UVLO (4.1V) 1.24V REFERENCE Standby 1.24V 20 mA nDIM UVLO 1.24V 75mV TLIM Thermal Limit SS/SD 100k 100k VREF nUVLO Reset Dominant Clock SYNC OSCILLATOR nUVLO GATE Artificial Ramp RT ISL COMP VCC Q S R DMAX = 90% PGND LEB AGND ISS SS/SD SS/SD t = 200 ns PWM FAULT FAULT 20 mA GM EA CSP IADJ ROFF IOFF Standby 9R R IS ILIM 40 mS Latch LEB 6 OVP OVLO 1.24V RSL ILIM Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 TYPICAL CHARACTERISTICS 95 95 93 93 Efficiency (%) Efficiency (%) Unless otherwise noted, –40°C ≤ TA = TJ≤ +125°C, VIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF 91 89 87 91 89 87 12 LEDs 500mA 85 8 12 16 20 24 Input Voltage (V) 28 32 6 LEDs 500mA 85 36 8 10 12 Input Voltage (V) G000 Figure 1. Boost Efficiency vs Input Voltage 14 16 G000 Figure 2. Boost Efficiency vs Input Voltage 505 1000 Switching Frequency (kHz) 900 Output Current (mA) 503 501 499 497 12 LEDs 495 10 15 20 25 Input Voltage (V) 30 700 600 500 400 300 35 40 60 80 G000 Figure 3. Boost Line Regulation 100 120 RT Resistance (kΩ) 140 160 G000 Figure 4. Switching Frequency vs RT Resistance 800 800 Output Current (mA) Output Current (mA) 800 600 400 600 400 200 200 1A Nominal 20 40 60 PWM Duty Cycle (%) 80 100 0.0 G000 Figure 5. 160 Hz Boost PWM Dimming 0.5 1.0 1.5 IADJ Voltage (V) 2.0 2.5 G000 Figure 6. IADJ Analog Dimming (RCS = 0.25 Ω) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 7 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, –40°C ≤ TA = TJ≤ +125°C, VIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF 95 430 94 425 Efficiency (%) Switching Frequency (kHz) 435 420 415 93 92 91 410 12V Input 36V Output @ 350mA 405 −40 −25 −10 5 20 35 50 65 80 Ambient Temperature (°C) 95 90 −40 −25 −10 110 125 Figure 7. Switching Frequency vs Ambient Temperature (RT = 100 kΩ) 95 110 125 G000 Figure 8. Efficiency vs Ambient Temperature 2.5 370 2.48 360 VREF Voltage (V) Output Current (mA) 5 20 35 50 65 80 Ambient Temperature (°C) G000 350 340 2.46 2.44 2.42 12V Input 36V Output @ 350mA 330 −40 −25 −10 5 20 35 50 65 80 Ambient Temperature (°C) 95 110 125 G000 Figure 9. Output Current vs Ambient Temperature 8 2.4 0 50 Ambient Temperature (°C) 100 G000 Figure 10. VREF Voltage vs Ambient Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 APPLICATION INFORMATION The TPS92690 is an N-channel MosFET (NFET) controller for boost, SEPIC, Cuk, and flyback current regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a variety of LED loads. The low-side current sense, with low adjustable threshold voltage, provides an excellent method for regulating output current while maintaining high system efficiency. The TPS92690 uses peak current mode control providing good noise immunity and an inherent cycle-by-cycle current limit. The adjustable current sense threshold provides a way to analog dim the LED current, which can also be used to implement thermal foldback. The dual function nDIM pin provides a PWM dimming input that controls the main GATE output for PWM dimming the LED current also. When designing, the maximum attainable LED current is not internally limited because the TPS92690 is a controller. Instead it is a function of the system operating point, component choices, and switching frequency allowing the TPS92690 to easily provide constant currents up to 5A. This simple controller contains all the features necessary to implement a high efficiency versatile LED driver. iL (t) IL-MAX ΔiL-PP IL IL-MIN t ON = DT S t OFF = (1-D)TS t 0 TS Figure 11. Basic CCM Inductor Current Waveform CURRENT REGULATORS Current regulators can be designed to accomplish different functions: boost, buck-boost, and flyback. The TPS92690 is designed to drive a ground referenced NFET and sense a ground referenced LED load. This control architecture is perfect for driving boost, SEPIC, flyback, or Cuk topologies. It does not work with a floating buck or buck-boost topology since the LED current sense amplifier is ground referenced. Looking at the boost design in the Typical Boost Application, the basic operation of a current regulator can be analyzed. During the time that the NFET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while the output capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode (D1) becomes forward biased and L1 provides energy to both CO and the LED load. Figure 11 shows the inductor current (iL(t)) waveform for a regulator operating in CCM. The average output LED current (ILED) is proportional to the average inductor current (IL), therefore if IL is tightly controlled, ILED is well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D) is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio: Boost VO - VIN VO (1) Buck-Boost (SEPIC/Cuk) VO D = VO + VIN (2) D = Flyback D = nVO nVO + VIN (3) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 9 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com where n is the primary to secondary turns ratio of the coupled inductor, n:1. PEAK CURRENT MODE CONTROL Peak current mode control is used by the TPS92690 to regulate the average LED current through an array of HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can use either a series resistor in the MosFET path or the MosFET RDS-ON for both cycle-by-cycle current limit and input voltage feed forward. The controller has a fixed switching frequency set by an internal programmable oscillator therefore slope compensation is added to mitigate current mode instability. A detailed explanation of this control method is presented in the following sections. SWITCHING FREQUENCY AND SYNCHRONIZATION The switching frequency of the TPS92690 is programmed using an external resistor (RT) connected from the RT pin to GND. This switching frequency is defined as: 1 ¦ SW = -11 2.29 ´ 10 ´ RT + 80 ´ 10-9 (4) See Typical Characteristics for a graph of switching frequency versus resistance on RT. For maximum operational range and best efficiency a switching frequency of 1MHz or lower is recommended. Switching frequencies as high as 2MHz are possible for reduced solution size but some factors need to be considered. Higher frequencies require increased gate drive current and result in higher AC losses, both of which result in decreased efficiency. It is also possible that the minimum on time (leading edge blanking time) limits the minimum operational duty cycle and reduces the input voltage range for a given output voltage. Alternatively, an external PWM signal can be applied to the SYNC pin to synchronize the part to an external clock. If the PWM signal frequency applied is higher than the base frequency set by the RT resistor, the internal oscillator is bypassed and the switching frequency is equal to the synchronized frequency. The PWM signal should have an amplitude between 2.5V and 5V. The TPS92690 triggers a switch-on time on the falling edge of the PWM signal and operates correctly regardless of the duty cycle of the applied signal. TPS92690 CCMP I LED COMP GM EA *RF CSP PWM VCS IADJ RCS *CF 0-5V 9R R To GATE IT GATE 0-400mV VLIM Artificial Ramp IS ILIM ILIM * RLIM Figure 12. Current Sensed and Control Circuitry (* optional) CURRENT SENSE/CURRENT LIMIT The TPS92690 implements peak current mode control using the circuit shown in Figure 12. The peak detection is accomplished with a comparator that monitors the main MosFET current, comparing it with the COMP pin. When the IS voltage (plus the DC level shift and the ramp discussed later) exceeds the COMP voltage, the MosFET is turned off. The MosFET is turned back on when the oscillator starts a new on-time and the cycle repeats. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 The IS pin incorporates a cycle-by-cycle over-current protection function. Current limit is accomplished by a redundant internal current sense comparator. If the voltage at the current sense comparator input (IS) exceeds the voltage at the ILIM pin, the MosFET is turned off and COMP is pulled to ground and discharged. The MosFET turns back on after either the 43µs current limit timeout has passed or after COMP is charged back up, whichever is longer. The IS input pin has an internal N-channel MosFET which pulls it down at the conclusion of every cycle. The discharge device remains on an additional 216 ns (typical) after the beginning of a new cycle to blank the leading edge spike on the current sense signal. This blanking time also results in a minimum switch-on time of 216 ns which determines a minimum duty cycle dependent upon switching frequency. IS sensing can be done in one of two ways. The most accurate current sensing is accomplished by using a resistor, RLIM. This adds a component that dissipates additional power but the result is higher accuracy and no limitation on the maximum MosFET drain voltage. For applications that have a maximum MosFET drain voltage below 75V MosFET RDS-ON sensing can be used by connecting the IS pin directly to the drain of the MosFET and eliminating RLIM. This results in higher efficiency but the accuracy depends on the accuracy of the MosFET RDSON. Care must be taken to use the maximum expected RDS-ON when setting the current limit threshold at ILIM. AVERAGE LED CURRENT The COMP pin voltage is dynamically adjusted, via the internal error amplifier, to maintain the desired regulation. Average LED current regulation is set using a sense resistor in series with the LEDs. The voltage across the sense resistor (VCS) is regulated to the IADJ voltage divided by 10. IADJ can be set to any value up to 2.45V by connecting it to VREF through a resistor divider for static output current settings. IADJ can also be used to change the regulation point if connected to a controlled voltage source up to 5V or potentiometer to provide analog dimming. It is also possible to configure IADJ to be used for thermal foldback functions. V ILED = CS RCS (5) VCS = VIADJ 10 (6) The TPS92690 maintains high accuracy at any level of VCS but note that the accuracy still is better with higher levels as offsets and other errors become a smaller percentage of the overall VCS voltage. However, power losses are also higher with higher VCS voltages. A good tradeoff for accuracy and efficiency is to set the maximum VCS voltage to between 100mV and 250mV. In some applications, such as a standard boost or flyback, the output capacitor can be connected from the output directly to ground. In these cases the CS pin can be directly connected to RCS. In other applications an additional filter may be desired on CS (RF and CF). These would include topologies where the current through RCS is not continuous such as in the Cuk configuration. Another example would be a boost regulator where PWM dimming is required and the output capacitor is connected directly across the LEDs. In these cases it is recommended to add a 47Ω resistor for RF and a 47nF capacitor for CF to achieve the best accuracy and line regulation. PRECISION REFERENCE (VREF) The TPS92690 includes a precision 2.45V reference. This can be used in conjunction with a resistor divider to set voltage levels for the ILIM pin and the IADJ pin to set the maximum current limit and LED current. It can also be used with high impedance external circuitry requiring a reference. To set the current limit (ICL) using VREF you can use the following equations: V ICL = LIM RLIM (7) VLIM = VILIM = VREF ´ RLIM1 RLIM1 + RLIM2 (8) When RDS-ON sensing is being used substitute RLIM in the above equation with RDS-ON. A small amount of capacitance (CLIM) can be placed from ILIM to ground for filtering if desired. If so, a value between 47pF and 100nF should be used but this value should not exceed the value of CCMP to avoid false triggering of the current limit. To set the IADJ voltage level using VREF use the following equation: Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 11 TPS92690 SLVSBK3 – DECEMBER 2012 VIADJ = VREF ´ www.ti.com R ADJ1 R ADJ1 + R ADJ2 (9) If desired, place a small capacitor (CADJ) from IADJ to ground for additional filtering. A value between 47pF and 100nF should be sufficient. LOW-LEVEL ANALOG DIMMING The IADJ pin of the TPS92690 can be driven as low as 0V. At some level however minimum on time is encountered. This level depends on the switching frequency used. When the voltage on IADJ is lowered beyond this point the TPS92690 begins to skip pulses to maintain average output current regulation. Depending on external components and regulator bandwidth this may or may not result in visible flicker. If flicker is present below this level higher inductor and/or output capacitors may help and a lower COMP capacitor value may help. In many cases this level occurs at very low LED current and it is more desirable to simply limit the low level on the IADJ pin as shown in Figure 13: TPS92690 VREF RADJ 2 IADJ RADJ 1 VADJ Figure 13. Limiting Minimum IADJ Voltage The resulting IADJ voltage can be found using the following equation: R ADJ1 VIADJ = (VREF - VADJ )´ R ADJ1 + R ADJ2 (10) SOFT-START/SHUTDOWN The TPS92690 can be placed into a low power shutdown by grounding the SS/SD pin (any voltage below 100mV). During low power shutdown, the device limits the quiescent current to approximately 40µA, typical. The SS/SD pin also has a 10uA current source (or 1uA when below the 100mV shutdown threshold), which charges a capacitor from SS/SD to GND to soft-start the converter. The SS/SD pin is attached through a PNP transistor to COMP therefore it controls the speed at which COMP rises at startup. When VCCUV is below the falling threshold, SS/SD is pulled down to reset the capacitor voltage to zero. Then when VCCUV rising threshold is exceeded, the pin is released and charges via the 10µA current source. VCC REGULATOR AND START-UP The TPS92690 includes a high voltage, low dropout bias regulator. When power is applied, or SS/SD is released, the regulator is enabled and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended bypass capacitance for the VCC regulator is 2.2 µF to 3.3 µF. This capacitor should be rated for 10V or greater and an X7R dielectric ceramic is recommended. The output of the VCC regulator is monitored by an internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the supply is also internally current limited. VCC may also be driven externally to increase the GATE voltage and reduce the RDS-ON of the external switching MosFET. The maximum voltage on this pin is 14V and should not exceed the VIN voltage. The bypass capacitor voltage rating may need to be increased accordingly. The start-up time of the TPS92690 to full output current depends on the value of CBYP, CSS (soft-start capacitor), CCMP, and CO (output capacitor) as shown in Figure 14: 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 VCMP 1.0V 0 tVCC tCMP tCO 1.0V 0.7V t 0 tVCC t CMP-SS tSS tCO Figure 14. Start-up Waveforms First, CBYP is charged to be above the VCC UVLO threshold of 4.1V. The CBYP charging time (tVCC) can be estimated as: 4.1V ´ CBYP t VCC = 30 mA (11) Assuming there is no CSS (top trace), or if CSS is less than 40% of CCMP, CCMP is then charged to 1V over the charging time (tCMP) which can be estimated as: 1V ´ CCMP t CMP = VCS ´ 35 mS (12) Once CCMP = 1V, the part starts switching to charge CO until the LED current is in regulation. The CO charging time (tCO) can be roughly estimated as: C ´ VO t CO = O ILED (13) If CSS is greater than 40% of CCMP (bottom trace), the compensation capacitor only charges to 0.7V over a smaller CCMP charging time (tCMP-SS) which can be estimated as: 0.7V ´ CCMP t CMP -SS = VCS ´ 35 mS (14) Then COMP clamps to SS, forcing COMP to rise (the last 300mV before switching begins) according to the CSS charging time (tSS) which can be estimated as: 0.3V ´ CSS t SS = 11 mA (15) The system start-up time tSU (for CSS < 0.4 CCMP) or tSU-SS (for CSS > 0.4 CCMP is defined as: t SU = t VCC + t CMP + t CO t SU-SS = t VCC + t CMP -SS + t SS + t CO (16) (17) As a general rule of thumb, standard smooth startup operation can be achieved with CSS = CCMP. If SD/SS is being driven by an external source the equations above may need to be modified depending on the current sourcing capability of the external source. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 13 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com OVER-VOLTAGE PROTECTION (OVP) TPS92690 VO 20 mA ROV2 OVP OVLO 1.24V ROV1 Figure 15. Over-voltage Protection Circuitry The TPS92690 includes a dedicated OVP pin which can be used for either input or output over-voltage protection. This pin features a precision 1.24V threshold with 20 µA (typical) of hysteresis current as shown in Figure 15. When the OVP threshold is exceeded, the GATE pin is immediately pulled low and a 20 µA current source provides hysteresis to the lower threshold of the OVP hysteretic band. The over-voltage turn-off threshold (VTURN-OFF) and the hysteresis (VHYSO) are defined by: R ´ ROV2 VTURN-OFF = 1.24V ´ OV1 ROV1 VHYSO = 20 mA ´ ROV2 (18) (19) INPUT UNDER-VOLTAGE LOCKOUT (UVLO) The nDIM pin is a dual function input that features an accurate 1.24V threshold with programmable hysteresis as shown in Figure 16. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO. When the pin voltage rises and exceeds the 1.24V threshold, 20 µA (typical) of current is driven out of the nDIM pin into the resistor divider providing programmable hysteresis. TPS92690 VIN 20 mA RUV2 RUV1 nDIM RUVH UVLO 1.24V (optional) Figure 16. UVLO Circuit When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra resistor to set the hysteresis. This allows the standard resistor divider to have smaller values minimizing PWM delays due to a pull-down MosFET at the nDIM pin (see PWM DIMMING section). In general, at least 3V of hysteresis is preferable when PWM dimming if operating near the UVLO threshold. The turn-on threshold (VTURN-ON) is defined as follows: R ´ RUV2 VTURN-ON = 1.24V ´ UV1 RUV1 (20) The hysteresis (VHYS) is defined as follows: UVLO Only VHYS = 20 mA ´ RUV 2 (21) PWM Dimming and UVLO æ RUVH ´ (RUV1 + RUV2 ) ö VHYS = 20 mA ´ ç RUV2 + ÷ ç ÷ RUV1 è ø 14 Submit Documentation Feedback (22) Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 PWM DIMMING The active low nDIM pin can be driven with a PWM signal which controls the main NFET. The brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness is approximately proportional to the PWM signal duty cycle (i.e. 30% nDIM high duty cycle ~30% LED brightness). This function can be ignored if PWM dimming is not required by using nDIM solely as a VIN UVLO input as described in the INPUT UNDERVOLTAGE LOCKOUT section or by tying it directly to VCC or VIN when UVLO is not required. Inverted PWM VIN TPS92690 DDIM RUV2 nDIM RUVH RUV1 QDIM Standard PWM Figure 17. PWM Dimming Circuit When using a MosFET (QDIM), connect the drain to the nDIM pin and the source to GND. Apply an external logic-level PWM signal to the gate of QDIM. Brightness is proportional to the negative duty cycle of the PWM signal. When using a Schottky diode (DDIM), connect the anode to the nDIM pin. Apply an external logic-level PWM signal to the cathode of the diode and brightness is proportional to the positive duty cycle of the PWM signal. CONTROL LOOP COMPENSATION Compensating the TPS92690 is relatively simple for most applications. To prevent subharmonic oscillations due to current mode control a minimum inductor value should be chosen. This minimum value can be approximated with the following equation: V ´ 425 ´ 103 Lmin = O (mH) 2 ´ ¦ SW (23) Compensating the control loop simply requires a capacitor from the COMP pin to ground. Most LED driver applications do not require high bandwidth response since there are no significant output transients and generally limited, low bandwidth input transients. The high output impedance (RO) of the error amplifier (typically 200MΩ) enables a low bandwidth system where standard poles and zeros, including the right half plane zero in many cases, can be neglected. In this case the bandwidth of the system generally becomes the bandwidth of the error amplifier. A CCMP value of 1nF to 100nF is recommended and results in the following dominant pole and crossover frequency: 1 ¦P1 = 2p ´ RO ´ CCMP (24) gm ¦C = 2p ´ CCMP (25) A 1nF capacitor results in a bandwith of approximately 5.2kHz while a 100nF capacitor results in a bandwidth of approximately 52Hz. Larger values are recommended for most applications unless higher bandwidth is required. Larger values are also recommended for applications requiring PWM dimming as it allows the COMP pin to hold its level more accurately during the LED current off time. In applications where the duty cycle (D) exceeds 0.5 (VIN < VO/2 for a boost regulator) the location of the right half plane zero should be calculated to ensure stability using the following equation: ¦RHPZ = rD ´ D'2 2p ´ D ´ L1 (26) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 15 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com Where D and D’ are calculated using the minimum input voltage. The crossover frequency fC should be a decade below fRHPZ for maximum stability. CCMP should be adjusted accordingly if required. THERMAL SHUTDOWN The TPS92690 includes thermal shutdown protection. If the die temperature reaches approximately 175°C the device shuts down (GATE pin low). If the die temperature is allowed to cool until it reaches approximately 150°C the device resumes normal operation. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 DESIGN CONSIDERATIONS This section describes the application level considerations when designing with the TPS92690. INDUCTOR The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy is stored in the inductor and transfered to the load in different ways (as an example, boost operation is detailed in the CURRENT REGULATORS section). The size of the inductor, the voltage across it, and the length of the switching subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is chosen to provide a desired ΔiL-PP. For a Cuk regulator the second inductor (L2) has a direct connection to the load, which is good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to the LED ripple current ΔiLED-PP since the inductor ripple in L2 is equal to that in L1. However, for boost and other buck-boost regulators, there is always an output capacitor which reduces ΔiLED-PP, therefore the inductor ripple can be larger than in the Cuk regulator case where output capacitance is minimal or completely absent. In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED). Therefore, for the CUK regulator with no output capacitance, ΔiLED-PP should also be less than 40% of ILED. For the boost and other buck-boost topologies, ΔiL-PP can be much higher depending on the output capacitance value. However, ΔiL-PP is suggested to be less than 100% of the average inductor current (ΔiL) to limit the RMS inductor current. ΔiL-PP is defined as: V ´D DiL -PP = IN L ´ fSW (27) Be sure to observe the minimum inductor value from the CONTROL LOOP COMPENSATION section. L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable RMS inductor current (IL-RMS). LED DYNAMIC RESISTANCE When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RCS. LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the forward voltage of a single LED (VLED) by the forward current (ILED) can lead to an incorrect calculation of the dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value. Figure 18. Dynamic Resistance Obtaining rLED is accomplished by refering to the manufacturer's LED I-V characteristic. It can be calculated as the slope at the nominal operating point as shown in Figure 18. For any application with more than 2 series LEDs, RCS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 17 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com OUTPUT CAPACITOR For boost, SEPIC, and flyback regulators, the output capacitor (CO) provides energy to the load when the recirculating diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a Cuk topology simply reduces the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases, CO is sized to provide a desired ΔiLED-PP. As mentioned in the INDUCTOR section, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED). CO should be carefully chosen to account for derating due to temperature and operating voltage. It must also have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested. INPUT CAPACITOR The input capacitor (CIN) only needs to provide the ripple current due to the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (ΔVIN-PP) which can be tolerated. ΔVIN-PP is suggested to be less than 10% of the input voltage (VIN). An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to minimize the large current draw from the input voltage source during the rising transition of the LED current waveform. The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested. For most applications, it is recommended to bypass the VIN pin with an 0.1µF ceramic capacitor placed as close as possible to the pin. In situations where the bulk input capacitance may be far from the TPS92690 device, a 10Ω series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150kHz filter to eliminate undesired high frequency noise. MOSFET SELECTION The TPS92690 requires an external NFET (Q1) as the main power MosFET for the switching regulator. Q1 is recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the power loss given the average transistor current and the NFET on-resistance (RDS-ON). In general, the NFET should be chosen to minimize total gate charge (Qg) when fSW is high and minimize RDS-ON otherwise. This minimizes the dominant power losses in the system. Frequently, higher current NFETs in larger packages are chosen for better thermal performance. RE-CIRCULATING DIODE A re-circulating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe operation during the ringing of the switch node and a current rating at least 10% higher than the average diode current. The power rating is verified by calculating the power loss through the diode. This is accomplished by checking the typical diode forward voltage from the I-V curve on the product datasheet and multiplying by the average diode current. In general, higher current diodes have a lower forward voltage and come in better performing packages minimizing both power losses and temperature rise. CIRCUIT LAYOUT The performance of any switching regulator depends as much upon the layout of the PCB as the component selection. Following a few simple guidelines maximimizes noise rejection and minimizes the generation of EMI within the circuit. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these paths. In the TPS92690 boost regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1, and RLIM (if used). These loops should be kept as small as possible and the connections between all the components should be short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect) should be just large enough to connect the components. To minimize excessive heating, large copper pours can be placed adjacent to the short current path of the switch node. The RT, COMP, CSP, IS, IADJ, ILIM, and SYNC pins are all high-impedance inputs which couple external noise easily, therefore the loops containing these nodes should be minimized whenever possible. In some applications the LED or LED array can be far away (several inches or more) from the TPS92690, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor. TYPICAL APPLICATION CIRCUITS spacer PWM Dim L1 D1 VOUT VIN RUV2 RUVH 1 ROV2 RUV1 nDIM TPS92690 VIN 16 VOUT CIN 2 OVP VCC 15 ROV1 CBYP 3 RT IS 14 RT ILED 4 CSS CCMP 5 6 SYNC GATE SS/SD PGND COMP CSP 13 CO Q1 12 RF 11 CF 7 AGND CLIM DAP 8 RLIM 1 RLIM 2 IADJ 10 ILIM RADJ 2 VREF RCS RADJ 1 9 CADJ CREF Figure 19. Boost Topology with PWM Dimming Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 19 TPS92690 SLVSBK3 – DECEMBER 2012 www.ti.com PWM Dim CCUK L1 L2 VIN RUV2 RUVH 1 nDIM TPS92690 VIN 16 D1 CIN RUV1 2 OVP VCC OVP 15 CBYP 3 IS RT 14 RT CO 4 CSS 5 CCMP 6 SYNC GATE SS/SD PGND COMP CSP 13 Q1 ILED 12 RF 11 ROV 1 CADJ CF 7 AGND CLIM IADJ RCS 10 Q2 DAP RADJ 1 Q3 RADJ 2 8 ILIM VREF 9 OVP RLIM1 CREF ROV 3 RLIM 2 ROV 2 Figure 20. Cuk Topology (buck-boost) PWM Dim T1 D1 VOUT VIN RUV2 RUV1 RUVH VOUT 1 nDIM TPS92690 VIN 16 ROV 2 CIN 2 VCC OVP 15 ROV 1 CBYP 3 IS RT 14 ILED RT 4 GATE SYNC 13 Q1 CSYNC1 RSYNC 5 PGND SS/SD 12 SYNC CSS 6 COMP CSP RF 11 CADJ CCMP CF 7 IADJ AGND CLIM ILIM RCS 10 DAP 8 RLIM1 CO CSYNC2 RADJ 1 RADJ 2 VREF 9 CREF RLIM 2 Figure 21. Quasi-Resonant Flyback Topology 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 TPS92690 www.ti.com SLVSBK3 – DECEMBER 2012 VIN RUV2 PWM Dim L1 D1 VOUT RUVH 1 nDIM ROV 2 RUV1 CS TPS92690 VIN 16 VOUT L2 CIN 2 VCC OVP 15 ROV 1 CBYP 3 IS RT 14 RT ILED 4 5 SYNC GATE SS/SD PGND COMP CSP 13 CO Q1 12 CSS 6 11 CADJ CCMP RCS 7 AGND CLIM IADJ 10 DAP 8 RLIM 1 RADJ 1 RADJ 2 ILIM VREF 9 CREF RLIM2 Figure 22. SEPIC Topology (buck-boost) PHYSICAL DIMENSIONS in millimeters unless otherwise noted Figure 23. 16-lead TSSOP Exposed Pad Package Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS92690 21 PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS92690PWP/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 TP92690 PWP TPS92690PWPR/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 TP92690 PWP TPS92690Q1PWP/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92690 Q1PWP TPS92690Q1PWPR/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92690 Q1PWP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Feb-2013 OTHER QUALIFIED VERSIONS OF TPS92690, TPS92690-Q1 : • Catalog: TPS92690 • Automotive: TPS92690-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS92690PWPR/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 TPS92690Q1PWPR/NOP HTSSOP B PWP 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92690PWPR/NOPB HTSSOP PWP 16 2500 349.0 337.0 45.0 TPS92690Q1PWPR/NOPB HTSSOP PWP 16 2500 349.0 337.0 45.0 Pack Materials-Page 2 MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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