DS7300 02

®
RT7300
Active PFC Controller with Critical Conduction Mode
General Description
Features
The RT7300 is an active Power Factor Correction (PFC)
controller with critical conduction mode (CRM) operation
that is designed to meet line current harmonic regulations
for the applications of AC/DC adapters, electronic ballasts
and medium off-line power converters (<300W). The CRM
and Feed-Forward schemes provide near unity power factor
across a wide range of input voltages and output powers.

Critical Conduction Mode (CRM) Operation

Constant On-Time Control (Voltage Mode)
Near Unity Power Factor
Ultra Low Start-up Current (<20μ
μA)
Input Voltage Feed-Forward Compensation
Wide Supply Voltage Range from 12V to 25V
Totem Pole Gate Driver with 600mA/−
−800mA
Maximum Frequency Clamping (120kHz)
DCM THD Optimization
Fast Dynamic Response
Light Load Burst Mode Operation
Brown-in/Brown-out Detection
Disable Function
Maximum/Minimum On-Time Limit
Cycle-by-Cycle Current Limit
Output Over Voltage Protection (OVP)
Output Under Voltage Protection (UVP)
Under Voltage Lockout (UVLO)
RoHS Compliant and Halogen Free
The totem-pole gate driver with 600mA sourcing current
and 800mA sinking current provides powerful driving
capability for power MOSFET to improve conversion
efficiency. The RT7300 features an extra low start-up
current (≤20μA) and supports a disable function to reduce
power consumption in standby mode, which makes it easy
to comply with energy saving regulations such as Blue
Angel, Energy Star and Energy 2000.



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

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This controller integrates comprehensive safety protection
functions for robust designs including input under voltage
lockout, output over voltage protection, under voltage
protection and cycle-by-cycle current limit.



The RT7300 is a cost-effective solution for PFC power
converter with minimum external components. It is
available in the SOP-8 package.
Simplified Application Circuit
BD
LPFC
Line
DOUT
VOUT+
RG
Q1
CSIN
COUT
RCS
Neutral
VOUTGD
RZCD
ZCD
RAUX
DVDD
RFF1
INV
VDD
CINV
CVDD
RSTART
CFF
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7300-02 March 2014
ROUT2
COMP
RCOMP
FF
RFF2
ROUT1
CS
RT7300
GND
CCOMP2
CCOMP1
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RT7300
Applications




Electrical Lamp Ballast
LED Lighting
AC/DC Adapter/Charger for Desktop PC, NB, TV, Monitor,
Etc.
Entry-Level Server, Web Server
Marking Information
RT7300GS : Product Number
RT7300
GSYMDNN
YMDNN : Date Code
Pin Configurations
(TOP VIEW)
Ordering Information
RT7300
Package Type
S : SOP-8
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
INV
8
VDD
COMP
2
7
GD
FF
3
6
GND
CS
4
5
ZCD
SOP-8
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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DS7300-02 March 2014
RT7300
Functional Pin Description
Pin No.
Pin Name
Pin Function
Inverting Input of the Internal Error Amplifier. Connect a resistive divider from output
voltage to this pin for voltage feedback. It also used for OVP and UVP detections.
1
INV
2
COMP
Output of the Internal Error Amplifier. Connect a compensation network between this pin
and GND for dynamic load performance.
3
FF
Feed-Forward Input for Line Voltage. This pin senses the line input voltage via a
resistive divider. Connect a suitable capacitor to filter out the line voltage ripple & noise.
4
CS
Current Sense Input. The current sense resistor between this pin and GND is used for
current limit setting.
5
ZCD
Zero Current Detection Input. Input from secondary winding of PFC choke for detecting
demagnetization timing of PFC choke. This pin also can be used to enable/disable the
controller.
6
GND
Ground of the Controller.
7
GD
Gate Driver Output for External Power MOSFET.
8
VDD
Supply Voltage Input. The controller will be enabled when VDD exceeds Von_th (16V
typ.) and disabled when VDD decreases lower than Voff_th (9V typ.).
Function Block Diagram
Blank & Maximum
Frequency Clamping
ZCD
S
Zero Current Detect
Clamping
Circuit
Start
Leading Edge Blanking
COMP
+
+
80µs
De-bounce
Brown-In
80µs
De-bounce
Brown-Out
2.5V
FF
GD
+
0.4V
0.6V
R
Soft
Driver
Disable
CS
1.1V
Q
Feed- Forward &
THD Optimize
Ramp Generator
-
UVLO
VDD
GND
+
GM
-
-
2.75V
- OVP
+
+
- UVP
0.4V
+
INV
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7300-02 March 2014
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RT7300
Operation
Critical Conduction Mode (CRM)
The Critical Conduction Mode is also called Transition
Mode or Boundary Mode. Figure 1 shows the CRM
operating at the boundary between Continuous Conduction
Mode (CCM) and Discontinuous Conduction Mode (DCM).
IL_pk  | sinθ | =
VIN_pk | sinθ | TON
LPFC
(2)
VIN
 TON
LPFC
Iin_avg = 1  IPK
2
IL_pk =
In CRM, the power switch turns on immediately when the
inductor current decreases to zero. The CRM is the
preferred control method for medium power (<300W)
applications due to the features of zero current switching
and lower peak current than that in DCM.
Inductor Current
DCM
CRM
CCM
Figure 1. Inductor Current of DCM, CRM and CCM
Figure 2 shows a typical Boost converter. When the
MOSFET turns on with a fixed on-time (TON), the inductor
current can be calculated by the following equation (1).
VIN
COUT
VIN
 TON
LPFC
(1)
If the input voltage is a sinusoidal waveform and rectified
by a bridge rectifier, the inductor current can be expressed
with equation (2). When the converter operates in CRM
with constant on-time voltage mode control, the envelope
of inductor peak current will follow the input voltage
waveform with in-phase. The average inductor current will
be half of the peak current shown as Figure 3. Therefore,
the near unity power factor is easy to be achieved by this
control scheme.
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IQ1
MOSFET Current
Iin_avg
Average Input Current
IDOUT
Output Diode Current
Figure 3. Inductor Current of CRM with Constant
On-Time Voltage Mode Control
The controller will be enabled when VDD exceeds Von_th
(16V typ.) and disabled when VDD decreases lower than
Voff_th (9V typ.).
RLOAD
Figure 2. Typical Boost Converter
IL_PK =
Peak Inductor Current
Under Voltage Lockout
DOUT
Q1
Input Voltage
IL_PK
VQ1_GATE MOSFET Gate Voltage
Constant On-Time Voltage Mode Control
LPFC
VIN
The maximum VDD voltage is set at 27V typically for over
voltage protection shown as Figure 4. An internal 29V
zener diode is also used to avoid over voltage stress for
the internal circuits.
When the VDD is available, the precise reference is
generated for internal circuitries such as Error Amplifier,
Current Sense, OVP, UVP, Brown-in and Brown-out. The
internal reference equips with excellent temperature
coefficient performance so that the RT7300 can be
operated in varied environments.
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RT7300
Bias &
Band Gap
UVLO
+
ICOMP_Sourcing Current
VDD
Hys. = 7V
-
>1mA
29V
+
10µs
De-Bounce
Max. Sourcing Current
16V
+
+
UV
27V
OVP
OV
0.4V
2.25V
2.5V 2.75V
GM
=1
00
µA
/V
Figure 4. VDD and UVLO
INV
Feedback Voltage Detection
Figure 5 shows the feedback voltage detection circuit.
The INV pin is the inverting input of the Error Amplifier
with 2.5V reference voltage. Over voltage and under voltage
protections are provided with threshold voltage 2.75V and
0.4V respectively. If the INV voltage is over 2.75V or under
0.4V, the gate driver will be disabled to prevent output
over voltage condition or feedback open condition. Although
the INV is an input pin with high impedance, it is suggested
that the bias current of the potential divider should be over
30μA for noise immunity.
COMP
2.5V
VOUT+
ROUT1
ROUT2
INV
2.75V
+
GM
- OVP
+
CINV
-
0.4V
UVP
Figure 6. Non-linear GM
Feed-Forward Compensation
The FF pin is an input pin with high impedance to detect
the line input voltage shown as Figure 7. A proper voltage
divider should be applied to sense the line voltage after
bridge diode rectifier. Since the FF voltage is proportional
to the line input voltage, it provides a feed-forward signal
to compensate the loop bandwidth for high line and low
line input conditions. The FF pin is also used for the
detection of Brown-in and Brown-out functions to protect
converter from over stress at low input voltage situation.
+
1.1V
Figure 5. Feedback Voltage Detection
Transconductance Error Amplifier
The RT7300 implements transconductance error amplifier
with non-linear GM design to regulate the Boost output
voltage and provide fast dynamic response. The
transconductance value is 100μA/V in normal operation.
When the INV voltage increases over 2.75V or decreases
under 2.25V, the output of error amplifier will source or
sink 1mA maximum current at COMP pin respectively
shown as Figure 6. Thus, the non-linear GM design can
provide fast response for the dynamic load of PFC
converters even though the bandwidth of control loop is
lower than line frequency.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7300-02 March 2014
+
-
VCSIN
RFF1
RFF2
0.6V
FF
+
80µs
De-bounce
Brown-In
80µs
De-bounce
Brown-Out
Feed- Forward & THD
Optimize Ramp Generator
CFF
2.5V
INV
+
+
GM
-
PWM OFF
-
COMP
Figure 7. FF Detection Circuit
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RT7300
The constant on-time, TON, can be derived from the following
equations.
P i = 1  Vpk  IL_pk
4
ILPFC
IL_pk =
Vpk
 TON
LPFC
Vpk
V 2pk
 TON = 1 
 TON
P i = 1  Vpk 
4
LPFC
4 LPFC
4  P i  LPFC
 TON =
V 2pk
T1 = Ton
Then, the VComp can be derived from equation (3) and (4).
Cramp  VComp
4  P i  LPFC
=
2
Iramp
V pk
4  P i  LPFC Iramp

Cramp
V 2pk
(5)
In order to compensate the variation, the Iramp is designed
to be proportional to the squared input voltage shown as
equation (6).
VComp (FF) =
2  P i  LPFC  gmramp
Cramp
CRM
ILPFC
T1 = Ton
T2
T3
Ts,min
 T1  T2 
Vpk
iavg = 1 
 T1 
2 LPFC
Ts,min
According to equation (5), the V Comp is reversely
proportional to the squared input voltage so that the VComp
has a large variation for the change of line voltage between
high and low input voltages. This variation will impact TON,
Burst mode entry level and loop bandwidth.
Iramp (Vpk ) = k  V 2pk  gmramp
Vpk
iavg = 1 
 T1
2 LPFC
(3)
In RT7300, the Ton is implemented by a constant current
charging a capacitor till VComp threshold voltage is reached.
Therefore, the TON is a function of Vcomp.
Cramp  VComp
TON =
Iramp
(4)
VComp =
T2
Ts
DCM
Figure 8. Inductor Current in CRM and DCM
In order to compensate the distortion of DCM operation,
the average current in DCM must be equal to the average
current in CRM. It is implemented by increasing the ontime (Iramp) in DCM to achieve the optimized THD for input
current.
TS,min
(8)
T'1 = T1 
= T1  1
(T1  T2 )
D'
(9)
I'ramp = Iramp  D'
(6)
(7)
When k = 0.5, the Vcomp is compensated to be
proportional to the power only. So, the Ton will be stable
to support good power factor for high and low line voltage
conditions.
Input Current Waveform
Without THD Optimization
With THD Optimization
THD Optimization
When the controller operates in a very low input voltage
level, the switching frequency will be clamped at a
maximum frequency 120kHz to reduce EMI. In this
condition, the inductor current will be operated in DCM,
the input average current will be distorted due to the blank
duration T3 shown as Figure 8.
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DCM
CRM
DCM
Figure 9. Input Current with THD Optimization
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DS7300-02 March 2014
RT7300
Ramp Generator
The RT7300 provides constant on-time voltage mode
control to achieve near unity power factor for the CRM
boost converters. Figure 10 shows the Ramp Generator
with Feed-Forward compensation and THD optimization
circuit for the constant on-time operation.
FF
DOUT
N1
k x V2FF
Q1
NAUX
COUT
VOUT-
RZCD
Upper
Clamp
gmramp
+
GM
Cramp
D'
VOUT+
ZCD
Lower
Clamp
VZCDA
1.6V
VZCDT
1V
+
Q Dmag
R
Q
+
-
0.25V/1V
S
-
+
Disable
Ramp Generator
2.5V
INV
+
+
GM
-
Figure 11. ZCD Block Diagram
PWM OFF
-
COMP
Figure 10. Ramp Generator
The capacitance Cramp is 6.5pF (typ.).
The charging current of ramp generator is modulated
following the squared FF voltage with line voltage
compensation and the THD optimization scheme is
implemented to compensate the harmonic distortion when
the converter is operated in DCM.
The RT7300 provides shutdown function to save power
consumption in standby mode. When the ZCD pin is pulled
lower than 250mV, the gate driver will be turned off and
operate in standby mode with low quiescent current less
than 600μA. Once the ZCD pin is released, the controller
will be activated.
The RT7300 also provides ZCD time-out detection function.
If the controller runs at maximum frequency and there is
no ZCD signal being detected after 4μs delay time, the
PWM will be turned on for ZCD time-out detection.
ZCD and Enable Function
In CRM operation, when the power switch turns on, the
inductor current increases linearly to the peak value. When
the power switch turns off, the inductor current decreases
linearly to zero. The zero current can be detected by the
ZCD pin with the auxiliary winding of Boost inductor.
Figure 11 and Figure 12 show the ZCD block diagram and
related waveforms. The ZCD block diagram provides zero
current detection, voltage clamp and shutdown control
functions. When the inductor current decreases to zero,
the auxiliary winding voltage will turn from high to low.
Once the ZCD voltage decreases to the VZCDT threshold,
the controller will generate a signal for gate driver. The
hysteresis voltage between the threshold VZCDA and VZCDT
is designed to avoid mis-triggering. In order to prevent
over voltage stress, the ZCD pin voltage is clamped at
VZCDH if the input voltage is too high from the auxiliary
winding and the ZCD pin voltage is clamped at VZCDL if the
input voltage is lower than zero.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7300-02 March 2014
VAUX
ILPFC
GD
VZCD
Upper Clamp
VZCDA
VZCDT
VZCD_en
VZCD_dis
Lower Clamp
Figure 12. ZCD Related Waveforms
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RT7300
Absolute Maximum Ratings









(Note 1)
Supply Voltage, VDD ----------------------------------------------------------------------------------------------------Gate Driver Output, GD --------------------------------------------------------------------------------------------------Other Pins ------------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 -----------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8, θJA -----------------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) -----------------------------------------------------------------------------------------------------
Recommended Operating Conditions


−0.3 to 30V
−0.3V to 20V
−0.3V to 6V
0.625W
160°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Voltage, VDD ----------------------------------------------------------------------------------------------------- 12V to 25V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specification)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
25.5
27
28.5
V
VDD Section
VDD OVP Threshold Voltage
VOVP
--
10
--
s
VDD On Threshold Voltage
VON_TH
15
16
17
V
VDD Off Threshold Voltage
VOFF_TH
8
9
10
V
Zener Voltage
29
--
--
V
Operating Supply Current
VZ
IDD_OP
I ZCD = 0, @ GATE = open, 70kHz
--
--
2.5
mA
Quiescent Current
IQ
Turn on in burst mode @ gate open
--
--
1.7
mA
PFC is disabled
--
--
0.6
mA
IDD_ST
Before VON_TH
--
--
20
A
Upper Clamp Voltage
VZC_DH
I ZCD = 2.5mA
4.5
4.8
5.5
V
Lower Clamp Voltage
VZC_DL
I ZCD = 2.5mA
0.3
0.65
--
V
Arming Voltage
VZC_DA
(Note 5)
--
1.6
--
V
Trigger Voltage
Delay Time Between Trigger
Point and Gate Turn On
ZCD Time-Out
VZC_DT
(Note 5)
--
1
--
V
--
100
170
ns
--
4
--
s
Sourcing Current Capability
2.5
--
6.5
mA
Sinking Current Capability
2.5
--
--
mA
VDD OVP De-bounce Time
Standby Current
Start-Up Current
ZCD Section
TZC_TOUT
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DS7300-02 March 2014
RT7300
Parameter
Disable Voltage
Symbol
VZCD_ DIS
Restart Voltage
VZCD_ EN
Test Conditions
Pull-High Current After Disable
Min
Typ
Max
Unit
--
--
250
mV
1
--
--
V
30
75
100
A
--
--
1
A
FF Section
Input Bias Current
I BIAS
Leakage Current of FF Pin
Brown-In Threshold
VBR_IN
1.04
1.1
1.16
V
Brown-Out Threshold
VBR_OUT
0.55
0.6
0.65
V
40
80
150
s
2.475
2.5
2.525
V
--
--
1
A
If |V ERROR| < 0.25V
80
100
120
A/V
Otherwise
--
1
--
mA
4.25
--
--
V
INV OVP Threshold Voltage
2.65
2.75
2.85
V
INV UVP Threshold Voltage
0.3
0.4
0.5
V
--
20
--
s
Brown-In/Out De-bounce Time
GM Section
Non-Inv erting Input Reference
VREF
Including Offset, Full VDD Range,
TA = 25C
INV Bias Current
Transconduction
gm
Non-linear Gm
COMP Maximum Voltage
VCOMP_OP
PWM Section
INV OVP/UVP De-bounce Tim e
Burst Mode Entry
Lev el High
VBURST_H
Measure at COMP Pin
0.3
0.35
0.4
Lev el Low
VBURST_L
Measure at COMP Pin
0.2
0.25
0.3
1.5
2
4
s
2.15
2.5
2.85
A/V
TON(MIN)_PFC = 3pF x 2.5V / (IZCD x
0.02), IZCD = 75A
4.4
5.4
6.4
s
LEB + Delay (Note 6)
240
400
570
ns
0.35
0.4
0.45
V
De-bounce Time of Burst Mode
Ramp Charging Current
gm RAMP
Minimum On-Time
V
Current Sense Section
Leading Edge Blanking Time
Current Sense Threshold
Voltage
Gate Driver Section
T LEB_PFC
Rising Time
TR
CL = 1nF
--
40
80
ns
Falling Time
TF
CL = 1nF
--
30
70
ns
Gate Output Clamping Voltage
VCLAMP
VDD = 25V
--
13
--
V
--
12
--
k
VCS_PFC
Internal Pull Low Resistor
Oscillator Section
Valley Mask Tim e
T MASK
7
8.5
10
s
Duration of Starter
T START
T ON(MAX)_PFC Maximum TON(MAX)_PFC
75
130
300
s
--
50
--
s
Maximum On-Time
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RT7300
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
Note 6. Leading edge blanking time and internal propagation delay time is guaranteed by design.
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is a registered trademark of Richtek Technology Corporation.
DS7300-02 March 2014
RT7300
Typical Application Circuit
Typical Application Circuit for Boost PFC Pre-Regulator
DS
Line
BD
F1
LPFC
DOUT
RG
VOUT+
Q1
CSIN
COUT
RCS
RNTC
Neutral
VOUT7
GD
RZCD
5
RS
ZCD
INV
CAUX
8
DVDD
1
VDD
CINV
COMP
3
ROUT2
2
RCOMP
FF
CFF
RFF2
ROUT1
CCS
CVDD
RSTART
RFF1
4
RT7300
RAUX
DZ
CS
CCOMP2
CCOMP1
GND
6
Typical Application Circuit for Single Stage PFC Converter
Line
F1
BD
T1
DOUT
CSIN
RSN
RSTART
RNTC
RG
Q2
DZ
COUT2
VOUTU2A
Q1
Neutral
VOUT+
RS
COUT1
RCN
RFB1 CFB1
7
GD
RZCD
5
ZCD
DVDD
8
RINV
1
DINV
RFF1
RFF2
VDD
COMP
ROUT1
RCS
CN VDD
OUT
RT8456
CP
FB
GND
RFB2 CFB2
ROUT2
U2B
2
CCOMP
GND
3
4
CCS
INV
6
FF
CFF
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DS7300-02 March 2014
CS
RT7300
RAUX
CVDD
RS
U3
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RT7300
Typical Operating Characteristics
Non-inverting Input Reference vs. VDD
2.54
2.52
75°C
25°C
125°C
−10°C
−40°C
2.50
2.48
2.46
2.44
9
14
19
24
Non-inverting Input Reference vs. Temperature
2.56
Non-inverting Input Reference (V)1
Non-inverting Input Reference (V)1
2.56
2.54
2.52
2.50
2.48
2.46
VDD = 16V
2.44
29
-50
-25
0
VDD (V)
100
100
VDD = 10V
VDD = 26V
VDD = 16V
96
94
92
90
VCOMP = 0.5V
88
-50
-25
25
50
125
94
92
VCOMP = 4V
75
100
-50
125
-25
0
25
50
75
100
125
Temperature (°C)
ICOMP vs. VCOMP (Sourcing)
ICOMP vs. VCOMP (Sinking)
1800
Non-linear Region
Non-linear Region
1500
I COMP (µA) 1
-500
I COMP (µA) 1
100
96
Temperature (°C)
0
75
VDD = 10V
VDD = 26V
VDD = 16V
98
90
0
50
Transconduction vs. Temperature
102
Transconduction (µA/V)1
Transconduction (µA/V)1
Transconduction vs. Temperature
102
98
25
Temperature (°C)
-1000
VDD = 26V, TA = 25°C
VDD = 10V, TA = 25°C
VDD = 26V, TA = 125°C
VDD = 10V, TA = 125°C
VDD = 26V, TA = −40°C
VDD = 10V, TA = −40°C
-1500
-2000
1200
VDD = 26V, TA = 25°C
VDD = 10V, TA = 25°C
VDD = 26V, TA = 125°C
VDD = 10V, TA = 125°C
VDD = 26V, TA = −40°C
VDD = 10V, TA = −40°C
900
600
300
-2500
0
0
1
2
3
4
VCOMP (V)
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5
0
1
2
3
4
5
VCOMP (V)
is a registered trademark of Richtek Technology Corporation.
DS7300-02 March 2014
RT7300
Maximum COMP Voltage vs. VDD
Maximum COMP Voltage vs. Temperature
4.43
Maximum COMP Voltage (V)1
Maximum COMP Voltage (V)1
4.440
4.435
4.430
4.425
4.420
4.415
4.410
4.42
4.41
4.40
4.39
4.38
4.37
VDD = 10V
4.36
8
10.5
13
15.5
18
20.5
23
25.5
-50
28
-25
0
VDD (V)
Burst Mode Entry Level vs. VDD
75
100
125
Burst Mode Entry Level vs. Temperature
0.40
0.35
Burst Mode Entry Level (V)1
Burst Mode Entry Level (V)1
50
Temperature (°C)
0.40
VBurst_H
0.30
0.25
VBurst_L
0.20
0.15
0.10
0.05
0.00
0.35
VBurst_H
0.30
0.25
VBurst_L
0.20
0.15
0.10
0.05
0.00
8
10.5
13
15.5
18
20.5
23
25.5
28
-50
-25
0
VDD (V)
3.0
30
2.5
25
On-Time (µs)
35
2.0
VDD = 16V
VDD = 26V
VDD = 10V
1.0
50
75
100
125
On-Time vs. Feed-Forward pin Voltage
3.5
1.5
25
Temperature (°C)
On-Time vs. COMP Voltage
On-Time (µs)
25
20
15
VCOMP = 4V
VCOMP = 2V
10
0.5
5
FF = 2.8V
0.0
0
0
1
2
3
4
COMP Voltage (V)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7300-02 March 2014
5
0.5
1
1.5
2
2.5
3
Feed-Forward pin Voltag (V)
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13
RT7300
Application Information
Start-Up Circuit Design
VCSIN
BD
Line
RStart =
CSIN
Neutral
IDD_ST
IchVDD
RT7300
DVDD
CVDD
(11)
where VBNO is the Brown-out voltage. Note that the startup resistor must have adequate voltage rating for reliability.
2 resistors in series can be applied for most of applications.
IST
RSTART
VDD
2  VBNO
IDD_ST  IchVDD  Ileakage
AUX.
For example, the system required start-up time is 3sec,
VBNO = 75V and maximum IDD_ST = 20μA. If CVDD = 22μF
is selected and the leakage current of CVDD can be ignored,
the start-up resistor should be less than 772kΩ.
Ileakage
GND
Figure 13. Start-Up Circuit
Brown-In and Brown-Out
tstart
VDD
The FF pin is used for the detection of Brown-in and Brownout functions to protect converter from over stress at low
input voltage situation. A proper voltage divider should be
applied to sense the line voltage after bridge diode rectifier
shown as Figure 15.
VON_TH
VOFF_TH
VCSIN
RFF1
Supplied by IST
IDD
IDD_ST ~20µA
Supplied by AUX. and IST
RFF2
-
0.6V
+
80µs
De-bounce
Brown-In
80µs
De-bounce
Brown-Out
Figure 15. Brown-In/Brown-Out Application Circuit
Figure 13 and Figure 14 show the equivalent start-up circuit
and VDD waveform during start-up. In general, the startup time (tstart) is required from system specification. The
charging current (IchVDD) can be estimated by the following
equation.
CVDD  VON_TH
t start
GD
Brown-Out
Brown-In
Brown-Out
Figure 16. Brown-In/Brown-Out Waveform
The start-up resistor (Rstart) connected between VCSIN and
VDD should be able to support the charging current
(IchVDD), start-up current (IDD_ST) and leakage current
(Ileakage) of CVDD before the VDD is supported by the
auxiliary winding. The maximum start-up resistance can
be calculated by the equation (11).
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
VCSIN
(10)
where CVDD is the capacitor connected between VDD and
GND, VON_TH is the power on threshold (16V typ.).
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14
+
FF
CFF
-
~ mA
Figure 14. Start-Up Waveforms of VDD and IDD
IchVDD =
1.1V
The Brown-in threshold voltage at FF pin is set at 1.1V. In
other words, the controller will be active when the input
voltage increases to be higher than the threshold voltage.
Once the Brown-in voltage (VBNI in rms) is decided, the
resistor RFF1 and RFF2 can be estimated by the equation
(12). For the noise immunity and power saving
consideration, RFF2 is suggested to be around 100kΩ.
is a registered trademark of Richtek Technology Corporation.
DS7300-02 March 2014
RT7300
RFF1

RFF2
2  VBNI
1
1.1V
Zero Current Detection
(12)
The capacitor CFF is applied to filter out the input ripple
voltage. The corner frequency should be lower than line
frequency (fline). If the FF pin voltage is not flat, the PF
and THD performance will be degraded.
1
< 0.1 fline
2  (RFF1 // RFF2 )  CFF
(13)
where VOUT is the output voltage of the PFC converter and
N is the turn ratio of auxiliary winding and Boost inductor.
Boost Inductance Design
Differ from the traditional transient mode PFC, the Boost
inductor design is based on the RT7300 internal parameters
and the parameter “S”.
S=
RFF1  RFF2
RFF2
(14)
Assume the maximum input power is Pin, the inductance
of the Boost inductor can be derived as following equations.
IL_pk = 2 
=
Pin
 2
VIN(MIN)
2  VIN(MIN)

LPFC
LPFC =
VCOMP  CRamp
 2  VIN(MIN) 2 
0.5  gmRamp  
 


S


2
 2  m  VCOMP_OP  CRamp  S2
2
(μH)
MOSFET Selection
The RT7300 is designed to operate using an external Nchannel power MOSFET. Important parameters for the
power MOSFET are breakdown voltage (BVDSS), threshold
voltage (VGS_TH), on-resistance (RDS(ON)), total gate charge
(Qg) and maximum current (ID(MAX)). The gate driver voltage
is from VDD and clamped under 13V typically. Lower Qg
characteristics results in lower power losses and lower
RDS(ON) results in higher efficiency. For high voltage
application, it is important to select a device with low gate
charge and balance the power consumption between
switching loss and conduction loss.
Diode Selection
8  Pin  gmRamp
= m  S  13.63
Pin
The zero current of inductor is detected from the auxiliary
winding shown as typical application circuit. The RZCD is
used to limit the current into ZCD pin to be lower than
2.5mA. Thus, the RZCD is determined by the equation as
below.
VOUT
R ZCD >
N  2.5mA
(17)
(15)
where “m” is the ratio of VComp/VComp_op which is the
derating factor of the maximum power. It's suggested to
use 0.6 to 0.9 for the m factor.
Since there is no reverse recovery loss of diode when
converter operates in CRM, the diode choosing is based
on reverse voltage, forward current and switching speed.
ID(RMS) = IL_pk 
2  VIN(MIN)
  VOUT
(18)
VD(PK) = VOUT
(19)
Current Limit Setting
The maximum current of the power MOSFET is limited
by the current sense resistor between the CS pin and
GND. The threshold voltage at CS pin is 0.4V typically.
The current sense resistor can be calculated by the
equation (16) with the peak current of MOSFET.
RCS = 0.4V  80%
IL_pk
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7300-02 March 2014
Output Capacitor Selection
The hold-up time and output voltage (VOUT) are the major
requirements for determining the output capacitance. The
narrow VOUT range can improve the efficiency of DC/DC
converter in next power stage. Lower ESR can reduce
the power loss of PFC converter and get longer lifetime.
(16)
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RT7300
2  PIN   THoldup
0.8
2
2
VOUT
 VOUT(MIN)
Maximum Power Dissipation (W)1
COUT(MIN) =
(20)
IC(RMS) =
2
IL_pk

2  VIN(MAX)  PIN

  VOUT
 VOUT
2

2
   ac RMS load current 

(21)
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 package, the thermal resistance, θJA, is 160°C/W
on a standard JEDEC 51-3 single-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (160°C/W) = 0.625W for
SOP-8 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 17 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
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16
Single-Layer PCB
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 17. Derating Curve of Maximum Power
Dissipation
Layout Considerations
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply. Please refer
to the guidelines when designing a PCB layout for
switching power supply.

The current path(1) from input capacitor, inductor,
MOSFET, RCS return to input capacitor and the current
path(2) from input capacitor, inductor,output diode,
output filter capacitor return to input capacitor are high
frequency current loops. The path(3) from GD
pin,MOSFET, RCS to ground is also a high frequency
current loop. They must be as short as possible to
decrease noise coupling and kept a space to other low
voltage traces, such as IC control circuit paths,
especially. Besides, the path(4) between MOSFET
ground(b) and IC ground(d) is recommended to be as
short as possible, too.
It is good for reducing noise, output ripple and EMI issue
to separate ground traces of input capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control circuit(d).
Finally, connect them together on input capacitor
ground(a). The areas of these ground traces should be
kept large.
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DS7300-02 March 2014
RT7300

Placing bypass capacitor for abating noise on IC is highly
recommended. The capacitors CINV and CCS should be
placed as close to controller as possible.
In addition, apply sufficient copper area at the anode
and cathode terminal of the diode for heat-sinking. It is
recommended to apply a larger area at the quiet cathode
terminal. A large anode area will induce high-frequency
radiated EMI.
Line
F1
VOUT+
(c)
RNTC
(1)
GD
Neutral
ZCD
(2)
VOUT-
CS
(a)
CCS
(3)
RT7300
(b)
Input capacitor
Ground(a)
(4)
GND
VDD
RCS
(d)
INV
Trace
Trace
Trace
CINV
COMP
IC
Ground(d)
Auxiliary
Ground(c)
MOSFET
Ground(b)
FF
Figure 18. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
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17
RT7300
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
8-Lead SOP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS7300-02 March 2014