® RT8012A Dual 1A/1.5A-1.2MHz Synchronous Step-Down Converters General Description Features The RT8012A is a dual PWM, current mode, stepdown converter. Its input voltage range is from 2.6V to 5.5V and has a constant 1.2MHz switching frequency, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. Each output voltage is adjustable from 0.8V to 5V. Internal power switches with low on-resistance of the dual step-down regulators increase efficiency and eliminate the need for external Schottky diodes. The RT8012A can run at 100% duty cycle for low dropout operation that extends battery life in portable systems. With independent Enable and Power Good pins, it is easy to control the power up sequence of the two converters, which is important in some applications. z High Efficiency : Up to 95% z 1.2MHZ Constant Switching Frequency 1A and 1.5A Load Current on Each Channel Respectively Low RDS(ON) Internal Switches No Schottky Diode Required 0.8V Reference Allows Low Output Voltage Low Dropout Operation : 100% Duty Cycle Internally Compensated < 2μ μA Shutdown Current Power Good Output Voltage Monitor Internal Soft-Start Easy Power Sequence Control Over temperature Protection Short Circuit Protection Thermally Enhanced 16-Lead WQFN Package RoHS Compliant and 100% Lead (Pb)-Free z z z z z z z z z z z Ordering Information z RT8012A z z Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. z Suitable for use in SnPb or Pb-free soldering processes. z z z Portable Instruments Microprocessors and DSP Core Supplies Cellular Phones Wireless and DSL Modems PC Cards Digital Cameras Pin Configurations (TOP VIEW) Marking Information YMDNN : Date Code 16 15 14 13 1 12 FB1 2 11 EN1 VDD PVDD1 PGND 3 10 17 4 5 6 LX2 PGOOD2 PVDD2 PVDD2 PGND LX2 BH=YM DNN FB2 EN2 BH= : Product Code 7 9 8 LX1 PGND ` z z Note : ` Applications GND PGOOD1 Package Type QW : WQFN-16L 4x4 (W-Type) WQFN-16L 4x4 Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8012A Typical Application Circuit VIN 5V L1 2.2uH 5, 6 R3 100k 16 C3 22uF EN2 VDD RT8012A LX2 C2 10uF PGOOD1 FB2 14 R4 200k R2 100k 13 PGOOD1 Chip Enable EN1 11 LX1 PGND 15 GND Chip Enable 9 PVDD1 1 PGOOD2 PGOOD2 PVDD2 R1 100k VOUT2 1.2V/1.5A 2, 3 10 C1 10uF FB1 7 L2 3.3uH 12 R6 625k 4, 17 (Exposed Pad) VOUT1 3.3V/1.0A C4 10uF R5 200k Figure 1. Dual Output 3.3V and 1.2V Step Down Regulators 1 PGOOD2 C5 0.1uF L1 2.2uH 5, 6 R2 100k C3 22uF 16 EN2 VDD C2 10uF PGOOD1 R3 200k 14 13 Chip Enable EN1 11 LX1 LX2 FB2 9 RT8012A PGND 15 GND PGOOD2 VOUT2 1.2V/1.5A 2, 3 10 C1 10uF PVDD2 R1 100k PVDD1 VIN 5V FB1 4, 17 (Exposed Pad) 7 L2 3.3uH 12 R5 625k R4 200k VOUT1 3.3V/1.0A C4 10uF Figure 2. Dual Output 3.3V and 1.2V Step Down Regulators (Power up sequence is 3.3V first and then 1.2V). Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8012A-06 September 2012 RT8012A Functional Pin Description Pin No. 1 2, 3 Pin Name PGOOD2 PVDD2 4, 8, PGND 17 (Exposed Pad) 5,6 LX2 7 LX1 9 PVDD1 10 VDD 11 EN1 12 FB1 13 PGOOD1 14 GND Pin Function Power Good Indicator of Regulator 2. Open-drain logic output that is opened when the output voltage exceeds 90% of the regulation point. Power Input Supply of Regulator 2. Decouple this pin to PGND with a capacitor. Power Ground. The exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. Internal Power MOSFET Switches Output of Regulator 2. Connect this pin to the inductor. Internal Power MOSFET Switches Output of Regulator 1. Connect this pin to the inductor. Power Input Supply of Regulator 1. Decouple this pin to PGND with a capacitor. Signal Input Supply. Decouple this pin to GND with a capacitor. Normally V DD is equal to PVDD1 and PVDD2. Keep the voltage difference between VDD, PVDD1 and PVDD2 less than 0.5V. Regulator 1 Chip Enable. A logic high level at this pin enables Regulator 1, while a logic low level causes Regulator 1 to shut down. Feedback Pin of Regulator 1. Receives the feedback voltage from a resistive divider connected across the output. Power Good Indicator of Regulator 1. Open-drain logic output that is opened when the output voltage exceeds 90% of the regulation point. Signal Ground. Return the feedback resistive dividers to this ground, which in turn connects to PGND at one point. Regulator 2 Chip Enable. A logical high level at this pin enables regulator 2, while a logic low level causes Regulator 2 to shut down. A 1μA pull up current from VDD 15 EN2 will be injected to EN2 pin when Regulator 1 is ready (VFB1 exceeds 90% of regulation point). Tie this pin to PGOOD1 and add a capacitor between this pin and GND will introduce a delay time before enabling Regulator 2. The delay time can be adjusted by different capacitance. 16 FB2 Feedback Pin of Regulator 2. Receives the feedback voltage from a resistive divider connected across the output. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8012A Function Block Diagram Regulator 1, 2 PVDD1/ PVDD2 ISEN Slope Compensation OSC 0.8V FB1/ FB2 Output Clamp EA OC Limit InternalSoft Start 0.72V PGOOD Driver Control Logic PGND 0.4V OTP UVP VDD EN & SHDN Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 VREF PGOOD1/ PGOOD2 POR GND EN1/ EN2 LX1/ LX2 EN1 EN2 Shutdown is a registered trademark of Richtek Technology Corporation. DS8012A-06 September 2012 RT8012A Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Input Voltage, VDD, PVDD1, PVDD2 --------------------------------------------------------------- −0.3V to 6V LX1, LX2 Pin Voltage --------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V) < 20ns ---------------------------------------------------------------------------------------------------------------- −5V to 8V Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V) Power Dissipation, PD @ TA = 25°C WQFN-16L 4x4 ---------------------------------------------------------------------------------------------------- 1.852W Package Thermal Resistance (Note 2) WQFN-16L 4x4, θJA ----------------------------------------------------------------------------------------------- 54°C/W WQFN-16L 4x4, θJC ---------------------------------------------------------------------------------------------- 7°C/W Junction Temperature --------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV Recommended Operating Conditions z z z (Note 4) Supply Input Voltage, VDD, PVDD1, PVDD2 --------------------------------------------------------------- 2.6V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (PVDD1 = PVDD2 = VDD = 3.6V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage VREF 0.784 0.8 0.816 V 500 830 1100 μA -- -- 2 μA 2.3 2.43 2.55 V -- 150 -- mV 0.68 0.72 0.76 V -- -- 100 Ω 1 1.2 1.4 MHz EN1 Input High 1.4 -- -- V EN1 Input Low -- -- 0.4 V 0.85 1 1.15 V EN2 Hysteresis -- 200 -- mV C5 = 0.1μF 70 100 130 ms -- 1 -- μA DC Bias Current (PVDD1, PVDD2, VDD total) Under Voltage Lockout Threshold Active, not Switching, VFB1, VFB1 = 0.75V EN1, EN2 = 0 VDD Rising VDD Hysteresis FB Threshold for PGOOD Transition PGOOD Pull-Down Resistance Switching Frequency Switching Frequency EN2 Rising EN2 Threshold EN2 Delay EN2 Pull-up current (Note 5) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8012A Parameter Symbol Test Conditions Min Typ Max Unit Regulator 1 Switch On Resistance, High R FET_H ISW = 0.2A -- 300 450 mΩ Switch On Resistance, Low R FET_L ISW = 0.2A -- 260 390 mΩ Peak Current Limit I LIM 1.2 1.6 2.2 A -- -- 1 %V -- -- 1 % Output Voltage Line Regulation VIN = 2.6V to 5.5V Measured by sever loop, EA Output Voltage Load Regulation output from 0.773V to 1.376V Regulator 2 Switch On Resistance, High R FET_H ISW = 0.5A -- 180 300 mΩ Switch On Resistance, Low R FET_L ISW = 0.5A -- 90 150 mΩ Peak Current Limit I LIM 1.7 2.2 3 A -- -- 1 %V -- -- 1 % Output Voltage Line Regulation Output Voltage Load Regulation VIN = 2.6V to 5.5V Measured by sever loop, EA output from 0.336V to 0.948V Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. EN2 pull-up current only is activated when Regulator-1 is ready (VFB1 > 0.72V). No pull-up current (<0.1μA) appear when VFB1 < 0.72V. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS8012A-06 September 2012 RT8012A Typical Operating Characteristics Regulator 2 Efficiency vs. Output Current 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Regulator 1 Efficiency vs. Output Current 100 60 50 40 30 20 60 50 40 30 20 VIN = 5V, VOUT = 3.3V L = 3.3uH, COUT = 10uF 10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VIN = 5V, VOUT = 1.2V L = 2.2uH, COUT = 10uF 10 0 0.00 Output Current (A) 0.25 0.50 0.75 1.00 1.25 1.50 Output Current (A) Regulator 1 Load Transient Response Regulator 2 Load Transient Response VIN = 5V, VOUT = 3.3V, IOUT = 0A to 1A L = 3.3uH, COUT = 10uF VIN = 5V, VOUT = 1.2V, IOUT = 0A to 1.5A L = 2.2uH, COUT = 10uF VOUT (50mV/Div) VOUT (50mV/Div) IOUT (500mA/Div) IOUT (500mA/Div) Time (100μs/Div) Time (100μs/Div) Regulator 1 Load Transient Response Regulator 2 Load Transient Response VOUT (50mV/Div) VOUT (50mV/Div) IOUT (500mA/Div) IOUT (500mA/Div) VIN = 5V, VOUT = 3.3V, IOUT = 200mA to 600mA L = 3.3uH, COUT = 10uF Time (100μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 VIN = 5V, VOUT = 1.2V, IOUT = 200mA to 800mA L = 2.2uH, COUT = 10uF Time (100μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8012A Regulator 1 Ripple Regulator 2 Ripple VIN = 5V, VOUT = 3.3V, IOUT = 1A L = 3.3uH, COUT = 10uF VIN = 5V, VOUT = 1.2V, IOUT = 1.5A L = 2.2uH, COUT = 10uF VOUT (10mV/Div) VOUT (10mV/Div) VLX (5V/Div) VLX (5V/Div) Time (1μs/Div) Time (1μs/Div) Regulator 1 Power On from EN Regulator 2 Power On from EN VEN (2V/Div) VEN (2V/Div) VOUT (2V/Div) VOUT (2V/Div) I IN (500mA/Div) I IN (500mA/Div) VIN = 5V, VOUT = 3.3V, IOUT = 1A VIN = 5V, VOUT = 1.2V, IOUT = 1.5A Time (1ms/Div) Time (1ms/Div) Regulator 1 Power On from VIN Regulator 2 Power On from VIN VIN (2V/Div) VIN (2V/Div) VOUT (2V/Div) VOUT (2V/Div) IOUT (500mA/Div) IOUT (500mA/Div) VIN = 5V, VOUT = 3.3V, IOUT = 1A Time (1ms/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 VIN = 5V, VOUT = 1.2V, IOUT = 1.5A Time (1ms/Div) is a registered trademark of Richtek Technology Corporation. DS8012A-06 September 2012 RT8012A Regulator 1 Power Good Delay Regulator 2 Power Good Delay VIN (2V/Div) VOUT (2V/Div) VIN (2V/Div) PGOOD (5V/Div) PGOOD (5V/Div) VOUT (2V/Div) IOUT (1A/Div) VIN = 5V, VOUT = 3.3V, IOUT = 1A IOUT (1A/Div) VIN = 5V, VOUT = 1.2V, IOUT = 1.5A Time (1ms/Div) Time (1ms/Div) Regulator 2 Load Regulation 1.230 3.339 1.228 3.338 1.226 Output Voltage (V) Output Voltage (V) Regulator 1 Load Regulation 3.340 3.337 3.336 3.335 3.334 3.333 3.332 3.331 1.224 1.222 1.220 1.218 1.216 1.214 1.212 VIN = 5V, VOUT = 3.3V 3.330 VIN = 5V, VOUT = 1.2V 1.210 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.00 0.25 0.50 Output Current (A) Regulator 1 Output Voltage vs. Temperature 1.00 1.25 1.50 Regulator 2 Output Voltage vs. Temperature 3.36 1.24 3.35 1.23 3.34 Output Voltage (V) Output Voltage (V) 0.75 Output Current (A) 3.33 3.32 3.31 3.3 1.22 1.21 1.20 1.19 3.29 VIN = 5V, VOUT = 3.3V, IOUT = 0A 3.28 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 125 VIN = 5V, VOUT = 1.2V, IOUT = 0A 1.18 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8012A Switching Frequency vs. Temperature 1400 1350 1350 1300 1300 Frequency (kHz) Frequency (kHz) Switching Frequency vs. Input Voltage 1400 1250 1200 1150 1100 1050 1000 1250 1200 1150 1100 1050 VOUT = 1.2V, IOUT = 300mA 2.5 3 3.5 1000 4 4.5 5 5.5 VIN = 5V, VOUT = 1.2V, IOUT = 300mA -50 -25 0 3.0 2.2 2.9 2.1 2.0 1.9 1.8 1.7 1.6 1.5 VOUT = 3.3V 4 125 2.7 2.6 2.5 2.4 2.3 2.2 2.1 VOUT = 1.2V 2.0 4.3 4.6 4.9 5.2 5.5 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Regulator 1 Current Limit vs. Temperature Regulator 2 Current Limit vs. Temperature 2.5 1.8 2.4 1.7 2.3 1.6 Output Current (A) Output Current (A) 100 2.8 Input Voltage (V) 1.5 1.4 1.3 1.2 2.2 2.1 2.0 1.9 1.8 1.7 1.1 1.0 75 Regulator 2 Inductor Peak Current vs. Input Voltage 2.3 Inductor Peak Current (A) Inductor Peak Current (A) Regulator 1 Inductor Peak Current vs. Input Voltage 1.3 50 Temperature (°C) Input Voltage (V) 1.4 25 1.6 VIN = 5V, VOUT = 3.3V -50 -25 0 25 1.5 50 75 100 Temperature (°C) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 125 VIN = 5V, VOUT = 1.2V -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS8012A-06 September 2012 RT8012A Applications Information The basic RT8012A application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Inductor Selection Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy. However, they are usually more expensive than the similar powered iron inductors. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. ⎡V ⎤ ⎡ V ⎤ ΔIL = ⎢ OUT ⎥ × ⎢1 − OUT ⎥ f L × V IN ⎦ ⎣ ⎦ ⎣ Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔIL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : VOUT ⎤ ⎡ VOUT ⎤ ⎡ L=⎢ × ⎢1 − ⎥ ⎥ f I V L(MAX) × Δ IN(MAX) ⎦ ⎣ ⎦ ⎣ Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 Different core materials and shapes will change the size/ current and price/current relationship of an inductor. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : IRMS = IOUT(MAX) VOUT VIN VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎡ 1 ⎤ ΔVOUT ≤ ΔIL ⎢ESR + ⎥ 8fC OUT ⎦ ⎣ is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8012A The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : VOUT = VREF (1 + R1) R2 where VREF is the internal reference voltage (0.8V typ.) Selecting Ceramic Input and Output Capacitors The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Output Voltage Programming The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 3. V OUT R1 FB RT8012A R2 GND Figure 3. Setting the Output Voltage Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as : Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : VIN quiescent current and I2R losses. 1. The VIN quiescent current appears due to two factors including the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from VIN to ground. The resulting ΔQ/Δt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, R SW and external inductor RL. In continuous mode, the average output current flowing is a registered trademark of Richtek Technology Corporation. DS8012A-06 September 2012 RT8012A RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. dependent. For WQFN-16L 4x4 package, the thermal resistance θJA is 54°C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = ( 125°C − 25°C) / 54°C/W = 1.852W for WQFN-16L 4x4 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. The Figure 4 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 2.0 Maximum Power Dissipation (W) through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows : Checking Transient Response Four Layers PCB 1.8 1.6 WQFN 16L 4x4 1.4 The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Figure 4. Derating Curve of Maximum Power Dissipation Thermal Considerations Layout Considerations For continuous operation, do not exceed the maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature differential between junction to ambient. The maximum power dissipation can be calculated by following formula : Follow the PCB layout guidelines for optimal performance of RT8012A. PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8012A-06 September 2012 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Temperature (°C) ` Keep the traces of the main current paths as short and wide as possible. ` Put the input capacitor as close as possible to the device pins (VIN and GND). ` LX node is with high frequency voltage swing and should be kept small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up. ` Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT8012A. ` Connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8012A Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.380 0.010 0.015 D 3.950 4.050 0.156 0.159 D2 2.000 2.450 0.079 0.096 E 3.950 4.050 0.156 0.159 E2 2.000 2.450 0.079 0.096 e L 0.650 0.500 0.026 0.600 0.020 0.024 W-Type 16L QFN 4x4 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 14 DS8012A-06 September 2012