Application Note 87
November 2000
Linear Technology Magazine Circuit Collection, Volume V
Data Conversion, Interface and Signal Conditioning Products
Richard Markell, Editor
INTRODUCTION
Application Note 87 is the fifth in a series that excerpts
useful circuits from Linear Technology magazine to preserve them for posterity. This application note highlights
data conversion, interface and signal conditioning circuits
from issue VI:1 (February 1996) through issue VIII:4
(November 1998). Like its predecessor, AN67, this Application Note includes circuits for high speed video, interface and hot swap circuits, active RC and switched capacitor filter circuitry and a variety of data conversion and
instrumentation circuits. There are also several circuits
that cannot be so neatly categorized. So, without further
ado, I’ll let the authors describe their circuits.
Note: Article Titles appear in this application note exactly
as they originally appeared in Linear Technology magazine. This may result in some inconsistency in the usage
of terminology.
TABLE OF CONTENTS
Introduction ......................................................................................................................................................... 1
DATA CONVERTERS
The LTC®1446 and LTC1446L: World’s First Dual 12-Bit DACs in SO-8 Packages ............................................... 3
Multichannel A/D Uses a Single Antialiasing Filter................................................................................................ 4
LTC1454/54L and LTC1458/58L: Dual and Quad 12-Bit, Rail-to-Rail, Micropower DACs .................................... 5
Micropower ADC and DAC in SO-8 Give PC 12-Bit Analog Interface .................................................................... 7
The LTC1594 and LTC1598: Micropower 4- and 8-Channel 12-Bit ADCs ........................................................... 10
MUX the LTC1419 Without Software ................................................................................................................. 13
The LTC1590 Dual 12-Bit DAC is Extremely Versatile......................................................................................... 14
New 16-Bit SO-8 DAC Has 1LSB Max INL and DNL Over Industrial Temperature .............................................. 16
LTC1659, LTC1448: Smallest Rail-to-Rail 12-Bit DACs Have Lowest Power ...................................................... 18
An SMBus-Controlled 10-Bit, Current Output, 50µA Full-Scale DAC .................................................................. 19
INTERFACE CIRCUITS
Simple Resistive Surge Protection for Interface Circuits .................................................................................... 20
The LTC1343 and LTC1344 Form a Software-Selectable Multiple-Protocol Interface Port
Using a DB-25 Connector ................................................................................................................................... 22
The LT1328: a Low Cost IrDA Receiver Solution for Data Rates up to 4Mbps ................................................... 34
LTC1387 Single 5V RS232/RS485 Multiprotocol Transceiver ............................................................................ 36
A 10MB/s Multiple-Protocol Chip Set Supports Net1 and Net2 Standards ......................................................... 37
Net1 and Net2 Serial Interface Chip Set Supports Test Mode............................................................................. 44
OPERATIONAL AMPLIFIERS/VIDEO AMPLIFIERS
LT1490/LT1491 Over-the-Top™ Dual and Quad Micropower Rail-to-Rail Op Amps........................................... 46
The LT1210: A 1-Ampere, 35MHz Current Feedback Amplifier........................................................................... 47
The LT1207: An Elegant Dual 60MHz, 250mA Current Feedback Amplifier ........................................................ 50
AN87-1
Application Note 87
Micropower, Dual and Quad JFET Op Amps Feature C-Load™ Capability
and PicoAmpere Input Bias Currents.................................................................................................................. 54
The LT1210: High Power Op Amp Yields Higher Voltage and Current ................................................................ 56
New Rail-to-Rail Amplifiers: Precision Performance from Micropower to High Speed ....................................... 59
LT1256 Voltage-Controlled Amplitude Limiter ................................................................................................... 61
The LT1495/LT1496: 1.5µA Rail-to-Rail Op Amps ............................................................................................. 62
Send Camera Power and Video on the Same Coax Cable ................................................................................... 64
200µA, 1.2MHz Rail-to-Rail Op Amps Have Over-The-Top Inputs ...................................................................... 65
Low Distortion Rail-to-Rail Op Amps Have 0.003% THD with 100kHz Signal .................................................... 66
The LT1167: Precision, Low Cost, Low Power Instrumentation Amplifier Requires
a Single Gain-Set Resistor .................................................................................................................................. 67
Level Shift Allows CFA Video Amplifier to Swing to Ground on a Single Supply ................................................ 70
LT1468: An Operational Amplifier for Fast, 16-Bit Systems ............................................................................... 71
TELECOMMUNICATIONS CIRCUITS
How to Ring a Phone with a Quad Op Amp ........................................................................................................ 73
A Low Distortion, Low Power, Single-Pair HDSL Driver Using the LT1497 ........................................................ 79
COMPARATORS
Ultralow Power Comparators Include Reference ................................................................................................ 80
A 4.5ns, 4mA, Single-Supply, Dual Comparator Optimized for 3V/5V Operation ................................................ 82
INSTRUMENTATION CIRCUITS
LTC1441-Based Micropower Voltage-to-Frequency Converter ........................................................................... 86
Bridge Measures Small Capacitance in Presence of Large Strays ...................................................................... 87
Water Tank Pressure Sensing, a Fluid Solution .................................................................................................. 89
0.05µV/°C Chopped Amplifier Requires Only 5µA Supply Current ..................................................................... 92
4.5ns Dual-Comparator-Based Crystal Oscillator has 50% Duty Cycle and Complementary Outputs ................. 93
LTC1531 Isolated Comparator............................................................................................................................ 94
FILTERS
The LTC1560-1: A 1MHz/500kHz Continuous-Time, Low Noise, Elliptic Lowpass Filter .................................... 96
The LTC1067 and LTC1067-50: Universal 4th Order Low Noise, Rail-to-Rail Switched Capacitor Filters ........... 98
Universal Continuous-Time Filter Challenges Discrete Designs ........................................................................ 102
High Clock-to-Center Frequency Ratio LTC1068-200 Extends Capabilities of Switched Capacitor
Highpass Filter ................................................................................................................................................. 104
Clock-Tunable, High Accuracy, Quad 2nd Order, Analog Filter Building Blocks................................................ 106
MISCELLEANEOUS
Biased Detector Yields High Sensitivity with Ultralow Power Consumption ..................................................... 110
Zero-Bias Detector Yields High Sensitivity with Nanopower Consumption....................................................... 111
Transparent Class-D Amplifiers Featuring the LT1336 ..................................................................................... 112
Single-Supply Random Code Generator ........................................................................................................... 118
APPENDIX A: COMPONENT VENDOR CONTACTS ......................................................................... 120
INDEX ............................................................................................................................ 123
, LTC, and LT are registered trademarks of Linear Technology Corporation; Adaptive Power, Burst Mode, C-Load, FilterCAD, No RSENSE, Operational Filter, Over-The-Top, PolyPhase, PowerPath
and UltraFast are trademarks of Linear Technology Corporation. Gelcell is a trademark of Johnson Controls, Inc.; Kool Mµ is a registered trademark of Magnetics, Inc.; Pentium is a registered
trademark of Intel Corp.; VERSA-PAC is a trademark of Coiltronics, Inc.
AN87-2
Application Note 87
Data Converters
THE LTC1446 AND LTC1446L: WORLD’S FIRST
DUAL 12-BIT DACS IN SO-8 PACKAGES
by Hassan Malik and Jim Brubaker
LTC1446L has an output swing of 0V to 2.5V. It can
operate on a single supply with a wide range of 2.7V to
5.5V. It dissipates 1.35mW (ICC typical = 450µA) at a 3V
supply.
Dual 12-Bit Rail-to-Rail Performance in a Tiny SO-8
An Autoranging 8-Channel ADC with Shutdown
The LTC1446 and LTC1446L are dual 12-bit, single-supply, rail-to-rail voltage output digital-to-analog converters. Both of these parts include an internal reference and
two DACs with rail-to-rail output buffer amplifiers, packed
in a small, space-saving 8-pin SO or PDIP package. A
power-on reset initializes the outputs to zero-scale at
power-up.
Figure 1 shows how to use an LTC1446 to make an
autoranging ADC. The microprocessor sets the reference
span and the common pin for the analog input by loading
the appropriate digital code into the LTC1446. VOUTA
controls the common pin for the analog inputs to the
LTC1296 and VOUTB controls the reference span by setting
the REF+ pin on the LTC1296. The LTC1296 has a shutdown pin that goes low in shutdown mode. This will turn
off the PNP transistor supplying power to the LTC1446.
The resistor and capacitor on the LTC1446 outputs act as
a lowpass filter for noise.
The LTC1446 has an output swing of 0V to 4.095V, making
each LSB equal to 1mV. It operates from a single 4.5V to
5.5V supply, dissipating 3.5mW (ICC typical = 700µA). The
22µF
+
5V
VCC
CH0
CS
DOUT
µP
CLK
8 ANALOG
INPUT CHANNELS
LTC1296
DIN
CH7
COM
SSO
REF +
REF –
74HC04
47k
47k
5V
0.1µF
2N3906
CLK
VOUTB
DIN
VCC
100Ω
0.1µF
CS/LD
LTC1446
GND
100Ω
DOUT
VOUTA
0.1µF
Figure 1. An Autoranging 8-Channel ADC with Shutdown
AN87-3
Application Note 87
A Wide-Swing, Bipolar-Output DAC with
Digitally Controlled Offset
Figure 2 shows how to use an LTC1446 and an LT1077 to
make a wide bipolar-output-swing 12-bit DAC with an
offset that can be digitally programmed. VOUTA, which can
be set by loading the appropriate digital code for DAC A,
sets the offset. As this value changes, the transfer curve
for the output moves up and down, as shown in the figure.
5V
8.192
0.1µF
VOUTB
CLK
VOUTA = 0V
(ZERO SCALE)
VOUT
15V
4.096
4.99k
1%
DIN
VCC
µP
CS/LD
DOUT
VOUTA = 2.048V
(MID SCALE)
+
LTC1446
10k
1%
GND
VOUTA
LT1077
VOUT = 2 { VOUTB–VOUTA }
0
–
DIN
VOUTA = 4.096V
(FULL SCALE)
–4.096
–15V
49.9k
1%
TO DIN OF NEXT DAC
100k
1%
–8.192
Figure 2. A Wide-Swing, Bipolar Output DAC with Digitally Controlled Offset
MULTICHANNEL A/D USES
A SINGLE ANTIALIASING FILTER
by LTC Applications Staff
The circuit in Figure 3 demonstrates how the LTC1594’s
independent analog multiplexer can simplify the design of
a 12-bit data acquisition system. All four channels are
MUXed into a single 1kHz, fourth-order Sallen-Key antialiasing filter, which is designed for single-supply operation. Since the LTC1594’s data converter accepts inputs
from ground to the positive supply, rail-to-rail op amps
were chosen for the filter to maximize dynamic range. The
LT1368 dual rail-to-rail op amp is compensated for the
0.1µF load capacitors (C1 and C2) that help reduce the
amplifier’s output impedance and improve supply rejection at high frequencies. The filter contributes less than
1LSB of error due to offsets and bias currents. The filter’s
noise and distortion are less than −72dB for a 100Hz,
2VP-P offset sine input.
AN87-4
The combined MUX and A/D errors result in an integral
nonlinearity error of ±3LSB (maximum) and a differential
nonlinearity error of ±0.75LSB (maximum). The typical
signal-to-noise plus distortion ratio is 68dB, with approximately −78dB of total harmonic distortion. The LTC1594
is programmed through a 4-wire serial interface that
allows efficient data transfer to a wide variety of microprocessors and microcontrollers. Maximum serial clock
speed is 200kHz, which corresponds to a 10.5kHz sampling rate.
The complete circuit consumes approximately 800µA
from a single 5V supply. For ratiometric measurements,
the A/D’s reference can also be taken from the 5V supply.
Otherwise, an external reference should be used.
Application Note 87
5V
0.015µF
0.1µF
+
7.5k
1/2
LT1368
5V
7.5k
0.03µF
–
C2
0.1µF
1µF
CH0
VCC
CH1
MUX OUT
7.5k
ANALOG
INPUTS
+
7.5k
CH2
LTC1594
CH3
0.1µF
DIN
CS
1/2
LT1368
0.015µF
C1
0.1µF
–
0.03µF
SHA IN
CLK
VREF
VCC
DATA IN
COM
DOUT
CLOCK
GND
CS
DATA OUT
CHIP SELECT
Figure 3. Simple Data Acquisition System Takes Advantage of the LTC1594’s
MUX OUT/SHA IN Loop to Filter Analog Signals Prior to A/D Conversion
LTC1454/54L AND LTC1458/58L: DUAL AND QUAD
12-BIT, RAIL-TO-RAIL, MICROPOWER DACS
by Hassan Malik and Jim Brubaker
Dual and Quad Rail-to-Rail DACs Offer
Flexibility and Performance
The LTC1454 and LTC1454L are dual 12-bit, single supply, rail-to-rail voltage-output digital-to-analog converters. The LTC1458 and LTC1458L are quad versions of this
family. These DACs have an easy-to-use, SPI-compatible
interface. A CLR pin and power-on-reset both reset the
DAC outputs to zero scale. DNL is guaranteed to be less
than 0.5LSB. Each DAC has its own rail-to-rail voltage
output buffer amplifier. The onboard reference is brought
out to a separate pin and can be connected to the REFHI
pins of the DACs. There is also a REFLO pin that can be
used to offset the DAC range. For further flexibility the
×1/×2 pin for each DAC allows the user to select a gain of
either 1 or 2. The LTC1454/54L are available in 16-pin
PDIP and SO packages, and the LTC1458/58L are available
in 28-pin SO or SSOP packages.
5V and 3V Single Supply and Micropower
The LTC1454 and LTC1458 operate from a single 4.5V to
5.5V supply. The LTC1454 dissipates 3.5mW (ICC typical
= 700µA), whereas the LTC1458 dissipates 6.5mW (ICC
typical = 1.3mA). There is an onboard reference of 2.048V
and a nominal full scale of 4.095V when using the onboard
reference and a gain-of-2 configuration.
The LTC1454L and LTC1458L operate on a single supply
with a wide range of 2.7V to 5.5V. The LTC1454L dissipates 1.35mW (ICC typical = 450µA), whereas the LTC1458L
dissipates 2.4mW (ICC typical = 800µA) from a 3V supply.
There is a 1.22V onboard reference and a convenient full
scale of 2.5V when using the onboard reference and a
gain-of-2 configuration.
Flexibility Allows a Host of Applications
These products can be used in a wide range of applications, including digital calibration, industrial process control, automatic test equipment, cellular telephones and
portable, battery-powered systems.
AN87-5
Application Note 87
A 12-Bit DAC with Digitally Programmable
Full Scale and Offset
The transfer characteristic is:
Figure 4 shows how to use one LTC1458 to make a 12-bit
DAC with a digitally programmable full scale and offset.
DAC A and DAC B are used to control the offset and full
scale of DAC C. DAC A is connected in a ×1 configuration
and controls the offset of DAC C by moving REFLOC above
ground. The minimum value to which this offset can be
programmed is 10mV. DAC B is connected in a ×2
configuration and controls the full scale of DAC-C by
driving REFHIC . Note that the voltage at REFHIC must be
less than or equal to VCC/2, corresponding to DAC B’s
code ≤ 2,500 for VCC = 5V, since DAC-C is being operated
in ×2 mode for full rail-to-rail output swing.
VOUTC = 2 × [DC × (2 × DB – DA) + DA] × REFOUT
where REFOUT = The reference output
DA = (DAC A digital code)/4096 this sets the offset
DB = (DAC B digital code)/4096 this sets the full scale
DC = (DAC C digital code)/4096
A Single-Supply, 4-Quadrant Multiplying DAC
The LTC1454L can also be used for four-quadrant multiplying with an offset signal ground of 1.22V. This application is shown in Figure 5. The inputs are connected to
REFHIB or REFHIA and have a 1.22V amplitude around a
signal ground of 1.22V. The outputs will swing from 0V to
2.44V, as shown by the equation with the figure.
5V
0.1µF
LTC1458L/LTC1458
VOUT
X1/X2C
VCC
5V
VOUTC
X1/X2B
0.1µF
CS/LD
VOUTB
DIN
REFHIC
GND
500Ω
CLR
REFHIB
X1/X2 B
CLR
VCC
CLK
CLK
REFHI B
DIN
DIN
GND
CS/LD
REFLOB
REFLOD
REFLOA
DOUT
REFHI D
REFHIA
X1/X2 A
REF
VOUT A
VCC
CLK
VIN A: 1.22V ± 1.22V
REFHI A
1.22V
REFOUT
N/C
N/C
VOUTA
VOUTD
X1/X2A
X1/X2D
VCC
VOUT A
VO =
A/B
=
Figure 4. A 12-Bit DAC with Digitally Controlled
Zero Scale and Full Scale
AN87-6
VIN B: 1.22V ± 1.22V
GND
LTC1454L
REFLO
CS/LD
REFLOC
DOUT
VOUT B
VOUT B
(VIN – VREF)
(
VIN – 1.22
)(
GAIN
5k
(
)
DIN – 1 +1 + V
REF
4096
)
1454_4.eps
D
2.05 IN –1.05 + 1.22V
4096
Figure 5. Single-Supply, 4-Quadrant Multiplying DAC
Application Note 87
MICROPOWER ADC AND DAC IN SO-8
GIVE PC 12-BIT ANALOG INTERFACE
by LTC Applications Staff
to transfer data to the DAC and ADC, CTS is used to receive
conversion results from the LTC1298 and the signal on TX
selects either the LTC1446 or the LTC1298 to receive input
data. The LTC1298’s and LTC1446’s low power dissipation allows the circuit to be powered from the serial port.
The TX and RTS lines charge capacitor C4 through diodes
D3 and D4. An LT1021-5 regulates the voltage to 5V.
Returning the TX and RTS lines to a logic high after
sending data to the DAC or completion of an ADC conversion provides constant power to the LT1021-5.
Needing to add two channels of simple, inexpensive, low
powered, compact analog input/output to a PC computer,
The LTC1298 ADC and LTC1446 DAC were chosen. The
LTC1298 and the LTC1446 are the first SO-8 packaged 2channel devices of their kind. The LTC1298 draws just
340µA. A built-in auto shutdown feature further reduces
power dissipation at reduced sampling rates (to 30µA at
1ksps). Operating on a 5V supply, the LTC1446 draws just
1mA (typ). Although the application shown is for PC data
acquisition, these two converters provide the smallest,
lowest power solutions for many other analog I/O applications.
Using a 486-33 PC, the throughput was 3.3ksps for the
LTC1298 and 2.2ksps for the LTC1446. Your mileage may
vary.
Listing 1 is C code that prompts the user to either read a
conversion result from the ADC’s CH0 or write a data word
to both DAC channels.
The circuit shown in Figure 6 connects to a PC’s serial
interface using four interface lines: DTR, RTS, CTS and TX.
DTR is used to transmit the serial clock signal, RTS is used
5V
LT1021-5
6
510Ω
510Ω 2
3
INPUT 2
510Ω
510Ω 4
CS
VCC
CH0
CLK
CH1
DOUT
GND
DIN
8
7
2
0.1µF
6
4
3
D
Q
PR
CLR
CK
Q
47µF
5
1
+
1
C4
150µF
+
INPUT 1
1/2 74HC74
LTC1298
4 x 1N914
2
4
6
5
D3
1N914
1
2
3
4
CLK
VOUTB
DIN
VCC
CS/LD
DOUT
GND
VOUTA
2
8
4
7
6
0.1µF
5
3
D
Q
PR
CLR
CK
Q
7
3 2
4
1/2 74HC74
LTC1446
5
1
8
9
6
5
12
6
11
14
AOUT1
1
13
51k
SELECT
51k
DIN
51k
SCLK
10
0.1µF
AOUT2
DOUT
D4
1N914
TX
RTS
DTR
CTS
DI1466_01.eps
5V
Figure 6. Communicating Over the Serial Port, the LTC1298 and LTC1446 in SO-8
Create a Simple, Low Power, 2-Channel Analog Interface for PCs
Listing 1. C Code to Configure the Analog Interface
#define
#define
#define
#define
#define
#define
#define
port 0x3FC
inprt 0x3FE
LCR 0x3FB
high 1
low 0
Clock 0x01
Din 0x02
/* Control register, RS232 */
/* Status reg. RS232 */
/* Line Control Register */
/* pin 4, DTR */
/* pin 7, RTS */
AN87-7
Application Note 87
#define Dout 0x10
/* pin 8, CTS input */
#include<stdio.h>
#include<dos.h>
#include<conio.h>
/* Function module sets bit to high or low */
void set_control(int Port,char bitnum,int flag)
{
char temp;
temp = inportb(Port);
if (flag==high)
temp |= bitnum;
/* set output bit to high */
else
temp &= ~bitnum;
/* set output bit to low */
outportb(Port,temp);
}
/* This function brings CS high or low (consult the schematic) */
void CS_Control(direction)
{
if (direction)
{
set_control(port,Clock,low);
/* set clock high for Din to be read */
set_control(port,Din,low);
/* set Din low */
set_control(port,Din,low);
/* set Din high to make CS goes high */
}
else {
outportb(port, 0x01);
/* set Din & clock low */
Delay(10);
outportb(port, 0x03);
/* Din goes high to make CS go low */
}
}
/* This function outputs a 24-bit (2x12) digital code to LTC1446L */
void Din_(long code,int clock)
{
int x;
for(x = 0; x<clock; ++x)
{
code <<= 1;
/* align the Din bit */
if (code & 0x1000000)
{
set_control(port,Clock,high);
/* set Clock low */
set_control(port,Din,high);
/* set Din bit high */
}
else {
set_control(port,Clock,high);
/* set Clock low */
set_control(port,Din,low);
/* set Din low */
}
set_control(port,Clock,low);
/* set Clock high for DAC to latch */
}
AN87-8
Application Note 87
}
/* Read bit from ADC to PC */
Dout_()
{
int temp, x, volt =0;
for(x = 0; x<13; ++x)
{
set_control(port,Clock,high);
set_control(port,Clock,low);
temp = inportb(inprt);
/* read status reg. */
volt <<= 1;
/* shift left one bit for serial transmission
*/
if(temp & Dout)
volt += 1;
/* add 1 if input bit is high */
}
return(volt & 0xfff);
}
/* menu for the mode selection */
char menu()
{
printf(“Please select one of the following:\na: ADC\nd: DAC\nq: quit\n\n”);
return (getchar());
}
void main()
{
long code;
char mode_select;
int temp,volt=0;
/* Chip select for DAC & ADC is controlled by RS232 pin 3 TX line. When LCR’s bit 6 is set,
the DAC is selected and the reverse is true for the ADC. */
outportb(LCR,0x0);
/* initialize DAC */
outportb(LCR,0x64);
/* initialize ADC */
while((mode_select = menu()) != ‘q’)
{
switch(mode_select)
{
case ‘a’:
{
outportb(LCR,0x0);
/* selecting ADC */
CS_Control(low);
/* enabling the ADC CS */
Din_(0x680000, 0x5);
/* channel selection */
volt = Dout_();
outportb(LCR,0x64);
/* bring CS high */
set_control(port,Din,high);
/* bring Din signal high */
printf(“\ncode: %d\n”,volt);
}
break;
case ‘d’:
AN87-9
Application Note 87
{
printf(“Enter DAC input code (0 – 4095):\n”);
scanf(“%d”, &temp);
code = temp;
code += (long)temp << 12; /* converting 12-bit to 24-bit word */
outportb(LCR,0x64);
/* selecting DAC */
CS_Control(low);
/* CS enable */
Din_(code,24);
/* loading digital data to DAC */
outportb(LCR,0x0);
/* bring CS high */
outportb(LCR,0x64);
/* disabling ADC */
set_control(port,Din,high);
/* bring Din signal high */
}
break;
}
}
}
THE LTC1594 AND LTC1598: MICROPOWER
4- AND 8-CHANNEL 12-BIT ADCS
by Marco Pan
includes a simple, efficient serial interface that reduces
interconnects and, thereby, possible sources of corrupting digital noise. Reduced interconnections also reduce
board size and allow the use of processors having fewer
I/O pins, both of which help reduce system costs.
Micropower ADCs in Small Packages
The LTC1594 and LTC1598 are micropower 12-bit ADCs
that feature a 4- and 8-channel multiplexer, respectively.
The LTC1594 is available in a 16-pin SO package and the
LTC1598 is available in a 24-pin SSOP package. Each ADC
ANALOG INPUTS
0V TO 5V
RANGE
The LTC1594 and LTC1598 include an auto shutdown
feature that reduces power dissipation when the converter
is inactive (whenever the CS signal is a logic high).
5V
1
2
3
4
5
6
7
8
9
10
11
12
CH5
CH4
CH6
CH3
CH7
CH2
GND
CH1
CLK LTC1598 CH0
CS MUX
DIN
VCC
MUXOUT
COM
ADCIN
GND
VREF
CS ADC
DOUT
NC
VCC
CLK
NC
C6
0.015µF
24
1µF
23
+
22
21
20
R4, 7.5k
1/2
LT1368
C2
0.1µF
5V
R2, 7.5k
C4
0.03µF
–
19
18
1µF
17
R1, 7.5k
16
15
14
C3
0.03µF
13
R3, 7.5k
C5
0.015µF
+
1/2
LT1368
–
C1
0.1µF
DATA OUT
DATA IN
CHIP SELECT
CLOCK
Figure 7. Simple Data Acquisition System Takes Advantage of the LTC1598’s
MUX OUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion
AN87-10
1598_02.eps
Application Note 87
5V
1µF
1
2
3
4
5
6
7
8
CH0
CH1
CH2
V+
5V
+
LTC1391
+
16
1µF
15
D
14
V–
13
+
12
–
CH3
DOUT
CH4
DIN
CH5
CS
CH6
CLK
CH7
GND
1/2 LT1368
5V
0.1µF
17
ADCIN
11
10
9
64R
20 CH0
32R
21 CH1
16R
22 CH2
8R
23 CH3
4R
24 CH4
2R
1 CH5
R
2 CH6
R
3 CH7
16
15, 19
VREF VCC
CS ADC
CS MUX
8-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
–
CLK
DOUT
DIN
LTC1598
18
8
MUXOUT
COM
NC
GND
NC
+
1µF
10
6
5, 14
µP/µC
11
7
12
13
4, 9
1598_03.eps
Figure 8. Using the MUXOUT/ADCIN Loop of the LTC1598 to Form a PGA with Eight Gains in a Noninverting Configuration
MUXOUT/ADCIN Loop
Economizes Signal Conditioning
The MUXOUT and ADCIN pins form a very flexible external
loop that allows PGA and/or processing analog input
signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
Figure 7 shows the loop being used to antialias filter
several analog inputs. The output signal of the selected
MUX channel, present on the MUXOUT pin, is applied to
R1 of the Sallen-Key filter. The filter bandlimits the analog
Table 1. PGA Gain for Each MUX Channel of Figures 8 and 9
Mux Channel
Noninverting Gain
Inverting Gain
0
1
–1
1
2
–2
2
4
–4
3
8
–8
4
16
–16
5
32
–32
6
64
–64
7
128
–128
signal and its output is applied to ADCIN. The LT1368 railto-rail op amps used in the filter will, when lightly loaded
as in this application, swing to within 8mV of the positive
supply voltage. Since only one circuit is used for all
channels, each channel sees the same filter characteristics.
Using MUXOUT/ADCIN Loop as PGA
Combined with the LTC1391 (as shown in Figure 8) the
LTC1598’s MUXOUT/ADCIN loop and an LT1368 can be
used to create an 8-channel PGA with eight noninverting
gains for each channel. The output of the LT1368 drives
the ADCIN and the resistor ladder. The resistors above the
selected MUX channel form the feedback for the LT1368.
The loop gain for this amplifier is (RS1/RS2) + 1. RS1 is the
summation of the resistors above the selected MUX channel and RS2 is the summation of the resistors below the
selected MUX channel. If CH0 is selected, the loop gain is
1 since RS1 is 0. Table 1 shows the gain for each MUX
channel. The LT1368 dual rail-to-rail op amp is designed
to operate with 0.1µF load capacitors. These capacitors
provide frequency compensation for the amplifiers, help
reduce the amplifiers’ output impedance and improve
AN87-11
Application Note 87
5V
supply rejection at high frequencies. Because the LT1368’s
IB is low, the RON of the selected channel will not affect the
loop gain given by the formula above. In the case of the
inverting configuration of Figure 9, the selected channel’s
RON will be added to the resistor that sets the loop gain.
+
1/2 LT1368
LTC1598
18
MUXOUT
The LTC1598 can be combined with the LTC1391 8channel, serial-interface analog multiplexer to create a
differential A/D system. Figure 10 shows the complete 8channel, differential A/D circuit. The system uses the
LTC1598’s MUX as the noninverting input multiplexer
and the LTC1391 as inverting input multiplexer. The
LTC1598’s MUXOUT drives the ADCIN directly. The
inverting multiplexer’s output is applied to the LTC1598’s
COM input. The LTC1598 and LTC1391 share the CS, DIN,
and CLK control signals. This arrangement simultaneously
selects the same channel on each multiplexer and maximizes the system’s throughput. The dotted-line connection daisy-chains the MUXes of the LTC1391 and LTC1598
together. This configuration provides the flexibility to
select any channel in the noninverting input MUX with
respect to any channel in the inverting input MUX. This
allows any combination of signals applied to the inverting
and noninverting MUX inputs to be routed to the ADC for
conversion.
2
3
4
5
6
7
CH7
8
CH0
CH1
CH2
20
CH0
64R
21
CH1
32R
22
CH2
16R
23
CH3
8R
24
CH4
4R
1
CH5
2R
2
CH6
R
3
CH7
8
COM
LTC1598
18
MUXOUT
CH1
CH2
23
CH3
24
CH4
1
CH5
2
CH6
16
3
CH7
15
D
14
–
V
13
8
COM
DOUT
CH4
DIN
CH5
CS
CH6
CLK
CH7
GND
CS ADC
CS MUX
+
12-BIT
SAMPLING
ADC
CLK
DIN
–
DOUT
NC
NC
GND
1µF
10
6
5, 14
7
11
12
13
1598_04.eps
5V
22
CH3
16
15, 19
VREF VCC
Figure 9. Using the MUXOUT/ADCIN Loop of the LTC1598
to Form a PGA with Eight Inverting Gains
CH0
V+
17
ADCIN
4, 9
21
1µF
1
128R
20
5V
CH0
5V
128R
8-Channel, Differential, 12-Bit A/D System
Using the LTC1391 and LTC1598
LTC1391
0.1µF
–
17
ADCIN
16
15, 19
VREF VCC
CS ADC
CS MUX
8-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
–
CLK
DIN
DOUT
NC
GND
4, 9
NC
1µF
10
6
5, 14
7
11
12
13
1598_05.eps
12
11
10
9
DIN
CLK
CS
DOUT
Figure 10. Using the LTC1598 and LTC1391 as an 8-Channel, Differential 12-Bit ADC System: Opening the Indicated Connection
and Shorting the Dashed Connection Daisy-Chains the External and Internal MUXes, Increasing Channel-Selection Flexibility.
AN87-12
Application Note 87
MUX THE LTC1419 WITHOUT SOFTWARE
by LTC Applications Staff
process repeats. At any time, the input multiplexer channel
can be reset to 0 by applying a logic-high pulse to pin 7 of
the counter.
The circuit shown in Figure 11 uses hardware instead of
software routines to select multiplexer channels in a data
acquisition system. The circuit features the LTC1419
800ksps 14-bit ADC. It receives and converts signals from
a 74HC4051 8-channel multiplexer. Three of the four
output bits from an additional circuit, a 74HC4520 dual 4bit binary counter, are used to select a multiplexer channel. A logic high power-on or processor-generated reset is
applied to the counter’s pin 7.
This data acquisition circuit has a throughput of 800ksps
or 100ksps/channel. As shown in Figure 12, the SINAD is
76.6dB for a full-scale ±2.5V, 1.19kHz sine wave input
signal.
0
fSAMPLE = 100ksps
fIN = 1.19kHz
VIN = ±2.5V
–20
AMPLITUDE (dB)
–40
After the counter is cleared, the multiplexer’s channel
selection input is 000 and the input to channel 0 is applied
to the LTC1419’s S/H input. The channel-selection counter
is clocked by the rising edge of the convert start (CONVST)
signal that initiates a conversion. As each CONVST pulse
increments the counter from 000 to 111, each multiplexer
channel is individually selected and its input signal is
applied to the LTC1419. After each of the eight channels
has been selected, the counter rolls over to zero and the
–60
–80
–100
–120
–140
0
10
20
30
DI_MUX_02.EPS
AIN 2
AIN 3
AIN 4
AIN 5
AIN 6
AIN 7
14
15
12
1
5
2
4
+
0.1µF
VCC
0
16
0.1µF
COM
1
3
1µF
3
INH
4
GND
5
VSS
A
B
2
6
3
8
4
+
6
7
10µF
0.1µF
5
6
7
0.1µF
C
7
8
9
74HC4520
14
13
12
11
10
3
4
5
6
–5V
1Q0 1Q1 1Q2 1Q3
1
1CLK
2Q3
2
1CE
2Q2
7
1CLEAR
2Q1
15
2CLEAR
2Q0
16
VCC
2CE
2CLK
9
10
11
12
13
14
+
AVDD
–
AIN
DVDD
VREF
VSS
AIN
COMP
BUSY
AGND
CS
D13 (MSB)
CONVST
D12
RD
D11
SHDN
D10
D0
D9
D1
D8
D2
D7
D3
D6
D4
DGND
D5
28
27
26
25
BUSY
24
23
CONVERT
CONTROL
22
21
20
19
18
17
16
15
DI_MUX_01.EPS
5V
GND
8
0.1µF
LTC1419
1
2
10µF
+
AIN 1
13
–5V
10µF
5V
AIN O
50
Figure 12. FFT of the MUXed LTC1419’s
Conversion of a Full-Scale 1.19kHz Sine Wave
5V
74HC4051
40
INPUT FREQUENCY (kHz)
0.1µF
DATA 0–13
CLEAR
COUNT
Figure 11. This Simple Stand-Alone Circuit Requires no Software to Sequentially Sample
and Convert Eight Analog Signal Channels at 14-bit Resolution and 100ksps/Channel.
AN87-13
Application Note 87
The PGA’s gain is set using the following equation:
THE LTC1590 DUAL 12-BIT DAC
IS EXTREMELY VERSATILE
by LTC Applications Staff
n
CMOS multiplying DACs make versatile building blocks
that go beyond their basic function of converting digital
data into analog signals. This article details some of the
other circuits that are possible when using the LTC1590
dual, serially interfaced 12-bit DAC.
The circuit shown in Figure 13 uses the LTC1590 to create
a digitally controlled attenuator using DACA and a programmable gain amplifier (PGA) using DACB. The
attenuator’s gain is set using the following equation:
VOUT = –VIN D
2n
where VOUT
VIN
n
D
The attenuator’s gain varies from 4095/4096 to 1/4096. A
code of 0 can be used to completely attenuate the input
signal.
5V
16
where VOUT
VIN
n
D
The gain is adjustable from 4096/4095 to 4096/1. A code
of 0 is meaningless, since this results in infinite gain and
the amplifier operates open loop. With either configuration, the attenuator’s and PGA’s gain are set with 12 bits
accuracy.
VIN A
±10V
VOUT = –VIN 16D
2n
PROGRAMMABLE
ATTENUATOR
1
0.01µF
33pF
SERIAL CLOCK
CHIP SELECT/
DAC LOAD
DATA OUT
CLEAR
14 CLK
11 CS/LD
4 DOUT
15 CLR
7 AGND
10 DGND
24-BIT SHIFT REGISTER AND LATCH
VREF A RFB A
13 DIN
15V
2
LTC1590
DATA IN
= output voltage
= input voltage
= DAC resolution in bits
= value of code applied to DAC
(min code = 001H)
A further modification to the basic attenuator and PGA is
shown in Figure 14. In this circuit, DACA’s attenuator
circuit is modified to give the output amplifier a gain set by
the ratio of resistors R3 and R4. The equation for this
attenuator with output gain is
= output voltage
= input voltage
= DAC resolution in bits
= value of code applied to DAC
(min code = 000H)
0.1µF
VOUT = –VIN 2
D
OUT1A 3
2
–
OUT2A 4
3
+
DACA
8
1/2 LT1358
1
VOUT A
VOUT = –VIN D
2n
n
OUT2B 5
5
OUT1B 6
6
DACB
VOUT = –VIN 2
D
+
1/2 LT1358
VREF B RFB B
–
4
7
VOUT B
0.01µF
33pF
9
8
DI1590_01.EPS
VIN B
±10V
PROGRAMMABLE
GAIN AMPLIFIER
–15V
Figure 13. Driving DACA’s Reference Input (VREF) and Tying the Feedback Resistor (RFB) to the Op Amp’s Output Creates a
12-Bit- Accurate Attenuator. Reversing the VREF and RFB Connections Configures DACB as a Programmable-Gain Amplifier.
AN87-14
Application Note 87
VIN A
±10V
5V
0.1µF
1k
15k
1
16
2
SERIAL CLOCK
CHIP SELECT/
DAC LOAD
DATA OUT
CLEAR
13 DIN
14 CLK
11 CS/LD
4 DOUT
15 CLR
7 AGND
10 DGND
24-BIT SHIFT REGISTER AND LATCH
VREF A RFB A
DATA IN
15V
R4
15k
R3
1k
0.01µF
33pF
OUT1A 3
2
–
OUT2A 4
3
+
OUT2B 5
5
+
OUT1B 6
6
DACA
8
1/2 LT1358
1
VOUT A
VOUT = –VIN 16D
2n
LTC1590
DACB
1/2 LT1358
VREF B RFB B
9
8
15k
–
4
n
VOUT = –VIN 2
16D
7
VOUT B
0.01µF
33pF
DI1590_02.EPS
R1
1k
1k
R2
15k
–15V
VIN B
±10V
Figure 14. Modifying the Basic Attenuator and PGA Creates Gain for the
Attenuator (R3 and R4) and Attenuation at the PGA’s Input (R1 and R2).
With the values shown, the attenuator’s gain has a range
of –1/256 to –16. This range is easily modified by changing
the ratio of R3 and R4. In the other half of the circuit, an
attenuator has been added to the input of DACB, configured as a PGA. The equation for this PGA with input
attenuation is
The cutoff frequency range is a function of the DAC’s
resolution and the digital data that sets the effective
resistance. The effective resistance is
n
VOUT = –VIN 2
16D
Using this effective resistance, the cutoff frequency is
This sets the gain range from effectively –1/16 to –256.
Again, this range can be modified by changing the ratio of
R1 and R2.
The LTC1590 can also be used as the control element that
sets a lowpass filter’s cutoff frequency. This is shown in
Figure 15. The DAC becomes an adjustable resistor that
sets the time constant of the integrator formed by U4 and
CI. With the integrator enclosed within a feedback loop, a
lowpass filter is created.
n
RREF = RI 2
D
fC =
D
2n+1 • π • RI • CI
The cutoff frequency range varies from 0.0000389/RC to
0.159/RC. As an example, to set the minimum cutoff
frequency to 10Hz, make RI = 8.25k and CI = 470pF. At an
input code of 1, the cutoff frequency is 10Hz. The cutoff
frequency increases linearly with increasing code,
becoming 40.95kHz at a code of 4095. Generally, as the
code changes by ±1 bit, the cutoff frequency changes by
an amount equal to the frequency at D = 1. In this example,
the cutoff frequency changes in 10Hz steps.
AN87-15
Application Note 87
15V
10k
10k
0.01µF
10k
VIN A
2
3
–
8
U2A
1/2 LT1358
1
+
15V
15V
0.01µF
1
5V
2
0.01µF
16
3
VREF A RFB A
DATA IN
SERIAL CLOCK
CHIP SELECT/
DAC LOAD
13
DIN
14
CLK
11
CS/LD
4
DOUT
15
CLR
DATA OUT
CLEAR
7 AGND
24-BIT SHIFT REGISTER AND LATCH
0.1µF
OUT2A 4
–
8
U3A
1/2 LT1358
3
2
1
+
+
8
U4A
1/2 LT1358
5
DACB
OUT1B 6
6
+
U3B
1/2 LT1358
–
4
7
RI
6
–
5
+
0.01µF
D
2n+1 • π • RI • CI
CI
U4B
1/2 LT1358
4
6
VOUT A
CI
fC =
OUT2B 5
9
1
–
RI
U1 LTC1590
VREF B RFB B
5
VIN B
2
DACA
10 DGND
10k
OUT1A 3
7
VOUT B
0.01µF
8
+
U2B
1/2 LT1358
–
7
–15V
–15V
4 0.01µF
10k
10k
DI1590_03.EPS
–15V
Figure 15. This LTC1590-Controlled Dual Single-Pole Lowpass Filter Uses RI and the DAC’s Input Code to Create
an Effective Resistance that Sets the Integrator’s Time Constant and, Therefore, the Circuit’s Cutoff Frequency.
NEW 16-BIT SO-8 DAC HAS 1LSB MAX INL AND DNL
OVER INDUSTRIAL TEMPERATURE
by Jim Brubaker and William C. Rempfer
New generations of industrial systems are moving to 16
bits and hence require high performance 16-bit data
converters. The new LTC1595/LTC1596 16-bit DACs provide the easiest to use, most cost effective, highest performance solution for industrial and instrumentation applications. The LTC1595/LTC1596 are serial input, 16-bit,
multiplying current output DACs. Features of the new
DACs include:
AN87-16
❏ ±1LSB maximum INL and DNL over the industrial
temperature range
❏ Ultralow, 1nV-s glitch impulse
❏ ±10V output capability
❏ Small SO-8 package (LTC1595)
❏ Pin-compatible upgrade for industry-standard 12-bit
DACs (DAC8043/8143 and AD7543)
Application Note 87
0V–10V and ±10V Output Capability
VREF
(–10V TO 10V)
Precision 0V–10V Outputs with One Op Amp
Figure 16 shows the circuit for a 0V–10V output range.
The DAC uses an external reference and a single op amp
in this configuration. This circuit can also perform 2quadrant multiplication where the reference input is driven
by a ±10V input signal and VOUT swings from 0V to –VREF.
The full-scale accuracy of the circuit is very precise
because it is determined by precision-trimmed internal
resistors. The power dissipation of the circuit is set by the
op amp dissipation and the current drawn from the DAC
reference input (7k nominal). The supply current of the
DAC itself is less than 10µA.
An advantage of the LTC1595/LTC1596 is the ability to
choose the output op amp to optimize the accuracy,
speed, power and cost of the application. Using an LT1001
provides excellent DC precision, low noise and low power
dissipation (90mW total for Figure 16’s circuit). For higher
speed, an LT1007, LT1468 or LT1122 can be used. The
LT1122 will provide settling to 1LSB in 3µs for a full-scale
transition. Figure 17 shows the 3µs settling performance
obtained with the LT1122. The feedback capacitor in
Figure 16 ensures stability. In higher speed applications,
it can be used to optimize transient response. In slower
applications, the capacitor can be increased to reduce
glitch energy and provide filtering.
7
µP
6
5
1
8
VDD VREF
2
RFB
5
LOAD
LTC1595
LD
OUT1
3
–
1/2 LT1112
GND
4
2
RFB
33pF
CLK
SRI
LTC1595
OUT1
3
–
LD
+
GND
4
LT1001
VOUT
0V TO
–VREF
1595_04.EPS
Figure 16. With a Single External Op Amp, the DAC
Performs 2-Quadrant Multiplication with ±10V Input and
0V to –VREF Output. With a Fixed –10V Reference, it
Provides a Precision 0V–10V Unipolar Output.
VOUT
5V/DIV
GATED VOUT
500µV/DIV
1µs/DIV
Figure 17. When Used with an LT1122 (in the Circuit of Figure
16), the LTC1595/LTC1596 Can Settle in 3µs to a Full-Scale
Step. The Top Trace Shows the Output Swinging from 0V to 10V.
The Bottom Trace Shows the Gated Settling Waveform Settling
to 1LSB (1/3 of a Division) in 3µs.
R3
20k
33pF
CLK
SRI
6
DATA
1
8
VDD VREF
R2
20k
VREF
(–10V TO 10V)
5V
0.1µF
7
CLOCK
5V
+
R1
10k
–
1/2 LT1112
+
VOUT
(–VREF TO VREF)
1595_05.EPS
Figure 18. With a Dual Op Amp, the DAC Performs 4-Quadrant Multiplication.
With a Fixed 10V Reference, it Provides a ±10V Bipolar Output.
AN87-17
Application Note 87
Precision ±10V Outputs with a Dual Op Amp
Figure 18 shows a bipolar, 4-quadrant multiplying application. The reference input can vary from –10V to 10V and
VOUT swings from –VREF to +VREF. If a fixed 10V reference
is used, a precision ±10V bipolar output will result.
Unlike the unipolar circuit of Figure 16, the bipolar gain
and offset will depend on the matching of the external
resistors. A good way to provide good matching and save
board space is to use a pack of matched 20k resistors (the
10k unit is formed by placing two 20k resistors in parallel).
The LT1112 dual op amp is an excellent choice for high
precision, low power applications that do not require high
speed. The LT1469 or LT1124 will provide faster settling.
Again, with op amp selection the user can optimize the
speed, power, accuracy and cost of the application.
LTC1659, LTC1448: SMALLEST RAIL-TO-RAIL
12-BIT DACS HAVE LOWEST POWER
by Hassan Malik
In this age of portable electronics, power and size are the
primary concerns of most designers. The LTC1659 and
the LTC1448 are rail-to-rail, 12-bit, voltage output DACs
that address both of these concerns. The LTC1659 is a
single DAC in an MSOP-8 package that draws only 250µA
from a 3V or 5V supply, whereas the LTC1448 is a dual
DAC in an SO-8 package that draws 450µA from a 3V or 5V
supply.
Figure 19 shows a convenient way to use the LTC1659 in
a digital control loop where 12-bit resolution is required.
The output of the LTC1659 will swing from 0V to VREF,
because there is a gain of one from the REF pin to VOUT at
full-scale. Because the output can only swing up to VCC,
VREF should be less than or equal to VCC to prevent the loss
of codes and degradation of PSRR near full-scale.
DIN
µP
AN87-18
VCC
REF
CLK
LTC1659
CS/LD
GND
VOUT
CONTROL
VOLTAGE
(0V TO VREF)
Figure 19. 12-Bit DAC for Digital Control Loop
1659_01
LT1236
VIN
(7.2V to 40V)
IN
OUT
GND
0.1µF
DIN
To obtain full dynamic range, the REF pin can be connected
to the supply pin, which can be driven from a reference to
guarantee absolute accuracy (see Figure 20). The LT1236
is a precision 5V reference with an input range of 7.2V to
40V. In this configuration, the LTC1659 has a wide output
swing of 0V to 5V. The LTC1448 can be used in a similar
configuration where dual DACs are needed.
VREF ≤ VCC
2.7V to 5.5V
µP
CLK
CS/LD
VCC
LTC1659
REF
VOUT
CONTROL
VOLTAGE
(OV TO 5V)
GND
1659_02
Figure 20. 12-Bit DAC with Wide Output Swing
Application Note 87
Digitally Controlled LCD Bias Generator
AN SMBus-CONTROLLED 10-BIT, CURRENT OUTPUT,
50µA FULL-SCALE DAC
by Ricky Chow
The LTC1427-50 is a 10-bit, current-output DAC with an
SMBus interface. This device provides precision, fullscale current of 50µA ±1.5% at room temperature (±2.5%
over temperature), wide output voltage DC compliance
(from –15V to (VCC – 1.3V)) and guaranteed monotonicity
over a wide supply-voltage range. It is an ideal part for
applications in contrast/brightness control or voltage
adjustment in feedback loops.
Figure 21 is a schematic of a digitally controlled LCD bias
generator using a standard SMBus 2-wire interface. The
LT1317 is configured as a boost converter, with the output
voltage (VOUT) determined by the values of the feedback
resistors, R1 and R2. The LTC1427-50’s DAC current
output is connected to the feedback node of the LT1317.
The LTC1427-50’s DAC current output increases or
decreases according to the data sent via the SMBus. As the
DAC output current varies from 0µA to 50µA, the output
voltage is controlled over the range of 12.7V to 24V. A
1LSB change in the DAC output current corresponds to an
11mV change in the output voltage.
D1
L1
VOUT*
6
5
SW
VIN
2–4
CELLS
LT1317
SHDN
1µF
3
SHDN
GND
4
VCC = 3.3V
R1
226k
1%
FB
LTC1427-50
2
1
R2
12.1k
1%
VC
1
4700pF
100k
2
3
C1
1µF
4
SHDN
VCC
AD1
IOUT
AD0
SCL
GND
SDA
µP
8
(e.g., 8051)
7
6
5
P1.2
P1.1
P1.0
*VOUT = 12.7V–24V IN 11mV STEPS
15mA FROM 2 CELLS
35mA FROM 3 CELLS
L1 = 10µH (SUMIDA CD43
MURATA-ERIE LQH3C
OR COILCRAFT DO1608)
D1 = ON SEMICONDUCTOR MBR0530
Figure 21. Digitally Controlled LCD Bias Generator
AN87-19
Application Note 87
Interface Circuits
Tf ~ 10µs
T1/2 = 120µs
SIMPLE RESISTIVE SURGE PROTECTION FOR
INTERFACE CIRCUITS
by LTC Applications Staff
VOLTAGE
VP
VP/2
Surges and Circuits
Many interface circuits must survive surge voltages such
as those created by lightning strikes. These high voltages
cause the devices within the IC to break down and conduct
large currents, causing irreversible damage to the IC.
Engineers must design circuits that tolerate the surges
expected in their environments. They can quantify the
surge tolerance of circuitry by using a surge standard.
Standards differ mainly in their voltage levels and wave
forms. At LTC, we test surge resistance using the circuit
of Figure 22. We describe the voltage wave form (Figure
23) by its peak value VP, the “front time” TF (roughly, the
rise time), and the “time to half-value” T1/2 (roughly, the
time from the beginning of the pulse to when the pulse
decays to half of VP). Surges are similar to ESD, but
challenge circuits in a different way. A surge may rise to
1kV in 10ms, whereas an ESD pulse might rise to 15kV in
only a few ns. However, the surge lasts for more than
100ms, whereas the ESD pulse decays in about 50ns.
Thus, the surge challenges the power dissipation ability of
the protection circuitry, whereas the ESD challenges the
turn-on time and peak current handling. The Linear Technology LT1137A has on-chip circuitry to withstand ESD
pulses up to 15kV (IEC 801-2). This circuitry also increases the surge tolerance of the LT1137A relative to a
standard 1488/1489.
RB
10k
VP
HV SUPPLY
T1/2
TIME
TF CONTROLLED BY R2 × COUT
T1/2 CONTROLLED BY C1 × R1
VP SET BY HV SUPPLY
Figure 23. LTC Surge-Test Waveform
Designing for Surge Tolerance
Many designers enhance the surge tolerance of a circuit
by placing a transient voltage suppressor (TVS) in parallel
with the vulnerable IC pins, as shown in Figure 24. The
TVS contains Zener diodes, which break down at a certain
voltage and shunt the surge current to ground. Thus, the
TVS clamps the voltage at a level safe for the IC. The TVS,
like any protection circuitry, increases the manufacturing
cost and complexity of the circuit. Alternately, designers
can use a series resistor to protect the vulnerable pins, as
shown in Figure 25. The resistor reduces the current
1
0.1µF
+
C1
7µF
3kV
R1
50Ω
3W
VCC –
VCC+
14
0.1µF
1488
R2
75Ω, 2W
2
13
3
12
4
11
5
10
6
9
7
8
TVS
COUT
0.05µF
4kV
TF CONTROLLED BY R2 × COUT
T1/2 CONTROLLED BY C1 × R1
VP SET BY HV SUPPLY
Figure 22. LTC Surge-Test Circuit: TF Controlled by R2 • COUT; T1/2
Controlled by C1 • R1; VP Set by HV Supply
AN87-20
Tf
TVS
DUT
TVS
TVS
Figure 24. 1488 Line Driver with TVS Surge Protection
Application Note 87
1
0.1µF
5V
2×
0.1µF
2
V+
V–
28
3
2V/DIV
26
LT1137A
TO
LINE
0.1µF
27
VCC
2 × 0.1µF
4
25
RS
5
24
RS
6
23
RS
7
22
RS
8
21
RS
9
20
RS
10
19
RS
11
18
RS
12
17
13
16
5µs/DIV
RS = 0Ω
130kBd
(a)
TO LOGIC
2V/DIV
5V
0.1µF
ON/OFF
14
(b)
15
Figure 27. Output Waveforms with Series Resistor
1
0.1µF
5V
flowing into the IC to a safe level. Resistive protection
simplifies design and inventory and may offer lower cost.
The resistance must be large enough to protect the IC, but
not so large that it degrades the frequency performance of
the circuit. Larger surge amplitudes require increased
resistance to protect the IC. More robust ICs need less
V+
V–
28
0.1µF
Figure 25. LT1137A with Resistive Surge Protection
2
27
VCC
26
3
2 × 0.1µF
LT1137A
2 × 0.1µF
4
25
RS
5
24
RS
6
23
RS
7
22
RS
8
21
800
RS
9
20
600
RS
10
19
400
RS
11
18
RS
12
17
SCOPE
LT1137A SAFE CURVE
1488 SAFE CURVE
1000
200
0
0
100
200
300
400
R SERIES (Ω)
500
600
Figure 26. Safe Curves for 1488 (SN75188N) and LT1137A. Safe
Curves Represent the Highest VP for Which No IC Damage
Occurred After 10 Surges
130k baud
+
2.5nF
1200
SAFE SURGE VP (V)
5µs/DIV
RS = 600Ω
130kBd
3kΩ
5V
13
14
ON/OFF
16
15
Figure 28. Testing Line Driver Output Waveform
AN87-21
Application Note 87
resistance for protection against a given surge amplitude.
Linear’s LT1137A is protected by a much smaller resistor
than a 1488, as shown in Figure 26. These curves are
empirical “rules of thumb.” You should test actual circuits.
The series resistor may have an adverse effect on the
frequency performance of the circuit. When protecting a
receiver, the resistor has little effect. Figures 27a and 27b
show the effect of a 600Ω resistor on the driver-output
wave form. These waveforms were obtained with the test
circuit of Figure 28. A 600Ω resistor is adequate for 1kV
surges, but has minimal effect on the driver wave form up
to 130kbaud, even with a worst-case load of 3kΩ||2.5nF.
You must choose the series resistor carefully to withstand
the surge. Unfortunately, neither voltage ratings nor power
ratings provide an adequate basis for choosing surgetolerant resistors. Usually, through-hole resistors will
withstand much larger surges than surface mount resistors of the same value and power rating. Typical 1/8 Watt
THE LTC1343 AND LTC1344 FORM A SOFTWARESELECTABLE MULTIPLE-PROTOCOL INTERFACE PORT
USING A DB-25 CONNECTOR
by Robert Reay
Introduction
With the explosive growth in data networking equipment
has come the need to support many different serial protocols using only one connector. The problem facing interface designers is to make the circuitry for each serial
protocol share the same connector pins without introducing conflicts. The main source of frustration is that each
serial protocol requires a different line termination that is
not easily or cheaply switched.
With the introduction of the LTC1343 and LTC1344, a
complete software-selectable serial interface port using
an inexpensive DB-25 connector becomes possible. The
chips form a serial interface port that supports the V.28
(RS232), V.35, V.36, RS449, EIA-530, EIA-530A or X.21
protocols in either DTE or DCE mode and is both NET1 and
NET2 compliant. The port runs from a single 5V supply and
AN87-22
surface mount resistors are not suitable for protecting the
LT1137A. If you use surface mount components, you may
need ratings of 1W or more. With the LT1137A, you can
use carbon film 1/4W through-hole resistors against surges
up to about 900V, and 1/2W carbon film resistors against
surges up to about 1200V. Unfortunately, using series or
parallel combinations of resistors does not increase the
surge handling as one would expect.
Resistive Surge Protection
The LT1137A has proprietary circuitry that makes it more
robust against ESD and surges than the standard 1488/
1489. The greater surge tolerance of the LT1137A makes
it practical to use resistive surge protection, reducing
inventory and component cost relative to TVS surge
protection. The major considerations are the surge tolerance required, the resulting resistor value needed, resistor
robustness and frequency performance.
supports an echoed clock and loop-back configuration
that helps eliminate glue logic between the serial controller
and the line transceivers.
A typical application is shown in Figure 29. Two LTC1343s
and one LTC1344 form the interface port using a DB-25
connector, shown here in DTE mode.
Each LTC1343 contains four drivers and four receivers
and the LTC1344 contains six switchable resistive terminators. The first LTC1343 is connected to the clock and
data signal lines along with the diagnostic LL (local loopback) and TM (test mode) signals. The second LTC1343 is
connected to the control-signal lines along with the diagnostic RL (remote loop-back) signal. The single-ended
driver and receiver could be separated to support the RI
(ring-indicate) signal. The switchable line terminators in
the LTC1344 are connected only to the high speed clock
and data signals. When the interface protocol is changed
via the digital mode selection pins (not shown), the drivers
and receivers are automatically reconfigured and the
appropriate line terminators are connected.
Application Note 87
CTS
DSR
DCD
DTR
RTS
RL
D3
D2
D1
TM
RXD
RXC
TXC
R3
R4
R2
TXD
LL
D3
D2
D1
LTC1343
LTC1343
D4
SCTE
D4
R1
R3
R4
R2
R1
LTC1344
13 5
22 6
10 8
23 20 19
4
21
1
7
25
16 3
9
17 12 15
11 24 14 2
18
LL A (141)
TXD A (103)
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
TM A (142)
SGND (102)
SHIELD (101)
RTS A (105)
RL A (140)
RTS B
DTR A (108)
DTR B
DCD A (109)
DCD B
DSR A (107)
CTS A (106)
DSR B
CTS B
DB-25 CONNECTOR
Figure 29. LTC1343/LTC1344 Typical Application
GENERATOR
Review of Interface Standards
The serial interface standards RS232, EIA-530, EIA-530A,
RS449, V.35, V.36 and X.21 specify the function of each
signal line, the electrical characteristics of each signal, the
connector type, the transmission rate and the data exchange protocols. The RS422 (V.11) and RS423 (V.10)
standards merely define electrical characteristics. The
RS232 (V.28) and V.35 standards also specify their own
electrical characteristics. In general, the US standards
start with RS or EIA, and the equivalent European standards start with V or X. The characteristics of each
interface are summarized in Table 2.
BALANCED
INTERCONNECTING
CABLE
A
A'
C
B'
RECEIVER
C'
Figure 30. Typical V.10 Interface
A'
A
R1
51.5Ω
S1
Table 2 shows only the most commonly used signal lines.
Note that each signal line must conform to only one of four
electrical standards, V.10, V.11, V.28 or V.35.
S2
R2
51.5Ω
LTC1344
LTC1343
R8
6k
R3
124Ω
R6
10k
R4
20k
B
RECEIVER
R7
10k
S4
V.10 (RS423) Interface
C'
R5
20k
S3
B'
A typical V.10 unbalanced interface is shown in Figure 30.
A V.10 single-ended generator (output A with ground C)
LOAD
CABLE
TERMINATION
GND
Figure 31. V.10 Receiver Configuration
AN87-23
Application Note 87
Table 2. Interface Summary
Clock and Data Signals
Control Signals
Test Signals
TXD
SCTE
TXC
RXC
RXD
RT S
DTR
DSR
DCD
CTS
RI
LL
RL
TM
CCITT#
(103)
(113)
(114)
(115)
(104)
(105)
(108)
(107)
(109)
(106)
(125)
(141)
(140)
(142)
RS232
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
EIA-530
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
———
V.10
V.10
V.10
EIA-530A
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.10
V.11
V.11
V.10
V.10
V.10
V.10
RS449
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.10
V.10
V.10
V.35
V.35
V.35
V.35
V.35
V.35
V.28
———
V.28
V.28
V.28
———
———
———
———
V.36
V.11
V.11
V.11
V.11
V.11
V.11
———
V.11
V.11
V.11
———
V.10
V.10
V.10
X.21
V.11
V.11
V.11
V.11
V.11
V.11
———
V.11
———
———
———
———
———
is connected to a differential receiver with input A' connected to A and input B' connected to the signal-return
ground C. The receiver’s ground C' is separate from the
signal return. Usually, no cable termination between A'
and B' is required for V.10 interfaces. The V.10 receiver
configuration for the LTC1343 and LTC1344 is shown in
Figure 31.
In V.10 mode, switches S1 and S2 inside the LTC1344 and
S3 inside the LTC1343 are turned off. Switch S4 inside the
LTC1343 shorts the noninverting receiver input to ground
so the B input at the connector can be left floating. The
cable termination is then the 30k input impedance to the
ground of the LTC1343 V.10 receiver.
V.11 (RS422) Interface
A typical V.11 balanced interface is shown in Figure 32. A
V.11 differential generator with outputs A and B and
ground C is connected to a differential receiver with
ground C', input A' connected to A and input B' connected
to B. The V.11 interface has a differential termination at the
A typical V.28 unbalanced interface is shown in Figure 34.
A V.28 single-ended generator (output A with ground C) is
connected to a single-ended receiver with input A' connected to A and ground C' connected via the signal return
ground to C. In V.28 mode, all switches are off except S3
inside the LTC1343, which connects a 6k impedance (R8)
to ground in parallel with 20k (R5) plus 10k (R6), for an
combined impedance of 5k, as shown in Figure 35. The
noninverting input is disconnected inside the LTC1343
receiver and connected to a TTL level reference voltage for
a 1.4V receiver trip point.
A'
A
LTC1344
LTC1343
R8
6k
R5
20k
R6
10k
S1
RECEIVER
S2
S3
R3
124Ω
A'
B
B'
C
C'
100Ω
MIN
Figure 32. Typical V.11 Interface
AN87-24
V.28 (RS232) Interface
LOAD
CABLE
TERMINATION
A
receiver end with a minimum value of 100Ω. The termination resistor is optional in the V.11 specification, but for
the high speed clock and data lines, the termination is
required to prevent reflections from corrupting the data. In
V.11 mode, all switches are off except S1 inside the
LTC1344, which connects a 103Ω differential termination
impedance to the cable, as shown in Figure 33.
R1
51.5Ω
BALANCED
INTERCONNECTING
CABLE
GENERATOR
———
R2
51.5Ω
R4
20k
B
B'
C'
R7
10k
S4
GND
Figure 33. V.11 Receiver Configuration
RECEIVER
Application Note 87
LOAD
BALANCED
INTERCONNECTING
CABLE
GENERATOR
LOAD
CABLE
TERMINATION
50Ω
CABLE
TERMINATION
125Ω
125Ω
50Ω
50Ω
50Ω
B
B'
C
C'
C'
C
RECEIVER
A'
A
RECEIVER
A'
A
BALANCED
INTERCONNECTING
CABLE
GENERATOR
Figure 36. Typical V.35 Interface
Figure 34. Typical V.28 Interface
A'
A'
A
R1
51.5Ω
S1
S2
LTC1344
R8
6k
R2
51.5Ω
R5
20k
R1
51.5Ω
R6
10k
S3
R3
124Ω
R4
20k
B
LTC1344
LTC1343
R8
6k
R5
20k
R6
10k
RECEIVER
S1
S2
B'
R7
10k
S4
C'
A
LTC1343
GND
Figure 35. V.28 Receiver Configuration
V.35 Interface
A typical V.35 balanced interface is shown in Figure 36. A
V.35 differential generator with outputs A and B and
ground C is connected to a differential receiver with
ground C', input A' connected to A and input B' connected
to B. The V.35 interface requires T or delta network
termination at the receiver end and the generator end. The
receiver differential impedance measured at the connector
must be 100 ±10Ω, and the impedance between shorted
terminals (A' and B') and ground (C') is 150 ±15Ω.
In V.35 mode, both switches S1 and S2 inside the LTC1344
are on, connecting the T-network impedance, as shown in
Figure 37. Both switches in the LTC1343 are off. The 30k
input impedance of the receiver is placed in parallel with
the T-network termination, but does not affect the overall
input impedance significantly.
The generator differential impedance must be 50Ω to
150Ω, and the impedance between shorted terminals (A
and B) and ground (C) is 150Ω ±15Ω. For the generator
termination, switches S1 and S2 are both on and the top
R3
124Ω
R2
51.5Ω
RECEIVER
S3
R7
10k
R4
20k
B
B'
S4
C'
GND
Figure 37. V.35 Receiver Configuration
side of the center resistor is brought out to a pin so it can
be bypassed with an external capacitor to reduce common
mode noise, as shown in Figure 38.
Any mismatch in the driver rise and fall times or skew in
driver propagation delays will force current through the
center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
This spike can cause EMI problems that are reduced by
capacitor C1, which shunts much of the common mode
energy to ground rather than down the cable.
A
LTC1344
V.35
DRIVER
124Ω
51.5Ω
S2
ON
S1
ON
51.5Ω
B
C1
100pF
C
Figure 38. V.35 Driver Using the LTC1344
AN87-25
Application Note 87
Table 3. LTC1343/LTC1344 Mode Selection
M2
M1
M0
CTRL/
CLK
D1
D2
D3
D4
R1
R2
R3
R4
V.10/RS423
0
0
0
X
V.10
V.10
V. 1 0
V.10
V.10
V.10
V.10
V.10
RS530A clock & data
0
0
1
0
V.10
V.11
V. 1 1
V.11
V.11
V.11
V.11
V.10
RS530A control
0
0
1
1
V.10
V.11
V.10
V.11
V.11
V.10
V.11
V.10
Reserved
0
1
0
X
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
LTC1343 Mode Name
X.21
0
1
1
X
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.35 clock & data
1
0
0
0
V.28
V.35
V.35
V.35
V.35
V.35
V.35
V.28
V.35 control
1
0
0
1
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
RS530/RS449/V.36
1
0
1
X
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.28/RS232
1
1
0
X
V.28
V.28
V. 2 8
V.28
V.28
V.28
V.28
V.28
No Cable
1
1
1
X
Z
Z
Z
Z
Z
Z
Z
Z
LATCH
21
LTC1344
DCE/
DTE M2
22
23
M1 M0 (DATA)
24
1
CONNECTOR
(DATA)
R1, 10k
LTC1343
M0
17
R2, 10k
20
CTRL/CLK
M1
LATCH
M2
18
R3, 10k
22
19
21
VCC
VCC
NC
R4, 10k
DCE/DTE
VCC
VCC
NC
CABLE
LTC1343
DCE/DTE
M2
VCC
20
22
CTRL/CLK
M1
LATCH
M0
21
19
18
17
(DATA)
Figure 39. Mode Selection by Cable
AN87-26
Application Note 87
PORT #1
M1
M2
DCE/DTE
CONNECTOR #1
M0
LATCH
PORT #2
M1
M2
DCE/DTE
CONTROLLER
CONNECTOR #2
M0
LATCH
M1
M1
M2
M2
DCE/DTE
DCE/DTE
LATCH 1
CONNECTOR #3
M0
LATCH 2
LATCH 3
The pull-up resistors R1–R4 ensure a binary 1 when a pin
is left unconnected and also ensure that the two LTC1343s
and the LTC1344 enter the no-cable mode when the cable
is removed. In the no-cable mode, the LTC1343 power
supply current drops to less than 200µA and all LTC1343
driver outputs and LTC1344 resistive terminators are
forced into a high impedance state. Note that the data latch
pin, LATCH, is shorted to ground for all chips.
The interface protocol may also be selected by the serial
controller or host microprocessor, as shown in Figure 40.
PORT #3
M0
The interface protocol may be selected by simply plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable, as shown in
Figure 39.
LATCH
Figure 40. Mode Selection by Controller
LTC1343/LTC1344 Mode Selection
The interface protocol is selected using the mode select
pins M0, M1, M2 and CTRL/CLK, as summarized in Table
3. The CTRL/CLK pin should be pulled high if the LTC1343
is being used to generate control signals and pulled low if
used to generate clock and data signals.
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 =
0. For the control signals, CTRL/CLK = 1 and the drivers
and receivers will operate in RS232 (V.28) electrical mode.
For the clock and data signals, CTRL/CLK = 0 and the
drivers and receivers will operate in V.35 electrical mode,
except for the single-ended driver and receiver, which will
operate in the RS232 (V.28) electrical mode. The DCE/DTE
pin will configure the port for DCE mode when high, and
DTE when low.
The mode selection pins M0, M1, M2 and DCE/DTE can be
shared among multiple interface ports, while each port
has a unique data-latch signal that acts as a write enable.
When the LATCH pin is low, the buffers on the MO, M1,
M2, CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high, the buffers latch the
data, and changes on the input pins will no longer affect
the chip.
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VCC.
Loop-Back
The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 41 shows
a complete DTE interface in the loop-back configuration
and Figure 42 the DCE loop-back configuration. The loopback configuration is selected by pulling the LB pin low.
Enabling the Single-Ended Driver and Receiver
When the LTC1343 is being used to generate the control
signals (CTRL/CLK = high) and the EC pin is pulled low, the
DCE/DTE pin becomes an enable for driver 1 and receiver
4 so their inputs and outputs can be tied together, as
shown in Figure 43.
AN87-27
Application Note 87
SERIAL
CONTROLLER
LL
LTC1343
LTC1344
D1
LTC1344
LL
LL
LTC1343
R4
SERIAL
CONTROLLER
LL
TXD
D2
TXD
TXD
103Ω
R3
TXD
SCTE
D3
SCTE
SCTE
103Ω
R2
SCTE
D4
R1
RXD
D2
RXD
TM
R4
TM
TM
D1
TM
1
0
1
0
0
0
1
0
1 0 1 0 0
1 0 1 1 0
1
0
1
LTC1343
LATCH
RXD
EC
103Ω
LB
R3
DCE/DTE
RXD
CTRL/CLK
RXC
M2
D3
M1
RXC
M0
RXC
M0
M1
M2
DCE/DTE
LATCH
103Ω
M0
M1
M2
DCE/DTE
LATCH
R2
LATCH
RXC
EC
TXC
LB
D4
DCE/DTE
TXC
CTRL/CLK
TXC
M2
103Ω
M1
R1
M0
TXC
0
1
0
1
0
LTC1343
RL
RL
D1
RTS
D2
RTS
DTR
D3
DTR
RL
R4
RL
RTS
R3
RTS
DTR
R2
DTR
D4
R1
D2
CTS
RI
R4
RI
RI
D1
RI
LATCH
CTS
EC
CTS
LB
R3
DCE/DTE
CTS
CTRL/CLK
DSR
M2
D3
M1
DSR
M0
DSR
LATCH
R2
EC
DSR
LB
DCD
DCE/DTE
D4
CTRL/CLK
DCD
M2
DCD
M1
R1
M0
DCD
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
Figure 41. Normal DTE Loop-Back
AN87-28
Figure 42. Normal DCE Loop-Back
Application Note 87
LTC1343
5
DCE/DTE
D1
21
16
VCC
39
20
24
R4
26
CTRL/CLK
EC
Figure 43. Single-Ended Driver and Receiver Enable
The EC pin has no affect on the configuration when CTRL/
CLK is high except to allow the DCE/DTE pin to become an
enable. When DCE/DTE is low, the driver 1 output is
enabled. The receiver 4 output goes into three-state, and
the input presents a 30k load to ground.
When DCE/DTE is high, the driver 1 output goes into threestate, and the receiver 4 output is enabled. The receiver 4
input presents a 30k load to ground in all modes except
when configured for RS232 operation, when the input
impedance is 5k to ground.
Multiprotocol Interface with DB-25
or µDB-26 Connectors
A multiprotocol serial interface with a standard DB-25
connector EIA-530 pin configuration is shown in Figure
44. (Figures 44–47 follow on pp. 30–33). The signal lines
must be reversed in the cable when switching between
DTE and DCE using the same connector. For example, in
DTE mode, the RXD signal is routed to receiver 3, but in
DCE mode, the TXD signal is routed to receiver 3. The
interface mode is selected by logic outputs from the
controller or from jumpers to either VCC or GND on the
mode-select pins. The single-ended driver 1 and receiver
4 of the control chip share the RL signal on connector pin
21. With EC low and CTRL/CLK high, the DCE/DTE pin
becomes an enable signal.
Single-ended receiver 4 can be connected to pin 22 to
implement the RI (ring indicate) signal in RS232 mode
(see Figure 45). In all other modes, pin 22 carries the
DSR(B) signal.
A cable selectable multiprotocol interface is shown in
Figure 46. Control signals LL, RL and TM are not implemented. The VCC supply and select lines M0 and M1 are
brought out to the connector. The mode is selected in the
cable by wiring M0 (connector pin 18) and M1 (connector
pin 21) and DCE/DTE (connector pin 25) to ground (connector pin 7) or letting them float. If M0, M1 or DCE/DTE
are floating, pull-up resistors R3, R4 and R5 will pull the
signals to VCC. The select bit M1 is hard wired to VCC. When
the cable is pulled out, the interface goes into the no-cable
mode.
A cable-selectable multiprotocol interface found in many
popular data routers is shown in Figure 47. The entire
interface, including the LL signal, can be implemented
using the tiny µDB-26 connector.
Conclusion
The LTC1343 and LTC1344 allow the designer of a multiprotocol serial interface to spend all of his time on the
software rather than the hardware. Simply drop the chips
down on the board, hook them up to the connector and a
serial controller, apply the 5V supply voltage and you’re off
and running. In addition, the chip set’s small size and
unique termination topology allow many ports to be
placed on a board using inexpensive connectors and
cables.
AN87-29
Application Note 87
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
2
43
42
4
CHARGE
PUMP
3
C5
1µF
41
8
R1
100k
C11
1µF
C9
1µF
C12
1µF
40
GND
23
LB
2
43
42
4
CHARGE
PUMP
41
8
R2
100k
LB
D2
D3
35
34
33
D4
R2
R3
28
27
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
21
DCE
19
M2
18
M1
17
M0
R1
40
GND
23
LB
26
EC
24
DCE/DTE
M2
M1
M0
Figure 44. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
AN87-30
7
1
RXD A
RXD B
RXC A
RXC B
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
TM A
LL A
SGND
SHIELD
C13
3.3µF
38
37
36
16
LATCH
C10
1µF
39
D1
32
31
30
29
15
VCC
VCC
DCE
TM A
LTC1343
14
DTE_CTS/DCE_RTS
24
44
10
12
13
DTE_DSR/DCE_DTR
EC
1
9
DTE_DCD/DCE_DCD
DTE
LL A
25
7
DTE_DTR/DCE_DSR
18 17 19 20 22 23 24 1
26
21
DCE
19
M2
18
M1
17
M0
6
DTE_RTS/DCE_CTS
16 15
R3
R2
5
DTE_RL/DCE_RL
10
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
R1
3
VCC
9
15
12
17
9
3
16
D4
15
DTE_TM/DCE_LL
7
32
31
30
29
28
27
D3
14
DTE_RXD/DCE_TXD
6
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
10
12
13
DTE_RXC/DCE_SCTE
4
38
37
36
35
34
33
D2
9
DTE_TXC/DCE_TXC
5
18
7
DTE_SCTE/DEC_RXC
DB-25 CONNECTOR
DCE/
DTE M2 M1 M0
39
D1
6
DTE_TXD/DCE_RXD
2
VEE
C4
3.3µF
LTC1343
5
DTE_LL/DCE_TM
VCC
C2
1µF
+
C1
1µF
44
+
C3
1µF
1
21
RL A
4 RTS A
19 RTS B
20
DTR A
23
DTR B
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13
CTS B
RL A
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
Application Note 87
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
2
43
42
4
CHARGE
PUMP
3
C5
1µF
D2
7
RXC
D3
9
TXC
D4
10
12
13
VCC
LL
R1
100k
C11
1µF C9
1µF
40
GND
23
LB
C12
1µF
44
2
43
42
4
CHARGE
PUMP
41
8
6
CTS
7
DSR
9
DCD
VCC
10
12
13
14
DTR
15
CTX
VCC
LATCH
R2
100k
16 15 18 17 19 20 22 23 24 1
TM A (142)
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
VCC
24
SCTE A (113)
11
SCTE B
2
TXD A (103)
14
TXD B
18
LL A (141)
VCC
VCC
C10
1µF
7
1
SGND (102)
SHIELD (101)
C13
3.3µF
39
D1
D2
D3
35
34
33
D4
32
31
30
29
R1
R2
27
26
21
DCE
19
M2
18
M1
17
M0
EC
CTS A (106)
CTS B
DSR A (107)
DSR B/RI A (125)
DCD A (109)
DCD B
20
DTR A (108)
23
DTR B
4
RTS A (105)
19
RTS B
21
RL A (140)
28
R3
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
40
GND
23
LB
5
13
6
22
8
10
38
37
36
16
RL
10
LTC1343
5
RI
24
1
3
VCC
EC
9
3
16
17
9
15
12
26
21
DCE
19
M2
18
M1
17
M0
15
TXD
7
25
R3
R2
6
38
37
36
35
34
33
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
14
SCTE
4
39
32
31
30
29
28
27
R1
DB-25 FEMALE
CONNECTOR
DCE/
DTE M2 M1 M0
5
D1
6
RXD
2
VEE
C4
3.3µF
LTC1343
5
TM
LB
41
8
VCC
C2
1µF
+
C1
1µF
44
+
C3
1µF
1
RIEN = RS232
24
M2
M1
M0
Figure 45. Controller-Selectable Multiprotocol DCE Port with Ring-Indicate and DB-25 Connector
AN87-31
Application Note 87
C6
100pF
C7
100pF
3
C8
100pF
8
12 13
11
LTC1344
VCC
5V
14
2
43
42
4
CHARGE
PUMP
3
C5
1µF
41
8
D4
10
12
13
R3
32
31
30
29
28
27
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
R1
100k
C11
1µF
C9
1µF
40
GND
23
LB
C12
1µF
44
43
42
CHARGE
PUMP
41
8
6
7
DTE_DTR/DCE_DSR
9
10
12
13
DTE_DCD/DCE_DCD
14
DTE_DSR/DCE_DTR
15
DTE_CTS/ DCE_RTS
R2
100k
LB
7
9
10
16 15
18 17 19 20 22
23 24 1
VCC
D1
15
12
17
9
3
16
7
DCE
RXD A
RXD B
RXC A
RXC B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
SGND
1
SHIELD
VCC
C10
1µF
VCC
R3
10k
VCC
R4
10k
VCC
R5
10k
25
C13
3.3µF
21
18
DCE/DTE
M1
M0
4 RTS A
19 RTS B
20
DTR A
23
DTR B
D3
35
34
33
D4
32
31
30
29
R1
R2
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13
CTS B
28
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
24
EC
VCC
CABLE WIRING FOR MODE SELECTION
MODE
PIN 18
PIN 21
V.35
PIN 7
PIN 7
EIA-530, RS449,
NC
PIN 7
V.36, X.21
RS232
PIN 7
NC
CABLE WIRING FOR DTE/DCE
SELECTION
MODE
PIN 25
DTE
PIN 7
DCE
NC
Figure 46. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
AN87-32
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
VCC
38
37
36
D2
27
40
GND
23
LB
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
39
R3
16
VCC
6
LTC1343
5
DTE_RTS/DCE_CTS
24
1
3
VCC
EC
2
4
4
38
37
36
35
34
33
D3
9
DTE_TXC/DCE_TXC
5
D2
7
DTE_SCTE/DEC_RXC
DB-25 CONNECTOR
DCE/
DTE M2 M1 M0
39
D1
6
DTE_TXD/DCE_RXD
2
VEE
C4
3.3µF
LTC1343
5
VCC
C2
1µF
+
C1
1µF
44
+
C3
1µF
1
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
Application Note 87
C6
100pF
C7
100pF
3
C8
100pF
8
12 13
11
LTC1344
VCC
5V
14
2
43
42
4
CHARGE
PUMP
3
C5
1µF
41
8
D4
10
12
13
R3
32
31
30
29
28
27
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
R1
100k
C11
1µF
C9
1µF
40
GND
23
LB
C12
1µF
44
43
42
CHARGE
PUMP
41
8
LB
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
7
1
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
SHIELD
VCC
C10
1µF
VCC
R3
10k
VCC
R4
10k
VCC
R5
10k
25
C13
3.3µF
21
18
DCE/DTE
M1
M0
39
D1
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
40
GND
23
LB
DCE
RXD A
RXD B
RXC A
RXC B
SGND
VCC
28
27
16
R2
100k
VCC
R3
15
VCC
18 17 19 20 22 23 24 1
R2
14
DTE_CTS/DCE_RTS
16 15
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13
CTS B
26
LL B
10
12
13
DTE_DSR/DCE_DTR
10
32
31
30
29
9
DTE_DCD/DCE_DCD
9
4 RTS A
19 RTS B
20
DTR A
23
DTR B
7
DTE_DTR/DCE_DSR
7
38
37
36
35
34
33
6
DTE_RTS/DCE_CTS
6
LTC1343
5
DTE_LL/DCE_LL
24
1
3
VCC
EC
2
4
4
38
37
36
35
34
33
D3
9
DTE_TXC/DCE_TXC
5
D2
7
DTE_SCTE/DEC_RXC
µDB-26 CONNECTOR
DCE/
DTE M2 M1 M0
39
D1
6
DTE_TXD/DCE_RXD
2
VEE
C4
3.3µF
LTC1343
5
VCC
C2
1µF
+
C1
1µF
44
+
C3
1µF
1
D2
D3
D4
R1
24
EC
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
LL B
VCC
CABLE WIRING FOR MODE SELECTION
MODE
PIN 18
PIN 21
V.35
PIN 7
PIN 7
EIA-530, RS449,
NC
PIN 7
V.36, X.21
RS232
PIN 7
NC
CABLE WIRING FOR DTE/DCE
SELECTION
MODE
PIN 25
DTE
PIN 7
DCE
NC
Figure 47. Cable-Selectable Multiprotocol DTE/DCE Port with µDB-26 Connector
AN87-33
Application Note 87
VCC
THE LT1328: A LOW COST IRDA RECEIVER SOLUTION
FOR DATA RATES UP TO 4MBPS
by Alexander Strong
D2
HSDL-4220
RD2
6.8Ω
1/2W
IrDA SIR
The LT1328 circuit in Figure 48 operates over the full 1cm
to 1 meter range of the IrDA standard at the stipulated light
levels. For IrDA data rates of 115kbps and below, a 1.6µs
pulse width is used for a zero and no pulse for a one. Light
levels are 40mW/sr (milliwatts per steradian) to 500mW/
sr. Figure 49 shows a scope photo for a transmitter input
(top trace) and the LT1328 output (bottom trace). Note
that the input to the transmitter is inverted; that is, transmitted light produces a high at the input, which results in
a zero at the output of the transmitter. The Mode pin (pin
7) should be high for these data rates.
An IrDA- compatible transmitter can also be implemented
with only six components, as shown in Figure 50. Power
requirements for the LT1328 are minimal: a single 5V
supply and 2mA of quiescent current.
C3
1000pF
LIGHT IN
D1
BPU22NF
TEMIC
IN
VBIAS
FILT
MODE
C2
10nF
8
VCC (5V)
LT1328
FILT LO
VCC
6
C1
330pF
C4
0.1µF
GND
HIGH – SIR
LOW – FIR
AND 4PPM
7
+
C5
10µF
DATA
TTL DATA OUT
Figure 48. LT1328 IrDA Receiver—Typical Application
Q4
2N7002
Q3
2N7002
RD3
10k
DRIVER
1328_02.eps
Figure 50. IrDA Transmitter
IrDA FIR
The second fastest tier of the IrDA standard addresses
576kbps and 1.152Mbps data rates, with pulse widths of
1/4 of the bit interval for zero and no pulse for one. The
1.152Mbps rate, for example, uses a pulse width of 217ns;
the total bit time is 870ns. Light levels are 100mW/sr to
500mW/sr over the 1cm to 1 meter range. A photo of a
transmitted input and LT1328 output is shown in Figure
51. The LT1328 output pulse width will be less than 800ns
wide over all of the above conditions at 1.152Mbps. Pin 7
should be held low for these data rates and above.
4ppm
The last IrDA encoding method is for 4Mbps and uses
pulse position modulation, thus its name: 4ppm. Two bits
are encoded by the location of a 125ns wide pulse at one
of the four positions within a 500ns interval (2 bits •
1/500ns = 4Mbps). Range and input levels are the same as
for 1.152Mbps. Figure 52 shows the LT1328 reproduction
of this modulation.
TRANSMITTER
INPUT
TRANSMITTER
INPUT
LT1328 OUTPUT
LT1328 OUTPUT
2µs/DIV
Figure 49. IrDA 115kbps Modulation
AN87-34
RD1
100Ω
TRANSMIT
INPUT
200ns/DIV
Figure 51. IrDA 1.152Mbps Modulation
Application Note 87
BIAS
TRANSMITTER
INPUT
RFB
PHOTODIODE
IN 1
8 VBIAS
D1
PREAMP
C3
RIN
LT1328 OUTPUT
+
RGM
–
200ns/DIV
Figure 52. IrDA 4ppm Modulation
LT1328 Functional Description
Figure 53 is a block diagram of the LT1328. Photodiode
current from D1 is transformed into a voltage by feedback
resistor RFB. The DC level of the preamp is held at VBIAS by
the servo action of the transconductance amplifier’s gm.
The servo action only suppresses frequencies below the
Rgm/CFILT pole. This highpass filtering attenuates interfering signals, such as sunlight or incandescent or fluorescent
lamps, and is selectable at pin 7 for low or high data rates.
For high data rates, pin 7 should be held low. The highpass
filter breakpoint is set by the capacitor C1 at f = 25/(2π •
Rgm • C), where Rgm = 60k. The 330pF capacitor (C1) sets
a 200kHz corner frequency and is used for data rates
above 115kbps. For low data rates (115kbps and below),
the capacitance at pin 2 is increased by taking pin 7 to a
TTL high. This switches C2 in parallel with C1, lowering the
highpass filter breakpoint. A 10nF cap (C2) produces a
6.6kHz corner. Signals processed by the preamp/gm
amplifier combination cause the comparator output to
swing low.
gm CELL
FILTER 2
C1
330pF
6
3
FILTER LO
GND
7
MODE
C2
10nF
4
VCC
–
5 DATA
OUT
+
COMPARATOR
Figure 53. LT1328 Block Diagram
Conclusion
In summary, the LT1328 can be used to build a low cost
receiver compatible with IrDA standards. Its ease of use
and flexibility also allow it to provide solutions to numerous other photodiode receiver applications. The tiny MSOP
package saves on PC board area.
AN87-35
Application Note 87
LTC1387 SINGLE 5V RS232/RS485 MULTIPROTOCOL
TRANSCEIVER
by Y.K. Sim
INTERFACE
LTC1387
RS232
A
A
CONTROLLER
RA
RS485
120Ω
RA
Introduction
RS232
B
B
The LTC1387 is a single 5V supply, logic-configurable,
single-port RS232 or RS485 transceiver. The LTC1387
offers a flexible combination of two RS232 drivers, two
RS232 receivers, an RS485 driver, an RS485 receiver and
an onboard charge pump to generate boosted voltages for
true RS232 levels from a single 5V supply. The RS232
transceivers and RS485 transceiver are designed to share
the same port I/O pins for both single-ended and differential signal communication modes. The RS232 transceiver
supports both RS232 and EIA562 standards, whereas the
RS485 transceiver supports both RS485 and RS422
standards. Both half-duplex and full-duplex communication are supported.
RB
RB
RX
RS485
Y
DY
DY
Z
DZ
5V
DZ/SLEW
DX1
VCC
ON
**TX2A-5V
(DPST)
RXEN
7.5k
=
*FMMT619
* ZETEX
** AROMAT
RXEN
DXEN
DXEN
485/232
MODE
(516) 543-7100
(908) 464-3550
1387_02.eps
RS232
MODE
RXEN = 1
DXEN = 0
MODE = 0
RS485
TRANSMIT MODE
RXEN = 0
DXEN = 1
MODE = 1
RS485
RECEIVE MODE
RXEN = 1
DXEN = 0
MODE = 1
SHUTDOWN
MODE
RXEN = 0
DXEN = 0
MODE = X
Figure 55. Full-Duplex RS232, Half-Duplex RS485
INTERFACE
LTC1387
RS232
A
A
RS485
CONTROLLER
INTERFACE
LTC1387
RS232
RXD
RA
A
120Ω
A
RS485
B
B
Y
RB
RA
RS485
RB
B
B
RS232
DY
Y
DZ
DZ/SLEW
Y
RB
RS485
DY
Z
Z
ON
RXEN
DXEN
485/232
RB
DY
DX1
VCC
RX1
RS485
120Ω
DY
Z
RA
120Ω
RA
RS485
CONTROLLER
DZ
DZ/SLEW
DX1
VCC
ON
RXEN
RXEN
DXEN
DXEN
MODE
485/232
1387_01.eps
RS232
TRANSMIT MODE
RXEN = 0
DXEN = 1
MODE = 0
RS232
RECEIVE MODE
RXEN = 1
DXEN = 0
MODE = 0
RS485
TRANSMIT MODE
RXEN = 0
DXEN = 1
MODE = 1
RS485
RECEIVE MODE
RXEN = 1
DXEN = 0
MODE = 1
SHUTDOWN
MODE
RXEN = 0
DXEN = 0
MODE = X
Figure 54. Half-Duplex RS232, Half-Duplex RS485
AN87-36
RXEN
DXEN
MODE
1387_03.eps
RS232 MODE
RXEN = 1
DXEN = 1
MODE = 0
RS485 MODE
RXEN = 1
DXEN = 1
MODE = 1
SHUTDOWN MODE
RXEN = 0
DXEN = 0
MODE = X
Figure 56. Full-Duplex RS232 (1-Channel), Full-Duplex RS422
Application Note 87
A logic input selects between RS485 and RS232 modes.
Three additional control inputs allow the LTC1387 to be
reconfigured easily via software to adapt to various communication needs, including a one-signal line RS232 I/O
mode (see function tables in figures). Four examples of
interface port connections are shown in Figures 54–57.
A SLEW input pin, active in RS485 mode, changes the
driver transition between normal and slow slew-rate modes.
In normal RS485 slew mode, the twisted pair cable must
be terminated at both ends to minimized signal reflection.
In slow-slew mode, the maximum signal bandwidth is
reduced, minimizing EMI and signal reflection problems.
Slow-slew-rate systems can often use improperly terminated or even unterminated cables with acceptable results.
If cable termination is required, external termination resistors can be connected through switches or relays.
The LTC1387 features micropower shutdown mode,
loopback mode for self-test, high data rates (120kbaud for
RS232 and 5Mbaud for RS485) and 7kV ESD protection at
the driver outputs and receiver inputs.
INTERFACE
RS232
LTC1387
RXD
A
A
CONTROLLER
RA
RS485
120Ω
RA
RX1
RS232
CTS
B
B
RB
RB
RX2
RS485
RS232
Y
TXD
Y
DY
RS485
120Ω
DY
DX1
RS232
Z
RTS
Z
RS485
DZ
DZ/SLEW
DX2/SLEW
ON
ON
RXEN
RXEN
DXEN
DXEN
485/232
MODE
TERMINATE
1387_04.eps
RS232 MODE
ON = 1
RXEN = 1
DXEN = 1
MODE = 0
RS485 MODE
ON= 1
RXEN = 1
DXEN = 1
MODE = 1
SHUTDOWN MODE
ON = 0
RXEN = 0
DXEN = 0
MODE = X
Figure 57. Full-Duplex RS232 (2-Channel), Full-Duplex RS485
with Slew and Termination Control
A 10MB/s MULTIPLE-PROTOCOL CHIP SET SUPPORTS
NET1 AND NET2 STANDARDS
by David Soo
Introduction
Typical Application
Like the LTC1343 software-selectable multiprotocol transceiver, introduced in the August, 1996 issue of Linear
Technology , the LTC1543/LTC1544/LTC1344A chip set
creates a complete software-selectable serial interface
using an inexpensive DB-25 connector. The main difference between these parts is the division of functions: the
LTC1343 can be configured as a data/clock chip or as a
control-signal chip using the CTRL/CLK pin, whereas the
LTC1543 is a dedicated data/clock chip and the LTC1544
is a control-signal chip. The chip set supports the V.28
(RS232), V.35, V.36, RS449, EIA-530, EIA-530A and X.21
protocols in either DTE or DCE mode.
Figure 58 shows a typical application using the LTC1543,
LTC1544 and LTC1344A. By just mapping the chip pins to
the connector, the design of the interface port is complete.
The figure shows a DCE mode connection to a DB-25
connector.
The LTC1543 contains three drivers and three receivers,
whereas the LTC1544 contains four drivers and four
receivers. The LTC1344A contains six switchable resistive terminators that are connected only to the high speed
clock and data signals. When the interface protocol is
changed via the mode selection pins, M2, M1 and M0, the
AN87-37
Application Note 87
Cable-Selectable Multiprotocol Interface
Table 4. Mode-Pin Functions
LTC1543/LTC1544
Mode Name
M2
M1
M0
Not Used
0
0
0
EIA-530A
0
0
1
EIA-530
0
1
0
X.21
0
1
1
V.35
1
0
0
RS449/V.36
1
0
1
RS232/V.28
1
1
0
No Cable
1
1
1
drivers, receivers and line terminators are placed in their
proper configuration. The mode pin functions are summarized in Table 4. There are internal 50µA pull-up current
sources on the mode select pins, DCE/DTE and the INVERT
pins.
DTE vs DCE Operation
The LTC1543/LTC1544/LTC1344A chip set can be
configured for either DTE or DCE operation in one of two
ways. The first way is when the chip set is a dedicated DTE
or DCE port with a connector of appropriate gender. The
second way is when the port has one connector that can
be configured for DTE or DCE operation by rerouting the
signals to the chip set using a dedicated DTE or DCE cable.
Figure 58 is an example of a dedicated DCE port using a
female DB-25 connector. The complement to this port is
the DTE-only port using a male DB-25 connector, as
shown in Figure␣ 59.
If the port must accommodate both DTE and DCE modes,
the mapping of the drivers and receivers to connector pins
must change accordingly. For example, in Figure 58,
driver 1 in the LTC1543 is connected to pin 3 and pin 16
of the DB-25 connector. In DTE mode, as shown in Figure
59, driver 1 is mapped to pins 2 and 14 of the DB-25
connector. A port that can be configured for either DTE or
DCE operation is shown in Figure 60. This configuration
requires separate cables for proper signal routing.
AN87-38
The interface protocol may be selected by simply plugging
the appropriate interface cable into the connector. A cableselectable multiprotocol DTE/DCE interface is shown in
Figure 61. The mode pins are routed to the connector and
are left unconnected (1) or wired to ground (0) in the cable.
The internal pull-up current sources ensure a binary 1
when a pin is left unconnected and also ensure that the
LTC1543/LTC1544/LTC1344A enter the no-cable mode
when the cable is removed. In the no-cable mode, the
LTC1543/LTC1544 power supply current drops to less
than 200µA and all of the LTC1543/LTC1544 driver outputs will be forced into the high impedance state.
Adding Optional Test Signal
In some cases, the optional test signals local loopback
(LL), remote loopback (RL) and test mode (TM) are
required but there are not enough drivers and receivers
available in the LTC1543/LTC1544 to handle these extra
signals. The solution is to combine the LTC1544 with the
LTC1343. By using the LTC1343 to handle the clock and
data signals, the chip set gains one extra single-ended
driver/receiver pair. This configuration is shown in Figure
62.
Compliance Testing
A European standard EN 45001 test report is available for
the LTC1543/LTC1544/LTC1344A chip set. The report
provides documentation on the compliance of the chip set
to Layer 1 of the NET1 and NET2 standard. A copy of this
test report is available from LTC or from Detecon, Inc. at
1175 Old Highway 8, St. Paul, MN 55112.
Conclusion
In the world of network equipment, the product differentiation is mostly in the software and not in the serial
interface. The LTC1543, LTC1544 and LTC1344A provide
a simple yet comprehensive solution to standards compliance for multiple-protocol serial interface.
Application Note 87
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
RXD
6
RXC
D2
7
R2
10
TXD
11
12
13
NC
C10
1µF
R1
9
SCTE
14
2
C4
3.3µF
VEE
C12
1µF
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
VCC
3
23
16
22
17
21
9
R3
20
15
19
12
18
24
17
11
16
2
15
14
M0
7
M1
M2
1
DCE/DTE
1
VCC
2
VDD
3
CTS
VEE
GND
D1
4
DSR
D2
5
LTC1544
R1
7
DTR
R2
8
RTS
R3
10
LL
R4
9
11
12
13
NC
14
RXC A (115)
RXC B
TXC A (114)
TXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
SGND (102)
SHIELD (101)
28
C11
1µF
27
26
5
25
13
24
6
23
22
CTS A (106)
CTS B
DSR A (107)
DSR B
D3
6
DCD
RXD B
DB-25 FEMALE
CONNECTOR
VCC
C9
1µF
RXD A (104)
D3
8
TXC
C2
1µF
24
D1
21
M0
CHARGE
PUMP
2
LATCH
M1
27
26
VCC
M2
1
C13
1µF
DCE/DTE
C1
1µF
28
+
C3
1µF
3
22
8
21
10
20
20
19
23
18
4
17
19
16
18
DCD A (109)
DCD B
DTR A (108)
DTR B
RTS A (105)
RTS B
LL A (141)
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
M2
M1
M0
Figure 58. Controller-Selectable DCE Port with DB-25 Connector
AN87-39
Application Note 87
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
TXD
D1
6
SCTE
D2
7
11
12
13
14
C9
1µF
RTS
DTR
R2
10
RXD
C10
1µF
R1
9
RXC
R3
CTS
LL
14
22
24
21
11
20
15
19
12
18
17
17
9
16
3
15
16
1
VEE
GND
D1
D2
R1
7
R2
8
R3
10
R4
9
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SG
SHIELD
DB-25 MALE
CONNECTOR
28
C11
1µF
27
26
4
25
19
24
20
23
23
22
8
21
10
20
6
19
22
18
5
17
13
16
18
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
M2
M1
M0
Figure 59. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
AN87-40
TXD A (103)
RTS A (105)
RTS B
DTR A (108)
DTR B
D3
6
14
2
23
DCE/DTE
4
13
24
M2
3
12
16 15 18 17 19 20 22 23 24 1
7
VCC
1
VCC
2
VDD
11
9 10
M1
LTC1544
DSR
5 4 6 7
M0
5
DCD
VEE
C12
1µF
D3
8
TXC
2
C4
3.3µF
M0
CHARGE
PUMP
2
21
C2
1µF
M1
27
26
LATCH
M2
1
VCC
DCE/DTE
C1
1µF
28
+
C3
1µF
3
C13
1µF
DCD A (109)
DCD B
DSR A (107)
DSR B
CTS A (106)
CTS B
LL A (141)
Application Note 87
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
DTE_TXD/DCE_RXD
D1
6
DTE_SCTE/DCE_RXC
D2
7
S
R1
S
9
DTE_RXC/DCE_SCTE
R2
10
DTE_RXD/DCE_TXD
11
12
C2
1µF
2
C4
3.3µF
VEE
C12
1µF
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
24
2
23
14
22
24
21
11
R3
20
15
19
12
18
17
17
9
16
3
15
16
M0
7
M1
13
M2
14
DCE/DTE
C10
1µF
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
C9
1µF
1
1
VCC
2
VDD
3
VEE
GND
D1
4
D2
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
6
R1
7
R2
8
R3
10
R4
9
11
12
13
14
TXD B
RXD B
SCTE A
RXC A
SCTE B
RXC B
TXC A
TXC A
TXC B
TXC B
RXC A
SCTE A
RXC B
SCTE B
RXD A
TXD A
RXD B
TXD B
SG
SHIELD
28
C11
1µF
27
26
4
25
19
24
20
23
23
RTS A
CTS A
RTS B
CTS B
DTR A
DSR A
DTR B
DSR B
DCD A
DCD A
D3
LTC1544
DTE_DSR/DCE_DTR
DCE
RXD A
DB-25
CONNECTOR
VCC
5
DTE_DCD/DCE_DCD
DTE
TXD A
D3
8
DTE_TXC/DCE_TXC
21
M0
CHARGE
PUMP
2
LATCH
M1
27
26
VCC
M2
1
C13
1µF
DCE/DTE
C1
1µF
28
+
C3
1µF
3
22
8
21
10
20
6
19
22
18
5
17
13
16
18
DCD B
DCD B
DSR A
DTR A
DSR B
DTR B
CTS A
RTS A
CTS B
RTS B
LL A
LL A
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
DCE/DTE
M2
M1
M0
Figure 60. Controller-Selectable DTE/DCE Port with DB-25 Connector
AN87-41
Application Note 87
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
25
C5
1µF
LTC1543
5
DTE_TXD/DCE_RXD
D2
7
R1
9
DTE_RXC/DCE_SCTE
R2
10
DTE_RXD/DCE_TXD
11
12
NC
13
14
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
VCC
2
23
14
22
24
21
11
DTE
DCE
TXD A
RXD A
TXD B
RXD B
SCTE A
RXC A
SCTE B
RXC B
TXC A
TXC A
TXC B
TXC B
RXC A
SCTE A
RXC B
SCTE B
RXD A
TXD A
RXD B
TXD B
D3
8
DTE_TXC/DCE_TXC
VEE
C12
1µF
24
D1
6
DTE_SCTE/DCE_RXC
2
C4
3.3µF
M0
4
21
C2
1µF
M1
CHARGE
PUMP
2
LATCH
M2
27
26
VCC
DCE/DTE
C1
1µF
28
1
C13
1µF
+
C3
1µF
3
R3
20
15
19
12
18
17
17
9
16
3
15
16
M0
7
M1
M2
1
DCE/DTE
SG
SHIELD
DB-25
CONNECTOR
C10
1µF
C9
1µF
VCC
1
VCC
2
VDD
VEE
GND
25
DCE/DTE
21
M1
18
M0
4
RTS A
19
RTS B
20
DTR A
23
DTR B
28
C11
1µF
27
26
3
DTE_RTS/DCE_CTS
D1
24
4
DTE_DTR/DCE_DSR
D2
5
LTC1544
R1
7
DTE_DSR/DCE_DTR
R2
8
DTE_CTS/DCE_RTS
R3
10
R4
9
11
12
NC
13
14
23
22
8
21
10
20
6
19
22
18
5
17
13
16
CABLE WIRING FOR MODE SELECTION
PIN 18
MODE
PIN 21
PIN 7
V.35
PIN 7
NC
RS449, V.36
PIN 7
PIN 7
RS232
NC
D4
M0
M1
M2
DCE/DTE INVERT
15
CABLE WIRING FOR
DTE/DCE SELECTION
MODE
PIN 25
DTE
PIN 7
DCE
NC
NC
Figure 61. Cable-Selectable Multiprotocol DTE/DCE Port
AN87-42
CTS A
CTS B
DSR A
DSR B
D3
6
DTE_DCD/DCE_DCD
25
DCD A
DCD A
DCD B
DCD B
DSR A
DTR A
DSR B
DTR B
CTS A
RTS A
CTS B
RTS B
Application Note 87
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
44
C5
1µF
D1
D2
7
DTE_SCTE/DCE_RXC
5 4 6 7
9 10
M0
41
VEE
C12
1µF
16 15 18 17 19 20 22 23 24 1
LTC1343
6
DTE_TXD/DCE_RXD
2
C4
3.3µF
8
5
DTE_LL/DCE_TM
21
C2
1µF
43
42
CHARGE
PUMP
4
3
LATCH
M1
C1
1µF
VCC
M2
2
+
C3
1µF
C13
1µF
DCE/DTE
1
D3
39
18
38
2
37
14
36
24
35
11
DTE
DCE
LL A
TM A
TXD A
RXD A
TXD B
RXD B
SCTE A
RXC A
SCTE B
RXC B
TXC A
TXC A
34
9
10
12
13
DTE_TXC/DCE_TXC
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
R3
16
DTE_TM/DCE_LL
20
22
11
25
R1
100k
33
D4
R4
CTRL
DCE
LATCH
M2
INVERT
M1
423SET
M0
GND
EC
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
LB
DTE_CTS/DCE_RTS
DTE_RL/DCE_RL
30
17
29
9
28
3
27
16
26
25
21
7
19
1
18
TXC B
TXC B
RXC A
SCTE A
RXC B
SCTE B
RXD A
TXD A
RXD B
TXD B
TM A
LL A
SG
SHIELD
17
24
DB-25
CONNECTOR
C9
1µF
3
VEE
GND
D1
4
D2
6
R1
7
R2
8
R3
10
R4
9
11
12
13
14
28
C11
1µF
27
26
4
25
19
24
20
23
23
RTS A
CTS A
RTS B
CTS B
DTR A
DSR A
DTR B
DSR B
DCD A
DCD A
D3
LTC1544
DTE_DSR/DCE_DTR
12
23
VCC
1
VCC
2
VDD
5
DTE_DCD/DCE_DCD
15
31
VCC
40
LB
C10
1µF
32
22
8
21
10
20
6
19
22
18
5
17
13
16
21
DCD B
DCD B
DSR A
DTR A
DSR B
DTR B
CTS A
RTS A
CTS B
RTS B
RL A
RL A
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
DCE/DTE
M2
M1
M0
Figure 62. Controller-Selectable Multiprotocol DTE/DCE Port with RLL, LL, TM and DB-25 Connector
AN87-43
Application Note 87
NET1 AND NET2 SERIAL INTERFACE CHIP SET
SUPPORTS TEST MODE
by David Soo
LTC1545, the optional circuits TM (Test Mode), RL (Remote
Loopback) and LL (Local Loopback) can now be
implemented.
Some serial networks use a test mode to exercise all of the
circuits in the interface. The network is divided into local
and remote data terminal equipment (DTE) and datacircuit-terminating equipment (DCE), as shown in Figure
63. Once the network is placed in a test mode, the local DTE
will transmit on the driver circuits and expect to receive the
same signals back from either a local or remote DCE. These
tests are called local or remote loopback.
The LTC1543/LTC1544/LTC1344A chip set has taken the
integrated approach to multiple protocol. By using this
chip set, the Net1 and Net2 design work is done. The
LTC1545 extends the family by offering test mode capability. By replacing the 6-circuit LTC1544 with the 9-circuit
LOCAL
DTE
LOCAL
DCE
LL
REMOTE RL
DCE
Figure 63. Serial Network
AN87-44
REMOTE
DTE
Figure 64 shows a typical application using the LTC1543,
LTC1545 and LTC1344A. By just mapping the chip pins to
the connector, the design of the interface port is complete.
The chip set supports the V.28, V.35, V.36, RS449, EIA530, EIA-530A or X.21 protocols in either DTE or DCE
mode. Shown here is a DCE mode connection to a DB-25
connector. The mode-select pins, M0, M1 and M2, are
used to select the interface protocol, as summarized in
Table 5.
Table 5. Mode-Pin Functions
LTC1543/LTC1544
Mode Name
M2
M1
M0
Not Used
0
0
0
EIA-530A
0
0
1
EIA-530
0
1
0
X.21
0
1
1
V.35
1
0
0
RS449/V.36
1
0
1
RS232/V.28
1
1
0
No Cable
1
1
1
Application Note 87
C6
C7
C8
100pF 100pF 100pF
Just a
marker
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
RXD
D2
7
R2
10
TXD
11
12
13
NC
C10
1µF
R1
9
SCTE
C9
1µF
14
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
VCC
3
23
16
22
17
21
9
R3
20
15
19
12
18
24
17
11
16
2
15
14
M0
7
M1
M2
1
DCE/DTE
1
VCC
2
VDD
3
VEE
GND
D1
4
DSR
D2
5
6
R1
7
DTR
R2
8
RTS
R3
10
LL
R4
9
11
12
13
NC
14
RXC A (115)
RXC B
TXC A (114)
TXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
SGND (102)
SHIELD (101)
28
C11
1µF
27
26
5
25
13
24
6
23
22
CTS A (106)
CTS B
DSR A (107)
DSR B
D3
LTC1544
DCD
RXD B
DB-25 FEMALE
CONNECTOR
VCC
CTS
RXD A (104)
D3
8
TXC
VEE
C12
1µF
24
D1
6
RXC
2
C4
3.3µF
M0
CHARGE
PUMP
2
21
C2
1µF
M1
27
26
LATCH
VCC
M2
1
C13
1µF
DCE/DTE
C1
1µF
28
+
C3
1µF
3
22
8
21
10
20
20
19
23
18
4
17
19
16
18
DCD A (109)
DCD B
DTR A (108)
DTR B
RTS A (105)
RTS B
LL A (141)
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
M2
M1
M0
1544 F23
Figure 64. Typical Application: Controller-Selectable DCE Port with DB-25 Connector
AN87-45
Application Note 87
Operational Amplifiers/Video Amplifiers
conventional amplifier would be limited to a battery voltage between 5V and ground, but the LT1491 can handle
battery voltages as high as 44V. The LT1491 can be shut
down by removing VCC. With VCC removed the input
leakage is less than 0.1nA. No damage to the LT1491 will
result from inserting the 12V battery backward.
LT1490/LT1491 OVER-THE-TOP DUAL AND QUAD
MICROPOWER RAIL-TO-RAIL OP AMPS
by Jim Coelho-Sousae
Introduction
The LT1490 is Linear Technology’s lowest power, lowest
cost and smallest dual rail-to-rail input and output operational amplifier. The ability to operate with its inputs above
VCC, its high performance-to-price ratio and its availability
in the MSOP package, sets the LT1490 apart from other
amplifiers.
An Over-the-Top Application
The battery current monitor circuit shown in Figure 65
demonstrates the LT1491’s ability to operate with its
inputs above the positive supply rail. In this application, a
When the battery is charging, Amp B senses the voltage
drop across RS. The output of Amp B causes QB to drain
sufficient current through RB to balance the inputs of Amp
B. Likewise, Amp A and QA form a closed loop when the
battery is discharging. The current through QA or QB is
proportional to the current in RS; this current flows into
RG, which converts it back to a voltage. Amp D buffers and
amplifies the voltage across RG. Amp C compares the
output of Amp A and Amp B to determine the polarity of
the current through RS. The scale factor for VOUT with S1
open is 1V/A. With S1 closed the scale factor is 1V/
100mA, and current as low as 5mA can be measured.
RS
0.2Ω
CHARGER
VOLTAGE
+
1N4001
VBATTERY = 12V
RA
2k
RA'
2k
QA
2N3904
+
1/4
LT1491
A
–
1/4
LT1491
C
–
LOGIC
+
RB
2k
RL
RB'
2k
+
1/4
LT1491
B
VSUPPLY = 5V, 0V
QB
2N3904
–
+
1/4
LT1491
D
RG
10k
–
90.9k
LOGIC HIGH (5V) = CHARGING
LOGIC LOW (0V) = DISCHARGING
IBATTERY =
(VOUT)
(RS) (RG/RA) GAIN
VOUT
=
VOUT
10k
AMPS
GAIN
NOTE: RA = RB
S1
S1 = OPEN, GAIN = 1
S1 = CLOSED, GAIN = 10
Figure 65. LT1491 Battery Current Monitor—an “Over-The-Top” Application
AN87-46
Application Note 87
THE LT1210: A 1-AMPERE, 35MHz
CURRENT FEEDBACK AMPLIFIER
by William Jett and Mitchell Lee
to be switched into a high impedance, low current mode,
reducing dissipation when the device is not in use. The
LT1210 is available in the 7-pin TO-220 package, the 7-pin
DD surface mount package and the 16-pin SO-16 surface
mount package.
Introduction
The LT1210 current feedback amplifier extends Linear
Technology’s high speed driver solutions to the 1 ampere
level. The device combines a 35MHz bandwidth with a
guaranteed 1A output current, operation with ±5V to ±15V
supplies and optional compensation for capacitive loads,
making it well suited for driving low impedance loads.
Short circuit protection and thermal shutdown ensure the
device’s ruggedness. A shutdown feature allows the device
Twisted Pair Driver
Figure 66 shows a transformer-coupled application of the
LT1210 driving a 100Ω twisted pair. This surge impedance is typical of PVC-insulated, 24 gauge, telephonegrade twisted pair wiring. The 1:3 transformer ratio allows
just over 1W to reach the twisted pair at full output.
Resistor RT acts as a primary side back-termination. The
15V
+
4.7µF*
INPUT
100nF
RT
11Ω, 2.5W
+
LT1210
T1
–
1
+
4.7µF*
RL = 100Ω,
2.5W
3
100nF
845Ω
–15V
*TANTALUM
T1 = MIDCOM 671-7783 OR EQUIVALENT
274Ω
Figure 66. Twisted Pair Is Easily Driven for Applications Such as ADSL.
Voltage Gain is About 12. 5VP–P Input Corresponds to Full Output
15V
INPUT
5.6Ω
2.5W
+
LT1210
–
680Ω
T1
220Ω
–
1
RL = 100Ω,
5W
3
910Ω
LT1210
+
5.6Ω
2.5W
T1 = MIDCOM 671-7783 OR EQUIVALENT
–15V
Figure 67. In a Bridge Configuration, the LT1210 Can Deliver Almost
5W to a Twisted Pair (and Another 5W to the Back Termination)
AN87-47
Application Note 87
RT = 50Ω
2.5W
T1
T1
RL = 50Ω, 4W
15V
INPUT
5VPP
+
1µF
INPUT
5VPP
LT1210
–
RL = 50Ω
2.5W
15V
+
330nF
LT1210
10nF
–
10nF
–15V
680Ω
–15V
680Ω
220Ω
220Ω
T1 = COILTRONICS VERSA-PAC CTX-01-13033-X2
Figure 68. Matched to a 50Ω Load with a Balun-Mode
Transformer, this Circuit Delivers a Measured 35.6dBm (almost
4W). Full-Power Band Limits are 15kHz to Slightly Over 10MHz
overall frequency response is flat to within 1dB from
500Hz to 2MHz. Distortion products at 1MHz are below
–70dBc at a total output power of 560mW (load plus
termination), rising to –56dBc at 2.25W.
On a ±15V supply, a maximum output power of 5W is
available when a 10Ω load is presented to the LT1210.
With the transformer shown in Figure 66, a total load
impedance of approximately 22Ω limits the output to
2.25W. Bridging allows nearly maximum output power to
be delivered into standard 1:3 data communications transformers. Figure 67 shows a bridged application with two
LT1210s, delivering approximately 9W maximum into the
load and termination.
At first glance the resistor values would suggest a gain
imbalance between the inverting and noninverting sides of
the bridge. On close inspection, however, it is apparent
that both sides operate at a closed loop gain of 4 relative
to the input signal. This ensures symmetric swing and
maximum undistorted output.
T1 = COILTRONICS VERSA-PAC CTX-01-13033-X2
Figure 69. Wide Bandwidth can be Obtained with Even Higher
Impedance Transformations. Here, a 1:3 Step-Up Matches 100Ω
and Develops Nearly 4.5W. A Measured +33dBm Reaches the
50Ω Load. Full-Power Band Limits Are 80kHz to 18MHz
Suitable off-the-shelf components are available, such as
the Coiltronics Versa-Pac™ series. These are hexafilar
wound and give power bandwidths in excess of 10MHz.
One disadvantage is that using a limited number of 1:1
windings makes it impossible to exactly transform 50Ω to
the optimum 10Ω load. Nevertheless, there are several
useful connections.
In Figure 68 the windings are configured for a 2:4 step-up,
reflecting 12.5Ω into the LT1210. The circuit exhibits 18dB
gain and drives 50Ω to nearly +36dBm. The large-signal,
low frequency response is limited by the magnetizing
inductance of the transformer to about 15kHz. The high
frequency response is limited to 10MHz by the stack of four
secondary windings.
Matching 50Ω Systems
Reconfiguring the transformer windings allows double
termination at full power (Figure 69). Here the transformer
reflects 11.1Ω and the amplifier delivers over +33dBm to
the load. Paralleled input windings limit the low frequency
response to 80kHz, but fewer series secondary windings
extend the high frequency corner to 18MHz.
Few practical systems exhibit a 10Ω impedance, so a
matching transformer is necessary for applications driving other loads, such as 50Ω. Multifilar winding techniques exhibit the best high frequency characteristics.
The coupling capacitor shown in these examples is added
to block current flow through the transformer primary,
arising from amplifier offsets. The capacitor value is based
on setting XC equal to the reflected load impedance at the
AN87-48
Application Note 87
26
15V
23
+
20
LT1210
–
17
T1
10nF
RL = 50Ω, 9W
680Ω
GAIN (dB)
INPUT
5VP–P
14
11
8
5
100nF
2
220Ω
–1
–
–4
0.01
910Ω
0.1
1.0
10.0
FREQUENCY (MHz)
100
LT1210
+
Figure 71. Frequency Response of Figure 70's Circuit
10nF
–15V
T1 = CTX-01-13033-X2 VERSA-PAC
Figure 70. In this Bridge Amplifier, the LT1210 Delivers
+39.5dBm (9W) to a 50Ω Load. Power Band Limits Range from
40kHz to 14.5MHz. The Sixth, Otherwise-Unused Winding is
Connected in Parallel with One Secondary Winding to Avoid
Parasitic Effects Arising from a Floating Winding.
frequency where XL of the primary is also equal to the
reflected load. This isolates the amplifier from a low
impedance short at frequencies below transformer cutoff.
In applications where a termination resistor is positioned
between the LT1210 amplifier and the transformer, no
coupling capacitor is necessary. Note that a low frequency
signal, well below the transformer’s cutoff frequency,
could result in high dissipation in the termination resistor.
Another useful connection for the Versa-Pac transformer
is shown in Figure 70. A 2:3 transformation presents
11.1Ω to each LT1210 in a bridge, delivering a whopping
9W into 50Ω. In this circuit the lower frequency cutoff was
limited by the choice of coupling capacitor to approximately 40kHz (the transformer is capable of 15kHz). The
frequency response is shown in Figure 71.
Conclusion
The LT1210 combines high output current with a high slew
rate to form an effective solution for driving low impedance
loads. Power levels of up to 5W can be supplied to a load
at frequencies ranging from DC to beyond 10MHz.
AN87-49
Application Note 87
THE LT1207: AN ELEGANT DUAL 60MHZ, 250mA
CURRENT FEEDBACK AMPLIFIER
by LTC Applications Staff
Introduction
The LT1207 is a dual version of Linear Technology’s
LT1206 current feedback amplifier. Each amplifier has
60MHz bandwidth, guaranteed 250mA output current,
operates on ±5V to ±15V supply voltages and offers
optional external compensation for driving capacitive loads.
These features and capabilities combine to make it well
suited for such difficult applications as driving cable loads,
wide-bandwidth video and high speed digital
communication.
LT1088 Differential Front End
Using thermal conversion, the LT1088 wideband RMS/DC
converter is an effective solution for applications such as
RMS voltmeters, wideband AGC, RF leveling loops and
high frequency noise measurements. Its thermal conversion method achieves vastly wider bandwidth than any
other approach. It can handle input signals that have a
300MHz bandwidth and a crest factor of at least 40:1. The
thermal technique employed relies on first principles: a
wave form’s RMS value is defined as its heating value in a
load. Another characteristic of the LT1088 is its low
impedance inputs (50Ω and 250Ω), common to thermal
converters. Though this low impedance represents a difficult load to most drive circuits, the LT1207 can handle it
with ease.
Featuring high input impedance and overload protection,
the differential input, wideband thermal RMS/DC converter in Figure 72 performs true RMS/DC conversion over
a 0Hz to 10MHz bandwidth with less than 1% error,
independent of input-signal wave shape. The circuit consists of a wideband input amplifier, RMS/DC converter and
overload protection.1 The LT1207 provides high input
impedance, gain and output current capability necessary
to drive the LT1088’s input heater. The 5k/24pF network
across the LT1207’s 180Ω gain-set resistor is used to
adjust a slight peaking characteristic at high frequencies,
ensuring 1% flatness at 10MHz. The converter uses
matched pairs of heaters and diodes and a control ampli-
AN87-50
fier. R1 produces heat when the LT1207 drives it differentially. This heat lowers D1’s voltage. Differentially connected A3 responds by driving R2, heating D2 and closing
the loop. A3’s DC output directly relates to the input
signal’s RMS value, regardless of input frequency or wave
shape. A4’s gain trim compensates residual LT1088 mismatches. The RC network around A3 frequency compensates the loop, ensuring good settling time.
The LT1088 can suffer damage if the 250Ω input is driven
beyond 9VRMS at 100% duty cycle. An easy remedy to this
possibility is to reduce the driver supply voltage. This,
however, sacrifices crest factor. Instead, a means of
overload protection is included. The LT1018 monitors
D1’s anode voltage. Should this voltage become abnormally low, A5’s output goes low and pulls A6’s input low.
This causes A6’s output to go high, shutting down the
LT1207 and eliminating the overload condition. The RC
network on A6’s input delays the LT1207’s reactivation. If
the overload condition remains, shutdown is reinstated.
This oscillatory action continues, protecting the LT1088
until the overload is corrected. The RMS/DC circuit’s 1%
error bandwidth and CMRR performance are shown in
Figures 73 and 74, respectively.
CCD Clock Driver
Charge-coupled-devices (CCDs) are used in many imaging applications, such as surveillance, hand-held and
desktop computer video cameras, and document scanners. Using a “bucket-brigade,” CCDs require a precise
multiphase clock signal to initiate the transfer of lightgenerated pixel charge from one charge reservoir to the
next. Noise, ringing or overshoot on the clock signal must
be avoided, since they introduce errors into the CCD
output signal. These errors cause aberrations and perturbations in a displayed or printed image.
Two challenges surface in the effort to avoid these error
sources when driving a CCD’s input. First, CCDs have an
input capacitance that varies over a range of 100pF to
2000pF and varies directly with the number of sensing
elements (pixels). This presents a high capacitive load to
the clock-drive circuitry. Second, CCDs typically require a
clock signal whose magnitude is greater than the output
capabilities of 5V interfaces and control circuitry. An
VIN
+
10µF
0.1µF
+
–5V
–
10µF
+
10µF
8,9
A2
12
1/2
7
6 LT1207
+
11
0.1µF
5
5V
–5V
4
15
0.1µF
1,16
0.1µF
+
A1
1/2
2 LT1207
–
14
3
5V
10µF
806Ω
180Ω
806Ω
5k
10MHz
TRIM
24pF
–15V
0.1µF
14
7
3
1
2
3
–
10k
1
LT1004
1.2V
2k
15V
8
A5
1/2
LT1018
+
15V
0.1µF
13
6
1k
1N914
15V
9.09M
3
2
+
+
–15V
4.7k
–15V
A6
1/2
5 LT1018
–
4
6
7
+
1k
–15V
12k
15V
0.1µF
7
Q1
2N2219
9.09M
0.022µF
A4
1/2
6 LT1078
–
4
5
1
0.1µF
3300pF
0.1µF
8
A3
1/2
LT1078
–
15V
10k
FULL-SCALE
TRIM
10k
10
0.1µF
510k
15V
8
R2
D2
250Ω
0.01µF
1k
1k
R1
LT1088
5
2.7k
250Ω
D1
12
2.7k
500Ω
ZERO TRIM
(TRIM AT 1V OUTPUT)
15V
1.5M
10k
10k
VOUT
3k
LT1004
1.2V
1k
Application Note 87
+
Figure 72. Differential Input 10MHz RMS/DC Converter has 1% Accuracy, High Input Impedance and Overload Protection.
AN87-51
Application Note 87
COMMON MODE REJECTION RATIO, VCM = 5VRMS
1.0
A
>>1000:1
1000:1
ERROR (%)
0.5
0
B
–0.5
–1.0
0
2
4
6
8
10
FREQUENCY (MHz)
12
14
Figure 73. Error Plot for the Differential-Input RMS/DC
Converter. Gain Boost at A2 Preserves 1% Accuracy but
Causes Slight Peaking before Roll-Off. Boost Can be Set
for Maximum Bandwidth (A) or Minimum Error (B)
900:1
800:1
700:1
600:1
500:1
1% ERROR
POINT
= 10.2MHz
400:1
300:1
200:1
100:1
0
0
2
4
6
8
10
FREQUENCY (MHz)
12
14
Figure 74. Common Mode Rejection Ratio vs Frequency for the
Differential-Input RMS/DC Converter. Layout, Amplifier
Bandwidth and AC Matching Characteristics Determine the Curve
+
10µF
45pF
20V
0.1µF
1k
1k
SIMULATED
CCD ARRAY LOAD
1k
180pF
3
2
–
14
2
1
1CK
1D
12
13
1Q
5
10µF
500kHz
–10V
6
1k
74HC74
10
11
1Q
3300pF
0.1µF
2CK
2D
2Q
2Q
9
500kHz
510k
8
10µF
45pF
+
3
0.1µF
+
2MHz
13
4
4
10Ω
15
1/2
LT1207
5V
CLK
1,16
+
91pF
20V
0.1µF
1k
1k
180pF
1k
6
1/2
LT1207
91pF
5
8,9
+
–
11
7
10Ω
12
10
0.1µF
3300pF
0.1µF
10µF
+
–10V
1k
510k
Figure 75. The LT1207 Easily Tames the High Capacitance Loads of CCD Clock Inputs without Ringing or Overshoot
AN87-52
Application Note 87
A
A
B
B
Figure 76a. Trace A is the Quadrature Drive Signals. Trace B.
is the Voltage at the Input of the Simulated CCD of Figure 75,
Driven by HC Logic
amplifying filter built around the LT1207 will meet both
challenges.
Controlling clock signal rise and fall times is one way to
avoid ringing or overshoot. This is done by conditioning
the clock signal with a nonringing Gaussian filter. The
circuit shown in Figure 75 uses the LT1207 to filter and
amplify control circuitry clock output signals. To reduce
ringing and overshoot, each amplifier is configured as a
third-order Gaussian lowpass filter with a 1.6MHz cutoff
frequency.
Figures 76a and 76b compare the response of a digital 5V
clock-drive signal and the output of the LT1207, each
driving a 3300pF load. The digital clock circuit has two
Figure 76b. Trace A is the Quadrature Signals. Trace B
Shows the Voltage at the Input of the Simulated CCD of
Figure 75, Driven by the LT1207
major weaknesses that lead to jitter and image distortion.
The CCD’s output is changing during charge transfer,
producing glitches that decay exponentially. Conversely,
the LT1207 circuit's output has a flat top and controlled
rise and fall. If an ADC is used to sample a CCD output, the
conversion will be much more accurate when the LT1207
circuit is used to clock the pixel changes. With the LT1207’s
filter configuration, the output has a controlled rise and fall
time of approximately 300ns. Ringing and overshoot are
absent from the LT1207’s output. Wide bandwidth, high
output current capability and external compensation allow
the LT1207 to easily drive the difficult load of a CCD’s clock
input.
1. Thanks to Jim Williams for this Circuit
AN87-53
Application Note 87
MICROPOWER, DUAL AND QUAD JFET OP AMPS
FEATURE C-LOAD CAPABILITY AND PICOAMPERE
INPUT BIAS CURRENTS
by Alexander Strong
Applications
Figure 77 is a track-and-hold circuit that uses a low cost
optocoupler as a switch. Leakages for these parts are
usually in the nano amp region with 1 to 5 volts across the
output. Since there is less than 2mV across the junctions,
less than 0.5pA leakage can be achieved for both optocouplers. The input signal is buffered by one op amp while
the other buffers the stored voltage; this results in a droop
of 50µV/s with a 10nF cap.
Introduction
The LT1462/LT1464 duals and the LT1463/LT1465 quads
are the first micropower op amps (30µA typical, 40µA
maximum per amp for the LT1462; 140µA typical, 200µA
maximum per amp for the LT1464) to offer both pico
ampere input bias currents (500fA typical) and unity-gain
stability for capacitive loads up to 10nF. The outputs can
swing a 10k load to within 1.5 volts of either supply. Just
like op amps that require an order of magnitude more
supply current, the LT1462/LT1463 and the LT1464/
LT1465 have open loop gains of 600,000 and 1,000,000,
respectively. These unique features, along with a 0.8mV
offset, have not been incorporated into a single monolithic
amplifier before.
V+
1/4
LTC201
A
Figure 78 is a logging photodiode sensor using two
LT1462 duals or an LT1463 quad. The low input bias
current of the LT1462/LT1463 makes it a natural for
amplifying low level signals from high impedance transducers. The 500fA of input bias current contributes only
0.4fA/√Hz of current noise. For example, a 1M input
impedance converts the noise current to a noise voltage of
only 0.4nV/√Hz. Here, a photodiode converts light to a
13
15
4
14
16
C1, 10nF
POLYSTYRENE
5
1 MCT2
V–
V+
5
6
IN
+
–
1/4
LTC201
B
2
4
6
2
7 *R1
1/2
LT1464
1 MCT2
5
3
–
8
1/2
LT1464
+
1
VOUT
4
V–
2
1
2
6
4
0.5pA
= 0.05mV/SEC.
10nF
TOTAL SUPPLY CURRENT = 460µA MAX.
*R1 = 600Ω FOR ±15V SUPPLIES,
R1 = 0Ω FOR ±5V SUPPLIES
TYPICAL DROOP =
3
FUNCTION
MODE IN A IN B
TRACK AND HOLD
TRACK
0
0
HOLD
1
1
POSITIVE PEAK DETECTOR
RESET
0
0
STORE
0
1
NEGATIVE PEAK DETECTOR
RESET
0
0
STORE
1
0
MODE IN A IN B
LTC201 SWITCH IS OPEN FOR LOGIC “1”
Figure 77. Low-Droop Track-and-Hold Circuit/Peak Detector
AN87-54
1464_02.eps
Application Note 87
R8
100k
Q1
2N3904
C5
1µF
D1
1N4148
C1
1nF
+5
2
3
–
8
1/2
LT1462
+
4
–5
1
R2
24k
5
C2
200pF
6
+
1/2
LT1462
–
R4
10M
PHOTODIODE
R5
24k
7
C5
200pF
DC
OUT
3
2
1/2
LT1462
1
+5
–
R7
10M
D2
1N4148
R3
100k
C3
0.47µF
+
R10
50k
D3
1N4148
5
6
+
1/2
LT1462
–
7
4
–5
R6
100k
C4
10µF
8
+
R1
100Ω
R9
1M
R11
1M
AC
OUT
R13
10k
R12
10k
Figure 78. Logging Photodiode Amplifier
1464_03.eps DBD
Conclusion
The LT1462/LT1464 duals and the LT1463/LT1465 quads
combine many advantages found in many different op
amps, such as low power, (LT1464/LT1465 are 140µA,
LT1462/LT1463 are 30µA typical per amplifier), wide
input common mode range that includes the positive rail
and pico ampere input bias currents. Not only is the output
swing specified with 2k and 10k loads, gain is also
specified for the same load conditions, which is unheard1.6
1.4
1.2
DC OUTPUT (v)
current, which is converted to a voltage by the first op amp.
The first, second and third gain stages are logarithmic
amplifiers that perform a logarithmic compression. A DC
feedback path comprising R8, R9, C5 and Q1 is active only
for no-light conditions, which are very rare, due to the
picoampere sensitivity of the input. Q1 is off when light is
present, isolating the photodiode from C5. When the
feedback path is needed, a small filtered current through
R8 keeps the output of the third op amp within an acceptable range. The third op amp’s output voltage, which is
proportional to the photodiode current, can serve as a
logarithmic DC light meter. Figure 79 shows the relationship between DC output voltage and photodiode current.
The AC component of the output of third op amp is
compressed logarithmically and passed through capacitor
C3 and pot R10 for amplitude control. The fourth op amp
amplifies this AC signal which is generated across R13.
The logarithmic compression of the AC photodiode current allows the user to examine the AC signals for a wide
range of input currents.
1.0
0.8
0.6
0.4
0.2
0
10 –11
10 –9
10 –7
10 –5
PHOTODIODE CURRENT (A)
10 –3
1464_04.eps
Figure 79. DC Output of Logging Photodiode Amplifier
AN87-55
Application Note 87
of for micropower op amps. The 1MHz (LT1464/LT1465)
or 250kHz (LT1462/LT1463) bandwidth self adjusts to
maintain stability for capacitive loads up to 10nF. And
don’t forget the low 0.8mV offset voltage and DC gains of
1 million (LT1464/LT1465) or 600,000 (LT1462/LT1463)
even with 10k loads.
THE LT1210: HIGH POWER OP AMP YIELDS
HIGHER VOLTAGE AND CURRENT
by Dale Eagar
it while the second LT1210 further amplifies the input
signal. This telescoping arrangement can be cascaded
with additional stages to get more than ±30V. This amplifier is stable into capacitive loads, is short-circuit protected and thermally shuts down when overheated.
Introduction
The LT1210, a 1 amp current feedback operational amplifier,
opens up new frontiers. With 30MHz bandwidth, operation
on ±15V supplies, thermal shutdown and 1 amp of output
current, this amplifier single-handedly tackles many tough
applications. But can it handle output voltages higher than
±15V or currents greater than 1 ampere? This Design Idea
features a collection of circuits that open the door to high
voltage and high current for the LT1210.
Extending Power Supply Voltages
Fast and Sassy—Telescoping Amplifiers
Figure 82 shows the LT1210 connected in the extendedsupply mode. Placing an amplifier in the extended-supply
mode requires changing the return of the compensation
node from the power supply pins to system ground. R9
and C5 are selected for clean step response. The process
of relocating the return of the compensation node slows
the amplifier down to approximately 1MHz (see Figure␣ 83).
Need ±30V? Cascading LT1210’s will get you there. This
circuit (Figure 80) will provide the ±30V at ±1A and has
13MHz of full-power bandwidth (see Figure 81). How does
it work? The first LT1210 drives the “ground” of the
second LT1210 subcircuit, effectively raising and lowering
Another method of getting high voltage from an amplifier
is the extended-supply mode (see “Extending Op Amp
Supplies to Get More Voltage”; Linear Technology Volume IV Number 2 (June 1994), pp. 20–22). This involves
steering two external regulators with the power supply
pins of an op amp to get a high voltage amplifier.
1k
30V
TIP 29
15V
1kΩ
1µF
1k
15V
INPUT
1
1µF
300Ω
1
–
LT1210
60Ω
2
+
2
5
5
+
6
3
6.2k
0.01µF
0.01µF
1µF
6.2k
–15V
7
LT1210
7
6
3
1k
4
–
4
15V
1µF
TIP 30
1k
–30V
Figure 80. Telescoping Amplifiers
AN87-56
OUTPUT
Application Note 87
30
25
20
50Ω LOAD
GAIN (dB)
15
10
5
0
FIGURE 80's CKT
+10dBM INPUT
50Ω LOAD
–5
–10
–15
–20
10K
100K
1M
FREQUENCY (Hz)
10M
60M
Figure 81. Gain vs Frequency Plot of Telescoping Amplifier
Figure 82’s circuit will provide ±1A at ±100V, is stable into
capacitive loads and is short-circuit protected. The two
external MOSFETs need heat sinking.
Gateway to the Stars
The circuit of Figure 82 can be expanded to yield much
higher voltages; the first and most obvious way is to use
higher voltage MOSFETs. This causes two problems: first,
high voltage P-channel MOSFETs are hard to get; second,
and more importantly, at ±1A the power dissipated by the
MOSFETs is too high for single packages. The solution is
to build telescoping regulators, as shown in Figure 84.
This circuit can provide ±1A of current at ±200V and has
the additional power-dissipation ability of four MOSFETs.
Boosting Output Current
The current booster detailed in Figure 85 illustrates a
technique for amplifying the output current capability of an
op amp while maintaining speed. Among the many niceties of this topology is the fact that both Q1 and Q2 are
normally off and thus consume no quiescent current.
Once the load current reaches approximately 100mA, Q1
or Q2 turns on, providing additional drive to the output.
This transition is seamless to the outside world and takes
advantage of the full speed of Q1 and Q2. This circuit’s
small-signal bandwidth and full-power bandwidth are
shown in Figure 86.
Boosting Both Current and Voltage
The current-boosted amplifier shown in Figure 85 can be
used to replace the amplifiers in Figure 80, yielding ±10A
at ±30V. Placing the boosted amplifier in the circuits
shown in Figures 82 or 84 will yield peak powers into the
kilowatts.
Thermal Management
When the LT1210 is used with external transistors to
increase its output voltage and/or current range an
100V
100V
100k
100Ω
R8
300Ω
R7
INPUT
10k
1k
1
IRF640
15V
C5
8pF
R9
9.1k
+
5
6
AV = −
(
)
LOAD
0.01
3
15k
R8 R9 += R10
220Ω
7
LT1210
2
0.01µF
P6KE
15A
4
–
P6KE
15A
15V
R10 300Ω
R8 R9 − R7 R10
100Ω
0.01µF
IRF9640
100k
–100V
–100V
Figure 82. ±100V, ±1A Power Driver
AN87-57
Application Note 87
30
25
90Vp-p INTO 50Ω
20
GAIN (dB)
15
10
5
FIGURE 82 CKT
0
–5
–10
–15
–20
10K
100K
1M
FREQUENCY (Hz)
10M
60M
Figure 83. Gain vs Frequency Plot of Extended-Supply Amplifier
additional benefit can often be realized: system thermal
shutdown. Careful analysis of the thermal design of the
system can coordinate the overtemperature shutdown of
the LT1210 with the junction temperatures of the external
transistors. This essentially extends the umbrella of protection of the LT1210’s thermal shutdown to cover the
external transistors. The thermal shutdown of the LT1210
activates when the junction temperature reaches 150˚C
and has about 10˚C hysteresis. The thermal resistance
RθJC of the TO-220 package (LT1210CY) is 5˚C/Watt).
200V
0.47µF
250V
10k
1W
IRF640
15V
10k
1W
IRF640
0.1µF
15V
220Ω
300Ω
INPUT
18V
10k
5W
1k
1
4
–
7
LT1210
2
R9
9.1k
+
C5
8pF
±1A
±200V
5
0.01µF
R1
6.2Ω
0.033Ω
LOAD
6
3
Q1, D45VH4
0.01µF
3.6k
300Ω
1.8k
15V
IN
0.1
100Ω
4
–
7
LT1210
IRF9640
10k
1W
1
15V
2
OUT
5
+
6
3
0.01
Q2, D44VH4
IRF9640
10k
1W
0.47µF
250V
–200V
Figure 84. Cascode Power Amplifier
AN87-58
R2
6.2Ω
0.01µF
0.033Ω
–18V
Figure 85. ±10A/1MHz Current-Boosted Power Op Amp
Application Note 87
8
4AP–P INTO 1Ω
7
6
50Ω LOAD
5
GAIN (dB)
4
FIGURE 85 CKT
+10dBM INPUT
3
2
1
1Ω LOAD
0
–1
–2
10K
100K
1M
10M
FREQUENCY (Hz)
Figure 86. Gain vs Frequency Response of Current-Boosted Amplifier
Summary
The LT1210 is a great part; its performance in terms of
speed, output current and output voltage is unsurpassed.
Its C-Load™ output drive and thermal shutdown allow it to
take its place in the real world—no kid gloves are required
here. If the generous output specification of the LT1210
isn’t big enough for your needs, just add a couple of
transistors to dissipate the additional power and you are
on your way. Only the worldwide supply of transistors
limits the amount of power you could command with one
of these parts.
NEW RAIL-TO-RAIL AMPLIFIERS: PRECISION
PERFORMANCE FROM MICROPOWER TO HIGH SPEED
by William Jett and Danh Tran
used by both input and output signals, maximizing the
system’s dynamic range. Circuits that require signal sensing near the positive supply are straightforward using a
rail-to-rail amplifier.
Introduction
Applications
Linear Technology’s latest offerings expand the range of
rail-to-rail amplifiers with precision specifications. Railto-rail amplifiers present an attractive solution for signal
conditioning in many applications. For battery-powered or
other low voltage circuitry, the entire supply voltage can be
6.81k
VIN
6.81k
The ability to accommodate any input or output signal that
falls within the amplifier supply range makes these
amplifiers very easy to use. The following applications
demonstrate the versatility of the family of amplifiers.
100pF
11.3k
330pF
5.23k
–
5.23k
47pF
10.2k
1/2 LT1498
+
1000pF
–
1/2 LT1498
VOUT
+
VS
—
2
R2R_04.eps
Figure 87. 100kHz 4th Order Butterworth Filter
AN87-59
F
Application Note 87
10
10
10
0
GAIN (dB)
–30
VS = 3V
VIN = 2.7VP-P
VS = 3V
VO = 2.7VP-P
1
1
–40
–50
–60
–70
–80
THD (%)
–20
THD + NOISE (%)
–10
VS = 3V
f = 20kHz
0.1
0.1
0.01
0.01
–90
–100
–110
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0.001
0.01
0.1
1
AMPLITUDE (VP-P)
R2R_05.eps
Figure 88. Filter Frequency Response
10
0.001
100
1k
10k
FREQUENCY (Hz)
R2R_06.eps
100k
R2R_07.eps
Figure 89. Filter Distortion
vs Amplitude
Figure 90. Filter Distortion
vs Frequency
100kHz 4th Order Butterworth Filter for 3V Operation
The filter shown in Figure 87 uses the low voltage operation and wide bandwidth of the LT1498. Operating in the
inverting mode for lowest distortion, the output swings
rail-to-rail. The graphs in Figures 88–90 display the measured lowpass and distortion characteristics with a 3V
power supply. As seen from the graphs, the distortion with
a 2.7VP–P output is under 0.03% for frequencies up to the
cutoff frequency of 100kHz. The stop band attenuation of
the filter is greater than 90dB at 10MHz.
precision VOS specifications over the entire rail-to-rail
input range and have open loop gains of one million or
more. These characteristics, combined with low voltage
operation, makes for truly versatile amplifiers.
5V
+
VIN1
LT1218 S/D
VOUT
–
Multiplexer
A buffered MUX with good offset characteristics can be
constructed using the shutdown feature of the LT1218. In
shutdown, the output of the LT1218 assumes a high
impedance, so the outputs of two devices can be tied
together (wired OR, as they say in the digital world). As
shown in Figure 91, the shutdown pins of each LT1218 are
driven by a 74HC04 buffer. The LT1218 is active with the
shutdown pin high. The photo in Figure 92 shows the
switching characteristics with a 1kHz sine wave applied to
one input and the other input tied to ground. As shown,
each amplifier is connected for unity gain, but either
amplifier or both could be configured for gain.
Conclusion
The latest members of LTC’s family of rail-to-rail amplifiers
expand the versatility of rail-to-rail operation to micropower and high speed applications. The devices maintain
AN87-60
5V
+
VIN2
LT1218 S/D
–
INPUT
SELECT
R2R_08.eps
74HC04
Figure 91. MUX Amplifier
VIN1
VOUT
INPUT
SELECT
Figure 92. MUX Amplifier Waveforms
Application Note 87
LT1256 VOLTAGE-CONTROLLED AMPLITUDE LIMITER
by Frank Cox
Amplitude-limiting circuits are useful where a signal should
not exceed a predetermined maximum amplitude, such as
when feeding an A/D or a modulator. A clipper, which
completely removes the signal above a certain level, is
useful for many applications, but there are times when it is
not desirable to lose information. For instance, when video
signals have amplitude peaks that exceed the dynamic
range of following processing stages, simply clipping the
peaks at the maximum level will result in the loss of all
detail in the areas where clipping takes place. Often these
well illuminated areas are the primary subject of the scene.
Because these peaks usually correspond to the highest
level of luminosity, they are referred to as “highlights.” One
way to preserve some of the detail in the highlights is to
automatically reduce the gain (compress) at high signal
levels.
The circuit in Figure 93 is a voltage-controlled breakpoint
amplifier that can be used for highlight compression.
When the input signal reaches a predetermined level (the
breakpoint), the amplifier gain is reduced. As both the
breakpoint and the gain for signals greater than the
breakpoint are voltage programmable, this circuit is useful
for systems that adapt to changing signal levels. Adaptive
highlight compression finds use in CCD video cameras,
which have a very large dynamic range. Although this
circuit was developed for video signals, it can be used to
adaptively compress any signal within the 40MHz bandwidth of the LT1256.
The LT1256 video fader is connected to mix proportional
amounts of input signal and clipped signal to provide a
voltage-controlled variable gain. The clipped signal is
provided by a discrete circuit consisting of three transistors. Q1 acts as an emitter follower until the input voltage
exceeds the voltage on the base of Q2 (the breakpoint
voltage or VBP). When the input voltage is greater than
VBP, Q1 is off and Q2 clamps the emitters of the two
transistors to VBP plus a VBE. Q3, an NPN emitter follower,
Figure 94. Multiple-Exposure Photograph of a Single
Line of Monochrome Video, Showing Four Different
Levels of Compression
5V
Q1, Q2 = 2N4957
Q3 = 2N2857
2k
1.5k
LT1256
–
Q3
VIDEO
IN
100Ω
Q1
+
Q2
75Ω
1.5k
2k
–5V
+
10k
TO VFS
LT1256, PIN 12
1.5k
LT1004-2.5
5V
BREAK POINT
VOLTAGE
5V
VIDEO
75Ω OUT
100Ω
100k
TO VCONTROL
LT1256, PIN 3
–
+
LT1363
–
510Ω
–5V
1.5k
Figure 93. Voltage-Controlled Amplitude Limiter
AN87-61
Application Note 87
buffers the output and drops the voltage a VBE and thus the
DC level of the input signal is preserved to the extent
allowed by the VBE matching and temperature tracking of
the transistors used. The breakpoint voltage at the base of
Q2 must remain constant when this transistor is turning on
or the signal will be distorted. The LT1363 maintains a low
output impedance well beyond video frequencies and
makes an excellent buffer.
Figure 94 is a multiple-exposure photograph of a single
line of monochrome video, showing four different levels of
compression ranging from fully limited signal to unprocessed input signal. The breakpoint is set to 40% of the
peak amplitude to clearly show the effect of the circuit;
normally only the top 10% of video would be compressed.
THE LT1495/LT1496: 1.5µA RAIL-TO-RAIL OP AMPS
by William Jett
Introduction
Micropower rail-to-rail amplifiers present an attractive
solution for battery-powered and other low voltage circuitry. Low current is always desirable in battery-powered
applications, and a rail-to-rail amplifier allows the entire
supply range to be used by both the inputs and the output,
maximizing the system’s dynamic range. Circuits that
require signal sensing near either supply rail are easier to
implement using rail-to-rail amplifiers. However, until
now, no amplifier combined precision offset and drift
specifications with a maximum quiescent current of 1.5µA.
Operating on a minuscule 1.5µA per amplifier, the LT1495
dual and LT1496 quad rail-to-rail amplifiers consume
almost no power while delivering precision performance
associated with much higher current amplifiers.
readout is taken from a 0µA–200µA, 500Ω analog meter;
the LT1495 supplies a current gain of 1000 in this application. The op amp is configured as a floating I-to-I converter. It consumes only 3µA when not in use, so there is
no need for an on/off switch. Resistors R1, R2 and R3 set
the current gain. R3 provides a ±10% full- scale adjust for
the meter movement. With a 3V supply, maximum current
in the meter is limited by R2 + R3 to less than 300µA,
protecting the movement. Diodes D1 and D2 and resistor
R4 protect the inputs from faults up to 200V. Diode
currents are below 1nA in normal operation, since the
maximum voltage across the diodes is 375µV, the VOS of
the LT1495. C1 acts to stabilize the amplifier, compensating for capacitance between the inverting input and ground.
The unused amplifier should be connected as shown for
minimum supply current. Error terms from the amplifier
(base currents, offset voltage) sum to less than 0.5% over
the operating range, so the accuracy is limited by the
analog meter movement.
The LT1495/LT1496 feature “Over-The-Top” operation:
the ability to operate normally with the inputs above the
positive supply. The devices also feature reverse-battery
protection.
C1
100pF
R1
10M
R4
10k
Applications
The ability to accommodate any input or output signal that
falls within the amplifier supply range makes the LT1495/
LT1496 very easy to use. The following applications
highlight signal processing at low currents.
Nanoampere Meter
INPUT
CURRENT
D1, D2
2×
1N914
–
–
1.5V
1/2
LT1495
+
+
R2
9k
1.5V
R3
2k
µA 0µA TO
200µA
1495_05.eps
A simple 0nA–200nA meter operating from two flashlight
cells or one lithium battery is shown in Figure 95. The
AN87-62
1/2
LT1495
Figure 95. 0nA–200nA Current Meter
Application Note 87
100k
e IN
15nF
15nF
215k
215k
+
215k
100nF
30nF
1kHz. As with all RC filters, the filter characteristics are
determined by the absolute values of the resistors and
capacitors, so resistors should have a 1% tolerance or
better and capacitors a 5% tolerance or better.
10k
1/2 LT1495
–
100nF
Battery-Current Monitor
with Over-the-Top Operation
200k
10nF
VS = 5V, 0V
IS = 2µA + eIN/150k
ZEROS AT 50Hz AND 60Hz
10k
80.6k
15nF
The bidirectional current sensor shown in Figure 98 takes
advantage of the extended common mode range of the
LT1495 to sense currents into and out of a 12V battery
while operating from a 5V supply. During the charge cycle,
op amp A1 controls the current in Q1 so that the voltage
drop across RA is equal to IL • RSENSE. This voltage is then
amplified at the charge output by the ratio of RA to RB.
During this cycle, amplifier A2 sees a negative offset,
which keeps Q2 off and the discharge output low. During
the discharge cycle, A2 and Q2 are active and operation is
similar to that during the charge cycle.
100k
15nF
100nF
169k
169k
169k
+
100nF
1/2 LT1495
OUTPUT
–
30nF
200k
10nF
100k
LT1495/96 •TA03
Conclusion
Figure 96. 6th Order 10Hz Elliptic Lowpass Filter
6th Order, 10Hz Elliptic Lowpass Filter
Figure 96 shows a 6th order, 10Hz elliptic lowpass filter
with zeros at 50Hz and 60Hz. Supply current is primarily
determined by the DC load on the amplifiers and is
approximately 2µA + VO/150k (9µA for VO = 1V). The
overall frequency response is shown in Figure 97. The
notch depth of the zeros at 50Hz and 60Hz is nearly 60dB
and the stopband attenuation is greater than 40dB out to
The LT1495/LT1496 extends Linear Technology’s range
of rail-to-rail amplifier solutions to a truly micropower
level. The combination of extremely low current and
precision specifications provides designers with a versatile solution for battery-operated devices and other low
power systems.
IL
CHARGE
RSENSE
0.1Ω
0
DISCHARGE
–10
–
A2
1/2 LT1495
+
GAIN (dB)
–20
–30
–40
RA
RA
RA
Q2
2N3904
DISCHARGE
OUT
–50
RB
–60
0
10
100
FREQUENCY (Hz)
–
A1
1/2 LT1495
+
Q1
2N3904
CHARGE
OUT
1495_08.eps
RB
1000
1495_07.eps
Figure 97. Frequency Response of Figure
96’s 6th Order Elliptic Lowpass Filter
12V
5V
RA
Figure 98. Battery-Current Monitor
R
VO = IL B R SENSE
RA
FOR R A = 1k
R B = 10k
VO 1V
=
IL
A
AN87-63
Application Note 87
SEND CAMERA POWER AND VIDEO
ON THE SAME COAX CABLE
by Frank Cox
thus corrupting the signal. The circuit shown in Figure 99
takes a different approach to the problem by using all
active components.
Because remotely located video surveillance cameras do
not always have a ready source of power, it is convenient
to run both the power and the video signal through a single
coax cable. One way to do this is to use an inductor to
present a high impedance to the video and a low impedance to the DC. The difficulty with this method is that the
frequency spectrum of a monochrome video signal extends down to at least 30Hz. The composite color video
spectrum goes even lower, with components at 15Hz.
This implies a rather large inductor. For example, a 0.4H
inductor has an impedance of only 75Ω at 30Hz, which is
about the minimum necessary. Large inductors have a
large series resistance that wastes power. More importantly, large inductors can have a significant amount of
parasitic capacitance and stand a good chance of going
into self resonance below the 4MHz video bandwidth and
The circuitry at the monitor end of the coax cable supplies
all the power to the system. U1, an LT1206 current
feedback amplifier, forms a gyrator or synthetic inductor.
The gyrator isolates the low impedance power supply from
the cable by maintaining a reasonably high impedance
over the video bandwidth while, at the same time, contributing only 0.1Ω of series resistance. This op amp needs to
have enough bandwidth for video and sufficient output
drive to supply 120mA to the camera. The selected part has
a guaranteed output current of 250mA and a 3dB bandwidth of 60MHz, making it a good fit. Because the video
needs to be capacitively coupled, there is no need for split
supplies; hence a single 24V supply is used. The 24V
supply also gives some headroom for the voltage drop in
long cable runs.
C2
4.7µF
TANT
C3
1000µF
+
12V
+
C5
0.1µF
Q1
ZETEX ZTX749
C6
1000µF
+
R4
2k
100' RG58/U
20V DC
R5
10k
+
R1
10k
C1
20µF
3
+
CAMERA
U3
OUT LT1086CT-12 IN
R2
10k
2
C4
1000µF
7
+
U4
LT1363
–
+
VIDEO
OUT
6
4
R6
75Ω
C7
1000µF
R3
1k
562Ω
24V
24V
24V
C10
1000µF
0.1µF
R7
2.32k
C9
20µF FILM
R9
510k
R8
11.5k
R12
10k
0.1µF
3
R13
10k
2
+
7
6
U2
LT1363
–
R17
75Ω
4
R14
562Ω
+
4.7µF
24V
2
1
R10
0.1Ω
4
+
7
U1
LT1206CT
R15
280Ω
5
–
3
6
C13
100µF
+
4.7µF
TANT
+
+
R16
280Ω
C11
51pF
NC
+
C12
1000µF
R11, 100Ω
DI_VID_01.eps
Figure 99. Circuit Transmits Video and 12V Power on the Same Coax Cable
AN87-64
TO
MONITOR
Application Note 87
The camera end has an LT1086 fixed 12V regulator (U3) to
supply 12V to a black and white CCD video camera. U4, an
LT1363 op amp, supplies the drive for Q1, a fast, high
current transistor. Q1, in turn, modulates the video on the
20V DC. The collector of Q1 is the input to the 12V
regulator. This point is AC ground because it is well
bypassed as required by U3. U1 is set up to deliver 20V to
the cable. Because the 12V regulator in the camera end
needs 1.5V of dropout voltage, the balance of 6.5V can be
dropped in the series resistance of the cable. The output of
the LT1206 is set to 20V to give headroom between the
supply and the video.
200µA, 1.2MHz RAIL-TO-RAIL OP AMPS HAVE
OVER-THE-TOP INPUTS
by Raj Ramchandani
LT1491 op amps, with substantial improvements in speed.
The LT1638 is five times faster than the LT1490.
U2, another LT1363 video-speed op amp, receives video
from the cable, supplies some frequency equalization and
drives the cable to the monitor. Equalization is used to
compensate for high frequency roll off in the camera cable.
The components shown (R16, C11) gave acceptable monochrome video with 100 feet of RG58/U cable.
Battery Current Monitor
Introduction
The LT1638 is Linear Technology’s latest general-purpose, low power, dual rail-to-rail operational amplifier; the
LT1639 is a quad version. The circuit topology of the
LT1638 is based on Linear Technology’s popular LT1490/
The battery-current monitor shown in Figure 100 demonstrates the LT1639’s ability to operate with its inputs
above the positive rail. In this application, a conventional
amplifier would be limited to a battery voltage between 5V
and ground, but the LT1639 can handle battery voltages
RS
0.2Ω
CHARGER
VOLTAGE
+
1N4001
VBATTERY = 12V
RA
2k
RA'
2k
QA
2N3904
+
1/4
LT1639
A
–
1/4
LT1639
C
–
LOGIC
+
RB
2k
RL
RB'
2k
+
1/4
LT1639
B
VSUPPLY = 5V, 0V
QB
2N3904
–
+
1/4
LT1639
D
RG
10k
LOGIC HIGH (5V) = CHARGING
LOGIC LOW (0V) = DISCHARGING
IBATTERY =
NOTE: RA = RB
(VOUT)
(RS) (RG/RA ) GAIN
VOUT
–
90.9k
=
VOUT
10k
AMPS
GAIN
S1
S1 = OPEN, GAIN = 1
S1 = CLOSED, GAIN = 10
Figure 100. LT1639 Battery Current Monitor—an Over-The-Top Application
AN87-65
Application Note 87
as high as 44V. The LT1639 can be shut down by removing
VCC. With VCC removed, the input leakage is less then
0.1nA. No damage to the LT1639 will result from inserting
the 12V battery backward.
When the battery is charging, amplifier B senses the
voltage drop across RS. The output of amplifier B causes
QB to drain sufficient current through RB to balance the
inputs of amplifier B. Likewise, amplifier A and QA form a
closed loop when the battery is discharging. The current
through QA or QB is proportional to the current in RS. This
current flows into RG and is converted into a voltage.
Amplifier D buffers and amplifies the voltage across RG.
Amplifier C compares the outputs of amplifier A and
amplifier B to determine the polarity of current through RS.
The scale factor for VOUT with S1 open is 1V/A. With S1
closed the scale factor is 1V/100mA and currents as low
as 5mA can be measured.
response and can drive low impedance loads, which
makes them suitable for high performance applications.
The following applications demonstrate the versatility of
these amplifiers.
LOW DISTORTION RAIL-TO-RAIL OP AMPS HAVE
0.003% THD WITH 100kHz SIGNAL
by Danh Tran
Introduction
The LT1630/LT1632 duals and LT1631/LT1633 quads are
the newest members of Linear Technology’s family of railto-rail op amps, which provide the best combination of AC
performance and DC precision over the widest range of
supply voltages. The LT1630/LT1631 deliver a 30MHz
gain-bandwidth product, a 10V/µs slew rate and 6nV/√Hz
input-voltage noise. Optimized for higher speed
applications, the LT1632/LT1633 have a 45MHz gainbandwidth product, a 45V/µs slew rate and 12nV/√Hz
input voltage noise.
Applications
400kHz 4th Order Butterworth Filter for 3V Operation
The circuit shown in Figure 101 makes use of the low
voltage operation and the wide bandwidth of the LT1630 to
create a 400kHz 4th order lowpass filter with a 3V supply.
The amplifiers are configured in the inverting mode for the
lowest distortion and the output can swing rail-to-rail for
the maximum dynamic range. Figure 102 displays the
frequency response of the filter. Stopband attenuation is
greater than 85dB at 10MHz. With a 2.25VP-P, 100kHz
input signal, the filter has harmonic distortion products of
less than –87dBc.
The ability to accommodate any input and output signals
that fall within the device’ s supplies makes these amplifiers very easy to use. They exhibit a very good transient
10
0
–10
2.32k
2.32k
6.65k
VIN
47pF
–
2.74k
2.74k
220pF
GAIN (dB)
–20
5.62k
–
470pF
1/2 LT1630
1/2 LT1630
+
22pF 3V
+
VS/2
–30
–40
–50
–60
VOUT
–70
–80
1630/31 TA01
–90
0.1k
VS = 3V, 0V
VIN = 2.25VP-P
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1630/31 TA02
Figure 101. Single-Supply, 400kHz, 4th Order Butterworth Filter
AN87-66
Figure 102. Frequency Response of Filter
in Figure 101
Application Note 87
40dB Gain, 550kHz Instrumentation Amplifier
An instrumentation amplifier with a rail-to-rail output
swing, operating from a 3V supply, can be constructed
with the LT1632, as shown in Figure 103. The amplifier has
a nominal gain of 100, which can be adjusted with resistor
R5. The DC output level is equal to the input voltage (VIN)
between the two inputs multiplied by the gain of 100.
R5 450Ω
Common mode range can be calculated by the equations
shown with Figure 103. For example, the common mode
range is from 0.15V to 2.65V if the output voltage is at onehalf of the 3V supply. The common mode rejection is
greater than 110dB at 100Hz when trimmed with resistor
R1. Figure 103 shows the amplifier’s cutoff frequency of
550kHz.
R4 20k
50
40
R2 2k
1.5V
20
–
±
R3 2k
1/2
LT1632
–
+
–IN
1/2
LT1632
OUT
+
+IN
VOLTAGE GAIN (dB)
R1 20k
DIFFERENTIAL
INPUT
30
3V
10
VS = 3V
AV = 100
0
–10
COMMON MODE
INPUT
–20
–30
–40
–50
LOWER LIMIT COMMON MODE INPUT VOLTAGE
VCML =
( (
VOUT(DC) R2
AV
+ 0.1V
R5
1.0
1.1
UPPER LIMIT COMMON MODE INPUT VOLTAGE
VCMH =
( (
VOUT(DC) R2
AV
R5
+ 2.85V
1.0
1.1
AV =
R4
R3
(
1+
R2
R1
+
R3 + R2
R5
(
–60
= 100
–70
100
1k
10k
100k
FREQUENCY (Hz)
10M
1562 TA09
BW = 550kHz
VOUT(DC) = (+IN – (–IN))DC × GAIN
1M
Figure 104. Frequency Response of
Figure 103’s Instrumentation Amplifier
Figure 103. Single-Supply Instrumentation Amplifier
THE LT1167: PRECISION, LOW COST, LOW POWER
INSTRUMENTATION AMPLIFIER REQUIRES A SINGLE
GAIN-SET RESISTOR
by Alexander Strong
Introduction
The LT1167 is the next-generation instrumentation amplifier designed to replace the previous generation of monolithic instrumentation amps, as well as discrete, multiple
op amp solutions. Instrumentation amplifiers differ from
operational amplifiers in that they can amplify input signals that are not ground referenced. The output of an
instrumentation amplifier is referenced to an external
voltage that is independent of the input. Conversely, the
output voltage of an op amp, due to the nature of its
feedback, is referenced to the differential and common
mode input voltage.
Applications
Single-Supply Pressure Monitor
The LT1167’s low supply current, low supply voltage
operation and low input bias current (350pA max) allow it
to fit nicely into battery powered applications. Low overall
power dissipation necessitates using higher impedance
bridges. Figure 105 shows the LT1167 connected to a 3kΩ
bridge’s differential output. The picoampere input bias
currents will still keep the error caused by offset current to
a negligible level. The LT1112 level shifts the LT1167’s
reference pin and the ADC’s analog ground pins above
ground. This is necessary in single-supply applications
because the output cannot swing to ground. The LT1167’s
and LT1112’s combined power dissipation is still less than
the bridge’s. This circuit’s total supply current is just 3mA.
AN87-67
Application Note 87
5V
3k
20k
3k
3k
G = 100
499Ω
3k
DIGITAL
DATA
SERIAL
OUTPUT
REF
3
8
1
2
7
+
+IN
5
–
LTC1286
10k
6
LT1167
+
4
–IN
1/2 LT1112
20k
–
1167_02.eps
Figure 105. Single-Supply Pressure Monitor
ADC Signal Conditioning
The LT1167 is shown in Figure 106 changing a differential
signal into a single-ended signal. The single-ended signal
is then filtered with a passive 1st order RC lowpass filter
and applied to the LTC1400 12-bit analog-to-digital converter (ADC). The LT1167’s output stage can easily drive
the ADC’s small nominal input capacitance, preserving
signal integrity. Figure 107 shows two FFTs of the amplifier/ADC’s output. Figures 107a and 107b show the results
of operating the LT1167 at unity gain and a gain of ten,
respectively. This results in a typical SINAD of 70.6dB.
0
SUPPLY VOLTAGE = ±5V
fIN = 5.5kHz
fSAMPLE = 400ksps
SINAD = 70.6dB
LT1167 GAIN = 10
–20
AMPLITUDE (dB)
–40
–60
–80
–100
–120
0
25
50
5V
(A)
0
SUPPLY VOLTAGE = ±5V
fIN = 3kHz
fSAMPLE = 400ksps
SINAD = 70.6dB
LT1167 GAIN = 1
–20
0.1µF
+5V
0.1µF
R1
+
3
VREF
7
1k
1
LT1167
8
2
–
5
4
2
CX
AIN
LTC1400
AMPLITUDE (dB)
0.1µF
3
1
VCC
DOUT 5
CLK 6
SERIAL
INTERFACE
CONV 7
GND
4
–40
–60
–80
–100
VSS
–120
8
0
10µF
0.1µF
0.1µF
+
–5V
–5V
1167 AA .eps
Figure 106. The LT1167 Converting Differential Signals to SingleEnded Signals; the LT1167 is Ideal for Driving the LTC1400
AN87-68
1167 CC .eps
10µF
+
R1 = ∞
CX = 0.047µF
R1 = 5.6kΩ CX = 0.033µF
+
10µF
AV = 1
AV = 10
75 100 125 150 175 200
FREQUENCY (kHz)
25
50
75 100 125 150 175 200
FREQUENCY (kHz)
1167 BB .eps
(B)
Figure 107. Operating at a Gain of One (A) or
Ten (B), Figure 106’s Circuit Achieves
12-Bit Operation with a SINAD of 70.6dB
Application Note 87
Current Source
+VS
RG
Figure 108 shows a simple, accurate, low power programmable current source. The differential voltage across pins
2 and 3 is mirrored across RG. The voltage across RG is
amplified and applied across R1, defining the output
current. The 50µA bias current flowing from pin 5 is
buffered by the LT1464 JFET operational amplifier, which
increases the resolution of the current source to 3pA.
3
8
1
2
VIN–
LT1167
–
+
6
R1
VX
–
5
4
IL
– VS
LT1464
[( ) ( )]
+
V IN+ − V IN− G
VX
=
R1
R1
G = 49.4k Ω + 1
RG
IL=
Nerve-Impulse Amplifier
LOAD
1167_04.eps
Figure 108. Precision Current Source
The LT1167’s low current noise makes it ideal for ECG
monitors that have MΩ source impedances. Demonstrating the LT1167’s ability to amplify low level signals, the
circuit in Figure 109 takes advantage of the amplifier’s
high gain and low noise operation. This circuit amplifies
the low level nerve impulse signals received from a patient
at pins 2 and 3 of the LT1167. RG and the parallel
combination of R3 and R4 set a gain of ten. The potential
on LT1112’s pin 1 creates a ground for the common mode
signal. The LT1167’s high CMRR of 110db ensures that
the desired differential signal is amplified and unwanted
common mode signals are attenuated. Since the DC
portion of the signal is not important, R6 and C2 make up
a 0.3Hz highpass filter. The AC signal at LT1112’s pin 5 is
amplified by a gain of 101 set by R7/R8 + 1. The parallel
combination of C3 and R7 forms a lowpass filter that
decreases this gain at frequencies above 1kHz.
The ability to operate at ±3V on 0.9mA of supply current
makes the LT1167 ideal for battery-powered applications.
Total supply current for this application is 1.7mA. Proper
safeguards, such as isolation, must be added to this circuit
to protect the patient from possible harm.
Conclusion
The LT1167 instrumentation amplifier delivers the best
precision, lowest noise, highest fault tolerance, plus the
ease of use provided by single-resistor gain setting. The
LT1167 is offered in 8-pin PDIP and SO packages. The SO
uses significantly less board space than discrete designs.
PATIENT/CIRCUIT
PROTECTION/ISOLATION
3V
0.3Hz HIGHPASS
+INPUT
C1
R1
R3, 30k
RG, 6k
R4, 30k
R2, 1M
3
8
1
2
7
+
–
3V
C2, 0.47µF
5
6
LT1167
G = 10
5
+
4
R6
1M
–
1
+
8
7
1/2 LT1112
6
+
PATIENT
GROUND
7
+
–
VIN+
–
OUTPUT
1V/mV
4
–3V
2
R7, 10k
–3V
1/2 LT1112
R8
100
3
C3, 15nF
1167_05.eps
+
–INPUT
AV = 101
POLE AT 1kHz
Figure 109. Medical ECG Monitor
AN87-69
Application Note 87
LEVEL SHIFT ALLOWS CFA VIDEO AMPLIFIER TO
SWING TO GROUND ON A SINGLE SUPPLY
by Frank Cox
A current feedback (CFA) video amplifier can be made to
run off a single supply and still amplify ground-referenced
video with the addition of a simple and inexpensive level
shifter. The circuit in Figure 110 is an amplifier and cable
driver for a current output video DAC. The video can be
composite or component but it must have sync. The single
positive supply is 12V but could be as low as 6V for the
LT1227.
The output of the LT1227 CFA used here can swing to
within 2.5V of the negative supply with a 150Ω load over
the commercial temperature range of 0°C to 70°C. Five
diodes in the feedback loop are used, in conjunction with
C5, to level shift the output to ground. The video from the
output of the LT1227 charges C5 and the voltage across it
allows the output to swing to ground or even slightly
negative. However, the level of this negative swing will
depend on the video signal and so will be unpredictable.
When the scene is black, there must be sync on the video
for C5 to remain charged. A zero-level component video
signal with no sync will not work with this circuit. The CFA
output will try to go to zero, or as low as it can, and the
diodes will turn off. The load will be disconnected from the
CFA output and connected through the feedback resistor
to the network of R6 and R7. This causes about 150mVDC
to appear at the output, instead of the 0V that should be
there.
The ground-referenced video signal at the input needs to
be level shifted into the input common mode range of the
LT1227 (3V above negative supply). R4 and R5 shift the
input signal to 3V. In the process, the input video is
attenuated by a factor of 2.5. For correct gain, no offset and
with a zero source impedance, R4 would be 1.5k. To
compensate for the presence of R3, R4 is made 1.5k
minus R3, or 1.46k. The trade off is a gain error of about
1.5%. If R4 is left 1.5k, the gain is correct, but there is an
offset error of 75mV. R6, R7 and R8 set the gain and the
output offset of the amplifier. A noninverting gain of five is
taken to compensate for the attenuation in the input level
shifter and the cable termination.
The voltage offset on the output of this circuit is a rather
sensitive function of the value of the input resistors. For
instance, an error of 1% in the value of R6 will cause an
offset of 30mV (1% of 3V) on the output. This is in addition
to the offset error introduced by the op amp. Precision
resistor networks are available (BI Technologies,
12V
5V
75Ω VIDEO SOURCE
USED FOR TESTING
+
C3 47µF
SOURCE
C1
10µF
R1 75Ω
R5
*R2
1k
77.37Ω
FILM
+
C2
4.7µF
R6
499Ω
C4
0.1µF
C5 4.7µF
FILM
+
B
R9 75Ω
–
5× 1N4148
R8 1.5k
*R3
38.1Ω
R10
75Ω
A
R7
1.5k
*RESISTORS ARE A COMBINATION OF TWO 1% VALUES,
R2 IS A SERIES COMBINATION OF 75Ω AND 2.37Ω
R3 IS A PARALLEL COMBINATION OF 75Ω AND 77.3Ω
R4 IS A SERIES COMBINATION OF 1.3k + 160Ω = 1.46k
ALL RESISTORS ARE 1% METAL FILM
Figure 110. Amplifier and Cable Driver for Current-Output Video DAC
AN87-70
LOAD
LT1227
*R4
1.46k
Application Note 87
714-447-2345) with matching specifications of 0.1% or
better. These could be used for the level shifting resistors,
although this would make adjustments like the one made
to R4 difficult.
Fortunately, there is always synchronization information
associated with video. A simple circuit can be used to DC
restore voltage offsets produced by resistor mismatch, op
amp offset or DC errors in the input video. Figure 111
shows the additional circuitry needed to perform this
function. The LTC201A analog switch and C1 store the
offset error during blanking. The clamp pulse should be
3µs or wider and should occur during blanking. It can
conveniently be made by delaying the sync pulse with one
shots. If the sync tip is clamped, the clamp pulse must
start after and end before the sync pulse or offset errors
will be introduced. The integrator made with the LT1632
adjusts the voltage at point B (see Figure 110) to correct
the offset.
12V
5V
13
R1
10k
1/2 LTC201A
3, 14
R3 10k
2, 15
C2 6800pF
FILM
C1
10µF
FILM
R2
10k
12V
C3
0.1µF
–
TO FIGURE 110,
POINT A
R7 10k
1/2 LT1632
5V
1, 16 4, 5
+
TO FIGURE 110,
POINT B
R4
1.40k
VIDEO
R5
50k
HOLD
5V
C4 0.1µF
0V
SAMPLE
R6
20k
CLAMP PULSE
DC RESTORE LEVEL
(ADJUST FOR DESIRED
BLANKING LEVEL)
Figure 111. DC Restore Subcircuit
LT1468: AN OPERATIONAL AMPLIFIER FOR FAST,
16-BIT SYSTEMS
by George Feliz
Introduction
The LT1468 is a single operational amplifier that has been
optimized for accuracy and speed in 16-bit systems.
Operating from ±15V supplies, the LT1468 in a gain of
–1 configuration will settle in 900ns to 150µV for a 10V
step. The LT1468 also features the excellent DC
specifications required for 16-bit designs. Input offset
voltage is 75µV max, input bias current is 10nA maximum
for the inverting input and 40nA maximum for the noninverting input and DC gain is 1V/µV minimum.
16-Bit DAC Current-to-Voltage Converter
with 1.7µs Settling Time
The key AC specification of the circuit of Figure 112 is
settling time as it limits the DAC update rate. The settling
time measurement is an exceptionally difficult problem
that has been ably addressed by Jim Williams, in Linear
Technology Application Note 74. Minimizing settling time
is limited by the need to null the DAC output capacitance,
which varies from 70pF to 115pF, depending on code. This
capacitance at the amplifier input combines with the
feedback resistor to form a zero in the closed-loop frequency response in the vicinity of 200kHz–400kHz. Without a feedback capacitor, the circuit will oscillate. The
choice of 20pF stabilizes the circuit by adding a pole at
AN87-71
Application Note 87
10V
16
15V
20pF
VREF
6k
DAC
INPUTS
–
OPTIONAL NOISE FILTER
2k
LTC1597
VOUT
LT1468
DAC COUT
70pF–115pF
+
50pF
–15V
1LSB = 25.4nA
FULL SCALE = 1.67mA
153µV
10V
Figure 112. 16-Bit DAC I/V Converter with 1.7µs Settling Time
1.3MHz to limit the frequency peaking and is chosen to
optimize settling time. The settling time to 16-bit accuracy
is theoretically bounded by 11.1 time constants set by the
6kΩ and 20pF. Figure 112’s circuit settles in 1.7µs to
150µV for a 10V step. This compares favorably with the
1.33µs theoretical limit and is the best result obtainable
with a wide variety of LTC and competitive amplifiers. This
excellent settling requires the amplifier to be free of
thermal tails in its settling behavior.
to-noise ratio (SNR) of 90dB implies 56µVRMS noise at the
input. The noise for the amplifier, 100Ω/3000pF filter and
a high value 10kΩ source is 15µVRMS, which degrades the
SNR by only 0.3dB. The LTC1604 total harmonic distortion (THD) is a low –94dB at 100kHz. The buffer/filter
combination alone has 2nd and 3rd harmonic distortion
better than –100dB for a 5VP-P, 100kHz input, so it does
not degrade the AC performance of the ADC.
The buffer also drives the ADC from a low source impedance. Without a buffer, the LTC1604 acquisition time
increases with increasing source resistance above 1k and
therefore the maximum sampling rate must be reduced.
With the low noise, low distortion LT1468 buffer, the ADC
can be driven at maximum speed from higher source
resistances without sacrificing AC performance.
The LTC1597 current output DAC is specified with a 10V
reference input. The LSB is 25.4nA, which becomes 153µV
after conversion by the LT1468, and the full-scale output
is 1.67mA, which corresponds to 10V at the amplifier
output. The zero-scale offset contribution of the LT1468 is
the input offset voltage and the inverting input current
flowing through the 6k feedback resistor. This worst-case
total of 135µV is less than one LSB. At full-scale there is an
insignificant additional 10µV of error due to the 1V/µV
minimum gain of the amplifier. The low input offset of the
amplifier ensures negligible degradation of the DAC’s
outstanding linearity specifications.
With its low 5nV/√Hz input voltage noise and 0.6pA/√Hz
input current noise, the LT1468 contributes only an additional 23% to the DAC output noise voltage. As with any
precision application, and particularly with wide bandwidth amplifiers, the noise bandwidth should be minimized with an external filter to maximize resolution.
The DC requirements for the ADC buffer are relatively
modest. The input offset voltage, CMRR (96dB minimum)
and noninverting input bias current through the source
resistance, RS, affect the DC accuracy, but these errors are
an insignificant fraction of the ADC offset and full-scale
errors.
5V
15V
VIN
RS
+
16
100Ω
LT1468
LTC1604
–
3000pF
ADC Buffer
–15V
530kHz NOISE FILTER
The important amplifier specifications for an analog-todigital converter buffer application (Figure 113) are low
noise and low distortion. The LTC1604 16-bit ADC signal-
AN87-72
–5V
Figure 113. ADC Buffer
ADC
OUTPUTS
Application Note 87
Telecommunications Circuits
Not Your Standard Bench Supply
HOW TO RING A PHONE WITH A QUAD OP AMP
by Dale Eagar
Ring-tone generation requires two high voltages, 60VDC
and –180VDC. Figure 114 details the switching power
supply that delivers the volts needed to run the ring-tone
circuit. This switcher can be powered from any voltage
from 5V to 30V, and is shut down when not in use,
conserving power. The transformer and optocoupling
yield a fully floating output. Faraday shields in the transformer eliminate most switcher noise, preventing mystery
system noise problems later. Table 6 is the build diagram
of the transformer used in the switching power supply.
Requirements
When your telephone rings, exactly what is the phone
company doing? This question comes up frequently, as it
seems everyone is becoming a telephone company.
Deregulation opens many new opportunities, but if you
want to be the phone company you must ring bells. The
voltage requirement for ringing a telephone bell is a
87VRMS 20Hz sine wave superimposed on –48VDC.
Quad Op Amp Rings Phones
An Open-Architecture Ring-Tone Generator
When a phone rings, it rings with a cadence, a sequence
of rings and pauses. The standard cadence is one second
ringing followed by two seconds of silence. We use the
first 1/4 of the LT1491 as a cadence oscillator (developed
in Figures 115 and 116) whose output is at VCC for one
second and then at VEE for two seconds (see Figure 120).
What the module makers offer is a solution to a problem
that, by its nature, calls for unusual design techniques.
What we offer here is a design that you can own, tailor to
your specific needs, lay out on your circuit board and put
on your bill of materials. Finally, you will be in control of the
black magic (and high voltages) of ring-tone generation.
V+
R1
R2
F
+
LT1491
–
60V
MUR160
R3
T1
2
= SECONDARY GROUND
= PRIMARY GROUND
70T #34
0.47µF
C1
7
5V TO 30V
+
220µF
5
VIN
SW
FB
VC
200T #34
4
60V
3A
60V
F
V–
1
20T #26
4
LT1070
2
5
0.47µF
NOTE:
8
6
3
–180V
F
REPRESENTS A FLOATING GROUND,
NOT EQUAL TO
OR
MUR160
10k
1
FREQ
1
V+
180V
GND
3
0.01
5
4N28
V–
2
2k
10k
4
2N3904
RING
10k
1
330Ω
0.1µF
2
R
3 2
1
FREQ =
R3 C1
R1 =
DUTY FACTOR = 50%
DI_RING_01.eps
DI_RING_02.eps
Figure 114. The Switching Power Supply
Figure 115. Op Amp Intentionally Oscillates
AN87-73
Application Note 87
V+
R1
47k
F
R2
10k
F
+
R4
33k
V+
100K
+
LT1491
LT1491
–
–
R3
1.6M
HIGH = OSCILLATE
500K
C1
1µF
0.1µF
F
V–
V–
V+
2 SEC
1 SEC
150K
V+
GATE
V–
V+
V–
OUT
V–
1
Hz
3
DUTY FACTOR = 33.3%
FREQ =
1
S
20
DUTY FACTOR = 50%
OUTPUT STARTS HIGH ON POWERUP.
DI_RING_03.eps
Figure 116. Duty Factor is Skewed
Figure 117. Gated 20Hz Oscillator
DI_RING_04.eps
This sequence repeats every three seconds, producing the
all-too-familiar pattern.
Square Wave Plus Filter Equals Sine Wave
Thevenin will tell you that the output impedance of the
sequencer shown in Figure 118 is 120kΩ. This impedance
can be recycled and used as the input resistance of the filter
that follows. The filter detailed in Figure 119 uses the
Thevenin resistor on its input, yielding a slick, compact
design while distorting the nice waveform on the node
labeled “square out” to a half sine wave, half square wave.
The actual ringing of the bell is performed by a 20Hz AC
sine wave signal at a level of 87VRMS, superimposed on
–48VDC. The 20Hz signal is implemented with the second
amplifier in the LT1491 (Figure 117) which acts as a gated
20Hz oscillator. Connecting the circuit shown in Figure
116 to the circuit shown in Figure 117 and adding three
resistors yields the sequencer as shown in Figure 118. The
waveform, labled “Square Out,” is the fourth trace in
Figure 120. This waveform is the output of Figure 121.
Appending the filter to the waveform sequencer creates
the waveform engine detailed in Figure 119. The output of
this waveform engine is shown in the bottom trace in
10k
300k
100K
150k
+
+
47k
33k
1.6M
CR1 1N4148
500k
1µF
620k
0.1µF
20Hz
CADENCE
F
V–
Figure 118. Sequencer: Cadenced 20Hz Oscillator
AN87-74
SQUARE
WAVE
OUT
–
–
F
300k
LT1491
LT1491
V–
DI_RING_05.eps
Application Note 87
C4
0.047µF
Table 6. Ring-Tone High Voltage Transformer Build Diagram
Materials
–
R11
10k
RTHEVEVIN
120k
SINE
OUT
LT1491
+
OUTPUT
IMPEDANCE OF
FIGURE 118
C3
0.068µF
2
EFD 20–15–3F8 Cores
1
EFD 20–15–8P Bobbin
2
EFD 20– Clip
2
0.007" Nomex Tape for Gap
Start Pin 1 200T #34
F
DI_RING_06.eps
Figure 119. Filter to Remove the Sharp Edges
Winding 1
1 Wrap 0.002" Mylar Tape
Figure 120. This waveform engine is shown in block form
in Figure 122.
Mapping Out the Ring-Tone Generator in Block Form
Term Pin 8
Start Pin 2 70T #34
Winding 2
Term Pin 7
1 Wrap 0.002" Mylar Tape
We now build a system-level block diagram of our ring
tone generator. We start with the waveform engine of
Figure 122, add a couple of 15V regulators and a DC offset
(47k resistor), then apply some voltage gain with a high
voltage amplifier to ring the bell. This hypothetical system-level block diagram is detailed in Figure 123. Figure
124 shows the output waveform of the ring tone generator; the sequenced ringing starts when the high voltage
supply (Figure 114) is turned on, and continues as long as
the power supply is enabled.
1 SEC
POWER
2 SEC
NEXT
RING
Connect Pin 6 1T Foil Tape Faraday Shield
1 Wrap 0.002" Mylar Tape
Start Pin 4 20T #26
Winding 3
Term Pin 5
Finish with Mylar Tape
What’s Wrong with This Picture (Figure 123)
Careful scrutiny of Figure 123 reveals an inconsistency:
even though the three fourths of the LT1491 in the
waveform engine block are powered by ±15V, the final
amplifier is shown as powered from 60V and –180V; this
poses two problems: first the LT1491 is a quad op amp
and all four sections have to share the same supply pins,
and second, the LT1491 will not meet specification when
powered from 60V and –180V. This is because 240V is
greater than the absolute maximum rating of 44V (V+ to
V-). Linear Technology products are noted for their
robustness and conservative “specmanship,” but this is
going too far. It is time to apply some tricks of the trade.
V+
CADENCE
V–
V+
20Hz
V–
2 +
5 V
2 –
V
5
SINE
OUT
1 Wrap 0.002" Mylar Tape
Shields
ON
OFF
SQUARE
OUT
Connect Pin 3 1T Foil Tape Faraday Shield
2 +
5 V
2 –
V
5
DI_RING_07.eps
Figure 120. Timing of Waveform Engine
AN87-75
Application Note 87
10k
0.068µF
620k
100K
–
F
+
47k
10k
+
GATED
SINE WAVE
OUTPUT
LT1491
150k
+
LT1491
LT1491
33k
300k
–
–
F
1N4148
1.6M
16k
0.47µF
620k
F
0.47µF
1µF
F
DI_RING_08.eps
V–
Figure 121. Waveform synthesizer
Building High Voltage Amplifiers
Setting aside the waveform engine for a moment, we will
develop a high voltage amplifier. We start with the ±15V
regulators shown in Figure 123; these are not your run-ofthe-mill regulators, these are high differential voltage
regulators, constructed as shown in Figure 125. Using
these regulators and the final section of the LT1491 quad
op amp, we can build a high voltage amplifier. We will use
the ±15V regulators as the “output transistors” of our
15V
20Hz
V+
WAVEFORM
ENGINE
SINE
OUT
6V
SINE
OUT
POWER
3 SEC
V–
42V
F
SINE –48V
OUT
–138V
–6V
–15V
DI_RING_09.eps
60V
47k
15V
COM
0.01µF
100k
10k
620Ω
150k
IRF620
2N3906
15V
–
REF
V–
2N3904
15V
IRF9620
HV
F
+
–15V REG
–15V
REF –15V
IN
F
SINE
OUT
REF
+VIN
15V REG
OUT
DI_RING_11.eps
Figure 124. System Output
Figure 122. Waveform Engine
WAVEFORM
ENGINE
ON
OFF
VREF
REF
V+
amplifier, because they can both take the voltage and
dissipate the power required to provide the ring voltage
and current. By connecting the op amp to the regulators,
one gets a free cascode high voltage amplifier. This is
because the supply current for the op amp is also the
regulator current. The trouble one encounters when so
doing is that the input common mode range of the op amp
is not wide enough to accommodate the full output voltage
range of the composite amplifier. This would not be a
problem if the amplifier were used as a unity-gain noninverting amplifier, but in this system we need gain to get
from our 12VP-P to 87VRMS.
OUT
COM
F
620Ω
RL
F
100k
F
IN
–180V
REF
DI_RING_10.eps
REF +15V
–VIN
DI_RING_12.eps
Figure 123. High Voltage Amplifier
AN87-76
Figure 125. High Differential Voltage Regulators
Application Note 87
RFF
RL
RFB
V+
–
RFF
AV = –
X
X
IN
+
–
–
+
RFB
RFF
IN
+
RFB
RFF
AV = –
V–
Y
Figure 128. Trade Inputs and Outputs
RFB
RFF
AV = –
–
RFB
RL
RFB
RFF
V+
+
+
IN
+
Y
Y
Y
DI_RING_15.eps
Figure 126. Standard Op Amp Form
RFF
RL
DI_RING_13.eps
X
X
X
X
RFB
RL
–
X
X
X
Y
IN
–
V–
DI_RING_14.eps
AV = –
DI_RING_16.eps
RFB
RFF
Y
Figure 127. Hide the Batteries Inside the Op Amp
Figure 129. Pull the Batteries Back out of the Amplifier
Moving the amplifier’s output transistor function out of the
op amp and into the ±15V regulators moves the effective
amplifier output from the op amp output to the center of
the two supplies sourcing the ±15V regulators. This is a
transformative step in the evolution of amplifiers from low
voltage op amps to high voltage, extended supply
amplifiers.
Darwinistic mood, we might see that the power supplies
(batteries) are in fact an integral part of our amplifier. Such
an observation would lead us to redraw the circuit to look
like Figure 127 where the center of the two batteries are
brought out of the amplifier as the negative terminal of the
output.
Once that is done, one is free to swap the polarities of the
inputs and outputs, yielding the circuit shown in Figure
128. Finally we pull the two batteries back out of the
amplifier to get our morphed inverting amplifier (Figure
129). Isn’t assisting evolution fun?†
Inverting Op Amp Circuit Gets Morphed
Let’s focus on this transformative step as it relates to the
simple inverting amplifier shown in Figure 126.* Were we
to look at the amplifier in Figure 126 in some strange
150k
0.01µF
15V REG
15V
V+
WAVEFORM
ENGINE
OUT
SINE
OUT
10k
60V
IN
C6
R18
R21
LT1491
–
REF
V–
+
COM
RL
47k
F
F
–15V
180V
OUT COM
–15V REG
IN
DI_RING_17.eps
Figure 130. Post-Evolution Block Diagram
AN87-77
Application Note 87
60V
R2
47k
R3
10k
C2
0.47µF
3
R1
33k 2
+
U1A
LT1491
1
D1
1N4148
R16
100k
R5
100k
5
6
Q1
IRF628
R6
10k
C3
0.047µF
+
U1B
LT1491
–
R9
300k
7
R7
16k
–
R11
10k
10
C4
0.068µF
9
15V 100k
+
8
U1C
LT1491
13
–
12
C1
1µF
R4
1.6M
R10
620k
20Hz OSCILLATOR
R12
SMOOTHING FILTER 10k
C5
0.01µF
R14
10k
R13
130k
R15
47k
R17
620
4
–
U1D
LT1491
14
R18
100
+
C7
47µF
11
R24
430Ω
R23
4.7k
R26
2k
+
CADENCE OSCILLATOR
R8
620k
Q3
2N3904
Z1
*OPTO1
R25
4.7k
Q5
2N3904
LOAD UP TO TEN PHONES
Z2
15V
Q2
IRF9620
*LED OF OPTO 1 ILLUMINATES WHEN THE PHONE IS OFF THE HOOK
Figure 131. Ring-Tone Generator
Q4
2N3906
R21
150
POWER AMPLIFIER
–180V
R19
620
R20
100K
C6
0.033µF
DI_RING_18.eps
Applying the evolutionary forces just described to the
block diagram in Figure 123, we get the block diagram in
Figure 130. Actually Figure 130 contains three strangers,
R18, R21 and C6, parts not predicted by our evolutionary
path (unless R18 = 0Ω and R21 is open) These parts are
needed because, in our metamorphosis going from Figure
127 to Figure 128, the amplifier’s internal compensation
node was moved from ground to the amplifier’s output.
These parts correct the compensation for the new configuration.
protected on its output from shorts to ground or to either
the +60V or the –180V supply.
Ring-Trip Sense
Editor’s Notes:
Now that we can ring the telephone, we must sense when
the phone is picked up. This is done by sensing the DC
current flowing to the phone while it is ringing, using the
ring-trip sense circuit comprising R23–R26, C7, Q5 and
Opto1 of Figure 131, the complete ring-tone generator.
This circuit will ring more than ten phones at once, and is
AN87-78
Conclusion
Here is a ring tone generator you can own, a robust circuit
that is stable into any load. If your system design requires
a circuit with different specifications, you can easily tailor
this circuit to meet your needs. Don’t hesitate to call us if
we can help you with your design.
* The grounds X and Y, shown in Figures 126–129, are for illustrating the
effects of “evolution.” Ground X may be regarded as “arbitrary exemplary
ground,” and ground Y as “postmetamorphic exemplary ground.” Ground X
and ground Y are not the same.
† Evolutionary theory invloves pure, random chance. What you have done
here requires purposeful thought and design.
Application Note 87
A LOW DISTORTION, LOW POWER, SINGLE-PAIR
HDSL DRIVER USING THE LT1497
by George Feliz and Adolfo Garcia
Low Distortion Line Driver
Introduction
High speed digital subscriber line (HDSL) interfaces support full-duplex data rates up to 1.544Mbps over 12,000
feet using two standard 135Ω twisted-pair telephone
wires. The high data rate is achieved with a combination of
encoding 2 bits per symbol using two-binary, one-quaternary (2B1Q) modulation, and sophisticated digital signal
processing to extract the received signal. This performance is possible only with low distortion line drivers and
receivers. In addition, the power dissipation of the transceiver circuitry is critical because it may be loop-powered
from the central office over the twisted pair. Lower power
dissipation also increases the number of transceivers that
can placed in a single, non-forced–air enclosure. Singlepair HDSL requires the same performance as two-pair
HDSL over a single twisted pair and operates at twice the
fundamental 2B1Q symbol rate. In HDSL systems that use
2B1Q line coding, the signal passband necessary to carry
a data rate of 1.544Mbps is 392kHz. This signal rate will be
used to quantify the performance of the LT1497 in this
article.
The circuit of Figure 132 transmits signals over a 135Ω
twisted pair through a 1:1 transformer. The LT1497 dual
125mA, 50MHz current feedback amplifier was chosen
for its ability to cleanly drive heavy loads, while consuming a modest 7mA maximum supply current per amplifier
in a thermally enhanced SO-8 package. The driver
amplifiers are configured in gains of two (A1) and minus
one (A2) to compensate for the attenuation inherent in the
back-termination of the line and to provide differential
drive to the transformer. The transmit power requirement
for HDSL is 13.5dBm (22.4mW) into 135Ω, corresponding to a 1.74VRMS signal. Since 2B1Q modulation is a 4level pulse amplitude modulated signal, the crest factor
(peak to RMS) of this signal is 1.61. Thus, a 13.5dBm,
2B1Q modulated signal yields 5.6VP-P across the 135Ω
load. The corresponding output signal current is ±20.7mA
peak. This modest drive level increases for varying line
conditions and is tested with a standardized collection of
test loops that can have line impedances as low as 25Ω.
The LT1497’s high output current and voltage swing drive
the 135Ω line at the required distortion level of –72dBc.
For a data rate of 1.544Mbps and 2-bit-per-symbol
encoding, the fundamental frequency of operation is
392kHz.
560Ω
560Ω
5V
–
A1
1/2 LT1497
VIN
68.1Ω
+
1.1*
+
560Ω
135Ω
560Ω
–
A2
1/2 LT1497
–
68.1Ω
VOUT
5.6VP-P
*MIDCOM 671-7807
(800) 643-2661
+
DI 1497 01.eps
–5V
Figure 132. LT1497 HDSL Driver
AN87-79
Application Note 87
0
–50
2HD
–100
100 200 300 400 500 600 700 800 900 1000 1100
DI 1497 02
FREQUENCY (kHz)
Figure 133. Harmonic Distortion of Figure 132’s Circuit with a
400kHz Sine Wave and an Output Level of 5.6VP-P into 135Ω
The LT1497 provides such low distortion because it operates at only a fraction of its output current capability and
is well within its voltage swing limitations. There are other
LTC amplifiers that can achieve this performance, but at
the expense of higher power dissipation or a larger package.
AMPLITUDE (dBm)
AMPLITUDE (dBm)
0
–50
3IMD
–100
100
200
3IMD
300
400
FREQUENCY (Hz)
500
600
DI 1497 03
Figure 134. 2-Tone Intermodulation for Figure 132’s Circuit
With multicarrier applications such as discrete multitone
modulation (DMT) becoming as prevalent as single-carrier applications, another important measure of amplifier
dynamic performance is 2-tone intermodulation. This
evaluation is a valuable tool to gain insight to amplifier
linearity when processing more than one tone at a time.
Performance
The circuit of Figure 132 was evaluated for harmonic
distortion with a 400kHz sine wave and an output level of
5.6VP-P into 135Ω. Figure 133 shows that the second
harmonic is –72.3dB relative to the fundamental for the
135Ω load. Third harmonic distortion is not critical, because
received signals are heavily filtered before being digitized
by an A/D converter. Performance with a 50Ω load (to
simulate more challenging test loops) is slightly better at
–75dB. The output signal was attenuated to obtain maximum sensitivity of the HP4195A network analyzer used for
the measurements.
For this test, two sine waves at 300kHz and 400kHz were
used with levels set to obtain 5.6VP-P across the 135Ω
load. Figure 134 shows that the third-order intermodulation products are well below –72dB. With a 50Ω load,
performance is within 1dB–2dB of that with the 135Ω
load.
Conclusion
The circuit presented provides outstanding distortion performance in an SO-8 package with remarkably low power
dissipation. It is ideally suited for single pair digital subscriber line applications, especially for remote terminals.
Comparators
ULTRALOW POWER COMPARATORS
INCLUDE REFERENCE
by James Herr
The LTC1440–LTC1445 family features 1µA comparators
with adjustable hysteresis and TTL/CMOS outputs that
sink and source current and a 1µA reference that can drive
a bypass capacitor of up to 0.01µF without oscillation. The
parts operate from a 2V to 11V single supply or a ±1V to
±5V dual supply.
AN87-80
Undervoltage/ Overvoltage Detector
The LTC1442 can be easily configured as a window
detector, as shown in Figure 135. R1, R2 and R3 form a
resistive divider from VCC so that comparator A goes low
when VCC drops below 4.5V, and comparator B goes low
when VCC rises above 5.5V. A 10mV hysteresis band is set
by R4 and R5 to prevent oscillations near the trip points.
Application Note 87
VCC
operation. Comparators A and B, along with R1, R2 and
R3, monitor the battery voltage. When the battery voltage
drops below 2.65V comparator A’s output pulls low to
generate a nonmaskable interrupt to the microprocessor
to warn of a low-battery condition. To protect the battery
from over discharge, the output of comparator B is pulled
high by R7 when the battery voltage falls below 2.45V. Pchannel MOSFET Q1 and the LT1300 are turned off,
dropping the quiescent current to 20µA. Q1 is needed to
prevent the load circuitry from discharging the battery
through L1 and D1.
7
R1
1.33M
1%
V+
3 IN+ A
UNDERVOLTAGE
(4.5V)
OUT A 1
+
–
R2
84.5k
1%
POWER
GOOD
+
OUT B 8
4 IN – B
R3
392k
1%
R4
2.4M
5%
–
5 HYST
OVERVOLTAGE
(5.5V)
6 REF
R5
10k
5%
LTC1442
V–
C1
0.01µF
Comparators C and D provide the reset input to the
microprocessor. As soon as the boost converter output
rises above the 4.65V threshold set by R8 and R9, comparator C turns off and R10 starts to charge C4. After
200ms, comparator D turns off and the Reset pin is pulled
high by R12.
2
Figure 135. Window Detector
Single-Cell Lithium-Ion Battery Supply
Conclusion
Figure 136 shows a single cell lithium-ion battery to 5V
supply with the low-battery warning, low-battery shutdown and reset functions provided by the LTC1444. The
LT1300 micropower step-up DC/DC converter boosts the
battery voltage to 5V using L1 and D1. Capacitors C2 and
C3 provide input and output filtering.
With their built-in references, low supply current requirements and variety of configurations, Linear Technology’s
LTC1440–45 family of micropower comparators is ideal
for system monitoring in battery-powered devices such as
PDAs, laptop and palmtop computers and hand-held
instruments.
The voltage-monitoring circuitry takes advantage of the
LTC1444’s open-drain outputs and low supply voltage
R1
1.1M
5%
5
R2
82.5k
1%
1 CELL
LITHIUMION
BATTERY
4
6
V+
A
1/4 LTC1444
+
–
R7
51k
5%
–
7
SW
C2
100µF
3
1
NC
NC
R5
51k
5%
+
6
VIN
2
14
R4
2.4M
5%
D1
1N5817
+
B
1/4 LTC1444
7 + HYST
R3
1M
1%
L1
10µH
SUMIDA
CD54-100
3
5
2
SENSE
3
LT1300
ILIM
+
SEL
8
R6
430Ω
5%
C1
1µF
1
SHDN
PWR GND
8 REF
4
GND
1
2, 4
Q1
MMFT2955ETI
C3
100µF
R9
267k
1%
R8
732k
1% 11
R10
3.37M
5%
+
C
1/4 LTC1444
10
16
13
D
1/4 LTC1444
–
12
LTC1444
REF
+
R11
51k
5%
R12
51k
15 5%
VCC
NMI
µP
RESET
–
C4
0.22µF
9 V–
C2, C3: AUX TPSD107M010R0100 OR
SANYO OS-CON 16SA100M
Figure 136. Single-Cell to 5V Supply
AN87-81
Application Note 87
A 4.5ns, 4mA, SINGLE-SUPPLY, DUAL COMPARATOR
OPTIMIZED FOR 3V/5V OPERATION
by Joseph G. Petrofsky
VCC
2.7V–6V
1MHz–10MHz
CRYSTAL (AT-CUT)
2k
Introduction
220Ω
620Ω
The LT1720 is an UltraFast™ (4.5ns), low power (4mA/
comparator), single-supply, dual comparator designed to
operate on a single 3V or 5V supply. These comparators
feature internal hysteresis, making them easy to use, even
with slowly moving input signals. The LT1720 is fabricated in Linear Technology’s 6GHz complementary bipolar process, resulting in unprecedented speed for its low
power consumption.
Applications
GROUND
CASE
+
OUTPUT
1/2 LT1720
–
2k
0.1µF
1.8k
Figure 137. Simple 1MHz to 10MHz Crystal Oscillator
Crystal Oscillators
Figure 137 shows a simple crystal oscillator using one half
of an LT1720. The 2k–620Ω resistor pair set a bias point
at the comparator’s noninverting input. The 2k–1.8k–
0.1µF path sets the inverting input node at an appropriate
DC average level based on the output. The crystal’s path
provides resonant positive feedback and stable oscillation
occurs. Although the LT1720 will give the correct logic
output when one input is outside the common mode
range, additional delays may occur when it is so operated,
opening the possibility of spurious operating modes.
Therefore, the DC bias voltages at the inputs are set near
the center of the LT1720’s common mode range and the
220Ω resistor attenuates the feedback to the noninverting
input. The circuit will operate with any AT-cut crystal from
1MHz to 10MHz over a 2.7V to 6V supply range.
The output duty cycle for the circuit of Figure 137 is
roughly 50% but it is affected by resistor tolerances and,
to a lesser extent, by comparator offsets and timings.
Timing Skews
For a number of reasons, the LT1720 is an excellent choice
for applications requiring differential timing skew. The two
comparators in a single package are inherently well
matched, with just 300ps ∆tPD typical. Monolithic construction keeps the delays well matched vs supply voltage
AN87-82
and temperature. Crosstalk between the comparators,
usually a disadvantage in monolithic duals, has minimal
effect on the LT1720 timing due to the internal hysteresis.
The circuits of Figure 138 show basic building blocks for
differential timing skews. The 2.5k resistance interacts
with the 2pF typical input capacitance to create at least
±4ns delay, controlled by the potentiometer setting. A
differential and a single-ended version are shown. In the
differential configuration, the output edges can be smoothly
scrolled through ∆t = 0 with negligible interaction.
Fast Waveform Sampler
Figure 139 uses a diode-bridge-type switch for clean, fast
waveform sampling. The diode bridge, because of its
inherent symmetry, provides lower AC errors than other
semiconductor-based switching technologies. This circuit features 20dB of gain, 10MHz full power bandwidth
and 100µV/°C baseline uncertainty. Switching delay is less
than 15ns and the minimum sampling window width for
full power response is 30ns.
The input waveform is presented to the diode bridge
switch, the output of which feeds the LT1227 wideband
amplifier. The LT1720 comparators, triggered by the sample
command, generate phase-opposed outputs. These sig-
Application Note 87
LT1720
CIN
+
LT1720
CIN
INPUT
–
–
2.5k
CIN
CIN
DIFFERENTIAL ±4ns
RELATIVE SKEW
2.5k
INPUT
+
CIN
0ns–4ns SINGLEENDED DELAY
–
CIN
+
–
+
CIN
CIN
VREF
VREF
Figure 138. Timing-Skew Generation is Easy with the LT1720
nals are level shifted by the transistors, providing complementary bipolar drive to switch the bridge. A skew compensation trim ensures bridge-drive signal simultaneity
within 1ns. The AC balance corrects for parasitic capacitive bridge imbalances. A DC balance adjustment trims
bridge offset.
The trim sequence involves grounding the input via 50Ω
and applying a 100kHz sample command. The DC balance
is adjusted for minimal bridge ON vs OFF variation at the
output. The skew compensation and AC balance adjustments are then optimized for minimum AC disturbance in
the output. Finally, unground the input and the circuit is
ready for use.
Coincidence Detector
High speed comparators are especially suited for interfacing pulse-output transducers, such as particle detectors,
to logic circuitry. The matched delays of a monolithic dual
are well suited for those cases where the coincidence of
two pulses needs to be detected. The circuit of Figure 140
is a coincidence detector that uses an LT1720 and discrete
components as a fast AND gate.
The reference level is set to 1V, an arbitrary threshold. Only
when both input signals exceed this will a coincidence be
detected. The Schottky diodes from the comparator outputs to the base of the MRF-501 form the AND gate, while
the other two Schottkys provide for fast turn-off. A logic
AND gate could instead be used, but would add considerably more delay than the 300psec contributed by this
discrete stage.
This circuit can detect coincident pulses as narrow as
2.5ns. For narrower pulses, the output will degrade gracefully, responding, but with narrow pulses that don’t rise all
the way to high before starting to fall. The decision delay
is 4.5ns with input signals 50mV or more above the
reference level. This circuit creates a TTL compatible
output but it can typically drive CMOS as well.
Pulse Stretcher
For detecting short pulses from a single sensor, a pulse
stretcher is often required. The circuit of Figure 141 acts as
a one-shot, stretching the width of an incoming pulse to a
consistent 100ns. Unlike a logic one-shot, this LT1720based circuit requires only 100pV-s of stimulus to trigger.
The circuit works as follows: Comparator C1 functions as
a threshold detector, whereas comparator C2 is configured
as a one-shot. The first comparator is prebiased with a
threshold of 8mV to overcome comparator and system
offsets and establish a low output in the absence of an
input signal. An input pulse sends the output of C1 high,
which in turn latches C2’s output high. The output of C2 is
fed back to the input of the first comparator, causing
AN87-83
Application Note 87
5V
2.2k
2.2k
INPUT
±100mV FULL SCALE
+
OUTPUT
±1V FULLSCALE
LT1227
1k
–
909Ω
100Ω
= 1N5711
= CA3039 DIODE ARRAY
(SUBSTRATE TO –5V)
AC BALANCE
2.5k
3pF
5V
1.5k
3.6k
1.1k
1.1k
0.1µF
+
1/2 LT1720
CIN
–
SAMPLE
COMMAND
2k
SKEW
COMP
10pF
2.5k
1.1k
1.1k
+
1/2 LT1720
–
2k
MRF501
MRF501
CIN
DC BALANCE
500Ω
11
820Ω
8
680Ω
LM3045
6
9
10
13
820Ω
7
51Ω
51Ω
–5V
Figure 139. Fast Waveform Sampler Using the LT1720 for Timing-Skew Compensation
regeneration and latching both outputs high. Timing
capacitor C now begins charging through R and, at the end
of 100ns, C2 resets low. The output of C1 also goes low,
AN87-84
latching both outputs low. A new pulse at the input of C1
can now restart the process. Timing capacitor C can be
increased without limit for longer output pulses.
Application Note 87
This circuit has an ultimate sensitivity of better than 14mV
with 5ns–10ns input pulses. It can even detect an avalanche generated test pulse of just 1ns duration with
sensitivity better than 100mV.1 It can detect short events
better than the coincidence detector above because the
one-shot is configured to catch just 100mV of upward
movement from C1’s VOL, whereas the coincidence
detector’s 2.5ns specification is based on a full, legitimate
logic high.
Conclusion
The new LT1720 dual 4.5ns single-supply comparators
feature high speeds and low power consumption. They are
versatile and easy-to-use building blocks for a wide variety of system design challenges.
1 See Linear Technology Application Note 47, Appendix B. This circuit can
detect the output of the pulse generator described after 40dB of attenuation.
5V
5V
300Ω
+
MRF501
(GROUND
CASE LEAD)
1/2 LT1720
51Ω
–
3.9k
OUTPUT
5V
1k
–
0.1µF
1/2 LT1720
+
4× 1N5711
300Ω
51Ω
300ps AND GATE
COINCIDENCE COMPARATORS
Figure 140. A 2.5ns Coincidence Detector
5V
0.01µF
15k
–
OUTPUT
C1
1/2 LT1720
PULSE SOURCE
+
24Ω
R 1k
6.8k
C
100pF
1N5711
C2
1/2 LT1720
+
51Ω
100ns
–
50Ω
2k
2k
2k
Figure 141. A 1ns Pulse Stretcher
AN87-85
Application Note 87
Instrumentation Circuits
A = 50mV/DIV
B = 5V/DIV
LTC1441-BASED MICROPOWER
VOLTAGE-TO-FREQUENCY CONVERTER
by Jim Williams
C = 5V/DIV
D = 1mA/DIV
E = 5V/DIV
Figure 142 is a voltage-to-frequency converter. A 0V–5V
input produces a 0Hz–10kHz output, with a linearity of
0.02%. Gain drift is 60ppm/°C. Maximum current consumption is only 26µA, 100 times lower than currently
available units.
To understand the circuit’s operation, assume that C1’s
negative input is slightly below its positive input (C2’s
output is low). The input voltage causes a positive-going
ramp at C1’s input (trace A, Figure 143). C1’s output is
high, allowing current flow from Q1’s emitter, through
C1’s output stage to the 100pF capacitor. The 2.2µF
capacitor provides high frequency bypass, maintaining
low impedance at Q1’s emitter. Diode connected Q6 pro-
HORIZ = 20µs/DIV
Figure 143. Waveforms for the Micropower V/F Converter:
Charge-Based Feedback Provides Precision Operation with
Extremely Low Power Consumption.
vides a path to ground. The voltage to which the 100pF unit
charges is a function of Q1’s emitter potential and Q6’s
drop. C1’s CMOS output, purely ohmic, contributes no
voltage error. When the ramp at C1’s negative input goes
high enough, C1’s output goes low (trace B) and the
inverter switches high (trace C). This action pulls current
from C1’s negative input capacitor via the Q5 route (trace
D). This current removal resets C1’s negative input ramp
+V = 6.2 → 12V
LM334
INPUT
0–5V
10kHz
TRIM
1.2M* 200k
6.04k*
+
2.2µF
Q8
Q1
–
C1
1/2 LTC1441
0.01
LT1004
1.2V
x3
+
0.47µF
50pF
Q2
100k
Q3
100Hz TRIM
3M TYP
15k
Q5
Q4
Q7
100pF†
74C14
OUTPUT
= HP5082-2810
Q6
10M
2.7M
= 1N4148
0.1
Q1, Q2, Q8 = 2N5089
ALL OTHER = 2N2222
†
= POLYSTYRENE
* = 1% METAL FILM
GROUND ALL UNUSED 74C14 INPUTS
–
C2
1/2 LTC1441
+
DIVF_01.eps
Figure 142. 0.02% V/F Converter Requires only 26µA Supply Current
AN87-86
Application Note 87
CURRENT CONSUMPTION (µA)
35
modulate the voltage drop in the Q2–Q4 trio. This
correction’s sign and magnitude directly oppose the
–120ppm/°C 100pF polystyrene capacitor’s drift, aiding
overall circuit stability. Q8’s isolated drive to the CMOS
inverter prevents output loading from influencing Q1’s
operating point. This makes circuit accuracy independent
of loading.
30
25
20
SLOPE = 1.1µA/kHz
15
10
5
0
0
1
2
3
4 5 6 7 8 9 10 11 12
FREQUENCY (kHz)
DIVF_03.eps
Figure 144. Current Consumption vs Frequency for the
V/F Converter: Charge/Discharge Cycles Account for
1.1µA/kHz Current Drain Increase
to a potential slightly below ground. The 50pF capacitor
furnishes AC positive feedback (C1’s positive input is trace
E) ensuring that C1’s output remains negative long enough
for a complete discharge of the 100pF capacitor. The
Schottky diode prevents C1’s input from being driven
outside its negative common mode limit. When the 50pF
unit’s feedback decays, C1 again switches high and the
entire cycle repeats. The oscillation frequency depends
directly on the input-voltage-derived current.
Q1’s emitter voltage must be carefully controlled to get
low drift. Q3 and Q4 temperature compensate Q5 and Q6
while Q2 compensates Q1’s VBE. The three LT1004s are
the actual voltage reference and the LM334 current source
provides 12µA bias to the stack. The current drive provides
excellent supply immunity (better than 40ppm/V) and also
aids circuit temperature coefficient. It does this by using
the LM334’s 0.3%/°C tempco to slightly temperature
BRIDGE MEASURES SMALL CAPACITANCE
IN PRESENCE OF LARGE STRAYS
by Jeff Witt
Capacitance sensors measure a wide variety of physical
quantities, such as position, acceleration, pressure and
fluid level. The capacitance changes are often much smaller
than stray capacitances, especially if the sensor is remotely placed. I needed to make measurements with a
50pF cryogenic fluid level detector, with only 2pF full-scale
change, hooked to several hundred pF of varying cable
The Q1 emitter-follower delivers charge to the 100pF
capacitor efficiently. Both base and collector current end
up in the capacitor. The 100pF capacitor, as small as
accuracy permits, draws only small transient currents
during its charge and discharge cycles. The 50pF–100k
positive feedback combination draws insignificantly small
switching currents. Figure 144, a plot of supply current
versus operating frequency, reflects the low power design. At zero frequency, comparator quiescent current and
the 12µA reference stack bias account for all current drain.
There are no other paths for loss. As frequency scales up,
the 100pF capacitor’s charge-discharge cycle introduces
the 1.1µA/kHz increase shown. A smaller value capacitor
would cut power, but effects of stray capacitance and
charge imbalance would introduce accuracy errors.
Circuit start-up or overdrive can cause the circuit’s ACcoupled feedback to latch. If this occurs, C1’s output goes
low; C2, detecting this via the 2.7M–0.1µF lag, goes high.
This lifts C1’s positive input and grounds the negative
input with Q7, initiating normal circuit action.
To calibrate this circuit, apply 50mV and select the indicated resistor at C1’s positive input for a 100Hz output.
Complete the calibration by applying 5V and trimming the
input potentiometer for a 10kHz output.
capacitance. This required a circuit with high stability,
sensitivity and noise rejection, but one insensitive to stray
capacitance caused by cables and shielding. I also wanted
battery operation and analog output for easy interfacing to
other instruments. Two traditional circuit types have
drawbacks: integrators are sensitive to noise at the comparator and voltage-to-frequency converters typically measure stray as well as sensor capacitance. The capacitance
bridge presented here measures small transducer capacitance changes, yet rejects noise and cable capacitance.
AN87-87
Application Note 87
The bridge, shown in Figure 145, is designed around the
LTC1043 switched-capacitor building block. The circuit
compares a capacitor, CX, of unknown value, with a
reference capacitor, CREF. The LTC1043, programmed
with C1 to switch at 500Hz, applies a square wave of
amplitude VREF to node A, and a square wave of amplitude
VOUT and opposite phase to node B. When the bridge is
balanced, the AC voltage at node C is zero, and
The circuit operates from a single 5V supply and consumes 800µA. If the capacitances at nodes A and C are
kept below 500pF, the LT1078 micropower dual op amp
may be used in place of the LT1413, reducing supply
current to just 160µA.
If the relative capacitance change is small, the circuit can
be modified for higher resolution, as shown in Figure 146.
A JFET input op amp (LT1462) amplifies the signal before
demodulation for good noise performance, and the output
of the integrator is attenuated by R1 and R2 to increase the
sensitivity of the circuit. If ∆CX << CX, and CREF ≈ CX, then
VOUT = VREF CX
CREF
Balance is achieved by integrating the current from node
C using an op amp (LT1413) and a third switch on the
LTC1043 for synchronous detection. With CREF = 500pF
and VREF = 2.5V, this circuit has a gain of 5mV/pF, and
when measured with a DMM achieves a resolution of 10fF
for a dynamic range of 100dB. It also rejects stray capacitance (shown as ghosts in Figure 145) by 100dB. If this
rejection is not important, the switching frequency f can
be increased to extend the circuit’s bandwidth, which is
BW = f
VOUT – VREF ≈ VREF ∆CX (R1 + R2)
CREF R2
With CREF = 50pF, the circuit has a gain of 5V/pF and can
resolve 2fF. Supply current is 1mA. The synchronous
detection makes this circuit insensitive to external noise
sources and in this respect shielding is not terribly important. However, to achieve high resolution and stability,
care should be taken to shield the capacitors being measured. I used this circuit for the fluid level detector mentioned above, putting a small trim cap in parallel with CREF
to adjust offset and trimming R2 for proper gain.
CREF
COUT
COUT should be larger than CREF.
5V
5V
100k
VREF
1/2 LTC1043
4
6
5
+
V+
COSC
V–
1/2
LT1413
7
16
COUT
2.2nF
7
11
–
C1
0.01µF
17
A
1/4 LTC1043
8
CX
1µF
5V
5
LT1004-2.5
C
6
13
3
CREF
12
14
2
2
B
VREF
NOTE: SHADED PARTS REPRESENT
PARASITIC CAPACITANCES
Figure 145. A Simple, High Performance Capacitance Bridge
AN87-88
+
8
1/2
LT1413
–
4
1
VOUT
Application Note 87
Bridge circuits are particularly suitable for differential
measurements. When CX and CREF are replaced with two
sensing capacitors, these circuits measure differential
capacitance changes, but reject common mode changes.
VIN
5V
1/2 LTC1043
4
100k
6
VREF
5
CMRR for the circuit in Figure 146 exceeds 70dB. In this
case, however, the output is linear only for small relative
capacitance changes.
V+
COSC
16
3
+
1/2
LT1413
V–
7
17
10M 2
–
6
10k
8
–
5
2
100Ω
LT1004-2.5
5V
1/4 LTC1043
VREF
11
–
10k
10k
1
1/2
LT1462
7
CX
1µF
+
0.01µF
VREF
6
5
+
8
1/2
LT1462
7
4
VREF
1µF
CREF
13
12
5V
R1
10.0k 1%
8
1
1/2
LT1413
4
+
14
–
R2
100Ω 1%
100K
2
3
VREF
VOUT
Figure 146. A Bridge with Increased Sensitivity and Noise Performance
WATER TANK PRESSURE SENSING,
A FLUID SOLUTION
by Richard Markell
Introduction
Liquid sensors require a media compatible, solid state
pressure sensor. The pressure range of the sensor is
dependent on the height of the column or tank of fluid that
must be sensed. This article describes the use of the E G
& G IC Sensors Model 90 stainless steel diaphragm, 0 to
15psig sensor used to sense water height in a tank or
column.
Because large chemical or water tanks are typically located
outside in “tank farms,” it is insufficient to provide only an
analog interface to a digitization system for level sensing.
This is because the very long wires required to interconnect the system cause IR drops, noise and other corruption of the analog signal. The solution to this problem is to
implement a system that converts the analog to digital
signals at the sensor. In this application, we implement a
“liquid height to frequency converter.”
Circuit Description
Figure 147 shows the analog front-end of the system,
which includes the LT1121 linear regulator for powering
the system. The LT1121 is a micropower, low dropout
linear regulator with shutdown. For micropower
applications of this or other circuits, the ability to shut
down the entire system via a single power supply pin
allows the system to operate only when taking data (perhaps
every hour), conserving power and improving battery life.
AN87-89
Application Note 87
TO FIGURE 148
(9V)
12V
C1
0.1µF
8
IN
OUT
U3
LT1121
5
SHDN
OUT
GND
3
5
1 9V
R2
18k
R3
35.7k
C3
0.1µF
2
C2
1µF
R1
13k
6
12
R5
4.99k
LT1034
-1.2
10k
POT
13
4
+
U1D
LT1079
–
14
7
U1B
LT1079
–
3
6
1 PRESSURE 5
SENSOR
MODEL 90
11
R4
4.99k
2
R15
100k
R21
100k
R18
249k
R14
100k
R6
823Ω
GND
5k
INSIDE SENSOR IN MODEL 93
REPLACES R13 AND 10k POT
+
R13
3.32k
2
10k
POT
–
U2A
LT1490
7
3
+
1
VO
R8
3.01k
MODEL 90/MODEL 93
E G & G IC SENSORS (408) 432-1800
2
3
R16
100k
–
U1A
LT1079
R19
249k
1
R17
100k
+
R20
100k
DI_WT_01.eps
Figure 147. Pressure-Sensor Amplifier
FROM LT1121 (FIGURE 147) +9V
LM334
INPUT
FROM
PRESSURE
SENSOR
AMPLIFER
(FIG 147)
10kHz
TRIM
1.2M* 200k
6.04k*
+
2.2µF
Q8
Q1
–
C1
1/2 LTC1441
0.01µF
LT1004
1.2V
x3
+
0.47µF
50pF
Q2
100k
Q3
100Hz TRIM
3M TYP
15k
Q5
Q4
Q7
†
100pF
= HP5082-2810
OR 1N5711
Q6
10M
2.7M
= 1N4148
0.1µF
Q1, Q2, Q8 = 2N5089
ALL OTHER = 2N2222
†
= POLYSTYRENE
* = 1% METAL FILM
GROUND ALL UNUSED 74C14 AND 74C74 INPUTS PINS
0.1
74C14
–
C2
1/2 LTC1441
+
4
14 1
PRE VCC CLR
3
5 390k
CLK
Q
74C74
2
6
D
Q
7
DI_WT_02.eps
Figure 148. This 0.02% V/F Converter Requires only 26µA Supply Current
AN87-90
100k
Application Note 87
5.0
4.5
4.0
VOLTS
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
FEET
12
14
16
DI_WT_03.eps
Figure 149. Output Voltage vs Column Height
In Figure 147, U3, the LT1121, converts 12V to 9V to
power the system. The 12V may be obtained from a wall
cube or batteries.
Op amps U1A and U1B (each 1/4 of an LT1079) amplify the
bridge pressure sensor’s output and provide a differential
signal to U2A (an LT1490). Note that U2A must be a railto-rail op amp. The system’s analog output is taken from
U2A’s output.
Figure 149 plots the output voltage for the sensor system’s
analog front end versus the height of the water column that
impinges on the pressure transducer. Note that the pressure change is independent of diameter of the water
column, so that a tank of liquid would produce the same
resulting output voltage. Figure 150 is a photograph of our
test setup.
The remainder of the circuitry, shown in Figure 148, allows
transmission of analog data over long distances. The
circuit was designed by Jim Williams. The circuit takes a
DC input from 0V to 5V and converts it to a frequency. For
the pressure circuit in Figure 147, this translates to
approximately 0Hz to 5kHz.
Figure 150. Test Setup for Water-Column Sensor
The voltage-to-frequency converter shown in Figure 148
has very low power consumption (26µA), 0.02% linearity,
60ppm/˚C drift and 40ppm/V power supply rejection.
In operation, C1 switches a charge pump, comprising Q5,
Q6 and the 100pF capacitor, to maintain its negative input
at 0V. The LT1004s and associated components form a
temperature-compensated reference for the charge pump.
6000
5000
FREQUENCY (Hz)
The LT1034, a 1.2V reference, is used with U1D, 1/4 of an
LT1079 quad low power op amp, to provide a 1.5mA
current source to the pressure sensor. The reference
voltage is also divided down by R5, R8, R4 and the 10k
potentiometer and used to offset the output amplifier,
U2A, so that the signals are not too close to the supply
rails.
4000
3000
SENSOR #2
2000
1000
SENSOR #1
0
0
2
4
6
8
10
FEET
12
14
16
DI_WT_05.eps
Figure 151. Output Frequency vs Column
Height for Two Model 90 Sensors
AN87-91
Application Note 87
The 100pF capacitor charges to a fixed voltage; hence, the
repetition rate is the circuit’s only degree of freedom to
maintain feedback. Comparator C1 pumps uniform packets of charge to its negative input at a repetition rate
precisely proportional to the input-voltage-derived current. This action ensures that circuit output frequency is
determined strictly and solely by the input voltage.
Figure 151 shows the output frequency versus column
height for two different Model 90 transducers. Note the
straight lines, which are representative of excellent linearity.
0.05µV/˚C CHOPPED AMPLIFIER REQUIRES
ONLY 5µA SUPPLY CURRENT
by Jim Williams
Conclusion
A cost effective system is shown here consisting of a fluid
pressure sensor, IC Sensors Model 90. This sensor’s
output is fed to signal processing electronics that convert
the low level DC output of the bridge-based pressure
sensor to a frequency in the audio range depending on the
height of the fluid column impinging on the pressure
transducer.
a gain of 1000, presenting its output to a switched
demodulator similar to the aforementioned modulator.
Figure 152 shows a chopped amplifier that requires only
5.5µA supply current. Offset Voltage is 5µV, with 0.05µV/
˚C drift. A gain exceeding 108 affords high accuracy, even
at large closed-loop gains.
The micropower comparators (C1A and C1B) form a
biphase 5Hz clock. The clock drives the input-related
switches, causing an amplitude-modulated version of the
DC input to appear at A1A’s input. AC-coupled A1A takes
The demodulator output, a reconstructed, DC-amplified
version of the circuit’s input, is fed to A1B, a DC gain stage.
A1B’s output is fed back, via gain setting resistors, to the
input modulator, closing a feedback loop around the entire
amplifier. The configuration’s DC gain is set by the feedback resistor’s ratio, in this case 1000.
The circuit’s internal AC coupling prevents A1’s DC characteristics from influencing overall DC performance,
accounting for the extremely low offset uncertainty noted.
IN
CCOMP
0.1µF
1/2 CD4016
1 1/2 CD4016
13
Ø1
2
10
1M
1M
9
6
–
10M
4
Ø2
1µF
A1A
LT1495
3
5
12
1µF
+
Ø2
11
5V
1M
–
A1B
Ø1
OUT
+ LT1495
8
Ø1
–5V
10k
10M
10M
5V
+
–
C1B
LTC1440
C1A
LTC1440
Ø2
10k
–
+
10M
–5V
0.047µF
10M
Figure 152. 0.05µV/˚C Chopped Amplifier Requires only 5µA Supply Current
AN87-92
Application Note 87
The high open-loop gain permits 10ppm gain accuracy at
a closed-loop gain of 1000.
The desired micropower operation and A1’s bandwidth
dictate the 5Hz clock rate. As such, the resultant overall
1000
4.5ns DUAL-COMPARATOR-BASED CRYSTAL
OSCILLATOR HAS 50% DUTY CYCLE AND
COMPLEMENTARY OUTPUTS
by Joseph Petrofsky and Jim Williams
The circuit of Figure 153 creates a pair of complementary
outputs with a forced 50% duty cycle. Crystals are narrowband elements, so the feedback to the noninverting input
is a filtered analog version of the square wave output.
Changing the noninverting reference level can therefore
vary the duty cycle. C1 operates as in the previous example, where the 2k–600Ω resistor pair sets a bias point
at the comparator’s noninverting input. The 2k–1.8k–
0.1µF path sets the inverting input at the node at an
appropriate DC-average level based on the output. The
2.7V–6V
620Ω
1MHz–10MHz
CRYSTAL (AT-CUT)
220Ω
GROUND
CASE
+
C1
1/2 LT1720
OUTPUT
–
100k
2k
+
1.8k
0.1µF
A1
LT1636
0.1µF
–
OUTPUT SKEW (ps)
800
Figure 153’s circuit uses the LT1720 dual comparator in a
50% duty cycle crystal oscillator. Output frequencies of up
to 10MHz are practical.
2k
bandwidth is low. Full-power bandwidth is 0.05Hz with a
slew rate of about 1V/s. Clock-related noise, about 5µV,
can be reduced by increasing CCOMP, with commensurate
bandwidth reduction.
600
400
200
0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
AN70 F52
Figure 154. Output Skew Varies Only
800ps Over a 2.7V–6V Supply Excursion
crystal’s path provides resonant positive feedback, and
stable oscillation occurs. The DC bias voltages at the
inputs are set near the center of the LT1720’s common
mode range and the 220Ω resistor attenuates the feedback
to the noninverting input. C2 creates a complementary
output by comparing the same two nodes with the opposite input polarity. A1 compares band-limited versions of
the outputs and biases C1’s negative input. C1’s only
degree of freedom to respond is variation of pulse width;
hence, the outputs are forced to 50% duty cycle. The
circuit operates from 2.7V to 6V and the skew between the
edges of the of the two outputs is as shown in Figure 154.
There is a slight duty-cycle dependence on comparator
loading, so equal capacitive and resistive loading should
be used in critical applications. This circuit works well
because of the two matched delays and rail-to-rail–style
outputs of the LT1720
1k
0.1µF
+
C2
1/2 LT1720
100k
OUTPUT
–
Figure 153. Crystal Oscillator has Complementary Outputs and
50% Duty Cycle. A1’s Feedback Maintains Output Duty Cycle
Despite Supply Variations
AN87-93
Application Note 87
for 100µs using the power stored on the isolated external
capacitor. A 4-input, dual-differential comparator samples
at the end of the reference pulse and transmits the result
back to the nonisolated side. The nonisolated, powered
side latches the result of the comparator and provides a
zero-cross comparator output for triggering a triac.
LTC1531 ISOLATED COMPARATOR
by Wayne Shumaker
Introduction
The LTC1531 is an isolated, self-powered comparator that
receives power and communicates through internal isolation capacitors. The internal isolation capacitors provide
3000VRMS of isolation between the comparator and its
output. This allows the part to be used in applications that
require high voltage isolated sensing without the need to
provide an isolated power source. The isolated side provides a 2.5V pulsed reference output that can deliver 5mA
AC
120V
LOAD
25Ω
The LTC1531 can be used to isolate sensors such as in the
isolated thermistor temperature controller in Figure 155.
In this circuit, a comparison is made between the voltages
across a thermistor and a resistor that is driven by the 2.5V
R1
680k
1N4004
TECCOR
Q4008L4
OR EQUIVALENT
NEUTRAL
Applications
C1
0.01µF
R2
47k
3k
3W
ISOLATION
BARRIER
RTHERM =
1µF RO • eB (1/T – 1/TO)
B = 3807
TO = 297°K
1
+
750Ω
0.5W
150Ω
VCC
1k
SHDN
ZCPOS
VPW
ZCNEG
2.5V
ZCDATA
2N2222
+
100µF
+
20µF
50V
DANGER!
LETHAL VOLTAGES
IN THIS SECTION!
390Ω
5.6V
DATA
T
LTC1531
THERM
30k
YSI 44008
V4
R4
50k
CMPOUT
GND
LED
–5.6V
–
VALID
V1
V2
V3
+
Q D
VREG
R5*
1M
ISOGND
R6
22k
1
1
1
1 = ISOLATED GROUND
*HYSTERESIS = 1°C AT TO
Figure 155. Isolated Thermistor Temperature Controller
+
ISOLATION
BARRIER
VCC
1M
2.2µF
LT1389
1.74M
10M
10.2k
VPW
2.5V
ZCDATA
VREG
V1
LT1495
V2
DATA
Q D
–
1.13k
10.7k
+
VTRIP
+
33k
THERM
30k
YSI 44008
–
SHDN
ZC + ZC –
–
VCC
V3
K
+
V4
VALID
LTC1531
ISOGND
–
GND
GAIN SET FOR 0°C TO 200°C
CMPOUT
LT1495
+
COLD JUNCTION COMPENSATES 0°C TO 60°C
OUTPUT, VTRIP = 1 AT ≥100°C
RESPONSE TIME = 10 sec
RESOLUTION = 4mV ≥ 0.5°C
Figure 156. Overtemperature Detect
AN87-94
1531 TA08
UNUSED
OP AMP
Application Note 87
VREG output. As the thermistor resistance rises with
temperature, the voltage across the thermistor increases.
When it exceeds the voltage across R4, the comparator
output becomes zero and the triac control to the heater is
turned off. Hysteresis can be added in the temperature
control by using CMPOUT and R5. A 10° phase-shifted AC
line signal is supplied through R1, R2 and C1 to the zerocross comparator for firing the triac.
In the overtemperature detect application in Figure 156, an
isolated thermocouple is cold junction compensated with
the micropower LT1389 reference and the Yellow Springs
thermistor. The micropower LT1495 op amp provides
gain to give an overall 0°C–200°C temperature range,
adjustable by changing the 10M feedback resistor. The
isolated comparator is connected to compare at 1.25V or
the center of the temperature range. In this case, VTRIP
goes high when the temperature exceeds 100°C.
The LTC1531 can use the high impedance nature of
CMPOUT as a duty-cycle modulator, as in the isolated
voltage sense application in Figure 157. The duty-cycle
output of the comparator is smoothed with the LT1490
rail-to-rail op amp to reproduce the voltage at VIN. The
output time constant, R2 • C2, should approximately equal
the input time constant, 35 • R1 • C1. The factor of 35
results from CMPOUT being on for only 100µs at an
average sample rate of 300Hz.
Conclusion
The LTC1531 is a versatile part for sensing signals that
require large isolation voltages. The ability of the LTC1531
to supply power through the isolation barrier simplifies
applications; it can be combined with other micropower
circuits in a variety of isolated signal conditioning and
sensing applications.
ISOLATION
BARRIER
VCC
R2
10M
RESOLUTION = 4mV
SETTLING TIME CONSTANT = 10 sec
+
VCC
C2, 1µF
SHDN
ZC
+
ZC –
2.5V
ZCDATA
VCC
–
VREG
VIN
0V TO 2.5V
FULL-SCALE
INPUT
V1
V2
DATA
+
Q D
–
V3
V4
VCC
LT1490
+
VOUT
0V – VCC
FULL-SCALE
OUTPUT
R3
10M
2.2µF
VPW
VALID
CMPOUT
10k
GND
LTC1531
10k
ISOGND
R1
1M
C1
0.22µF
1531 TA05
Figure 157. Isolated Voltage Detect
AN87-95
Application Note 87
Filters
Delay-Equalized Elliptic Filter
THE LTC1560-1: A 1MHz/500kHz CONTINUOUS-TIME,
LOW NOISE, ELLIPTIC LOWPASS FILTER
by Nello Sevastopoulos
Although elliptic filters offer high Q and a sharp transition
band, they lack a constant group delay in the passband,
which implies more ringing in the time-domain step
response. In order to minimize the delay ripple in the
passband of the LTC1560-1, an allpass filter (delay equalizer) is cascaded with the LTC1560-1, as shown in Figure
160. Figures 161 and 162 illustrate the eye diagrams
before and after the equalization, respectively.
Introduction
The LTC1560-1 is a high frequency, continuous-time, low
noise filter in an SO-8 package. It is a single-ended input,
single-ended output, 5th order elliptic lowpass filter with
a pin-selectable cutoff frequency (fC) of 1MHz or 500kHz.
An eye diagram is a qualitative representation of the timedomain response of a digital communication system. It
shows how susceptible the system is to intersymbol
interference (ISI). Intersymbol interference is caused by
erroneous decisions in the receiver due to pulse overlapping and decaying oscillations of a previous symbol. A
pseudorandom 2-level sequence has been used as the
input of the LTC1560-1 to generate these eye diagrams.
The larger eye opening in Figure 162 is an indication of the
equalization effect that leads to reduced ISI. Note that in
Figure 160, the equalizer section has a gain of 2 for driving
and back-terminating 50Ω cable and load. For a simple
unterminated gain-of-1 equalizer, the 40.2k resistor
changes to 20k and the 49.9Ω resistor is removed from
the circuit. The 22pF capacitors are 1% or 2% dipped silver
mica or COG ceramic.
The LTC1560-1 delivers accurate fixed cutoff frequencies
of 500kHz and 1MHz without the need for internal or
external clocks.
Applications and Experimental Results
The LTC1560-1 can be used as part of a more complete
frequency-shaping system. Two representative examples
follow.
Highpass-Lowpass Filter
As a typical application in communication systems, where
there is a need to reject DC and some low frequency
signals, a 2nd order RC highpass network can be inserted
in front of the LTC1560-1 to obtain a highpass-lowpass
response. Figures 158 and 159 depict the network and its
measured frequency response, respectively. Notice that
the second resistor in the highpass filter is the input
resistance of the LTC1560-1, which is about 8.1k.
10
0
–10
15V
300pF
300pF
VIN
8.1k
–5V
1
8
2
7
3
6
4
5
1k
+
(OR 5V)
7
LT1360
5V
0.1µF
0.1µF
3
2
–
–40
–50
–70
–80
1560_06.eps
0.01µF
0.1µF
–15V
AN87-96
VOUT
–30
–60
4
0.01µF
Figure 158. A Highpass-Lowpass Filter
8
GAIN (dB)
–20
0.1µF
LTC1560-1
–90
20
100
1000
FREQUENCY (kHz)
10000
1560_07.eps
Figure 159. Measured Frequency
Response of Figure 158’s Circuit
Application Note 87
Conclusion
The LTC1560-1 is a 5th order elliptic lowpass filter that
features a 10-bit gain linearity at signal ranges up to 1MHz.
Being small and user friendly, the LTC1560-1 is suitable
for any compact design. It is a monolithic replacement for
larger, more expensive and less accurate solutions in
communications, data acquisitions, medical instrumentation and other applications.
20k
22pF
40.2k
9.75k
LTC1560-1
1
VIN
–5V
8
2
7
3
6
4
5
6.49k
22pF
2
(OR 5V)
3
0.1µF
+
1/2 LT1364
5V
1
6.65k
6
–
0.01µF
+
8
1/2 LT1364
5
0.1µF
0.1µF
5V
–
49.9Ω
7
VOUT
1560_08.eps
4
0.1µF
0.01µF
–15V
Figure 160. Augmenting the LTC1560-1 for Improved Delay Flatness
Figure 161. 2-level Eye Diagram of the LTC1560-1
Before Equalization
Figure 162. 2-level Eye Diagram of the Equalized Filter
AN87-97
Application Note 87
THE LTC1067 AND LTC1067-50: UNIVERSAL 4TH
ORDER LOW NOISE, RAIL-TO-RAIL SWITCHED
CAPACITOR FILTERS
by Doug La Porte
Some LTC1067 and LTC1067-50 Applications
High Dynamic-Range Butterworth Lowpass Filter with
Built-In Track-and-Hold Challenges Discrete Designs
LTC1067 and LTC1067-50 Overview
The LTC1067 and the LTC1067-50 are universal, 4th order
switched capacitor filters with rail-to-rail operation. Each
part contains two identical, high accuracy, very wide
dynamic-range 2nd order filter building blocks. Each building block, together with three to five resistors, provides
2nd order filter transfer functions, including lowpass,
bandpass, highpass, notch and allpass. These parts can be
used to easily design 4th order or dual 2nd order filters.
Linear Technology’s FilterCAD™ for Windows® filter
design software fully supports designs with these parts.
The center frequency of each 2nd order section is tuned by
an external clock. The LTC1067 has a 100:1 clock-tocenter frequency ratio. The LTC1067-50’s clock-to-center
frequency ratio is 50:1.
Figure 163 shows an LTC1067 configured as a 5kHz
Butterworth lowpass filter. This circuit runs on a 3.3V
power supply and uses an external logic gate to stop the
clock for track-and-hold operation. The transfer function
for this circuit, shown in Figure 164, is the classical
Butterworth response. This circuit can be used with either
the LTC1067 or the LTC1067-50. The broad-band noise for
the LTC1067 circuit is 45µVRMS and the DC offset is
typically less than 10mV. For the LTC1067-50, the broadband noise is 55µVRMS and the DC offset is typically less
than 15mV.
This circuit has tremendous dynamic range, even on low
supply voltages. Figure 165 shows a plot of the LTC1067’s
signal-to-noise plus total harmonic distortion (SINAD) vs
input signal level for a 1kHz input at three different power
supply voltages. SINAD is limited for small signals by the
noise floor of the LTC1067, for medium signals by the
part’s linearity and for large signals by the output signal
swing. The part’s low noise input stage and excellent
linearity allow the SINAD to exceed 80dB for signals as
small as 700mVP-P, while the rail-to-rail output stage
maintains this level for input signals approaching the
CMOS LOGIC GATE
3.3V
0.1µF
2
3
4
R41, 40.2k
R31, 49.9k
R21, 40.2k
VIN
R11
52.3k
5
6
7
8
V+
CLK
NC
AGND
V+
V–
SA
SB
LTC1067
LPA
LPB
BPA
BPB
HPA
HPB
INV A
INV B
16
500kHz
15
TRACK HOLD
14
10.000
0
–10.00
1µF
–20.00
13
12
GAIN (dB)
1
R42, 76.8k
11
R32, 40.2k
10
R22, 76.8k
–30.00
–40.00
–50.00
–60.00
–70.00
9
–80.00
VOUT
RL1, 59k
1067_03.EPS
–90.00
1k
10k
FREQUENCY (Hz)
100k
1067_04.EPS
Figure 163. High Dynamic-Range Butterworth LPF with Track-and-Hold Control
AN87-98
Figure 164. Transfer Function of the
LTC1067 5kHz Butterworth LPF
–50.00
–50.00
–55.00
–55.00
VSUPPLY = ±5V
–60.00
(NOISE + THD)/SIGNAL (dB)
(NOISE + THD)/SIGNAL (dB)
Application Note 87
VSUPPLY = 5V
–65.00
VSUPPLY = 3.3V
–70.00
–75.00
–80.00
–85.00
–90.00
VSUPPLY = ±5V
VSUPPLY = 5V
–60.00
VSUPPLY = 3.3V
–65.00
–70.00
–75.00
–80.00
–85.00
–90.00
–95.00
–95.00
–100.00
–100.00
0.1
1
INPUT VOLTAGE (Vp-p)
10
0.1
1
INPUT VOLTAGE (VP-P)
10
1067_06.EPS
1067_05.EPS
Figure 165. Dynamic Range of LTC1067 Butterworth LPF
Figure 166. Dynamic Range of LTC1067-50 Butterworth LPF
supply rails. Previous parts could not attain this high
dynamic range due to higher input noise levels, poor
linearity and limited output-stage signal swing. The low
noise and rail-to-rail output swing are especially crucial on
the lower 3.3V power supply, where every bit of detectable
signal range is precious. Figure 166 shows the same plot
for the LTC1067-50 circuit. The dynamic range is not quite
equal to that of the LTC1067, but is still very good. Recall
that, for the same clock frequency, the LTC1067-50 based
filter has double the bandwidth and half the supply current
of the LTC1067.
–100µV and the droop rate is less than –50µV/ms over the
full temperature range. These numbers compare very
favorably with dedicated track-and-hold amplifiers. When
the clock is restarted, the filter resumes normal operation
within ten clock cycles and the output will then correctly
reflect the input as soon as the filter’s mathematical
response allows.
Elliptic Lowpass Filter
The LTC1067 family is capable of much more challenging
filters. Figure 167 shows the schematic for a 25kHz elliptic
lowpass filter using the LT1067-50 operating on a 5V
supply. Maximum attenuation one octave from the –3dB
corner is the design goal for this filter. Figure 168 shows
the frequency response of the filter with the –3dB cutoff at
The LTC1067 and LTC1067-50 also perform a track-andhold function. Stopping the clock holds the output of the
filter at its last value. The LTC1067 is the best performing
part in this area. The LTC1067’s hold step is less than
1
5V
2
0.1µF
3
R61, 48.7k
4
R51
4.99k
R31, 49.9k
R21, 20k
R11
53.6k
VIN
5
6
7
8
V+
CLK
NC
AGND
+
V
V–
SA
SB
LTC1067-50
LPA
LPB
BPA
BPB
HPA
HPB
INV A
INV B
RH1, 93.1k
RL1, 25.5k
16
1.25MHz
15
14
13
1µF
R62, 6.04k
R52
12 4.99k
11
R32, 21k
10
R22, 24.9k
RG, 21k
9
RH2, 487k
RL2, 20k
–
1/2 LT1498
+
VOUT
1067_07.EPS
Figure 167. 25kHz Elliptic Lowpass Filter
AN87-99
Application Note 87
10.000
1
0
2
–10.00
GAIN (dB)
–20.00
3
3.3V
–30.00
4
0.1µF
–40.00
5
–50.00
R31, 200k
6
R21, 10k
7
–60.00
–70.00
R11
200k
–80.00
8
IN
V+
CLK
NC
AGND
V+
V–
LTC1067
SA
SB
LPA
LPB
BPA
INV A
–90.00
1k
10k
FREQUENCY (Hz)
BPB
HPA/NA HPB/NB
INV B
16
fCLK = 500kHz
15
1µF
14
13
12
OUT
11
R32, 200k
10
R22, 10k
9
R12, 200k
100k 200k
1067_09.eps
1067_08.EPS
Figure 168. Transfer Function of LTC1067-50 25kHz LPF
Figure 169. Low Noise, Low Voltage Narrow BPF
25kHz and –48dB of attenuation at 50kHz. The broad-band
noise of the filter is 85µVRMS and the DC offset is less than
15mV typically.
To achieve success in designing narrow-band bandpass
filters, you must start with precision components. In an LC
or RC design, you would have to start with 0.1% resistors,
1% inductors and 1% capacitors to have any hope of
finishing with a successful, repeatable design in production. A competing solution, a digital filter implementation,
also requires precision components. The full input signal
(signal, noise and out-of-band interference) must be correctly digitized and then processed with a DSP device to
finally determine the tone’s presence. If an out-of-band
interfering signal is 20dB greater than the desired tone, the
ADC must have an extra 20dB of dynamic range above the
signal’s requirement. To pull a small-signal tone from a
large signal interferer, you may need a 16-bit ADC to
digitize the signal just to get 12-bit resolution of the tone
after processing. The added cost, power, board space and
development time make this approach unattractive.
Narrow-Band Bandpass Filter Design
Extracts Small Signals Buried in Noise
Narrow-band bandpass filters are difficult to design but
are easily achievable with these parts. Most applications
for these filters involve extracting a low level signal from
a noisy environment. The noise may be the standard
broad-band, Gaussian-type noise or it may consist of
multiple interfering signals. For example, the signal may
be a low level tone or a narrow-bandwidth modulated
signal, in a voice-band system. The presence of the tone
must be detected even while the large voice signals are
present. A narrow-band bandpass filter will allow the tone
to be separated and detected even in this hostile environment. Numerous systems also require a narrow bandpass
filter to be swept across a band looking for the tones.
Switched capacitor filters allow the filter to be swept by
simply changing the clock frequency.
AN87-100
0
–10
GAIN (dB)
Although Figure 167 shows the filter powered by a single
5V supply, 3.3V or ±5V supply operation is also supported.
The maximum cutoff frequency is 15kHz for the 3.3V
supply and 35kHz for the ±5V supply. The same design and
schematic used with an LTC1067 will achieve a somewhat
lower noise, lower DC-offset filter. With the LTC1067, the
broad-band noise is 70µVRMS and the DC offset is typically
less than 10mV. The maximum operating frequencies for
the LTC1067 are one half of those for the LTC1067-50.
–20
–30
–40
4.0
4.5
5.0
5.5
6.0
FREQUENCY (kHz)
1067_10.eps
Figure 170. Frequency Response of Narrow BPF
Application Note 87
A precision switched capacitor filter provides a simple,
small, low power, repeatable, inexpensive solution. The
older MF-10-type parts do not have the necessary fO
accuracy to achieve a reliable, repeatable design. Figure
169 shows the schematic of a narrow-band bandpass filter
centered at 5kHz. The design uses two identical cascaded
sections, each with a Q of 20. Multiply the individual Q of
each section by 1.554 to calculate the total Q of a filter with
two identical fO, identical Q sections. This filter has a total
Q of 31. For tunable filter applications, simply lowering the
clock frequency lowers the center frequency of the filter.
Figure 170 shows the frequency response of this filter. The
broad-band noise of this filter is only 90µVRMS. Highly
selective bandpass filters are possible due to the LTC1067’s
excellent fO accuracy.
Higher Q, narrower bandwidth filters are achievable with
0.1% resistors or matched resistor networks. An LTC1067
mask-programmed part is ideal for these ultranarrow
filters. The well matched, on-chip resistors, coupled with
specified test conditions, yield a fully functioning filter
module, in an SO-8 package, without any of the hassles or
cost of procuring precision resistors or resistor networks.
1
5V
0.1µF
2
V+
CLK
NC
AGND
V+
V–
16
200Ω
fCLK = 125kHz
15
1µF
3
R51*
4.99k
R32
61.9k
R21
10k
4
5
6
7
LTC1067
SA
SB
LPA
LPB
BPA
HPA/NA
C21**
300pF
R11
18.7k
VIN***
BPB
HPB/NB
13
R62*
10k
12
R52*
4.99k
11
R32
464k
10
INV A
INV B
0
R22
75k
–30
RH1
40.2k
–40
–50
–60
–70
1067_11.eps
* R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORS
** C21 AND C22 IMPROVE THE NOTCH DEPTH WHERE
1
(30)(f NOTCH) <
< (75)(f NOTCH) WITHOUT
2π(R2X)(C2X)
C21 AND C22 THE NOTCH DEPTH IS LIMITED TO –35dB
Figure 171. Narrow-Band Notch Filter
–10
–20
9
*** VIN ≤ 1.25VP-P
One of the challenges of designing a switched capacitor
notch filter involves the broad-band nature of a notch filter.
The broad-band noise can be aliased down into the band
of interest. Optimal high performance notch filters should
employ some form of noise-band limiting. To accomplish
the noise-band limiting, the design in Figure 171 places
capacitors in parallel with the R2 resistors of each 2nd
order section. This forms a pole, set at fP = 1/
(2 • π • R2 • C2), that will limit the bandwidth. This pole
frequency must be low enough to have a band-limiting
effect but must not be so low as to affect the notch filter’s
response. The pole should be greater than thirty times the
notch frequency and less than seventy-five times the
notch frequency for the best results. Figure 172 shows the
frequency response of the filter. Note that the notch depth
is greater than –80dB. Without the use of the C21 and C22,
the notch depth is only about –35dB.
VOUT
C22**
30pF
8
Narrow-band notch filters are especially challenging designs. The requirement for most notch filters is to remove
a particular tone and not affect any of the remaining signal
bandwidth. This requires an infinitesimally narrow filter
that can only be approximated by a reasonably narrow
bandwidth. These types of filters, like the narrow-band
bandpass discussed above, require precision fO accuracy.
Figure 171 shows the schematic of this type of filter. This
filter is a 1.02kHz notch filter that is often used in telecommunication test systems.
GAIN (dB)
R61*
9.88k
14
Narrow-Band Notch Filter Design
Reaches 80dB Notch Depth
–80
–90
–100
800
900
1000
1100
FREQUENCY (Hz)
1200
LT1067_12.eps
Figure 172. Measured Frequency Response
of Figure 171’s Narrow-Band Notch Filter
AN87-101
Application Note 87
UNIVERSAL CONTINUOUS-TIME FILTER
CHALLENGES DISCRETE DESIGNS
by Max Hauser
The LTC1562 is the first in a new family of tunable, DCaccurate, continuous-time filter products featuring very
low noise and distortion. It contains four independent 2nd
order, 3-terminal filter blocks that are resistor programmable for lowpass or bandpass functions up to 150kHz,
and has a complete PC board footprint smaller than a
dime. Moreover, the part can deliver arbitrary continuoustime pole-zero responses, including highpass, notch and
elliptic, if one or more programming resistors are replaced
with capacitors. The center frequency (f0) of the LTC1562
is internally trimmed, with an absolute accuracy of 0.5%,
and can be adjusted independently in each 2nd order
section from 10kHz to 150kHz by an external resistor.
Other features include:
❏ Rail-to-rail inputs and outputs
❏ Wideband signal-to-noise ratio (SNR) of 103dB
❏ Total harmonic distortion (THD) of –96dB at 20kHz,
–80dB at 100kHz
❏ Built-in multiple-input summing and gain features;
capable of 118dB dynamic range
❏ Single- or dual-supply operation, 4.75V to 10.5V total
❏ “Zero-power” shutdown mode under logic control
❏ No clocks, PLLs, DSP or tuning cycles required
The LTC1562 provides eight poles of programmable continuous-time filtering in a total surface mount board area
(including the programming resistors) of 0.24 square
The practical circuit in Figure 173 is a dual lowpass filter
with a Butterworth (maximally-flat-passband) frequency
response. Each half gives a DC-accurate, unity-passbandgain lowpass response with rail-to-rail input and output.
With a 10V total power supply, the measured output noise
for one filter is 36µVRMS in a 200kHz bandwidth, and the
large-signal output SNR is 100dB. Measured THD at
1VRMS input is –83.5dB at 50kHz and –80dB at 100kHz.
Figure 174 shows the frequency response of one filter.
8th Order 30kHz Chebyshev Highpass Filter
Figure 175 shows a straightforward use of the highpass
configuration. Each of the four cascaded 2nd order sections
has an external capacitor in the input path. The resistors in
Figure 175 set the f0 and Q values of the four sections to
realize a Chebyshev (equiripple-passband) response with
0.05dB ripple and a 30kHz highpass corner. Figure 176
shows the frequency response. Total output noise for this
circuit is 40µVRMS.
2
3
5
5V
0.1µF
6
R23, 10k
8
9
RQ3, 5.62k
V– ALSO AT PINS 4, 7, 14 &17
ALL RESISTORS 1% METAL FILM
10
INV B
INV C
V1 B
V1 C
V2 B
V2 C
V–
V + LTC1562
SHDN
AGND
V2 A
V2 D
V1 A
V1 D
INV A
INV D
20
–10
18 R22, 10k
VOUT2
–5V
16
0.1µF
15
VOUT1
13
–20
–30
–40
12 R24, 10k
–50
RQ4, 13k
–60
11
RIN4, 10k
Figure 173. Dual, Matched 4th Order
100kHz Butterworth Lowpass Filter
AN87-102
0
19 RQ2, 13k
GAIN (dB)
R21, 10k
VIN1
Dual 4th Order 100kHz Butterworth Lowpass Filter
10
1
RQ1, 5.62k
RIN3
10k
Each of the four 3-terminal Operational Filter™ building
blocks in an LTC1562 has a virtual ground input, INV, and
two outputs, V1 and V2. These are described in detail in the
LTC1562 data sheet.
RIN2, 10k
RIN1
10k
VIN2
inches (155 mm2 )—smaller than a U.S. 10-cent coin. This
filter can also replace op amp–R-C active filter circuits and
LC filters in applications requiring compactness, flexibility, high dynamic range or fewer precision components.
–70
–80
10k
100k
FREQUENCY (Hz)
1M
Figure 174. Frequency Response of Figure 173’s Circuit
1562 TA02
Application Note 87
CIN2 24pF
TO CIN3
CIN1
150pF
1
CIN
RQ1, 10.2k
2
R21, 35.7k
3
5
5V
0.1µF
6
8
CIN3
150pF
FROM
HP C
R23, 107k
9
RQ3, 54.9k
10
INV B
NV C
V1 B
V1 C
V2 B
V2 C
V + LTC1562
V
RIN2 37.4k
20
19
RQ2, 22.1k
18
R22, 66.5k
AGND
V2 A
V2 D
V1 A
V1 D
INV A
INV D
1
VIN
RQ1 30.1k
– 16
SHDN
CIN2
150pF
RIN1
48.7k
–5V
R21 31.6k
0.1µF
15
13
R24, 127k
11
RQ4, 98.9k
CIN4
150pF
0.1µF
6
R23 31.6k
8
RQ3 34k
V– ALSO AT PINS 4, 7, 14 &17; ALL RESISTORS 1% METAL FILM
9
VOUT
1562 TA08
Figure 175. 8th Order Chebyshev Highpass
Filter with 0.05dB Ripple (fCUTOFF = 30kHz)
50kHz, 100dB Elliptic Lowpass Filter
10
20
V1B
V+
V–
SHDN
AGND
V2A
V2D
V1A
V1D
INVA
INVD
16
15
13
– 5V
0.1µF
R24 32.4k
VOUT
12
11 RQ4 11.5k
RIN4 32.4k
RIN3 31.6k
CIN3 18pF
Figure 177 illustrates how sharp-cutoff filtering can exploit
the Operational Filter capabilities of the LTC1562. In this
design, external capacitors are added and the virtualground inputs of the LTC1562 sum parallel paths to obtain
three notches in the stopband of a lowpass filter, as plotted
in Figure 178. This response falls 100dB in a little more
than one octave; the total output noise is 60µVRMS with the
rail-to-rail output for a peak SNR of 95dB from ±5V
supplies.
INVC
19 RQ2 13k
LTC1562 V1C
20-PIN SSOP
3
18 R22 57.6k
V2C
V2B
2
5
5V
12
INVB
V– ALSO AT PINS 4, 7, 14 &17
ALL RESISTORS 1% METAL FILM CIN4 10pF
Figure 177. 50kHz Elliptic Lowpass Filter
with 100dB Stopband Rejection
lowpass filters can be built from one LTC1562. The same
technique can add additional real poles to other filter
configurations as well, for example, augmenting Figure
173’s circuit to obtain a dual 5th order filter from a single
LTC1562.
Conclusion
Quadruple 3rd Order 100kHz Butterworth Lowpass Filter
Another example of the flexibility of the virtual-ground
inputs is the ability to add an extra, independent real pole
with an R-C-R “T” network. In Figure 179, a 10k input
resistor has been split into two parts and the parallel
combination of the two forms a 100kHz real pole with the
680pF external capacitor. Four such 3rd order Butterworth
The LTC1562 is the first truly compact universal active
filter, yet it offers instrumentation-grade performance
rivaling much larger discrete-component designs. It serves
applications in the 10kHz–150kHz range with an SNR as
high as 100dB or more (16+ equivalent bits). The LTC1562
is ideal for modems and other communications systems
and for DSP antialiasing or reconstruction filtering.
10
20
0
0
–10
–20
–30
GAIN (dB)
GAIN (dB)
–20
–40
–50
–60
– 40
– 60
–80
–70
–100
–80
–90
1k
10k
100k
FREQUENCY (Hz)
1M
–120
10
100
FREQUENCY (kHz)
500
1562 TA09
Figure 176. Frequency Response of Figure 175’s Circuit
Figure 178. Frequency Response of Figure 177’s Circuit.
AN87-103
Application Note 87
RIN1A
6.19k
RIN1B
3.83k
1
VIN1
RQ1, 10k
CIN1
680pF
VOUT1
R21, 10k
3
5
5V
0.1µF
RIN3B
3.83k
RIN3A
6.19k
RQ3, 10k
CIN3
680pF
ALL RESISTORS = 1% METAL FILM
8
9
VIN3
V1 B
V1 C
V2 B
V2 C
V + LTC1562
6
R23, 10k
INV C
IINV B
2
10
V–
SHDN
AGND
V2 A
V2 D
V1 A
V1 D
INV A
INV D
RIN2B
3.83k
20
19
18
RIN2A
6.19k
RQ2, 10k
R22, 10k
16
VIN2
CIN2
680pF
VOUT2
–5V
0.1µF
15
13
12
R24, 10k
11
RQ4, 10k
VOUT3
RIN4B
3.83k
RIN4A
6.19k
VIN4
CIN4
680pF
VOUT4
1562 TA07
Figure 179. Quad 3-Pole 100kHz Butterworth Lowpass Filter
HIGH CLOCK-TO-CENTER FREQUENCY RATIO
LTC1068-200 EXTENDS CAPABILITIES OF SWITCHED
CAPACITOR HIGHPASS FILTER
by Frank Cox
sums and differences of the clock and the input, in addition
to sums and differences of their harmonics. The input of
the filter must be band limited to remove frequencies that
will mix with the clock and end up in the passband of the
filter. Unfortunately, the passband of a highpass filter
extends upward in frequency by its very nature. If you have
to band limit the input signal too much you will also limit
the passband of the filter, and hence its usefulness.
The circuit in Figure 180 is a 1kHz 8th order Butterworth
highpass filter built with the LTC1068-200, a switched
capacitor filter (SCF) building block. In the past, commercially available switched capacitor filters have had limited
use as highpass filters because of their sampled-data
nature. Sampled-data systems generate spurious frequencies when the sampling clock of the filter and the
input signal mix. These spurious frequencies can include
What makes this filter different is the 200:1 clock-to-center
frequency ratio (CCFR) and the internal sampling scheme
of the LTC1068-200. Figure 181a shows the amplitude
response of the filter plotted against frequency from
RH2 10k
RH3 1.47k
LTC1068-200
1
VIN
R11 10k
R21 20k
2
R31 10k
3
4
R41 20k
5
6
7
8
5V
9
0.1µF
10
R43 11.3k
11
R33 10k
12
13
R23 11.3k
14
INV C
INV B
HPB/NB
HPC/NC
28
27
BPB
BPC
LPB
LPC
SB
SC
NC
23
V–
AGND
NC
V+
CLK
NC
NC
SA
SD
LPA
LPD
BPA
BPD
HPA/NA
HPD/ND
INV D
INV A
R22 10k
26 R32 24.3k
25
24
R42 10k
–5V
22
0.1µF
21
20
19
18
17
200kHz
R44 16.9k
R34 10k
16
15
R24 16.9k
RH4 14.7k
Figure 180. LTC1068-200 1kHz 8th Order Butterworth Highpass Filter
AN87-104
VOUT
Application Note 87
100Hz to 10kHz. For comparison, Figure 181b shows the
same filter built with an LTC1068-25. This is a 25:1 CCFR
part. The 200:1 CCFR filter delivers almost 30dB more
ultimate attenuation in the stopband. A standard amplitude vs frequency plot of a highpass filter can be misleading because it masks some of the aforementioned spurious signals introduced into the passband. Figure 182a is
a spectrum plot of the 200:1 filter with a single 10kHz tone
on the input. This plot shows that the spurious free
dynamic range (SFDR) of the LTC1068 highpass filter is in
excess of 70dB. In fact, the filter has a 70dB SFDR for all
input signals up to 100kHz. In a 200kHz sampled-data
system, you would normally need to band limit the input
below 100kHz, the Nyquist frequency. Because the
LTC1068 uses double sampling techniques, its useful
input frequency range extends to the Nyquist frequency
Note:
The filters for this article were designed using Linear Technology’s FilterCAD™ (version 2.0) for Windows®. This program made the design and
optimization of these filters fast and easy.
100Hz
10kHz
5kHz
100Hz
10dB/DIV
–10dB
10dB/DIV
–10dB
10dB/DIV
–10dB
and even above, albeit with some care. Figure 182b shows
the LTC1068-200 highpass filter with an input frequency
of 150kHz. There is a spurious signal at 50kHz, but even
though there is no input filtering, the SFDR is still 60dB.
For input signals from 100kHz to 150kHz, the filter demonstrates an SFDR of at least 60dB. The SFDR plot of the
same filter built with the LTC1068-25 is shown in Figure
183. Note that the lower CCFR (25:1) part still manages a
respectable 55dB SFDR with a 10kHz input. The LTC106825 is used primarily for band-limited applications, such as
lowpass and bandpass filters.
5kHz
10kHz
200Hz
100kHz
200kHz
DI_1068_02a. EPS
Figure 181a. Amplitude vs
Frequency Response of Figure
180’s Circuit
DI_1068_02b. EPS
Figure 181b. Amplitude vs Frequency
Response of Comparable Filter Using
the LTC1068-25
–10dB
–10dB
10dB/DIV
10dB/DIV
200Hz
Figure 182a. Spectrum Plot of
Figure 180’s Circuit with a Single
10kHz Input
DI_1068_03a. EPS
100kHz
200kHz
DI_1068_03b. EPS
Figure 182b. Spectrum Plot of Figure
180’s Circuit with a Single 150kHz Input
100Hz
12.5kHz
25kHz
Figure 183. Spectrum Plot of a Comparable Filter
Using the LTC1068-25 with a Single 10kHz Input
Shows a Respectable 55dB SFDR.
DI_1068_04. EPS
AN87-105
Application Note 87
power filter applications, the LTC1068-50 power supply
current is 4.5mA with a single 5V supply and 2.5mA with
a single 3V supply. The LTC1068 products are available in
a 28-pin SSOP surface mount package. The LTC1068 (the
100:1 part) is also available in a 24-pin DIP package.
CLOCK-TUNABLE, HIGH ACCURACY, QUAD 2ND
ORDER, ANALOG FILTER BUILDING BLOCKS
by Philip Karantzalis
Introduction
The LTC1068 product family consists of four monolithic,
clock-tunable filter building blocks. Each product contains
four matched, low noise, high accuracy 2nd order switched
capacitor filter sections. An external clock tunes the center
frequency of each 2nd order filter section. The LTC1068
products differ only in their clock-to-center frequency
ratio. The clock-to-center frequency ratio is set to 200:1
(LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or
25:1 (LTC1068-25). External resistors can modify the
clock-to-center frequency ratio. Designing filters with an
LTC1068 product is fully supported by the FilterCAD 2.0
design software for Windows. The internal sampling rate
of all the LTC1068 devices is twice the clock frequency.
This allows the frequency of input signals to approach
twice the clock frequency before aliasing occurs. Maximum clock frequency for LTC1068-200, LTC1068 and
LTC1068-25 is 6MHz with ±5V supplies; that for the
LTC1068-50 is 2MHz with a single 5V supply. For low
RL1 23.2k
LTC1068-200 Ultralow Frequency
Linear-Phase Lowpass Filter
Figure 184 shows an LTC1068-200 linear-phase 1Hz
lowpass filter schematic and Figure 185 shows its gain
and group delay responses. The clock frequency of this
filter is 400 times the –3dB frequency (f–3dB or fCUTOFF).
The large clock-to-fCUTOFF frequency ratio of this filter is
useful in ultralow frequency filter applications when minimizing aliasing errors could be an important consideration. For example, the 1Hz lowpass filter shown in Figure
184 requires a 400Hz clock frequency. For this filter, the
input frequencies that can generate aliasing errors are in
a band from 795Hz to 805Hz (2 • fCLK ±5 • f–3dB). For most
very low frequency signal-processing applications, the
signal spectrum is less than 100Hz. Therefore, Figure
184’s filter will process very low frequency signals without
significant aliasing errors, since its clock frequency is
400Hz and the aliasing inputs are in a small band around
800Hz.
RL2 14.3k
LTC1068-200
VIN
R11 14.3k
2
R31 10k
3
4
R41 15.4k
5
6
7
5V
0.1µF
9
10
R43 12.4k
R33 12.4k
11
12
13
R23 10k
14
HPB/NB
HPC/NC
BPB
BPC
LPB
LPC
SC
SB
NC
V–
AGND
NC
+
CLK
V
NC
NC
SD
SA
LPD
LPA
BPD
BPA
HPA/NA
HPD/ND
INV D
INV A
28
27
26
25
R22 15.4k
R32 10k
R52 5.11k
R62 9.09k
24
23
–5V
GAIN
–10
0.1µF
R64 9.09k
21
20
400kHz
R54 5.11k
19
18
VOUT
17
15
0.9
0
22
16
1.0
10
R34 10k
R24 15.4k
0.8
–20
0.7
–30
0.6
0.5
–40
GROUP
DELAY
–50
0.4
–60
0.3
–70
0.2
–80
0.1
0.0
–90
RB3 23.2k
0.1
1
FREQUENCY (Hz)
10
RL3 23.2k
Figure 184. Linear-Phase Lowpass Filter: f–3dB = 1Hz = fCLK/400
AN87-106
Figure 185. Gain and Group Delay
Response of Figure 184’s Circuit.
GROUP DELAY (s)
8
INV C
INV B
GAIN (dB)
1
R21 12.4k
Application Note 87
LTC1068-50 Single 3.3V Low Power
Linear-Phase Lowpass Filter
LTC1068-25 Selective Bandpass Filter
is Clock Tunable to 80kHz
Figure 186 is a schematic of an LTC1068-50-based, single
3.3V, low power, lowpass filter with linear phase. The
clock-to-fCUTOFF ratio is 50 to 1 (fCUTOFF is the –3dB
frequency). Figure 187 shows the gain and group delay
response. The flat group delay response in the filter’s
passband implies a linear phase. A linear-phase filter has
a transient response with very small overshoot that settles
very rapidly. A linear-phase lowpass filter is useful for
processing communication signals with minimum
intersymbol interference in digital communications transmitters or receivers. The maximum clock frequency for
this filter is 1MHz with a single 3.3V supply and 2MHz with
a single 5V supply. Typical power supply current is 3mA
with a single 3.3V supply and 4.5mA with a single 5V
supply.
Figure 188 shows a 70kHz bandpass filter based on the
LTC1068-25 operating with dual 5V power supplies. The
clock-to-center frequency ratio is 25 to 1. Figure 189
shows the gain response of Figure 188’s bandpass filter.
The passband of this filter extends from 0.95 • fCENTER to
1.05 • fCENTER. The stopband attenuation is greater than
40dB at 0.8 • fCENTER and 1.15 • fCENTER. The center
frequency can be clock tuned to 80kHz with dual 5V
supplies and to 40kHz with a single 5V supply. With
FilterCAD, the LTC1068-25 can be used to realize bandpass filters less selective than that shown in Figure 188,
which can be clock tuned up to 160kHz with dual 5V
supplies.
RA1 56.2k
RL2 9.09k
RB1 13.3k
RH2 34k
LTC1068-50
R21 20.5k
VIN
R11 22.6k
R31 10k
2
3
4
5
6
7
8
3.3V
9
0.1µF
10
1µF
R43 48.7k
11
R33 12.7k
12
13
R23 10.7k
14
HPB/NB
HPC/NC
BPB
BPC
LPB
LPC
SB
SC
NC
V–
NC
AGND
V+
CLK
NC
NC
SA
SD
LPA
LPD
BPA
BPD
HPA/NA
HPD/ND
INV D
INV A
28
27
150
10
R22 43.2k
140
0
26
25
24
R32 43.2k
–10
R42 196k
–20
23
22
21
500kHz
20
GAIN
130
120
110
–30
GROUP
DELAY
–40
100
–50
90
–60
90
–70
70
GROUP DELAY (µs)
R41 22.6k
INV C
INV B
GAIN (dB)
1
19
18
R44 34.8k
17
16
15
60
–80
1k
R34 14.3k
10k
FREQUENCY (Hz)
100k
R24 16.9k
VOUT
RB3 24.9k
Figure 187. Gain and Group Delay
Response of Figure 186’s Filter
RL3 26.7k
Figure 186. Low Power, Single 3.3V Supply,
10kHz, 8th Order, Linear-Phase Lowpass Filter
AN87-107
Application Note 87
RL2 23.2k
RH1 28k
10
RH2 11.3k
LTC1068-25
R11
29.4k
VIN
R21 4.99k
2
R31 24.9k
3
4
R41 20.5k
R51 4.99k
R61 11.3k
5
6
7
8
5V
0.1µF
9
10
R43 42.3k
11
R33 59k
12
13
R23 4.99k
14
INV C
INV B
HPB/NB
HPC/NC
BPC
BPB
LPC
LPB
SB
SC
NC
–
V
NC
AGND
+
CLK
V
NC
NC
SA
SD
LPA
LPD
BPA
BPD
HPA/NA
HPD/ND
INV D
INV A
0
–10
28
R22 4.99k
27
26
–20
R32 107k
GAIN (dB)
1
25
24
R62 56.2k
R52 4.99k
23
22
0.1µF
1.75MHz
–70
–80
–90
R54
4.99k
18
16
–50
–60
R64 10k
19
17
–40
–5V
21
20
–30
20
30
40
50 60 70 80
FREQUENCY (kHz)
90
100
R44 17.4k
R34 63.4k
15
Figure 189. Gain Response
of Figure 188’s Filter
R24 7.5k
RH3 15.4k
VOUT
RL3 45.3k
Figure 188. 70kHz, 8th order, Bandpass Filter
LTC1068 Square-Wave-to-Quadrature Oscillator Filter
Figure 190 shows the schematic of a LTC1068 based filter
that is specifically designed to produce a low harmonic
distortion sine and cosine oscillator from a CMOS-level
square wave input. The reference sine wave output of
Figure 190’s circuit is on pin 15 (BPD on the 24-pin
LTC1068 package) and the cosine output is on pin 16
(LPD on the 24-pin LTC1068 package). The output frequency of this quadrature oscillator is the filter’s clock
frequency divided by 128. The output of a CMOS CD4520
divide-by-128 counter is coupled with a 0.47µF capacitor
to the input to the LTC1068 filter operating with dual 5V
power supplies. The filter’s clock frequency is the input to
the CD4520 counter. The LTC1068 filter is designed to
pass the fundamental frequency component of a square
wave and attenuate any harmonic components higher
than the fundamental. An ideal square wave (50% duty
cycle) will have only odd harmonics (3rd, 5th, 7th and so
on), whereas a typical practical square wave has a duty
AN87-108
cycle less or more than 50% and will also have even
harmonics (2nd, 4th, 6th and so on). The filter of Figure
190 has a stopband notch at the 2nd and 3rd harmonics for
a square wave input with a frequency equal to the filter’s
clock frequency divided by 128. The filter’s sine wave
output (pin 15) is 1VRMS for a ±2.5V square wave input and
has less than 0.025% THD (total harmonic distortion) for
input frequencies up to 16kHz and less than 0.1% THD for
frequencies up to 20kHz. The cosine output (on pin 16,
referenced to pin 15’s sine wave output) is 1.25VRMS for
a ±2.5V square wave input and has less than 0.07% THD
for frequencies up to 20kHz.
The 20kHz frequency limit is due to the CD4520; with a
74HC type divide-by-128 counter, sine and cosine waves
up to 40kHz can be generated with the LTC1068-based
filter of Figure 190.
Application Note 87
RL2 12.4k
RL1 12.4k
RH2 55.2k
LTC1068
1
R11 22.4k
R21 10k
2
R31 12.4k
3
4
0.47µF
5
6
7
5V
0.1µF
8
9
R33 12.4k
10
R23 10k
11
12
INV C
INV B
HPB/NB
HPC/NC
BPB
BPC
LPB
LPC
SB
SC
AGND
V–
V+
CLK
SA
SD
LPA
LPD
BPA
BPD
HPD
HPA/NA
INV D
INV A
24
23
R22 10k
22
21
20
19
R32 12.4k
–5V
0.1µF
18
17
*COSINE WAVE OUT
16
15
R34 10k
*SINE WAVE OUT
f
fOUT = CLK
128
14
13
R24 10k
RH3 38.4k
RL3 16.5k
fCLK =
128 × fOUT
1
2
1Q0
CLK
1Q1
16
5V
1Q2
10
0.1µF
7
8
9
15
CD4520
GND
1Q3
2Q0
2Q1
2Q2
2Q3
3 ÷2
4 ÷4
* PIN 16'S COSINE WAVE OUTPUT IS REFERENCED TO
PIN 15'S SINE WAVE OUTPUT
5 ÷8
6 ÷16
11 ÷32
12 ÷64
13 ÷128
14 ÷256
Figure 190. Square-Wave-to-Quadrature Oscillator Converter
AN87-109
Application Note 87
Miscelleaneous
BIASED DETECTOR YIELDS HIGH SENSITIVITY WITH
ULTRALOW POWER CONSUMPTION
by Mitchell Lee
RF ID tags, circuits that detect a “wake-up” call and return
a burst of data, must operate on very low quiescent current
for weeks or months, yet have enough battery power in
reserve to answer an incoming call. For smallest size, most
operate in the ultrahigh frequency range, where the design
of a micropower receiver circuit is problematic. Familiar
techniques, such as direct conversion, super regeneration
or superheterodyne, consume far too much supply current for long battery life. A better method involves a
technique borrowed from simple field-strength meters: a
tuned circuit and a diode detector.
Figure 191 shows the complete circuit, which was tested at
470MHz. It contains a couple of improvements over the
standard L/C-with-whip field-strength meter. Tuned circuits
aren’t easily constructed or controlled at UHF, so a transmission line is used to match the detector diode (1N5711)
to a 6" whip antenna. The 0.22-wavelength section presents an efficient, low impedance match to the base of the
quarter-wave whip, but transforms the received energy to
a relatively high voltage at the diode for good sensitivity.
Biasing the detector diode improves the sensitivity by an
additional 10dB. The forward threshold is reduced to
essentially zero, so a very small voltage can generate a
meaningful output change. The detector diode’s bias point
is monitored by an LTC1440 ultralow power comparator,
and by a second diode, which serves as a reference.
When a signal at the resonant frequency of the antenna is
received, Schottky diode D1 rectifies the incoming carrier
and creates a negative-going DC bias shift at the noninverting input of the comparator. Note that the bias shift is
sensed at the base of the antenna where the impedance is
low, rather than at the Schottky where the impedance is
high. This introduces less disturbance into the tuned
antenna and transmission-line system. The falling edge of
the comparator triggers a one-shot, which temporarily
enables answer-back and other pulsed functions.
Total current consumption is approximately 5µA. Monolithic one-shots draw significant load current, but the
venerable ‘4047 is about the best in this respect. Alternatively, a discrete one-shot constructed from a quad NAND
gate draws negligible power.
Sensitivity is excellent. The finished circuit can detect
200mW radiated from a reference dipole at 100'. Range,
of course, depends on operating frequency, antenna orientation and surrounding obstacles; in the clear, a more
reasonable distance, such as 10', can be covered at
470MHz with only a few milliwatts.
All selectivity is provided by the antenna itself. Add a
quarter-wave stub (shorted with a capacitor) to the base
of the antenna for better selectivity and improved rejection
of low frequency signals.
9VDC
λ /4
D1
1N5711
2X9.1MΩ
λ /0.22
Z0 = 50Ω
DETECTOR
FB
27kΩ
+
LTC1440
100pF
–
CMOS
ONE-SHOT
(CD4047)
27kΩ
100pF
REFERENCE
D2
1N5711
DI1440_01.EPS
Figure 191. Micropower Field Detector for Use at 470MHz
AN87-110
Q
Q
Application Note 87
ZERO-BIAS DETECTOR YIELDS HIGH
SENSITIVITY WITH NANOPOWER CONSUMPTION
by Mitchell Lee
the origin reveals that it follows the ideal diode equation,
with scales of millivolts and nanoamperes. To use a zerobias diode at the origin, the external comparator circuitry
must not load the rectified output.
RF ID tags, circuits that detect a “wake-up” call and return
a burst of data, must operate on very low quiescent
current for months or years, yet have enough battery
power in reserve to answer an incoming call. For smallest
size, most operate in the ultrahigh frequency range, where
the design of a micropower receiver circuit is problematic.
Familiar techniques, such as direct conversion, super
regeneration or superhetrodyne, consume far too much
supply current for long battery life. A better method
involves a technique borrowed from simple field-strength
meters: a tuned circuit and a diode detector.
The LTC1540 nanopower comparator and reference is a
good choice for this application because it not only presents no load to the diode, but also draws only 300nA from
the battery. This represents a 10-times improvement in
battery life over biased detector schemes.2 The input is
CMOS, and input bias current consists of leakage in a
small ESD-protection cell connected between the input
and ground. The input leakage measures in the picoampere
range, whereas the 1N5712 leaks hundreds of picoamperes.
Any rectified output from the diode is loaded by the diode
itself, not by the LTC1540, and the sensitivity can match
that of a loaded, biased detector.
Figure 192 shows the complete circuit, which was tested
for proof-of-concept at 445MHz. This circuit contains a
couple of improvements over the standard L/C-with-whip
field-strength meter. Tuned circuits aren’t easily constructed or controlled at UHF, so a transmission line is
used to match the detector diode (1N5712) to a quarterwave whip antenna. The 0.23λ transmission-line section
transforms the 1pF (350Ω) diode junction capacitance to
a virtual short at the base of the antenna. At the same time,
it converts the received antenna current to a voltage loop
at the diode, giving excellent sensitivity.
The rectified output is monitored by the LTC1540 comparator. The LTC1540’s internal reference is used to set up
a threshold of about 18mV at the inverting input. A rising
edge at the comparator output triggers a one-shot, which
temporarily enables answer-back and any other pulsed
functions.
Total supply current is 400nA, consuming just 7mAH
battery life over a period of five years. Monolithic oneshots draw significant load current, but the ’4047 is about
the best in this respect. A one-shot constructed from
discrete NAND gates draws negligible power.
Biasing the detector diode can improve sensitivity,1 but
only when the diode is loaded by an external DC resistance. Careful curve-tracer examination of the 1N5712 at
2V–11V
λ/4
12M
FB
10k
3
5
+
6
7
LTC1540
4
O.23λ
10nF
–
2
1
8
CMOS ONE-SHOT
(CD4047)
Q
Q
10nF
180k
1N5712
Figure 192. Nanopower Field Detector
AN87-111
Application Note 87
Sensitivity is excellent, and the circuit can detect about
200mW from a reference dipole at 100 feet. Range, of
course, depends on operating frequency, antenna orientation and surrounding obstacles. Sensitivity is independent
of supply voltage; this receiver will work just as well with
a 9V battery as with a single lithium cell.
The length of the transmission line does not scale with
frequency. Owing to a decrease in diode reactance, the
electrical length will shorten as frequency increases. Adjust
the line length for minimum feed-point impedance at the
operating frequency. If an impedance analyzer is used to
TRANSPARENT CLASS-D AMPLIFIERS
FEATURING THE LT1336
by Dale Eagar
Introduction
Efficiency in the field of power conversion is like transparency in the field of light transmission. It is no wonder,
then, that Class-D amplifiers are often called transparent,
since they have no significant power losses. In contrast to
class-D amplifiers’ nearly lossless switching, class-A
through class-C amplifiers are throttling devices that
waste significant energy. Amplifiers of the “lower classes”
(A–C) are modeled as rheostats (variable resistors),
whereas class-D amplifiers are modeled as variacs (variable transformers). The ideal resistor dissipates power,
whereas the ideal transformer does not. Like transformers
(variacs), many class-D amplifiers can transfer energy in
both directions—input to output and output to input.
Class-D amplifiers also have a way of ignoring reactive
loads that can be uncanny. A class-D amplifier operating
with an AC output will draw very little additional input
power when a sizable capacitive or inductive load is placed
at its output. This is because the reactive load has AC
voltage across it and AC current flowing through it, but the
phase angle of the voltage and current is such that no real
power is dissipated. The class-D amplifier ends up shuttling power back and forth between its input and its output,
doing both with minimal loss. An ideal class-D amplifier
can be thought of as having no place to dissipate power,
since all of its components are lossless; that is, it contains
no resistors.
AN87-112
measure the line, a 1pF capacitor can be substituted for the
diode to avoid large signal effects in the diode itself.
Consult the manufacturer’s data sheet for accurate characterization of diode impedance at the frequency of interest.
Notes:
1. Eccles, W.H. Wireless Telegraphy and Telephony, Second Edition. Ben
Brothers Limited, London, 1918, page 272.
2. Lee, Mitchell. “Biased Detector Yields High Sensitivity with Ultralow Power
Consumption.” Page 110 of this application note.
The Electric Heater—a Simple Class-D Amplifier
Class-D amplifiers can be simple or complex, depending
on what is required by the application. A simple class-D
amplifier is the thermostatic switch in an electric heater.
The thermostat controls the heater by turning it on or off.
The switch is essentially lossless, dissipating practically
no power. This class-D amplifier is remarkably efficient,
since even the energy lost in the switch, power cord and
house wiring contributes to the desired result. The duty
factor, and hence the average amount of power delivered
to the heater, can assume an infinite number of values.
This is true even though a constant amount of heat is
delivered when the heater is on.
Quadrants of Energy Transfer
Class-D amplifiers have a property that requires new
terminology, a property that generally isn’t considered in
lower-class amplifiers. This property, quadrants of energy
transfer, describes the output characteristics of the classD amplifier. The output characteristics are plotted on a
imaginary X-Y plot (I’ve yet to see someone actually do
one on paper), one axis representing output voltage and
the other axis representing output current, with the intersection of the axes representing zero volts and zero amps.
A simple switcher that can only provide a positive output
current into a positive output voltage can be described as
a 1-quadrant device. This 1-quadrant device could be a
computer power supply, a battery charger or any supply
that delivers a positive voltage into a device that can only
consume power.
Application Note 87
The 2-quadrant converter can be one of two different
things: 1) A positive output voltage that can both source
and sink current, or 2) A positive current that can comply
both positive and negative output voltage. Finally, the 4quadrant converter can both source and sink current into
both positive and negitive output voltages.
Introducing the LT1336 Half-bridge Driver
Taking a side step from our main discussion, we will
introduce a component, the half-bridge power amplifier.
Figure 194 details the LT1336 driving power MOSFETs
and shows the symbolic representation of this subcircuit
that will appear in subsequent figures. Table 1 shows the
logical states of this half-bridge power driver.
1-Quadrant Class-D Converter
To illustrate the 1-quadrant class-D amplifier, we will
focus on the boost mode converter detailed in Figure 193
This circuit removes power from the source (12V automotive battery) and delivers it to the load (some as-yetunknown 55V device) This circuit is classified as “1
quadrant” because it can only regulate output voltage in
one polarity (positive) and it can output current in only one
polarity (positive).
4-Quadrant Class-D Amplifier
Class-D amplifiers are commonly used in subwoofer drivers. This is because subwoofers require a great deal of
power. A class AB amplifier driving a subwoofer will put
about half of its input power into its heat sink. Driving the
same subwoofer at the same volume with the same music,
a class-D amplifier will put about five percent of its input
+
+
HEFTY
WIRES
FROM CAR
BATTERY
9V-15V
C1
+
C2
+
C3
+
2x#14
#26
T150-52
D3
MUR110
C5
22µF
20V
1200µF, 16V ×4
12V
D4
MUR110
SEC
+
–
PRi
20T
SEC
4T
MICROMETALS
R1
1Ω
C4
T1
5
C6
1500pF
R2
100k
1
2
8
C7
0.1µF
C9
0.15
R7
1k
R6
2.4k
6
+
–
4
7
U2A
LT1215
+
C11
33µF
16V
+
C12
33µF
16V
4
FB
VREF
R5
15k
4
Q1
2N3904
COMP
VIN
8
D2
MBR1060
R4
2.49k
R3
51k
7
PRi
36µH 20
30A
U1 GTDR
LT1243
R16
20Ω
6
Q2
IRFZ44
+
C15
C19
1000µF, 63V ×6
R/C
C8
1µF
3
+
C14
R17
20Ω
D1
1N5819
C13
2200µF
25V
55V, 3.3A
+
Q3
IRFZ44
+
R12
0.01Ω
1W
ISEN
GND
5
R8
1k
+
1
U2B
LT1215
–
R9
1k
3
2
R13
0.01Ω
1W
R14
0.01Ω
1W
R15
0.01Ω
1W
R11
1k
C10
220pF
R10
100Ω
Figure 193. 200W, 12V to 55V Front End for Automotive Applications
AN87-113
Application Note 87
power into the heat sink. The difference is ten to one on the
heatsink size and two to one on the input power supply.
Figure 195 is the 200W class-D subwoofer driver. This
circuit uses the 200W front end developed in Figure 193 as
its power source. The circuit in Figure 195 performs as
follows: U1a, R1–R4 and C7 implement a 75kHz
pseudosawtooth oscillator. U1d is the input amplifier/
filter, with a gain of 6.1 and 200Hz Butterworth lowpass
response. U1b and U1c are comparators that compare the
sawtooth and the amplified/filtered input signal to form
two complimentary, pulse-width modulated square waves.
X1 and X2 are two half-bridge power drivers and M1 is the
subwoofer driver.
Table 7. Half-Bridge Power Driver Truth Table
In Top
In Bottom
Output
L
L
Floating
L
H
Ground
H
L
55V
H
H
Floating
energy ends up on the 55V bus, where the bus voltage
climbs during these periods of “negative energy delivered to the load.” Fortunately, C14–C19 of Figure 193 can
store this energy; otherwise the 55V bus would subject to
excessive voltage until someplace was found for the
energy to go.
One of the properties of Class-D, 4-quadrant amplification
is the ability to transfer power both to and from the load.
In our subwoofer driver, this happens when the driver
reaches the end of any given excursion and the combination of the driver spring and the acoustic spring drive the
cone back to center. During this time, energy is transferred from the driver back to the input of the class-D
amplifier stage. In the case shown in Figure 195, the
Class-D for Motor Drives
Substituting a motor and an inductor for the subwoofer in
Figure 195 and simplifying the control, we arrive at the
circuit shown in Figure 196. Connecting this circuit to the
front end shown in Figure 193 and then getting the motor
up to speed is no problem, but when one wants to slow the
T1
COILTRONICS
CTX100-P
12V 55V
D3
1N4148
IN
TOP
OUT
C1
1µF
R1
6.2k
IN
BOTTOM
C2 0.1µF
D5
1N4148
12V
2
V+
1
16
V+
ISEN
D1
1A
60V
IN TOP
IN BOTTOM
BOOST
13
TGD
12
TGF
SW
TSOU
4
BGD
IN TOP
15
S
GND
6
Q1
IRFZ44
11
9
BGF
R6, 10Ω
Q3
IRFZ44
8
PGND
7
Figure 194. Half-Bridge Driver Subcircuit and Symbolic Representation
AN87-114
Q2
IRFZ44
OUT
D2
1A
60V
IN BOTTOM
SW
GND
R4, 10Ω
R5, 10Ω
U1
LT1336
3
55V
R3, 10Ω
14
10
(SYMBOLIC REPRESENTATION)
C3
1µF
D4
1N4148
R2 2Ω
Q4
IRFZ44
Application Note 87
12V
R1
15k
12V
R3
1.8k
+
8
U1A
LT1365
–
R4
15k
10
5
9
6
18" SUBWOOFER
DRIVER
1mH, 6.5Ω
C8
0.1µF
R2
15k
12V 55V
4
+
U1B
LT1365
7
U1C
LT1365
1
55V 12V
F1
10A
M1
–
C7
220pF
R5
15k
75kHz
3
2
C4
0.015
C1
2.2µF
+
INPUT
R6
1.8k
R7
18k
+
–
11
R8
100Ω
R9
18k
C2
0.47µF
3
C5
0.022µF
2
C3
0.1µF
C6
2.2µF
+
U1D
LT1365
1
–
R10
51k
+
R11
10k
Figure 195. 200W-Powered Subwoofer
12V
15k
12V
1.8k
+
8
0.1µF
15k
U1A
LT1365
–
10
+
9
55V 12V
L1
1mH
U1B
LT1365
–
M
X1
X2
220pF
15k
3
2
12V
MOTOR
SPEED
AND
DIRECTION
LOAD
12V 55V
4
+
U1C
LT1365
–
1
3
–
U1D
LT1365
11
2
1
+
POT 1
Figure 196. Class-D Motor Drive
AN87-115
Application Note 87
+
12V BATTERY
R1
1Ω
–
+
+
+
C1
PRi
20T
SEC
4T
MICROMETALS
+
C2
C3
C4
D1
MUR110
1200µF, 16V ×4
+
C5
22µF
20V
5
6
C6
1.5µF
R2
100k
+
2
8
C7
0.1µF
C9
0.15µF R6
2.4k
R7
1k
COMP
20
4
VIN
VREF
VN2222
C11
33µF
16V
+
C12
33µF
16V
+
U1 GTDR
LT1243
+
C13
2200µF
25V
55V
+
C14
+
C15
6
1000µF, 63V ×6
R/C
C8
1µF
3
+
2k
4
FB
R5
15k
4
Q1
2N3904
T1
U2A
LT1215
–
12V
D2
MUR110
7
1
R4
2.49k
R3
51k
SEC
8
+
2x#14
#26
T150-52
ISEN
R12
0.01Ω
1W
GND
5
R8
1k
+
1
U2B
LT1215
–
R9
1k
3
2
R13
0.01Ω
1W
R14
0.01Ω
1W
R15
0.01Ω
1W
R11
1k
C10
220pF
R10
200Ω
R16
49.9k
Figure 197. 200W, 2-Quadrant Front End for Automotive Applications
motor down by turning pot 1 back toward its center,
disaster strikes. Rotational energy stored in the inertia of
the motor is converted back into electrical energy by the
motor and is presented to the output of the class-D
amplifier. L1, X1 and X2 do their job by transferring the
energy back into the 55V bus. The energy goes into C14–
C19 of Figure 193, charging them to some voltage
significantly above 55V, and something breaks. The problem here is that the circuit in Figure 193 is only a 1-quadrant
class-D amplifier.
Managing the Negative Energy Flow
Sound like a course in management? The negative energy
transferred through the class-D amplifier needs a home.
One simple home is a 62V power Zener diode strapped
AN87-116
across the 55V bus and bolted to a massive heat sink. One
could easily imagine the heat sink as the brake shoes
heating up as the electric vehicle winds down the mountain
road. Another place to put the energy is back into the 12V
battery. This will require upgrading the 12V to 55V frontend power converter from 1 quadrant to 2 quadrants.
The 2-Quadrant Class-D Converter
Converting Figure 193 to two quadrants involves replacing
D2 with a switch and activating the switch out of phase with
the switch formed by Q2 and Q3. The half-bridge power
driver shown in Figure 195 is just such a switch. Refer to
Figure 197. The ISENSE signal (U1, pin 3) needs to be offset
to accommodate negative current (add R16, Figure 197)
The ISENSE signal needs to be scaled for twice the range
C19
Application Note 87
(–30A to 30A rather than 0A to 30A); this is done by
changing R10.
Now we are happily winding down the mountain road,
watching the scenery unfold before us. We are happy in
knowing that we are recycling the energy released from
the descent by charging our batteries, while watching the
mountain bikers burn their descent energy off in brake
linings. Once again technology wins over sweat and brawn.
find some way to fail. We need to stop and drain off some
charge, trade batteries with someone climbing the other
side or put a power Zener on our battery. Figure 198 details
the active Zener circuit. Using the reference in U1 of Figure
197 and the unused half of U2 we are able to make a
hysteretic clamp that puts all of the heat into a resistor, R5.
This circuit will save the battery from destruction and drop
our level of smugness back to that of the mountain bikers.
Conclusion
A Trip Over the Great Divide
Climbing the great divide in an electric vehicle requires
some planning. Stops to recharge are necessary. Once on
top, the whole scheme changes: descending the hill,
charging our battery, all goes well until the battery is fully
charged; then we have to stop. Further descent would
overcharge our battery, boiling out the electrolyte. Not
only would this ruin our battery, in the end we would have
no place to put the energy and our class-D amplifier would
Class-D has been around for a long time: the venerable
electric heater with its bang-bang controller is a remarkably efficient and reliable class-D amplifier. Class-D drives
have been used for decades in golf carts, fork lifts, cranes
and industry. The advent of the half-bridge driver greatly
simplifies the Class-D Amplifier. Here at Linear Technology we have a family of half/full bridge MOSFET drivers.
For further information, contact us at the factory or refer to
the LT1158, LT1160, LT1162 or LT1336 data sheets.
VIN
R1
49.9k
R2
95k
R3
5M
8
U1
FIG 5
PIN 8
VREF
5.00V
6
R5
1Ω
200W
+
U2A
LT1215
7
R4
100Ω
IRFZ40
–
14A
0A
14.3V 14.6V
Figure 198. Wolf Creek Pass Adapter
AN87-117
Application Note 87
SINGLE-SUPPLY RANDOM CODE GENERATOR
by Richard Markell
Presented here is a truly random code generator that
operates from a single supply. The circuit allows operation
from a single 5V supply with a minimum of adjustments.
The circuit produces random ones and zeroes by comparing a stream of random noise generated in a Zener diode
to a reference voltage level. If the threshold is correctly set
and the time period is long enough, the noise will consist
of a random but equal number of samples above and
below threshold.
That Fuzz is Noise
The circuit shown in Figure 199 is the random noise
generator. Optimum noise performance is obtained from
a 1N753A Zener diode, which has a 6.2 volt Zener “knee.”
The diode is used to generate random noise. We have
found that optimum noise output for this diode occurs at
the “knee” of the I-V curve, where the Zener just starts to
limit voltage to 6.2 volts.
Operating a 6.2V Zener from a 5V supply required some
thought. Obviously, some type of voltage boosting scheme
was needed to provide the diode with the 8V or more that
it requires in this circuit. U1, an LTC1340 low noise,
voltage-boosted varactor driver, provides 9.2V at 20µA
from an input of 5V. This Zener current is the optimal for
noise output from the diode (at 20µA the output is about
20mVP-P).
The 1M and 249k resistors bias the input to operational
amplifier U2 to 1.25V to match the input common mode
range of comparator U3. The 1µF capacitor provides an AC
path for the noise. Note: be careful where you place any
additional capacitors in this part of the circuit or the noise
may be unintentionally rolled off. This is one circuit where
noise is desirable.
U2 is an LT1215 23MHz, 50V/µs, dual operational amplifier
that can operate from a single supply. It is used as a
wideband, gain-of-eleven amplifier to amplify the noise
from the Zener diode; the second op amp in U2 is unused.
U3, an LT1116 high speed, ground-sensing comparator,
AN87-118
receives the noise at its positive input. A threshold is set
at the negative comparator input and the output is adjusted via the 2k potentiometer for an equal number of
ones and zeroes. The 5k resistor and the 10µF capacitor
provide limited hysteresis so that the adjustment of the
potentiometer is not as critical. Latch U4, a 74HC373,
ensures that the output remains latched throughout one
clock period. The circuit’s output is taken from U4’s Q0
output.
Some Thoughts on Automatic Threshold Adjustment
Several circuit designers have asked about threshold
adjustment without manual knobs or potentiometers. One
way to implement this would be to have the microprocessor count the number of ones and zeroes over a given time
period and adjust the threshold (perhaps via a digital pot)
to produce the required density of ones.
A more “analog” method of adjusting threshold might be
to implement an integrator with reset. This circuit integrates the number of ones and zeroes over time to
produce a zero result for an adjustment that produces
equal numbers of ones and zeroes. Again, a digital pot
could be used to adjust threshold, with the threshold being
decreased for the case of “not enough ones” and increased for the case of “too many ones.”
After many more conversations with the “cyber illuminati,” the circuit in Figure 200 was devised. This circuit can
be used to replace the pot shown in the dashed box in
Figure 199. In operation, an LT1004-2.5 is used as a
reference at the front end of a precision voltage divider
string. A series of voltages is generated along the divider
string and a jumper is used to connect this voltage to a
buffer and then to the negative input of the LT1116
comparator. As was the case with the 2k pot, the voltage
at pin 2 (the negative input of the comparator) sets the
threshold for the comparator. The selection of voltage
taps on the resistor string is arbitrary; they were selected
to allow a good adjustment range (defined as allowing
jumper adjustment to 50% ones and 50% zeros) for a
sample of ten 1N753A Zener diodes used to produce
noise. The jumper could (and probably should) be replaced with analog switches controlled by a microprocessor
in medium- to high-volume applications.
Application Note 87
5V
U1
LTC1340
2
3
0.1µF
4
CP
AVCC
VCC
OUT
SHDN
AGND
IN
PGND
8
7
0.1µF
9.2V
6
10pF
5
5V
5V
5V
1000pF
+
~20mVP-P
NOISE
3
+
2
1.25V
–
1µF
4
1k
1
3
1µF
TANT
470k
249k
1µF
0.1µF
0.1µF
+
20
8
U2
LT1215
1M
1N753A
6.2V
+
1µF
1µF
+
1
2
+
VCC
1
+
8
3
U3
LT1116
5 LE
–
6
QO
11 LE
GND
10
4
47k
+
10µF
DO
2
2-LEVEL
OUTPUT
U4
74HC373
7
OE
1
5k
+
CLOCK IN
10µF
5V
2k
10 TURN
Figure 199. Single-Supply Random Code Generator
5V
15k
+
1µF
499
499
499
499
12k
1%
1%
1%
1%
1%
(1.30V) (1.25V) (1.20V) (1.15V) (1.10V)
0.01µF
5V
11k
1%
+
3
LT1004
-2.5
JUMPER SELECTS
THRESHOLD VOLTAGE
+
8
LT1490
2
–
1µF
1
TO LT1116
PIN 2 (FIGURE 1)
4
GROUND PINS 5 AND 6
Figure 200. Jumper Selects Threshold for Figure 199’s Circuit
AN87-119
Application Note 87
APPENDIX A: COMPONENT VENDOR CONTACTS
The tables on this and the following pages list contact
information for vendors of non-LTC parts used in the
application circuits in this publication. In some cases,
components from other vendors may also be suitable. For
information on component selection, consult the text of
the respective articles and the appropriate LTC data sheets.
Capacitors
Vendor
Product
Phone
URL
AVX
Chip Capacitors
(843) 946-0362
AVX
Tantalum Capacitors
(207) 282-5111
Electronic Concepts
400V Film Capacitors
(908) 542-7880
www.eci-capacitors.com
Kemet
Tantalum Capacitors
(408) 986-0424
www.kemet.com
www.avxcorp.com/products/capacitors
Marcon
High C/V Capacitors
(847) 696-2000
www.chemi-con.com/main/company/marcon.html
Murata Electronics
Capacitors
(770) 436-1300
www.iijnet.or.jp/murata/products/english
Nichicon
Electrolytic Capacitors
(847) 843-7500
www.nichicon-us.com
Panasonic
Poly Capacitors
(714) 373-7334
www.panasonic.com/industrial_oem/electronic_components/
electronic_components_capacitors_home.htm
Sanyo
Oscon Capacitors
(619) 661-6835
www.sanyovideo.com
Sprague
Capacitors
(207) 324-4140
www.comsprague.com
Taiyo Yuden
Chip Capacitors
(408) 573-4150
www.t-yuden.com
Tokin
Capacitors
(408) 432-8020
www.tokin.com
www.chemi-con.com/main
United Chemicon
Electrolytic Capacitors
(847) 696-2000
Vitramon
Ceramic Chip Capacitors
(203) 268-6261
www.vishay.com
Wima
Paper/Film Capacitors
(914) 347-2474
www.wimausa.com
Vendor
Product
Phone Number
URL
Agilent (formerly Hewlett
Packard)
IR LEDs
(800) 235-0312
www.semiconductor.agilent.com/ir
Central Semiconductor
Small Signal Discretes
(516) 435-1110
www.centralsemi.com
Chicago Miniature Lamp
LEDs
(201) 489-8989
www.sli-lighting.com/cml
Data Display Products
LEDs
(800) 421-6815
www.ddp-leds.com
Fuji
Schottky Diodes
(201) 712-0555
www.fujielectric/co/jp/eng/index-e.html
Diodes
General Semiconductor
Diodes
(516) 847-3000
www.gensemi.com
Motorola*
Discretes
(800) 441-2447
www.mot-sps.com/products/index.html
ON Semiconductor*
Discretes
(602) 244-6600
Panasonic
LEDs
(201) 348-5217
Temic
IR Photo Diodes
Zener/Small Signal
Diodes
(408) 970-5700
www.onsemi.com/home
www.panasonic.com/industrial_oem/semiconductors/
semiconductor_home.htm
www.temic.com
(408) 241-4588
www.vishay.com
Vishay
Zetex
Small Signal Discretes
(516) 543-7100
www.zetex.com
*Discretes formerly manufactured by Motorola are now manufactured by ON Semiconductor. Part numbers have not been chanaged as of January 2000
AN87-120
Application Note 87
Inductors and Transformers
Vendor
Product
Phone Number
URL
API Delevan
Inductors
(716) 652-3600
www.delevan.com
BH Electronics
Inductors
(612) 894-9590
www.bhelectronics.com
BI Technologies
Transformers
(714) 447-2656
www.bitechnologies.com
Coilcraft
Inductors
(847) 639-6400
www.coilcraft.com
Cooper
Inductors/ Transformers
(561) 752-5000
www.coiltronics.com
Dale
Inductors/ Transformers
(605) 665-1627
www.vishay.com/fp/fp.html#inductors
Gowanda
Inductors
(716) 532-2234
www.gowanda.com
Midcom
Inductors/ Transformers
(605) 886-4385/
(800) 643-2661
www.midcom-inc.com
Murata Electronics
Inductors
(814) 237-1431
www.murata.com
Panasonic
Inductors/Transformers
(714) 373-7334
www.panasonic.com/industrial_oem/electronic_components/
electronic_components_inductors_coils_and_transformers.htm
Philips
Inductors
(914) 246-2811
www.acm.components.philips.com
Philips
Planar Inductors
(914) 247-2036
www.acm.components.philips.com
Pulse
Inductors
(619) 674-8100
www.pulseeng.com
Sumida
Inductors
(847) 956-0667
www.japanlink.com/sumida
Tokin
Inductors
(408) 432-8020
www.tokin.com
Logic
Vendor
Product
Phone Number
URL
Fairchild
Logic
(207) 775-4502
www.fairchildsemi.com
Intersil (formerly Harris)
Logic
(800) 442-7747
www.intersil.com
*Motorola
Logic
(800) 441-2447
www.mot-sps.com/products/index.html
*ON Semiconductor
Logic
(602) 244-6600
www.onsemi.com/home
Toshiba
Logic
Single Gate Logic
(949) 455-2000/
(714) 455-2000
www.toshiba.com/taec
*Logic Devices formerly manufactured by by Motorola are now manufactured by ON Semiconductor; there have been no changes in part numbers as of January 2000
Resistors
Vendor
Product
Phone Number
URL
Allen Bradley
Carbon Resistors
(800) 592-4888
www.ab.com
AVX
Chip Resistors
(843) 946-0524
www.avxcorp.com/products/resistors/chiprstr.htm
BI Technologies
Resistors/Resistor
Networks
(714) 447-2345
www.bitechnologies.com
Bourns
Potentiometers, SIPs
(801) 750-7253
Dale
Sense Resistors
(605) 665-9301
www.bourns.com
www.vishayfoil.com
or www.vishay.com
www.irctt.com
IRC
Sense Resistors
(361) 992-7900
RG Allen
Metal Oxide Resistors
(818) 765-8300
www.rgaco.com
TAD
Chip Resistors
(800) 508-1521
www.tadcom.com
Taiyo Yuden
Chip Resistors
(408) 573-4150
www.t-yuden.com
Thin Film Technology
Thin Film Chip Resistors
(507) 625-8445
www.thin-film.com
Tocos
SMD Potentiometers
(847) 884-6664
www.tocos.com
AN87-121
Application Note 87
Transistors
Vendor
Product
Phone Number
URL
Central Semiconductor
Small Signal Discretes
(516) 435-1110
www.centralsemi.com
Fairchild
MOSFETs
(408) 822-2126
www.fairchildsemi.com
IR
MOSFETs
(310) 322-3331
www.irf.com
Motorola*
Discretes
(800) 441-2447
www.mot-sps.com/products/index.html
ON Semiconductor*
Discretes
(602) 244-6600
www.onsemi.com/home
Philips
Discretes
(401) 767-4427
www-us.semiconductors.philips.com
Siliconix
MOSFETs
(800) 554-5565
www.siliconix.com
Zetex
Small Signal Discretes
(631) 543-7100
www.zetex.com
*Discretes formerly manufacured by Motorola are now manufactured by ON Semiconductor; There are no changes in part numbers as of January 2000.
Miscellaneous
Vendor
Product
Phone Number
URL
Aavid
Heat Sinks
(714) 556-2665
www.aavid.com
Epson
Crystals
(310) 787-6300
www.eea.epson.com
Infineon
(formerly Siemens
Semiconductor)
Optoelectronics
(108) 257-7910
www.infineon.com/us/opto/content.htm
Magnetics, Inc.
Toroid Cores, etc.
(800) 245-3984
www.mag-inc.com
MF Electronics
Crystal Oscillators
(914) 576-6570
www.mfelec.com
www.murata.com
Murata Electronics
RF Devices
(770) 433-5789
QT Optoelectronics
RF Switches
(408) 720-1440
www.qtopto.com
Raychem
Fuses
(800) 227-4856
www.raychem.com
RF Micro Devices
RF Semiconductors
(336) 664-1233
www.rfmd.com
RTI/Ketema
Surge Suppressors
(714) 630-0081
www.rtie.rti-corp.com
Schurter
Fuses and Holders
(707) 778-6311
www.schurterinc.com
Thermalloy
Heat Sinks
(972) 243-4321
www.thermalloy.com
Toko
RF Products
(847) 699-3430
www.tokoam.com
Linear Technology Corporation
Product
Phone Number
URL
High Performance Analog ICs
(408) 432-1900
www.linear-tech.com
AN87-122
Application Note 87
Index
A
ADC. See Data Converters: D/A
Amplifiers 46–72
16-Bit Accurate 71, 71–72
ADC Buffer 72
Battery Current Monitor 46, 63, 65
Bridge 49
C-Load 54–56
Cable Driver 48
CCD Clock Driver 50–53
Chopped 92–93
Class-D 112–117
2-Quadrant Automotive Front End 116–117
200W, 12V to 55V Front End for Automotive
Applications 113
200W-Powered Subwoofer 115
Active Zener Circuit 117
Half-Bridge 113–114
Motor Drive 115
Current Feedback 47–49, 50–53, 70–71
Differential to Single-Ended ADC Driver 68
High Power 56–59
Instrumentation 67–69. See also Instrumentation Circuits
Medical ECG Monitor 69
Precision Current Source 69
Pressure Monitor 67
Single-Supply 67
JFET 54–56
Multiplexer 60
"Over-The-Top" 46, 65–66
Peak Detector 54
Photodiode, Logging 55
Power Driver 57, 58
Pressure Sensor 90
Programmable Gain 11–12
Rail-to-Rail 59–60, 62–63, 65–67
Telescoping 56
Track and Hold 54
Twisted Pair Driver 47
Video 61–62, 64–65, 70–71
DC-Restore Subcircuit 71
Level Shifter 70
Signal and Power Share Coax Cable 64–65
Voltage Controlled Limiter 61
XDSL 47, 79–80
C
C Language
Code to Configure PC Analog Interface 7–10
Comparators 80–85
1MHz to 10MHz Crystal Oscillator 82
Coincedence Detector 83, 85
Differential Timing Skew 82
Fast Waveform Sampler 82–83, 84
Isolated 94–95
Overtemperature Detector 94
Thermistor Temperature Controller 94
Voltage Detector 95
Low-Battery Warning, Shutdown and Reset for Li-Ion
Supply 81
Pulse Stretcher 83–85, 85
Window Detector 81
Converter
RMS/DC 51
Converters, Data. See Data Converters
Current Meter
0nA–200nA 62
Current Source
Precision 69
D
DAC. See Data Converters: D/A,
Data Converters 3–19
A/D, 12-Bit 7–10
4-Channel 10–12
8-Channel 10–12
Data Acquisition System 10
Differential 12
Differential to Single-Ended Conversion 68
Micropower 10–12
Multichannel 4
Programmable Attenuator 14
Programmable Gain Amplifier 11, 12, 14
A/D, 14-Bit 13
8-Channel 13
Multiplexer 13
A/D, 16-Bit
Buffer 72
D/A, 10-Bit 19
D/A, 12-Bit 3–4, 5, 7–10
4-Quadrant Multiplying 6
Autoranging, with Shutdown 3
Dual 14–15
for Digital Control Loop 18
Data Converters
D/A, 12-Bit (continued)
Micropower 5–6, 18
Quad 5–6
Wide Swing, Bipolar Output, with Digitally Controlled
Offset 4
with Programmable Full Scale and Offset 6
with Wide Output Swing 18
D/A, 16-Bit 16–18
2-Quadrant Multiplying 17
AN87-123
Application Note 87
4-Quadrant Multiplying 17
I/V Converter with 1.6µs Settling Time 72
Digitally Controlled LCD Bias Generator 19
Transmitter 34
Multiprotocol 22–29, 36–37
Cable-Selectable DTE/DCE Port 32, 33, 42
Controller-Selectable DCE Port 39, 45
Controller-Selectable DCE Port with Ring-Indicate 31
Controller-Selectable DTE Port 40
Controller-Selectable DTE/DCE Port 30, 41
Controller-Selectable DTE/DCE Port with RLL, LL, TM 43
Mode Selection 26
Net1 and Net2 Compliant 37–38, 44
Resistive Surge Protection for 20–22
LT1137A 21
Testing Line Driver Output Waveform 21
RS485 36, 37
Standards 23–25
Surge-Test Circuit 20
V.10 (RS423) 23–24
V.11 (RS422) 24, 36
V.28 (RS232) 24, 36, 37
V.35 25–29
F
Field Detector
Biased
Micropower 110
Zero-Bias
Nanopower 111
Filters 96–109
Antialiasing 4
Bandpass
Low Voltage, Narrow 100–101
Selective, Clock-Tunable to 80kHz 107
Continuous-Time
Universal 102–103
Highpass
1kHz 8th Order Butterworth 104–105
8th Order 30kHz Chebyshev 102
Highpass-Lowpass 96
Lowpass
1MHz/500kHz Continuous-Time, Low Noise, Elliptic 96–97
4th Order Butterworth 59
50kHz, 100dB Elliptic 103
6th Order Elliptic 63
Butterworth, with Track and Hold 98–99
Delay-Equalized Elliptic 96
Digitally Controlled 16
Dual 4th Order 100kHz Butterworth 102
Elliptic, 25kHz 99
Quad 3rd Order 100kHz Butterworth 103
Single 3.3V Low Power Linear Phase 107
Single-Supply 4th Order Butterworth 66
Ultrlow Frequency, Linear-Phase 106
Notch
Narrow-Band 101
Square-Wave-to-Quadrature Oscillator 108
Switched Capacitor
Universal 98–101, 106–108
L
LCD Bias Generator
Digitally Controlled 19
M
Miscelleaneous 110–119
Multiplexer 4, 10–12, 60
Multiplexing
Softwareless
for 14-Bit A/D 13
Mux. See Multiplexer
O
Operational Filter Blocks 102–103
Oscillator
Crystal
1MHz to 10MHz 82
with Complementary Outputs and 50% Duty Cycle 93
Sequencer for Ring-Tone Generator 74
Square-Wave-to-Quadrature 108
I
P
Instrumentation Circuits 86–95. See also Amplifiers:
Instrumentation
Bridge
High Performance Capacitance 87–89
with Increased Sensitivity 89
Chopped Amplifier 92–93
Pressure Sensor
Water Tank 89–92
Voltage-to-Frequency Converter 86, 90
Interface Circuits 20–45
1488 Line Driver with TVS Surge Protection 20
IrDA 34–35
Receiver 34
PC Analog Interface 7–10
PGA. See Amplifiers: Programmable Gain
Power Supply
60V and –180V, for Ring-Tone Generator 73
Li-Ion with Low-Battery Warning, Shutdown and Reset 81
Linear Technology Corporation
McCarthy Blvd., Milpitas, CA 95035-7417
AN87-124 1630
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
●
●
R
Random Code Generator
Single-Supply 118
T
Telecommunications Circuits 73–79
HDSL Driver 79
Ring-Tone Generator 73–78
an87f LT/LCG 1100 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000