PT2369 4 Inputs, 2.6Wx2 Class-AB Audio Amplifier with I2C Volume DESCRIPTION The PT2369 is an audio amplifier design for the low voltage (5V) application purpose, built-in stereo 2.6W Class-AB power amplifier with 32 steps I2C controlled volume, it also provides 4 sources selector, and unique noise suppressor circuit eliminates unpleasant pop noise during power or shutdown on/off, and provides SE/BTL selection for headphone connection. APPLICATIONS Portable DVD player Portable audio system Docking speaker system Flat panel monitor Other audio applications FEATURES Supply voltage: 3~6V 4 Stereo inputs 32 steps, I2C controlled volume from -40dB to +26dB (BTL) 2.6W x 2 Class-AB Power Amplifier (VDD=5V, RL=4Ω, THD=10%) BTL and SE output selectable Pop-Free circuitry eliminates unpleasant noises during power ON/OFF and changing the input source. Low power shutdown Over Temperature Protection Over Current Protection TSSOP 24 pin package with thermal pad BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT2369 APPLICATION CIRCUIT ORDER INFORMATION V1.2 Part Number Package Type Top Code PT2369-HT 24 pins, HTSSOP, 173mil PT2369-HT 2 January 2016 PT2369 PIN CONFIGURATION PIN DESCRIPTION Pin Name IN4L IN3L IN2L IN1L AVDD BYPASS AGND MUTE IN1R IN2R IN3R IN4R SDA SCL RVDD ROUTRGND ROUT+ LOUT+ LGND LOUTLVDD SD SE/BTL V1.2 I/O I I I I P I P I I I I I I I I O P O O P O P I I Description Left channel positive input 4 Left channel positive input 3 Left channel positive input 2 Left channel positive input 1 Power input for volume control Internal 1/2 reference bypassing Ground for volume control Mute Input, H=muted, L=normal (internal pull down) Right channel positive input 1 Right channel positive input 2 Right channel positive input 3 Right channel positive input 4 I2C data input I2C clock input Right channel power input Right channel negative output Power GND Right channel positive output Left channel positive output Power GND Left channel negative output Left channel power input Shutdown, L=shutdown, H=normal operate. L=BTL (speaker out), H=SE (Headphone out) 3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 January 2016 PT2369 FUNCTION DESCRIPTION INPUT SELECTOR AND VOLUME The PT2369 provides 4 stereo inputs selector; all of input pin should be AC coupled. Please note the input impedance is relative with volume setting, higher gain means lower input impedance, the minimum input impedance is around 18KΩ at the +26dB gain setting. In a general application, a 1μF capacitor is recommended for enough low frequency responses. All of volume and input selector setting is via I2C bus command; please refer to the software control section. DE-POP AND MUTE The PT2369 has internal de-pop mechanism for all of conditions, whatever in shutdown ON-OFF or power ON-OFF period. A voltage sensing circuit would monitor the bias, reference and VDD relations continuously to avoid pop noise happens, and volume controller default sets to mute-on to avoid any audible output, therefore, user must given a initial setting to the PT2369 after power-on period. If supply voltage was removed suddenly, the UVLO circuit will detects such changes and mute all of amplifier immediately to prevent pop noises. After power-on period, the I2C bus needs a short waiting time (Tini) to send the initial setting into I2C register. The Tini timing determinate by Cbypass capacitance, it is must waiting the Bypass voltage exceeds 0.3VDD to prevent initializing failed. The PT2369 has hardware mute and software mute could choose for general use, both mute signal is combine together in the internal circuit, whatever which was actives the outputs will be muted. Power-Off mute timing V1.2 Shutdown ON-OFF mute timing 4 January 2016 PT2369 POWER AMPLIFIER The power amplifier can driving up to 2.6W into 4Ω load and output configuration can be selected between BTL and single ended (SE) for different type load; a low impedance loudspeaker or a 32Ω headphone. The SE/BTL pin is determinate which mode activated; please refer to the application circuit for proper connection. To protect the amplifier output stage not be damaged by unusual short circuit, the maximum output current is limited by not exceeds 2.5A. SHUTDOWN The shutdown function could eliminate all of current consumption, pull the SD pin down to GND and whole chip current consumption will drop down to less than 1µA even the VDD still powered. When shutdown is active, the amplifier would be turn-off immediately and all of internal register will reminds original setting if the VDD is not removed. Sets the SD pin to high can turn-on the chip, de-pop circuit will associate in same time to avoid pop noise generated. THERMAL PROTECTION If chip is not well soldered on a board with broad copper foil, or operating ambient temperature exceeds thermal derating limit, the chip’s junction temperature will exceeds 150℃ and causes permanent damage. The thermal protection circuit will be activated when junction temperature exceed 150℃ to prevent long-time overheat damages. When thermal protection is activated the output will be temporary turn off for cooling down, and it will back to normal operation when junction temperature below 100℃. SYSTEM RESET A Power-On-Reset signals will reset all of registers to default value if the supply voltage is drop down to zero then rising up to exceeds 1.5V. After power-on-reset sequence user should given all of registers a validate value to ensure whole chip work properly. V1.2 5 January 2016 PT2369 CONTROL BUS SPECIFICATION BUS INTERFACE All functions of the PT2369 are controlled by the I 2C interface, the interface is consisting by SDA and SCL pins. Detail protocol of the I2C bus will discuss on the next section. It should be noted that the bus level pull-up resistors connected to the PT2369 positive supply voltage may required in some application especially the MCU output high level is no enough. DATA VALIDITY A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW State of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below. START AND STOP CONDITIONS A Start Condition is activated when 1) The SCL is set to HIGH and 2) SDA shifts from HIGH to LOW State. The Stop Condition is activated when 1) SCL is set to HIGH and 2) SDA shifts from LOW to HIGH State. Please refer to the timing diagram below. BYTE FORMAT Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an Acknowledge Bit. The MSB is first transmitted. V1.2 6 January 2016 PT2369 ACKNOWLEDGE During the Acknowledge clock pulse (ACK), the SDA output port of the master device (P) would be sets on Hi-Z state, if peripheral device (ex : audio processor) recognize the I2C command the SDA line will be pull-down by slave device during the SCL clock pulse held in HIGH state period. Please refer to the diagram below. The slave device that has been addressed to generate an Acknowledge after receiving each byte, otherwise, the SDA Line will remain at the High level in period of the ninth (9th) clock pulse. In this case, the host controller will generate a STOP sign in order to abort the transfer mission. TRANSMISSION WITHOUT ACKNOWLEDGE If the application does not need to verify the Acknowledge signal that generated by the slave device is right or not, host controller can just bypass the acknowledge check and transmit next data byte to the slave device. If this approach is used, there are greater chances of faulty operation as well as decrease in noise immunity. I2C BUS FORMAT S Slave Address A Sub Address A Data Bits A P S: Starting Term A: Acknowledge Bit P: Stop Term After the Data bits was written into the Data register, the Sub Address register will automatic point to next new Sub Address, therefore, user only need to send first Sub Address only and DATA bits can transmit continuously, does not need appoint a new Sub Address again. Next graph shows the Sub Address increasing sequence. 0x00 → 0x01 → SLAVE ADDRESS The PT2369 sub address is fixed on 0x86. MSB 1 0 0 0 0 1 LSB 0 1 SUB ADDRESS TABLE Sub Address 0x00 0x01 V1.2 Bit D7 AIN1 VOL4 D6 AIN0 VOL3 D5 0 VOL2 D4 0 VOL1 7 D3 0 VOL0 D2 0 0 D1 0 0 D0 0 MUTE January 2016 PT2369 DATA BYTE DEFINITION <1> MUTE (SUB ADDRESS 0X01) <2> AUDIO INPUT SELECTOR (SUB ADDRESS 0X00) Data Bit D0 AMUTE 0* 1 Mute Mute on Normal Input SEL IN1 IN2 IN3 IN4 Data Bit D7 AIN1 0* 0 1 1 D6 AIN0 0* 1 0 1 *=Default value <3> VOLUME CONTROL (SUB ADDRESS 0X01) Volume Gain (dB) BTL +26 +25 +24 +23 +22 +20 +18 +16 +14 +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -28 -32 -36 -40 *=Default value V1.2 SE +20 +19 +18 +17 +16 +14 +12 +10 +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -34 -38 -42 -46 Sub Address 0x01 D7 VOL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1* 8 D6 VOL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1* Data Bit D5 VOL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1* D4 VOL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1* D3 VOL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1* January 2016 PT2369 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Operating Temperature Storage Temperature Maximum Input Voltage ESD I/O Latch Up Symbol VDD Topr Tstg Vi max HBM MM ILU Min. 0 -45 -65 -0.3 -2 -200 -150 Max. 7 85 150 VDD+0.3 +2 +200 +150 Unit V ℃ ℃ V KV V mA ELECTRICAL CHARACTERISTICS Unless stated otherwise: VDD=5V, Test bandwidth=22~22KHz Parameter Symbol Test Conditions POWER SUPPLY Supply Voltage VDD VDD=3V SE VDD=5V Supply Current IDD VDD=3V BTL VDD=5V SD=1V Output ON Under Voltage Lock Out UVLO Output Off INPUT SELECTOR AND VOLUME Input Selector Input Isolation SIN F=1KHz VOL=-40dB Input Resistance Rin VOL=+26dB Inputs not selected Volume Control Maximum Gain Gmax BTL(code=00000) Minimum Gain Gmin BTL(code=11111) Vol=+26~+22dB Volume Step GSTEP Vol=+20~-24dB Vol=-28~-40dB Attenuation Error EA Vol=+26~-40dB Channel Balance EBL Vol=+26~-40dB Mute Level MUTE HW or SW Mute V1.2 9 Min. Typ. Max. Unit 3 - 5 5 6 8 10 3 2.7 6 9 11 12 15 1 - V - 90 200 20 50 - -1 -1 - 26 -40 1 2 4 0 0 -75 +1 +1 - mA µA V dB KΩ dB dB dB dB dB dB January 2016 PT2369 Parameter CLASS-AB AMPLIFIER Total Harmonic Distortion Output Power Load Resistance Symbol THD+N Po Vos Signal to Noise Ratio SNR Residual Noise Vno Thermal Protection Min. Typ. Max. Po=0.1W, RL=8Ω Po=1W, RL=8Ω Po=0.1W, RL=4Ω Po=1W, RL=4Ω RL=8Ω THD=1% RL=4Ω RL=3Ω BTL RL=8Ω THD=10% RL=4Ω RL=3Ω THD=1% RL=32Ω SE THD=10% RL=32Ω BTL terminal From -40~+26dB PO=1.1W/8Ω, Gain=0dB +26dB, BTL, A-weighted +20dB, SE, A-weighted +6dB, BTL, A-weighted 0dB, SE, A-weighted F=1KHz F=200Hz, CB=1µF Output OFF Output ON 3 - 0.15 0.05 0.15 0.05 1.3 2.1 2.2 1.6 2.6 2.9 100 130 4 5 0 95 150 75 30 15 90 60 150 90 10 2 - MUTE ON MUTE OFF Mute pin Shutdown OFF Shutdown ON SEBTL BTLSE VDD=3~5V VDD=3~5V VDD=3~5V VDD=3~5V Rpull up=1KΩ, Ack active 2 2 0.85 2 -5 - 300 0.9 0.5 100 0.4 0.8 0.8 0.6 500 0.8 5 - RL Output DC Offset Channel Separation Supply Rejection Ratio Test Conditions CS PSRR TSD Unit % W mW Ω mV mV dB μV μV μV μV dB dB ℃ CONTROL INTERFACE Mute Active Pull Down Resistance Shutdown SE/BTL I2C Bus Clock Rate I2C Low Level I2C High Level I2C Input Current SDA Pull Down Voltage V1.2 MUTE RDN SD SE/BTL Fclk VIL VIH IIN Vack 10 V KΩ V VDD KHz V V µA V January 2016 PT2369 PACKAGE THERMAL CHARACTERISTIC HTSSOP-24, 173MIL BODY WIDTH, WITH THERMAL PAD ON BOTTOM SIDE Parameter Thermal Resistance, Junction to Ambience (see note) Symbol Condition Min. Typ. Max. Unit θja Ta=25℃ - 36 - ℃/W Pdr Ta≤25℃ Ta=60℃ Ta≤85℃ - 3.4 2.5 1.8 - W Power Dissipation Rating Note: The thermal resistance is measured on PTC evaluation board; the chip is mounted on a board with 2 layers, 1oz copper foil, the thermal pad must be soldered and board area greater than 2 Inch2. TSSOP 24pin 173MIL Thermal Derating 4 Pd(W) 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 160 Ambient Temperature (C) V1.2 11 January 2016 PT2369 PACKAGE INFORMATION 24 PINS, HTSSOP, 173MIL Symbol Min. Nom. Max. A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 C 0.09 - 0.20 b 0.19 - 0.30 D 7.70 7.80 7.90 D1 2.70 - - E 6.30 6.40 6.50 E1 4.30 4.40 4.50 E2 1.50 - - e L 0.65 BSC. 0.45 0.60 L1 θ 0.75 1.00 REF. 0° - 8° Notes: 1. Refer to JEDEC MO-153. 2. All dimensions in millimeters. V1.2 12 January 2016 PT2369 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.2 13 January 2016