ANPEC APA4838R

APA4838
Stereo 2.8W Audio Power Amplifier with DC Volume Control
and Selectable Gain
Features
•
•
General Description
The APA4838 is a monolithic integrated circuit , which
provides DC volume control , and a stereo bridged
audio power amplifiers capable of producing 2.8W
(2.3W) into 3Ω with less than 10% (1.0%) THD+N.
APA4838 includes a DC volume control , stereo
bridge-tied and single-ended audio power amplifiers
, stereo docking outputs , and a selectable gain control , that makes it optimally fittable for notebook PC
, multimedia monitors , and other portable
applications. The attenuator range of the volume
control in APA4838 is from 0dB (DC_Vol=0.8VDD) to
–78dB (DC_Vol=0V) with 31 steps. Both of the depop
circuitry and the thermal shutdown protection circuitry
are integrated in APA4838 , that reduces pops and
clicks noise during power up or shutdown mode operation , and protects the chip from being destroyed
by over temperature failure. To simplify the audio
system design , APA4838 combines a stereo bridgetied loads (BTL) mode for speaker drive and a stereo
single-end (SE) mode for headphone drive into a
single chip , where both modes are easily switched
by the HP Sense input control pin signal. Besides
the low supply current design to increase the efficiency of the amplifiers , APA4838 also features a
shutdown function which keeps the supply current
only 0.7µA (typ).
Operating Voltage : 4.5V to 5V
Stereo switchable bridged/single-ended
power amplifiers
•
DC Volume Control Interface , 0dB to –78dB
with precision scale
•
•
•
Supply Current , IDD = 15mA at Stereo BTL
Low Shutdown Current , IDD = 0.7µA
Bridge-Tied Load (BTL) or Single-Ended-(SE)
Modes Operation
•
•
Output Power at 1% THD+N , VDD=5V
– 2.3W/Ch (typ) into a 3 Ω Load
– 2.0W/Ch (typ) into a 4 Ω Load
– 1.2W/Ch (typ) into a 8 Ω Load
Output Power at 10% THD+N , VDD=5V
– 2.8W/Ch (typ) into a 3 Ω Load
– 2.3W/Ch (typ) into a 4 Ω Load
– 1.5W/Ch (typ) into a 8Ω Load
•
Single-ended mode at 1.0% THD+N
– 95mW/Ch (typ) into 32Ω Load
•
•
Depop Circuitry Integrated
Pin Description
Thermal shutdown protection and over current
protection circuitry
•
•
•
High supply voltage ripple rejection
1
28
Right O ut +
Shutdown
2
27
V DD
G ain Select
3
26
Right O ut -
28-pin TSSOP-P (with enhanced thermal pad)
M ode
4
25
power package available
M ute
VDD
5
24
Right G ain 2
Right G ain 1
6
23
GN D
DC V ol
7
22
BY PA SS
GN D
8
21
HP Sense
Right Dock
9
20
GN D
Right In
10
19
Beep In
11
18
Left G ain 1
Left G ain 2
GN D
PC99 Compliant
Applications
•
•
•
Notebook and Desktop Computers
Multimedia Monitors
Left In
12
17
Left O ut -
Left Dock
13
16
V DD
GN D
14
15
Left O ut +
Portable Applications
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
1
www.anpec.com.tw
APA4838
Ordering and Marking Information
APA4838
P ackage C ode
R : T S S O P -P
Tem p. R ange
I : -4 0 to 8 5 ° C
H a n d lin g C o d e
TU : Tube
H a n d lin g C o d e
T em p. R an g e
P ac ka ge C od e
A P A 4838
XXXXX
A P A 4838 R :
TR : Tape & R eel
X X X X X - D a te C o d e
Block Diagram
20KΩ
Mode
Control
Mute
HP Sense
Left Gain2
Mode
20KΩ
Left Gain1
Gain Select
10KΩ
DC_Vol
20KΩ
10KΩ
Left Dock
0.33µF
Beep
Detect
0.33µF
Right In
Bias
Volume
Control
31 steps
+
Beep In
20KΩ
20KΩ
+ Left Out
Bias
+
Right
Audio Input 20KΩ
Left In
+
-
200KΩ
20KΩ
+
-
Left
Audio Input
200KΩ
- Left Out
+
-
20KΩ
0.068µF
Right Dock
20KΩ
20KΩ
+ Right Out
20KΩ
- Right Out
Shutdown
GND
+
VDD
Power
Management
10KΩ
10KΩ
20KΩ
Right Gain2
0.068µF
Click and Pop
Suppression
Circuitry
Right Gain1
Bypass
20KΩ
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
2
20KΩ
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APA4838
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
VDD
VIN
TA
TJ
TSTG
TS
VESD
PD
Parameter
Rating
Supply Voltage
-0.3 to 6
Input Voltage Range, HP sense, Shutdown,
-0.3 to VDD+0.3
Mute, Mode, Gain Select
Operating Ambient Temperature Range
-40 to 85
Maximum Junction Temperature
Internally Limited*1
Storage Temperature Range
-65 to +150
Soldering Temperature,10 seconds
260
Electrostatic Discharge
-2000 to 2000*2
Power Dissipation
Internally Limited
Unit
V
V
°C
°C
°C
°C
V
W
Note:
1.APA4838 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C
2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses
3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Recommended Operating Conditions
Supply Voltage, VDD
High level threshold voltage, VIH
Low level threshold voltage, VIL
Min.
Max.
Unit
4.5
5.5
V
Shutdown, Mute, Mode, Gain Select
2
HP Sense
Shutdown, Mute, Mode, Gain Select
4
V
1.0
HP Sense
3
Common mode input voltage, VICM
VDD-1.0
V
V
Thermal Characteristics
Symbol
Parameter
R THJA
Thermal Resistance from Junction to Ambient in Free Air
TSSOP-P*
Value
Unit
45
K/W
* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias.
The thermal pad on the TSSOP_P package with solder on the printed circuit board.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
3
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APA4838
Electrical Characteristics
Electrical Characteristics for Entire IC
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C
Symbol
VDD
IDD
ISD
Parameter
Supply Voltage
Quiescent Power Supply
Current
Shutdown Current
Test Conditions
APA4838
Typ.
Max.
5.5
Min.
4.5
Unit
V
VIN=0V, IO=0A
15
25
mA
VPIN 2= VDD
0.7
2.0
µA
Electrical Characteristics for Volume Attenuators
The following specifications apply for VDD= 5V. Limits apply for TA= 25°C
Symbol
Parameter
CRANGE
Attenuator Range
AM
Mute Attenuation
Test Conditions
Gain with VPIN 7=5V
Attenuation with VPIN 7=0V
VPIN 5=5V, Bridged Mode
VPIN 5=5V, Single-Ended Mode
APA4838
Typ. Max.
±0.5
-65
-78
-70
-70
Min.
Unit
dB
dB
Electrical Characteristics for BTL Mode Operation
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C
Symbol
VOS
PO
THD+N
PSRR
XTALK
SNR
VN
Parameter
Test Conditions
Output Offset Voltage
Output Power
VIN=0V
THD=1%, f=1kHz
RL=3Ω
RL=4Ω
RL=8Ω
THD=10%, f=1kHz
RL=8Ω
Total Harmonic Distortion + Noise AVD=2, f=1kHz
RL=4Ω , PO =1.5W
RL=8Ω , PO=1W
VRIPPLE=100mVRms CB=2.2µF,
Power Supply Rejection Ratio
RL=8Ω, f=1kHz
CB=2.2µF, f=1kHz, RL=8Ω
Channel Separation
VDD=5V, PO =1.1W, RL=8Ω,A-Wtd
Signal-to-Noise Ratio
Filter
RL=8Ω,A-Wtd Filter
Output Noise Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
4
APA4838
Typ.
5
2.3
2.0
1.2
Unit
mV
W
1.5
0.07
0.07
%
70
dB
90
dB
95
dB
30
µV
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APA4838
Electrical Characteristics (Cont.)
Electrical Characteristics for SE Mode Operation (Cont.)
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C
Symbol
VOS
PO
THD+N
PSRR
XTALK
SNR
VN
Parameter
Test Conditions
Output Offset Voltage
Output Power
VIN=0V
THD=1%,
THD=10%,
f=1kHz, RL=32Ω
f=1kHz, RL=32Ω
Total Harmonic Distortion AV= 1 , VOUT=1VRMS, RL=10kΩ, f=1kHz
plus Noise
PO =75mW, RL=32Ω, AV= 1, f=1kHz
Power Supply Rejection
VRIPPLE=100mVRMS , f=120Hz, CB=2.2µF
Ratio
Channel Separation
CB=2.2µF, RL=8Ω , f=1kHz
Signal-to-Noise Ratio
PO =75mW, RL=32Ω, A-Wtd Filter
Output Noise Voltage
RL=32Ω, A-Wtd Filter
APA4838
Typ.
5
95
110
mW
0.05
%
0.07
%
52
dB
90
102
20
dB
dB
µV
Unit
mV
Pin Description
Pin
I/O
Description
Name
GND
No
1, 8, 14,
20, 23
Shutdown
2
I Shutdown mode control signal input, place entire IC in shutdown mode when
held high, Idd=0.7uA
Gain Select
3
I Gain select input pin, logic high will switch the amplifier to external gain
mode, and logic low will switch to internal unity gain.
Mode
4
I Mode select input pin, fixed gain when logic L and gain adjustable mode
when logic H.
Mute
5
I Mute control input pin, active H.
VDD
6, 16, 27
Ground connection for circuitry.
Supply voltage input pin
DC_Vol
7
I Volume control function input pin.
Right Dock
9
O Right docking output pin
Right In
10
I Right channel audio input pin
Beep In
11
I Beep signal input pin
Left In
12
I Left channel audio input pin
Left Dock
13
O Right docking output pin
Left Out +
15
O Left channel positive output pin
Left Out -
17
O Left channel negative output pin
Left Gain 2
18
Connect pin 2 of the external gain setting resistor for left channel
Left Gain 1
19
Connect pin 1 of the external gain setting resistor for left channel
HP Sense
21
I Headphone sense control pin
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
5
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APA4838
Pin Description (Cont.)
Pin
I/O
Description
Name
Bypass
No
22
Bypass pin
Right Gain 1
24
Connect pin 1 of the external gain setting resistor for right channel
Right Gain 2
25
Connect pin 2 of the external gain setting resistor for right channel
Right Out -
26
O Right channel negative output pin
Right Out +
28
O Right channel positive output pin
Truth Table for Logic Inputs
Mute
Gain
HP
Mode
Select
Sense
Gain Mode of
Power Amplifier
DC Vol. Control
BTL Output
SE Output
0
0
0
0
Unity Gain Setting
Fixed Level
Vol. Fixed
-
0
0
0
1
Unity Gain Setting
Fixed Level
Muted
Vol. Fixed
0
0
1
0
Unity Gain Setting
Adjustable
Vol. Adjustable
-
0
0
1
1
Unity Gain Setting
Adjustable
Muted
Vol. Adjustable
0
1
0
0
External Gain Setting
Fixed Level
Vol. Fixed
-
0
1
0
1
External Gain Setting
Fixed Level
Muted
Vol. Fixed
0
1
1
0
External Gain Setting
Adjustable
Vol. Adjustable
-
0
1
1
1
External Gain Setting
Adjustable
Muted
Vol. Adjustable
1
X
X
X
-
-
Muted
Muted
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
6
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APA4838
Typical Application Circuit
VDD
VDD
1 µF
R_var
DC Vol Control
VDD
100KΩ
HP Sense
Internal gain select
3
7
19
18
100KΩ
21
5
Mute
Mode 4
10KΩ
13
- Left Out
20KΩ
12
+
0.33µ F
200KΩ
Right In
20KΩ
+
0.33µ F
20KΩ
Beep
Detect
Bias
10
Right Dock
17
20KΩ
+
11
Beep In
Right
Audio
Input
+
-
200KΩ
Left In
+
-
20KΩ
Volume
Control
31 steps
9
0.1µ F
0.1µ F
20KΩ
Power
Management
Pin
Ring
+ Left Out
To HP sense
Circuit
+ Right Out
Tip
Sleeve
10KΩ
- Right Out
26
+
220µ F
-
0.1µ F
Bypass
22
28
+
GND
15
Control
Pin
Headphone Jack
6,16,27
1,8,14,20,23
+
220µ F
1KΩ
20KΩ
Bias
20KΩ
VDD
0.068µ F
10KΩ
+
Left Dock
20KΩ
Mode
Control
+
-
To Control Pin on
Headphone Jack
Left
Audio
Input
20KΩ
20KΩ
10KΩ
Click and Pop
Suppression
Circuitry
1KΩ
20KΩ
0.068µ F
2.2µ F
2
24
25
Shutdown
20KΩ
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
7
20KΩ
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APA4838
Application Information
Volume Control Table
Gain (dB)
Voltage Range (% of Vdd)
Voltage Range (Vdd=5V)
Low
High
Recommended
Low
High
Recommended
0
77.5%
100.00%
100.000%
3.875
5.000
5.000
-1
75.0%
78.5%
76.875%
3.750
3.938
3.844
-2
72.5%
76.25%
74.375%
3.625
3.813
3.719
-3
70.0%
73.75%
71.875%
3.500
3.688
3.594
-4
67.5%
71.25%
69.375%
3.375
3.563
3.469
-5
65.0%
68.75%
66.875%
3.250
3.438
3.344
-6
62.5%
66.25%
64.375%
3.125
3.313
3.219
-8
60.0%
63.75%
61.875%
3.000
3.188
3.094
-10
57.5%
61.25%
59.375%
2.875
3.063
2.969
-12
55.0%
58.75%
56.875%
2.750
2.938
2.844
-14
52.5%
56.25%
54.375%
2.625
2.813
2.719
-16
50.0%
53.75%
51.875%
2.500
2.688
2.594
-18
47.5%
51.25%
49.375%
2.375
2.563
2.469
-20
45.0%
48.75%
46.875%
2.250
2.438
2.344
-22
42.5%
46.25%
44.375%
2.125
2.313
2.219
-24
40.0%
43.75%
41.875%
2.000
2.188
2.094
-26
37.5%
41.25%
39.375%
1.875
2.063
1.969
-28
35.0%
38.75%
36.875%
1.750
1.938
1.844
-30
32.5%
36.25%
34.375%
1.625
1.813
1.719
-32
30.0%
33.75%
31.875%
1.500
1.688
1.594
-34
27.5%
31.25%
29.375%
1.375
1.563
1.469
-36
25.0%
28.75%
26.875%
1.250
1.438
1.344
-38
22.5%
26.25%
24.675%
1.125
1.313
1.219
-40
20.0%
23.75%
21.875%
1.000
1.188
1.094
-42
17.5%
21.25%
19.375%
0.875
1.063
0.969
-44
15.0%
18.75%
16.875%
0.750
0.937
0.844
-46
12.5%
16.25%
14.375%
0.625
0.812
0.719
-48
10.0%
13.75%
11.875%
0.500
0.687
0.594
-50
7.5%
11.25%
9.375%
0.375
0.562
0.469
-52
5.0%
8.75%
6.875%
0.250
0.437
0.344
-78
0.0%
6.25%
0.000%
0.000
0.312
0.000
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2003
8
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APA4838
Typical Characteristics
THD+N vs. Frequency
10
VDD=5V
RL=3Ω
Po=1.8W
BTL
1
THD+N (%)
THD+N (%)
10
THD+N vs. Output Power
Av=2
Av=4
Av=8
0.1
VDD=5V
RL=3Ω
Av=2
BTL
1
f=20KHz
f=1KHz
0.1
f=20Hz
0.01
20
100
1k
0.01
10m
20k
100m
Frequency (Hz)
THD+N vs. Frequency
THD+N vs. Output Power
10
VDD=5V
RL=4Ω
Po=1.5W
BTL
VDD=5V
RL=4Ω
Av=2
BTL
1
1
THD+N (%)
THD+N (%)
3
Output Power (W)
10
0.1
1
Av=2
Av=4
Av=8
f=20KHz
0.1
f=1KHz
f=20Hz
0.01
20
100
1k
0.01
100m
20k
1
3
Output Power (W)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
500m
9
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APA4838
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=8Ω
Av=2
BTL
1
THD+N (%)
THD+N (%)
VDD=5V
RL=8Ω
Po=1.0W
BTL
Av=2
Av=4
Av=8
0.1
1
f=20KHz
0.1
f=1KHz
f=20Hz
0.01
20
100
1k
0.01
10m
20k
100m
Frequency (Hz)
2
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=8Ω
Po=250mW
SE
VDD=5V
RL=8Ω
Av=1
SE
1
THD+N (%)
THD+N (%)
1
Av=1
Av=2
Av=4
0.1
1
f=20KHz
0.1
f=1KHz
f=20Hz
0.01
20
100
1k
0.01
10m
20k
500m
Output Power (W)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
100m
10
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APA4838
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=16Ω
Av=1
SE
1
THD+N (%)
THD+N (%)
VDD=5V
RL=16Ω
Po=150mW
SE
Av=1
Av=2
Av=4
0.1
1
f=20KHz
0.1
f=20Hz
f=1KHz
0.01
20
100
1k
0.01
10m
20k
Frequency (Hz)
300m
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=32Ω
Av=1
SE
VDD=5V
RL=32Ω
Po=75mW
SE
1
1
THD+N (%)
THD+N (%)
100m
Av=1
Av=2
Av=4
0.1
f=20Hz
f=20KHz
0.1
f=1KHz
0.01
20
100
1k
0.01
10m
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
50m
100m 200m
Output Power (W)
11
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APA4838
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Swing
10
10
VDD=5V
RL=10KΩ
Av=1
SE
1
THD+N (%)
THD+N (%)
VDD=5V
RL=10KΩ
Vo=1VRMS
SE
Av=1
0.1
Av=2
1
0.1
f=20Hz
f=20KHz
Av=4
0.01
20
100
1k
f=1KHz
0.01
100m
20k
Crosstalk vs. Frequency
Crosstalk vs. Frequency
VDD=5V
RL=32Ω
-20 Po=75mW
Av=2
SE
VDD=5V
RL=8Ω
Po=1.0W
Av=2
BTL
-40
-60
-80
R-ch to L-ch
-100
-40
-60
-80
R-ch to L-ch
-100
L-ch to R-ch
L-ch to R-ch
-120
20
3
+0
Crosstalk (dB)
Crosstalk (dB)
-20
2
Output Swing (VRHS)
Frequency (Hz)
+0
500m
100
1k
-120
20k
20
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
100
1k
20k
Frequency (Hz)
12
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APA4838
Typical Characteristics (Cont.)
Noise Floor vs. Frequency
Noise Floor vs. Frequency
100
100
Noise Floor (µVRMS)
Noise Floor (µVRMS)
No Filter
A-Weight
10
VDD=5V
RL=8Ω
Av=2
BTL
1
20
100
1k
No Filter
A-Weight
10
VDD=5V
RL=32Ω
Av=1
SE
1
20k
20
100
Frequency (Hz)
1k
20k
Frequency (Hz)
Supply Current vs. Supply Voltage
Power Dissipation vs. Output Power
25
2
Power Dissipation (W)
Supply Current (mA)
1 .8
20
15
BTL
10
SE
5
RL=3Ω
1 .6
1 .4
1 .2
RL=4Ω
1
0 .8
0 .6
RL=8Ω
0 .4
VDD=5V
Av=2
BTL
0 .2
No Load
0
0
1
1 .5 2
2 .5
3
3 .5
4
4 .5 5 5 .5
0
1
1 .5
2
2 .5
Output Power (W)
Supply Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
0 .5
13
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APA4838
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
Gain vs. Voltage, 5V, SE
0 .2 5
4
0
-4
-1 2
Output Gain (dB)
Power Dissipation (W)
-8
0 .2
RL=8Ω
0 .1 5
RL=16Ω
0 .1
RL=32Ω
0 .0 5
-1 6
-2 0
-2 4
-2 8
-3 2
-3 6
-4 0
-4 4
-4 8
-5 2
-5 6
-6 0
VDD=5V
Av=2
SE
-6 4
VDD=5V
AV=1
SE
-6 8
-7 2
-7 6
0
-8 0
0
0 .0 5 0 .1 0 .1 5 0 .2 0 .2 5 0 .3 0 .3 5 0 .4
0
0 .5
Output Power (W)
1 .5
2
2 .5
3
3 .5
4
4 .5
5
DC Vol Input Voltage (V)
Output Power vs. Supply Voltage
Output Power vs. Supply Voltage
160
2 .2 5
2
140
Output Power (mW)
Output Power (W)
1
1 .5
THD+N=10%
1
THD+N=1%
0 .5
RL=8Ω
Av=2
BTL
120
100
THD+N=10%
80
60
THD+N=1%
40
RL=32Ω
Av=1
SE
20
0
0
2 .5
3
3 .5
4
4 .5
5
5 .5
2 .5
3 .5
4
4 .5
5
5 .5
Supply Voltage (V)
Supply Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
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14
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APA4838
Typical Characteristics (Cont.)
Output Power vs. Load Resistance
Output Power vs. Load Resistance
3
800
VDD=5V
Av=2
BTL
Output Power (mW)
Output Power (W)
2.5
2
1.5
1
VDD=5V
Av=1
SE
700
THD+N=10%
0.5
600
500
400
300
THD+N=10%
200
100
THD+N=1%
THD+N=1%
0
0
4 8
16
24
32
40
48
56
4 8
64
Load Resistance (Ω)
40
48
56
64
PSRR vs. Frequency
VDD=5V
Vin=100mVRMS
RL=8Ω
Cbypass=2.2µF
Av=2
BTL
-40
Gain Adjustable
-60
-80
-100
20
32
+0
Ripple Rejection Ratio (dB)
Ripple Rejection Ratio (dB)
-20
24
Load Resistance (Ω)
PSRR vs. Frequency
+0 6
16
Fixed Gain Mode
100
1k
-40
Gain Adjustable
-60
-80
Fixed Gain Mode
-100
20
20k
100
1k
20k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
VDD=5V
Vin=100mVRMS
RL=8Ω
-20 Cbypass=2.2µF
Av=1
SE
15
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APA4838
Typical Characteristics (Cont.)
Gain vs. Frequency
+12
Cf=0.22µF
Gain (dB)
+10
Cf=0.1µF
+8
+6
Cf=0.068µF
+4
VDD=5V
RL=8Ω
Av=2V/V
BTL
+2
-0
20
100
1k
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
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APA4838
Application Descriptions
BTL Operation
BTL Operation (Cont.)
The APA4838 output stage (power amplifier) has two
A BTL amplifier design has a few distinct advantages
pairs of operational amplifiers internally, allowed for
over the SE configuration, as it provides differential
different amplifier configurations for each channel.
drive to the load, thus doubling the output swing for a
Gain 1
specified supply voltage.
Gain 2
Four times the output power is possible as compared
to a SE amplifier under the same conditions. A BTL
-Out
Volum e Control
Am plifier output signal
configuration, such as the one used in APA4838, also
OP1
creates a second advantage over SE amplifiers.
RL
+Out
Vbias
Since the differential outputs, +Right Out, -Right Out,
+Left Out, and -Left Out, are biased at half-supply,
no need DC voltage exists across the load. This elimi-
OP2
nates the need for an output coupling capacitor which
Figure 1: APA4838 power amplifier internal configuration (each channel)
is required in a single supply, SE configuration.
The power amplifier OP1 gain is setting by internal
Single-Ended Operation
unity-gain or external gain setting which is selected
from Gain Select pin and the audio input signal come
Consider the single-supply SE configuration shown
from internal volume control block, while the second
Application Circuit. A coupling capacitor is required
amplifier OP2 is internally fixed in a unity-gain, in-
to block the DC offset voltage from reaching the load.
verting configuration. Figure 1 shows that the output
These capacitors can be quite large (approximately
of OP1 is connected to the input to OP2, which re-
33µF to 1000µF) so they tend to be expensive, oc-
sults in the output signals of with both amplifiers with
cupy valuable PCB area, and have the additional
identical in magnitude, but out of phase 180°.
drawback of limiting low-frequency performance of
Consequently, the differential gain for each channel
the system (refer to the Output Coupling Capacitor).
is 2X (Gain of SE mode).
The rules described still hold with the addition of the
By driving the load differentially through outputs -Out
following relationship:
and +Out, an amplifier configuration commonly re-
1
≤ 1 << 1
Cbypass x 125kΩ
RiCi
RLCC
ferred to as bridged mode is established. BTL mode
(1)
operation is different from the classical single-ended
SE amplifier configuration where one side of its load
is connected to ground.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
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APA4838
Application Descriptions (Cont.)
Output SE/BTL Operation
Output SE/BTL Operation (Cont.)
The ability of the APA4838 to easily switch between
In Figure 2, input HP Sense operates as follows:
BTL and SE modes is one of its most important costs
When the phonejack plug is inserted, the 1kΩ resis-
saving features. This feature eliminates the require-
tor is disconnected and the HP Sense input is pulled
ment for an additional headphone amplifier in appli-
high and enables the SE mode.
cations where internal stereo speakers are driven in
When this input goes high level, the +Out amplifier is
BTL mode but external headphone or speakers must
shutdown causing the speaker to mute. The -Out
be accommodated.
amplifier then drives through the output capacitor (CC)
Internal to the APA4838, two separate amplifiers drive
into the headphone jack.
–Out and +Out for each channel (see Figure 1). The
When there is no headphone plugged into the system,
HP Sense input controls the operation of the follower
the contact pin of the headphone jack is connected
amplifier that drives +Left Out and +Right Out.
from the signal pin, the voltage divider set up by re-
• When HP Sense is held low, the OP2 is turn on and
sistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls low
the APA4838 is in the BTL mode.
the HP Sense pin, enabling the BTL function.
•When HP Sense is held high, the OP2 is in a high
Docking Output Signal
output impedance state, which configures the
APA4838 as SE driver from -Out. IDD is reduced by
APA4835 internal first amplifier is used as audio sig-
approximately one-half in SE mode.
nal pre-amplfier and feedback resistor is connected
Control of the HP Sense input can be a logic-level
between Dock output pin and audio input pin.
TTL source or a resistor divider network or the ste-
However, the internal first amplifier’s closed-loop gain
reo headphone jack with switch pin as shown in Ap-
can be adjusted using external resistors. Use Equa-
plication Circuit.
tion 2 to determine the input and feedback resistor
values for a desired gain.
1kΩ
AV = -
VDD
100kΩ
Control
Pin
Ring
RF
Ri
(2)
The Dock output signal provides low distortion audio
quality for light driving output. ex. active speaker,
HP sense
Tip
monitors or audio/visual equipment. These two out-
Sleeve
puts can driving load of >1kΩ with rail-to-rail output
Headphone Jack
Figure 2: HP Sense input selection by phonejack
and output coupling capacitor is required when using
plug
these outputs.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
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APA4838
Application Descriptions (Cont.)
Docking Output Signal (Cont.)
Input Capacitor, Ci (Cont.)
Typical values for the output coupling capacitors are
This leakage current creates a DC offset voltage at
0.33µF to 1.0µF. If polarized coupling capacitors are
the input to the amplifier that reduces useful
used, connect their ’+’ terminals to the respective
headroom, especially in high gain applications. For
output pin.
this reason a low-leakage tantalum or ceramic ca-
The Right Dock and Left Dock channel outputs sig-
pacitor is the best choice. When polarized capaci-
nal are also used to driving internal volume control
tors are used, the positive side of the capacitor should
amplifier.
face the amplifier input in most applications as the
DC level there is held at VDD/2, which is likely higher
Input Capacitor, Ci
that the source DC level. Please note that it is impor-
In the typical application an input capacitor, Ci, is re-
tant to confirm the capacitor polarity in the application.
quired to allow the amplifier to bias the input signal to
Effective Bypass Capacitor, Cbypass
the proper DC level for optimum operation. In this
case, Ci and the minimum input impedance Ri form a
As other power amplifiers, proper supply bypassing
high-pass filter with the corner frequency determined
is critical for low noise performance and high power
in the follow equation:
supply rejection.
FC(highpass)=
1
2πRiCi
The capacitors located on the bypass and power
(3)
supply pins should be as close to the device as
The value of Ci is important to consider as it directly
possible. The effect of a larger half supply bypass
affects the low frequency performance of the circuit.
capacitor will improve PSRR due to increased half-
Consider the example where Ri is 100kΩ and the
supply stability. Typical application employ a 5V regu-
specification calls for a flat bass response down to
lator with 1.0µF and a 0.1µF bypass as supply filtering.
40Hz. Equation is reconfigured as follow:
This does not eliminate the need for bypassing the
Ci=
1
2πRifC
supply nodes of the APA4838. The selection of by-
(4)
pass capacitors, especially Cbypass, is thus depen-
Consider to input resistance variation, the Ci is 0.04µF
dent upon desired PSRR requirements, click and pop
so one would likely choose a value in the range of
performance.
0.1µF to 1.0µF.
To avoid start-up pop noise occurred, the bypass
A further consideration for this capacitor is the leak-
voltage should rise slower than the input bias voltage
age path from the input source through the input net-
and the relationship shown in equation (5) should be
work (Ri+Rf, Ci) to the load.
maintained.
1
1
<<
Cbypass x 125kΩ
RiCi
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
19
(5)
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APA4838
Application Descriptions (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.)
Power Supply Decoupling, Cs
The bypass capacitor is fed from a 125kΩ resistor
The APA4838 is a high-performance CMOS audio
inside the amplifier. Bypass capacitor, Cbypass, val-
amplifier that requires adequate power supply
ues of 3.3µF to 10µF ceramic or tantalum low-ESR
decoupling to ensure the output total harmonic dis-
capacitors are recommended for the best THD and
tortion (THD) is as low as possible. Power supply
noise performance.
decoupling also prevents the oscillations causing by
The bypass capacitance also effects to the start up
long lead length between the amplifier and the
time. It is determined in the following equation:
speaker. The optimum decoupling is achieved by
Tstart up = 5 x (Cbypass x 125kΩ)
(6)
using two different type capacitors that target on different type of noise on the power supply leads. For
Output Coupling Capacitor, Cc
higher frequency transients, spikes, or digital hash
In the typical single-supply (SE) configuration, an
on the line, a good low equivalent-series-resistance
output coupling capacitor (Cc) is required to block
(ESR) ceramic capacitor, typically 0.1µF placed as
the DC bias at the output of the amplifier thus pre-
close as possible to the device VDD lead works best.
venting DC currents in the load. As with the input
For filtering lower-frequency noise signals, a large
coupling capacitor, the output coupling capacitor and
aluminum electrolytic capacitor of 10µF or greater
impedance of the load form a high-pass filter gov-
placed near the audio power amplifier is
erned by equation.
recommended.
FC(highpass)=
1
2πRLCC
(7)
Optimizing Depop Circuitry
For example, a 330µF capacitor with an 8Ω speaker
Circuitry has been included in the APA4838 to mini-
would attenuate low frequencies below 60.6Hz. The
mize the amount of popping noise at power-up and
main disadvantage, from a performance standpoint,
when coming out of shutdown mode. Popping oc-
is the load impedance is typically small, which drives
curs whenever a voltage step is applied to the
the low-frequency corner higher degrading the bass
speaker. In order to eliminate clicks and pops, all
response. Large values of CC are required to pass
capacitors must be fully discharged before turn-on.
low frequencies into the load.
Rapid on/off switching of the device or the shutdown
function will cause the click and pop circuitry. The
value of Ci will also affect turn-on pops. (Refer to
Effective Bypass Capacitance) The bypass voltage
rise up should be slower than input bias voltage.
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APA4838
Application Descriptions (Cont.)
Optimizing Depop Circuitry (Cont.)
Shutdown and Mute Function (Cont.)
Although the bypass pin current source cannot be
The trigger point between a logic high and logic low
modified, the size of Cbypass can be changed to al-
level is typically 2.0V. It is best to switch between
ter the device turn-on time and the amount of clicks
ground and the supply voltage VDD to provide maxi-
and pops. By increasing the value of Cbypass, turn-
mum device performance.
on pop can be reduced. However, the tradeoff for
By switching the Shutdown pin to high level, the am-
using a larger bypass capacitor is to increase the turn-
plifier enters a low-current state, IDD<1µA. APA4838
on time for this device. There is a linear relationship
is in shutdown mode. On normal operating, Shut-
between the size of Cbypass and the turn-on time.
down pin pull to low level to keeping the IC out of the
In a SE configuration, the output coupling capacitor,
shutdown mode. The Shutdown pin should be tied
CC, is of particular concern. This capacitor discharges
to a definite voltage to avoid unwanted state changes.
through the internal 10kΩ resistors. Depending on
The APA4838 mutes the amplifier and DOCK out-
the size of CC, the time constant can be relatively
puts when VDD is applied to the Mute pin. Even while
large. To reduce transients in SE mode, an external
muted, the APA4838 will amplify a system alert (beep)
1kΩ resistor can be placed in parallel with the inter-
signal whose magnitude satisfies the PCBEEP de-
nal 10kΩ resistor. The tradeoff for using this resistor
tect circuitry. Applying 0V to the Mute pin returns the
is an increase in quiescent current.
APA4838 to normal operation. Prevent unanticipated
In the most cases, choosing a small value of Ci in the
mute behavior by connecting the Mute pin to VDD or
range of 0.33µF to 1µF, Cbypass being equal to 4.
ground. Do not let the Mute pin float.
7µF and an external 1kΩ resistor should be placed in
PCBEEP Detect Circuitry
parallel with the internal 10kΩ resistor should produce a virtually clickless and popless turn-on.
APA4838 integrates a PCBEEP detect circuit for note-
A high gain amplifier intensifies the problem as the
book and computer used. When Beep In signal is
small delta in voltage is multiplied by the gain. So it
greater than 1/2VDD, the PCBEEP mode is active.
is advantageous to use low-gain configurations.
APA4838 will force to BTL mode and the internal fixed
gain mode. The Beep In signal becomes the ampli-
Shutdown and Mute Function
fier input signal and plays on the system speaker with-
In order to reduce power consumption while not in
out coupling capacitor. Use input resistor between
use, the APA4838 contains a Shutdown pin to exter-
stereo input pin and Beep In to attenuate Beep In
nally turn off the amplifier bias circuitry. This shut-
signal. These resistors are shown as 200kΩ devices
down feature turns the amplifier off when a logic high
in Application Circuit. Use higher value resistors to
is placed on the Shutdown pin.
reduce the gain applied to the beep signal.
Copyright  ANPEC Electronics Corp.
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APA4838
Application Descriptions (Cont.)
PCBEEP Detect Circuitry (Cont.)
Internal and External Gain Selection (Cont.)
If the amplifier in the mute mode, it will out of mute
C LF
Gain 1
APA4838’s shutdown mode must be deactivated
before a system alert signal is applied to Beep In pin.
R I2
Gain 2
mode whenever PCBEEP mode enable. The
R F2
R LF
The APA4838 will return to previous setting when it
is out of PCBEEP mode. The Beep In pin should be
-Out
Volum e Control
Am plifier output signal
tied to a ground when not used to avoid unwanted
OP1
state changes.
Figure3: Bass Boost gain setting configuration
Mode Function
In some cases a designer may want to improve the
The APA4838’s Mode function has 2 states controlled
low frequency response of the bridged amplifier or
by the voltage applied to the Mode pin. By applying
incorporate a bass boost feature. Refer to the Figure,
0V to the Mode pin, forces the APA4838 to fixed gain
a resistor, RLF, and a capacitor, CLF, in parallel, can
amplifier and internal volume control block will be dis-
be placed in series with the feedback resistor of the
able and internal first amplifier output signal (Dock)
bridged amplifier as seen in Figure.
1
Fc=
2πRLFCLF
to power amplifier directly. When Mode pin goes to
high level, which uses the internal DC controlled vol-
(8)
ume control is selected. This mode sets the amplifier’s
The bridged-amplifier low frequency differential gain
gain according to the DC voltage applied to the DC
is:
Vol control pin. Do not let the Mode pin float when it
Fc=
does not used.
2x(RF2+RLF)
R12
(9)
Internal and External Gain Selection
Using the component values shown in Figure (RF2 =
APA4838 provides external gain setting for base
20kΩ,RLF = 20kΩ, and CLF = 0.068µF), a first-order, -
boost function or internal feedback gain setting which
6dB pole is created at 120Hz. Assuming R12 = 20kΩ,
is decided by Gain Select control input. If Gain Se-
the low frequency differential gain is 4. The input (Ci)
lect pin goes high level, the gain setting will be de-
and output (CO) capacitor values must be selected
fined by Gain1 and Gain2 pin. When Gain Select pin
for a low frequency response that covers the range
tied to low level, APA4835 power amplifier gain set-
of frequencies affected by the desired bass-boost
ting as unit gain by internal resistor.
operation.
Copyright  ANPEC Electronics Corp.
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APA4838
Application Descriptions (Cont.)
Internal and External Gain Selection (Cont.)
BTL Amplifier Efficiency
At low frequencies CLF is a virtual open circuit and at
An easy-to-use equation to calculate efficiency starts
high frequencies, its nearly zero ohm impedance
out as being equal to the ratio of power from the power
shorts RLF. The result is increased bridge-amplifier
supply to the power delivered to the load. The fol-
gain at low frequencies. The combination of RLF and
lowing equations are the basis for calculating ampli-
CLF form a -6dB corner frequency at
fier efficiency.
Efficiency =
Volume Adjustable and Fixed Gain selection
PO
PSUP
(10)
Where :
PO = VORMS x VORMS = VPxVP
2RL
RL
The APA4838 has an internal stereo volume control
whose setting is a function of the DC voltage applied
VORMS =
to the DC Vol control pin. The APA4838 volume con-
VP
√2
(11)
PSUP = VDD x IDDRMS = VDD x 2VP
πRL
trol consists of 31 steps that are individually selected
(12)
by a variable DC voltage level on the DC Vol control
Efficiency of a BTL configuration :
pin. The range of the steps, controlled by the DC
PO
VPxVP ) / (VDD x 2VP ) = πVP
=(
2VDD
PSUP
2RL
πRL
voltage, are from 0dB to -78dB. Each gain step cor-
(13)
responds to a specific input voltage range, as shown
in table. To minimize the effect of noise on the volPo (W) Efficiency (%) IDD(A) VPP(V) PD (W)
ume control pin, which can affect the selected gain
level, hysteresis and internal clock delay are
0.2
26.67
0.15
2.00
0.55
implemented. The amount of hysteresis corresponds
0.50
41.67
0.24
2.83
0.7
1.00
58.82
0.34
4.00
0.7
1.3
68.42
0.38
4.47
0.6
to half of the step width, as shown in volume control
graph.
For highest accuracy, the voltage shown in the ’recommended voltage’ column of the table is used to
**High peak voltages cause the THD to increase.
select a desired gain. This recommended voltage is
Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL
exactly halfway between the two nearest transitions.
Systems
The gain levels are 1dB/step from 0dB to -6dB, 2dB/
Table 1 calculates efficiencies for four different out-
step from -6dB to -52dB, and the last step at -78dB
put power levels when load is 8Ω.
as mute mode.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
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APA4838
Application Descriptions (Cont.)
BTL Amplifier Efficiency (Cont.)
Power Dissipation (Cont.)
The efficiency of the amplifier is quite low for lower
BTL mode : PD,MAX=
power levels and rises sharply as power to the load
4VDD2
2π2RL
(15)
is increased resulting in a nearly flat internal power
Since the APA4838 is a dual channel power amplifier,
dissipation over the normal operating range. Note
the maximum internal power dissipation is 2 times
that the internal dissipation at full output power is less
that both of equations depending on the mode of
than in the half power range. Calculating the efficiency
operation. Even with this substantial increase in power
for a specific system is the key to proper power sup-
dissipation, the APA4838 does not require extra
ply design. For a stereo 1W audio system with 8Ω
heatsink. The power dissipation from equation15,
loads and a 5V supply, the maximum draw on the
assuming a 5V-power supply and an 8Ω load, must
power supply is almost 3W.
not be greater than the power dissipation that results
A final point to remember about linear amplifiers
from the equation16:
(either SE or BTL) is how to manipulate the terms in
PD,MAX=
the efficiency equation to utmost advantage when
TJ,MAX - TA
θJA
(15)
possible. Note that in equation, V DD is in the
For TSSOP-28 package with and without thermal pad,
denominator. This indicates that as VDD goes down,
the thermal resistance (θJA) is equal to 45οC/W and
efficiency goes up. In other words, use the efficiency
50οC/W, respectively.
analysis to choose the correct supply voltage and
Since the maximum junction temperature (TJ,MAX) of
speaker impedance for the application.
APA4838 is 150οC and the ambient temperature (TA)
is defined by the power system design, the maximum
Power Dissipation
power dissipation which the IC package is able to
Whether the power amplifier is operated in BTL or
handle can be obtained from equation16. Once the
SE modes, power dissipation is a major concern. In
power dissipation is greater than the maximum limit
equation14 states the maximum power dissipation
(PD,MAX), either the supply voltage (V DD) must be
point for a SE mode operating at a given supply volt-
decreased, the load impedance (RL) must be in-
age and driving a specified load.
creased or the ambient temperature should be
SE mode : PD,MAX=
VDD 2
2π2RL
reduced.
(14)
In BTL mode operation, the output voltage swing is
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the
same given conditions is 4 times as in SE mode.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
24
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APA4838
Application Descriptions (Cont.)
Thermal Pad Considerations
The thermal pad must be connected to ground. The
package with thermal pad of the APA4838 requires
special attention on thermal design. If the thermal
design issues are not properly addressed, the
APA4838 4Ω will go into thermal shutdown when driving a 4Ω load.
The thermal pad on the bottom of the APA4838 should
be soldered down to a copper pad on the circuit board.
Heat can be conducted away from the thermal pad
through the copper plane to ambient. If the copper
plane is not on the top surface of the circuit board, 8
to 10 vias of 13 mil or smaller in diameter should be
used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must
be plated through and solder filled. The copper plane
used to conduct heat away from the thermal pad
should be as large as practical.
If the ambient temperature is higher than 25°C, a
larger copper plane or forced-air cooling will be required to keep the APA4838 junction temperature
below the thermal shutdown temperature (150°C).
In higher ambient temperature, higher airflow rate and/
or larger copper area will be required to keep the IC
out of thermal shutdown.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
25
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APA4838
Packaging Information
TS S O P / TS S O P -P ( R eference JE D E C R egistration M O -153)
e
N
2x E/2
E1
1
2
3
E
e/2
D
A2
A
(
2)
GAUGE
PLANE
A1
b
D1
S
EXPOSED THERMAL
PAD ZONE
E2
0.25
L
1
(L1)
(
3)
BOTTOM VIEW
(THERMALLY ENHANCED VARIATIONDS ONLY)
D im
A
A1
A2
b
D
D1
e
E
E1
E2
L
L1
R
R1
S
φ1
φ2
M illim eters
Inches
M in.
M ax.
1.2
0.00
0.15
0.80
1.05
0.19
0.3
6.4 (N =20PIN )
6.6 (N =20PIN )
7.7 (N =24PIN )
7.9 (N =24PIN )
9.6 (N =28PIN )
9.8 (N =28PIN )
4.2 B S C (N =20P IN )
4.7 B S C (N =24P IN )
3.8 B S C (N =28P IN )
0.65 B S C
6.40 B S C
4.30
4.50
3.0 B S C (N =20P IN )
3.2 B S C (N =24P IN )
2.8 B S C (N =28P IN )
0.45
0.75
1.0 R E F
0.09
0.09
0.2
0°
8°
12° R E F
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
26
M in.
M ax.
0.047
0.000
0.006
0.031
0.041
0.007
0.012
0.252 (N =20P IN ) 0.260 (N =20P IN )
0.303 (N =24P IN ) 0.311 (N =24P IN )
0.378 (N =28P IN ) 0.386 (N =28P IN )
0.165 B S C (N =20P IN )
0.188 B S C (N =24P IN )
0.150 B S C (N =28P IN )
0.026 B S C
0.252 BS C
0.169
0.177
0.118 B S C (N =20P IN )
0.127 B S C (N =24P IN )
0.110 B S C (N =28P IN )
0.018
0.030
0.039R E F
0.004
0.004
0.008
0°
8°
12° R E F
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APA4838
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
temperature
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak)
3°C/second max.
120 seconds max
Preheat temperature 125 ± 25°C)
60 – 150 seconds
Temperature maintained above 183°C
Time within 5°C of actual peak temperature 10 –20 seconds
Peak temperature range
220 +5/-0°C or 235 +5/-0°C
Ramp-down rate
6 °C /second max.
6 minutes max.
Time 25°C to peak temperature
VPR
10 °C /second max.
60 seconds
215-219°C or 235 +5/-0°C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bgas
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
27
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
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APA4838
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
D1
T2
J
C
A
B
T1
Application
TSSOP- 28
A
B
C
J
T1
T2
W
P
E
330 ±1
100 ref
13 ±0.5
2 ±0.5
16.4 ±0.2
2 ±0.2
16 ±0.3
12 ±0.1
1.75±0.1
F
D
D1
Po
P1
Ao
Bo
Ko
t
7.5 ±0.1
1.5 +0.1
1.5 min
4.0 ±0.1
2.0 ±0.1
6.9 ±0.1 10.2 ±0.1 1.8 ±0.1 0.3±0.05
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
28
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APA4838
Cover Tape Dimensions
Application
TSSOP- 28
Carrier Width
16
Cover Tape Width
21.3
Devices Per Reel
2000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003
29
www.anpec.com.tw