STA5620 Fully integrated RF front-end for GPS Preliminary Data Features ■ Low IF architecture (fIF = 4fO) ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7V supply voltage ■ SPI interface ■ 2kV HBM ESD protected ■ Compatible with GPS L1 ■ Standard QFN-32 package ■ Low power for portable designs VFQFPN-32L The magnitude data is internally integrated in order to control the variable gain amplifiers in accordance to the RF input signal strength. Description The chip is a fully integrated RF front-end able to down-convert the GPS L1 signal from 1575.42MHz to 4.092MHz. The IF signal is converted by a two bit ADC. Sign (SIGN), Magnitude (MAG) and the 16.368MHz sampling clock (GPS_CLK) are provided to the baseband. Table 1. An excellent quality of reception in critical environments is ensured by the good noise figure and linearity of the receiver. The on-chip oscillator supports crystal frequencies in the range of 10MHz to 40MHz. It is able to support TCXO providing also a buffered copy of the oscillator frequency. The chip, using STMicroelectronics BiCMOS SiGe technology, is housed in a QFN-32 package. Device summary Order code Marking Package Packing STA5620TR STA5620 VFQFPN-32L Tape & reel July 2007 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/29 www.st.com 1 Contents STA5620 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 5 6 7 2/29 3.1 RFA and MIXER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 IF section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Variable gain amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 PLL synthesizer and VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.9 Power control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin and I/O cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 RF_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 CHIP_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 TEST_EN1, TEST_EN2 and TEST_CLK . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 SPI_CS/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 SPI_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 SPI_DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 SPI_DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STA5620 8 Contents 7.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2 PLL N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 PLL R Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 Radio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.5 Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6 Debug register (sub-circuit enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.7 Radio trimming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.8 Receiver chain register (enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chip enable and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1.1 8.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3/29 List of tables STA5620 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. 4/29 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins list description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL N divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL R divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Radio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Debug register (sub-circuit enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Radio trimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Receiver chain register (enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STA5620 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins connection diagram (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip enable and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VFQFPN 32L (5x5x1.0mm) mechanical data and package dimensions . . . . . . . . . . . . . . 25 Reel, leader and trailer dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Carrier tape requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5/29 Block diagram 1 STA5620 Block diagram Figure 1. Block diagram AGC_CTRL RF chain IF_TEST IFB IR Mixer IF filter SIGN RF_IN RFA AGC 2 bits ADC Combiner MAG Polyphase Filter mag Buffer mag GCE & RFE 0˚ 90˚ CP CMOS Drivers PFD GPS_CLK /R /N TEST_EN1 TEST_EN2 TEST_CLK GCE Test Logic / 48 LO96 /2 MST SPI_CS/ SPI_CLK SPI_DI SPI_DO MODE RF_EN Xtal SPI Interface XTAL_CLK <chip config> reset Reset Generator Xtal Osc XCE xtal_clk CHIP_EN 6/29 xtal_clk XO XI AC00324 STA5620 2 Pins description Pins description Table 2. Pins list description PIN Symbol Description 1 VCC 2 AGC_CTRL 3 VCC 4 RF_IN 5 VCC RF amplifier power supply 6 GND Negative Supply Pin Gnd 7 GND Negative Supply Pin Gnd 8 VCC Charge pump power supply Supply pin 9 VCC Digital section power supply Supply pin 10 VCC VCO power supply Supply pin 11 VCC Crystal oscillator power supply Supply pin 12 XTAL_IN 13 XTAL_OUT Output Side of Crystal Oscillator 14 TEST_EN1 Test enable 1. Only for ST internal use Digital – input 15 CHIP_EN Chip Enable Digital – input 16 RF_EN RF/IF Receiver Chain Enable Digital – input 17 MODE Power-On Default Configuration Selector Digital – input 18 XTAL_CLK Crystal Oscillator Buffered Output Digital – output 19 GPS_CLK GPS Reference Clock Digital – output 20 TEST_CLK Test Clock. Only for ST internal use Digital – output 21 TEST_EN2 Test enable 2. Only for ST internal use Digital – input 22 SPI_DI Serial Parallel Interface Data Input Digital – input 23 SPI_CLK Serial Parallel Interface Clock Digital – input 24 SPI_CS/ Serial Parallel Interface Chip Select (Active Low) Digital – input 25 SPI_DO Serial Parallel Interface Data Output Digital – output 26 MAG Magnitude Data Digital – output 27 SIGN Sign Data Digital – output 28 GND_IO Output Drivers Ground 29 VCC_IO I/Os power supply Supply pin 30 VCC SPI power supply Supply pin 31 VCC A/D converter power supply Supply pin 32 IF_TEST IF section power supply Automatic Gain Control Pin Mixer power supply RF section input Input Side of Crystal Oscillator or TCXO Input RF/IF Receiver Chain Test Output Type Supply pin Analog – input Supply pin Analog – RF input Supply pin Analog – input Analog – output Gnd Analog – output 7/29 Pins description 8/29 VCC VCC VCC XTAL_IN XTAL_OUT TEST_EN1 CHIP_EN RF_EN Pins connection diagram (bottom view) 9 10 11 12 13 14 15 16 XTAL_CLK GND 6 19 GPS_CLK VCC 5 20 TEST_CLK RF_IN 4 21 TEST_EN2 VCC 3 22 SPI_DI AGC_CTRL 2 23 SPI_CLK VCC 1 24 SPI_CS 32 31 30 29 28 27 26 25 SPI_DO 18 MAG 7 SIGN GND GND_IO MODE VCC_IO 17 VCC 8 VCC VCC IF_TEST Figure 2. STA5620 AC00325 STA5620 Functional description 3 Functional description 3.1 RFA and MIXER section The 1575.42 MHz RF signal at the output of the external SAW filter is amplified by a RF amplifier (RFA) and then down converted by an image rejection mixer. The good performances of the cascade configuration and the technology choice guarantee a noise figure better than 4.5dB in typical conditions. In fact, the RFA gain is high enough to minimize the effects on the noise figure of the following integrated stages. The linearity of the RFA and Mixer section ensures immunity to RF blockers close to the GPS signal. Then it allows the use of low quality external pre-selection filters. Two ninety degrees out of phase signals are derived from the VCO and send to the input of the image rejection mixer. A minimum image rejection ratio of 20dB is guaranteed. The chosen IF frequency is 4fo = 4.092MHz. 3.2 IF section The output of the mixer combiner is processed through an integrated filter able to select the GPS L1 bands. The IF filter cuts any out-of-band signal including the mixer products. In addition it acts as an anti-aliasing filter for the A/D converter. An attenuation of 20dB is guaranteed at 12fo = 12.276 MHz. The IF filter characteristic is calibrated by an internal loop which compensates process, temperature and voltage variations. In order to let the baseband reconstruct the received information, the IF filter must not introduce an excessive phase shift within the signal bandwidth. 3.3 Variable gain amplifiers A cascade of variable gain amplifiers and the relevant control circuit balance the system gain in relationship to the RF input signal strength. In that way the signal level at the input of the A/D converter is suitably compensated. The device is able to self-adjust the AGC gain by integrating the MAG output by a dedicated circuit in order to obtain 33% of MAG bit duty cycle. The loop is compensated by an external capacitor connected to the AGC_CTRL pin. The relevant voltage is used to control the variable gain amplifiers. The internal loop can be by-passed by setting a voltage to the AGC_CTRL input pin. A dynamic range of around 55dB is typically achieved. 3.4 A/D converter The task of the A/D converter is to determine the sign and the magnitude of the received signal. The A/D converter sampling frequency is 16fo = 16.368 MHz. Those baseband chips with just one bit input will use only the sign bit. In that case the AGC_CTRL pin must be connected to ground. 9/29 Functional description 3.5 STA5620 PLL synthesizer and VCO The PLL synthesizer is fully integrated on-chip, it is made by the voltage controlled oscillator (VCO), prescaler, dividers, phase-frequency detector (PFD), charge pump (CP) and loop filter. Both the reference divider R and the feedback divider N are programmable helping the user to choose the reference clock. The R divider ranges from 1 to 63 while the N divider from 56 to 4095. In order to achieve good phase noise performances, a LC voltage controlled oscillator has been chosen. Quadrature signals are provided by means of a Polyphase filter. A programmable loop filter is integrated on-chip to reduce the number of external components. The loop stability is guaranteed for any of the supported crystals and comparison frequencies. The charge pump is programmable and the output current can be selected among the following values: 50µA, 100µA, 150µA and 200µA. 3.6 Crystal oscillator The reference oscillator circuit is a CMOS inverter able to work with external crystals up to 40 MHz. The crystal must be connected between the xtal input and the xtal output pins. The load capacitances must be chosen in accordance to the values specified by the crystal manufacturer. A limiting resistor can be placed at the output of the inverter in order to contain the power dissipated in the crystal within its specified maximum value. When a TCXO is used the external reference clock must be applied to the XTAL_IN terminal. 3.7 Output buffers The RF front-end provides a set of four different signals to the baseband chip. The SIGN and the MAG outputs are the sampled bit streams of the down-converted received signal. GPS_CLK, nominally equal to 16.368 MHz, is the clock signal used by the baseband. Its source can be chosen among the crystal oscillator signal and the VCO signal by means of a 96 divider. XTAL_CLK is the buffered copy of either the crystal oscillator or the TCXO signal. In order to let the application find the best compromise between electro-magnetic interferences and the drivers speed, the output stages slew-rate can be programmed by SPI. 3.8 SPI interface A SPI interface manages the communication between the baseband chip and the RF frontend. Four lines are required to accomplish this task: a data input line (SPI_DI), a data output line (SPI_DO), a clock line (SPI_CLK) and a chip select line (SPI_CS/) active low. Any information can be passed to the RF receiver through the SPI interface depending on the CHIP_EN and RF_EN input pins status. 10/29 STA5620 3.9 Functional description Power control modes Three different power control modes can be chosen by means of the CHIP_EN and the RF_EN pins. If the CHIP_EN pin is forced low the device goes to stand-by mode with very low power consumption. On the other hand, if CHIP_EN is set high, two scenarios are possible: 1. IIf RF_EN = 0 the crystal oscillator and only one output buffer are enabled, XTAL_CLK if MODE = 1 or GPS_CLK if MODE = 0; 2. If RF_EN = 1 the whole chip is active and functional. Only if MODE = 0 the XTAL_CLK output is disabled. A logic reset of the SPI registers is generated by the low to high transitions of the CHIP_EN pin. External pin strapping dominates until some SPI commands reverse the priority and overrides the strapping until next reset. 11/29 Electrical specifications STA5620 4 Electrical specifications 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Min Max Unit All supply voltages -0.3 3.6 V TJ Junction operating temperature -40 125 °C TS Storage temperature -65 150 °C - 2 kV - 200 V - 750 V VCC ESDHBM Electro static discharge – Human body model Electro static discharge – Machine model ESDMM ESDCDM Electro static discharge - Charged device model 4.2 Thermal data Table 4. Thermal data Symbol Parameter Ambient operating temperature Tamb Rth j-amb Thermal resistance junction to ambient 4.3 Electrical characteristics Table 5. Electrical characteristics (VCC = 2.7V, TJ = 25°C unless otherwise noted) Symbol Parameter Test conditions Value Unit -40 to 85 °C 40 °C/W Min Typ Max Unit Analog, Digital 2.56 2.7 3.3 V I/O supply 1.7 3.3 V Supply VCC Vcc_IO Total power consumption Internal blocks ON 15 19 mA ICC_CLK Clock only power consumption Crystal oscillator ON 1.5 1.8 mA ICC_STB Stand-by power consumption Internal blocks OFF 1 μA 1575.42 MHz 4.092 MHz ICC RFA – MIXER – IF FILTER – VGA fIN RFA Input frequency fIF IF frequency GC Conversion gain 12/29 VGA at max gain 105 VGA at min gain 50 dB STA5620 Table 5. Electrical specifications Electrical characteristics (continued) (VCC = 2.7V, TJ = 25°C unless otherwise noted) Symbol ΔGC Parameter VGA range Test conditions Set VAGC_CTRL < 0.3V for maximum gain VAGC_CTRL AGC Control Voltage Range GSENS NF_RF-IF P_1dB IRR Typ Max 55 0 VGA sensitivity Unit dB Vcc V 36 dB/V RF-IF-VGA noise figure f = 4.092MHz VGA at max gain 4.5 dB RF-IF-VGA 1dB input compression point VGA at min gain -57 dBm Mixer image rejection ratio f = 2 to 6 MHz 20 dB 6 MHz IFF3dB IF filter cut-off frequency IFFATT IF filter out of band attenuation f = 12.276MHz RFA Input voltage stat. wave ratio ZS=50Ω VSWRIN Min 20 dB 2:1 - 40 MHz 10 msec Crystal oscillator – Integer-N synthesizer – VCO FXTAL tSTART-UP PXTAL_IN XTAL frequency XTAL oscillator start-up time Reference input signal sensitivity RDIV Reference divider range FLO LO operating frequency NDIV VCO divider range KV (1) 10 XTAL_IN pin DC blocked. No crystal mounted. XTAL_OUT load <10pF. 1 VCO phase noise 100 kHz offset PNPLL PLL phase noise 1 kHz offset ICP(1) Charge pump current ΔICP(1) 63 56 f = 1571.328 MHz PNVCO dBm 1571.328 VCO gain (1) -20 Charge pump current steps MHz 4095 300 MHz/V -80 -65 50 - dBc/Hz dBc/Hz 200 µA 50 µA 16.368 MHz 33 % 50 % ADC – Output signals – GPS clock fADC ADC sampling frequency τ MAG MAG duty cycle τ SIGN SIGN duty cycle fCLOCK Output clock frequency 16.368 MHz τ CLOCK Output clock duty cycle 50 % Internally regulated 13/29 Electrical specifications Table 5. STA5620 Electrical characteristics (continued) (VCC = 2.7V, TJ = 25°C unless otherwise noted) Symbol Parameter Test conditions Min Typ Max Unit Input and output buffers VIH CMOS input high level VIL CMOS input high level CIN CMOS input capacitance VOH CMOS output high level VOL CMOS output low level tRISE(2) tFALL(2) CMOS output rise time CMOS output fall time 1. This value is guaranteed by design. 2. Simulation data. 14/29 0.8·VCC V 0.2·VCC V 1 pF 0.9·VCC V 0.1·VCC V CL=10pF, from 10% to 90% Slew-rate = fast 3 ns CL=10pF, from 10% to 90% Slew-rate = slow 6 ns CL=10pF, from 10% to 90% Slew-rate = fast 3 ns CL=10pF, from 10% to 90% Slew-rate = slow 6 ns STA5620 Pin and I/O cells 5 Pin and I/O cells 5.1 Mode This pin allows a choice of initial configuration of the registers at reset. This pin will always be an input. In application this pin will be connected either LO or HI. When it is low the chip is configured to use 16.368MHz as reference frequency, otherwise the reference frequency is 19.2MHz. To use other reference frequencies the MODE bit must be overwritten by SPI. 5.2 RF_EN This pin provides control over the operating state of the RF and PLL sections. When it is low those blocks are off, when high the status of the blocks depends of CHIP_EN. This pin will always be an input. 5.3 CHIP_EN This pin provides control over the operating state of the chip. When it is low the entire chip is disabled and only a leakage current is present (< 10µA). On the rising edge it provides the SPI with a reset signal, the SPI default status depends on MODE and RF_EN pins status. When it is high the entire chip is enabled. This pin will always be an input. 5.4 TEST_EN1, TEST_EN2 and TEST_CLK Those PINs are for ST test only. In the application TEST_EN1 must be set LOW, TEST_EN2 must be set HIGH (VCC_IO) and TEST_CLK must be not connected. 15/29 SPI bus protocol 6 STA5620 SPI bus protocol The SPI port is used for data exchange between STA5620 and a GPS base band. The SPI port is controlled by four pins SPI_CLK, SPI_DI, SPI_DO and SPI_CS/. These pins are inputs only, except for SPI_DO, the data output. The SPI Bus protocol is based on a 2-phase transfer made of an address cycle and a data cycle. The two functions in the bus interface layer are: Figure 3. SPI byte write CS/ SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO AC00327 Figure 4. SPI byte read CS/ SCLK SDI A7 SDO A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 AC00326 6.1 SPI_CS/ This package pin provides the frame and CS/ connection for the serial interface (SPI). This pin will always be an input. 6.2 SPI_CLK This package pin provides the clock connection for the serial interface (SPI). This pin will always be an input. 6.3 SPI_DI This package pin provides the data input connection for the serial interface (SPI). This pin will always be an input. 6.4 SPI_DO This package pin provides the data output connection for the serial interface (SPI). This pin will always be an output. 16/29 STA5620 Registers 7 Registers 7.1 Register map Table 6. Register map Address R/W Bit 7 6 5 4 3 - - - - ----------------- NDIV[11:8] ----------------- 0xC0/40 0xC1/41 1 0 --------------------------------------------------- NDIV[7:0] ---------------------------------------------------- 0xC2/42 - - 0xC3/43 ----------------------------------- RDIV[5:0] ---------------------------------Reserved GCE 0xD0/50 - 0xD1/51 ENM Reserved AGC 0xD2/52 - - - 0xE0/60 RFE - PLL N Divider Table 7. PLL N divider Name 0x40 Bit LSR IF MIX PLL R Divider Table 8. PLL R divider RFA -------------- LFC[2:0] --------------- PLL VCO ----- CPI[1,0] ----- Reserved Default value MODE = 0 (decimal) Default value MODE = 1 (decimal) Description 96 1555 PLL Feedback Divider Division Ratio Description nnnn nnnn [0:7] 7.3 MST IFB XXXX nnnn [0:3] NDIV 0x41 XCE Reserved 7.2 Register address 2 Register address Name Bit Default value MODE = 0 (decimal) Default value MODE = 1 (decimal) 0x42 RDIV XXrr rrrr [0:5] 1 19 Reference Divider Division Ratio Note that registers 40, 41 and 42 are delivered on a single 24 bit bus. New register values are delivered synchronously to the bus only after register 42 is written. 17/29 Registers STA5620 7.4 Radio configuration register Table 9. Radio configuration register Register address Name Bit Default value MODE = 0 Default value MODE = 1 Description MST = 0 GPS_CLK output equal to Xtal MST XXXX XXX y [0] 0 1 MST = 1 GPS_CLK output equal to LO96 LSR = 0 slow slew rate mode not active LSR XXXX XX y X [1] 1 1 LSR = 1 slow slew rate mode active 0x43 XCE = 0 XTAL_CLK buffer is OFF XCE XXXX X y XX [2] 0 1 XCE = 1 XTAL_CLK buffer is ON GCE = 0 GPS_CLK buffer is OFF GCE XXXX y XXX [3] 1 1 GCE = 1 GPS_CLK buffer is ON 7.5 Test register Table 10. Test register Register address Name Bit Default value MODE = 0 Default value MODE = 1 Description IFB = 0 The IF Buffer is OFF 0x50 IFB XXXX XXX y [1] 0 0 IFB = 1 The IF Buffer is ON 18/29 STA5620 Registers 7.6 Debug register (sub-circuit enables) Table 11. Debug register (sub-circuit enables) Register address Name Bit Default value MODE = 0 Default value MODE = 1 Description VCO = 0 The VCO block is OFF VCO XXXX XXX y [0] 1 1 VCO = 1 The VCO block is ON PLL = 0 The PLL block is OFF PLL XXXX XX y X [1] 1 1 PLL = 1 The PLL block is ON RFA = 0 The RF Amplifier is OFF RFA XXXX X y XX [2] 1 1 RFA = 1 The RF Amplifier is ON MIX = 0 The Mixer is OFF MIX XXXX y XXX [3] 1 1 MIX = 1 The Mixer is ON 0x51 IF = 0 The IF chain from Polyphase filter to ADC is OFF IF XXX y XXXX [4] 1 1 IF = 1 The IF chain from Polyphase filter to ADC is ON AGC = 0 The Automatic Gain Control is OFF AGC XX y X XXXX [5] 1 1 AGC = 1 The Automatic Gain Control is ON ENM y XXX XXXX [7] 1 1 ENM = 0 The whole chip is OFF except the Xtal Osc and the GPS_CLK and/or XTAL_CLK buffers ENM = 1 RF chain is On (If RFE bit or RF_EN pin = 1) 19/29 Registers STA5620 7.7 Radio trimming register Table 12. Radio trimming register Register address Name Default value MODE = 0 Bit Default value MODE = 1 Description CPI = 00 50µA charge pump current CPI = 01 100µA charge pump current CPI XXXX XX yy [0:1] 11 11 0x52 CPI = 10 150µA charge pump current CPI = 11 200µA charge pump current LFC XXXy yyXX [2:4] 110 110 7.8 Receiver chain register (enable) Table 13. Receiver chain register (enable) Register address 0x60 Name RFE Bit XXXX XXX y [0] Default value MODE = 0 0 Loop filter control Default value MODE = 1 0 Description RFE = 0 The RF chain is controlled by RF_EN pin RFE = 1 The RF chain is ON 20/29 STA5620 8 Chip enable and reset timing Chip enable and reset timing Figure 5. Chip enable and reset timing VDD Power CHIP_EN Mode = 1 MODE Mode = 0 Internal Oscillator reset Xce (XTAL_CLK enable) <chip config> Power -on 8.1 MODE Clock Out Pin setting Enable (min 1µs) Internal reset (min. 4ms) Chip Config setting AC00328 Principle of operation With power supply applied and CHIP_EN inactive the chip is in stand-by mode consuming just a minimal leakage current (<10µA). Applying CHIP_EN High turns-on the chip and starts the Crystal oscillator. Two internal counters driven by the Oscillator output are used to create two timing periods to: ● The first time period (Clock Out Enable) is long enough to safely enable XTAL_CLK as early as possible by default during oscillator startup. ● The second period (Internal reset) generates an internal reset pulse long enough to guarantee open-loop clock stabilization (driven either by internal oscillator or by off-chip TCXO) and be able to load the chip default configuration. The default initial configurations depend on the state of the MODE input pin. After this phase, the chip configuration may be modified by the baseband unit with a set of SPI commands, allowing a more specific configuration to be set 21/29 Chip enable and reset timing 8.1.1 STA5620 Operating modes The below table shows how select a particular default operating mode: Table 14. Operating modes Operating modes STA5620 current consumption CHIP_EN RF_EN HIGH HIGH LOW HIGH 1.5mA HIGH LOW LOW HIGH 1μA LOW x LOW HIGH MODE = 0 15mA MODE = 1 16mA Fully operating RF Chain OFF Crystal oscillator ON Stand-by All internal blocks OFF TEST_EN1 TEST_EN2 HIGH = VCC_IO; LOW = GND MODE LOW → sets the STA5620 internal dividers to work with 16.368 MHz reference and GPS_CLK = ON and XTAL_CLK = OFF; HIGH → sets the STA5620 internal dividers to work with 19.2 MHz reference and GPS_CLK = ON and XTAL_CLK = ON; In both cases GPS_CLK pin provides 16.368MHz clock to Base Band and SIGN pin provides the DATA to Base Band. CHIP_EN LOW → the device goes to stand-by mode with very low power consumption. HIGH → sets ON the internal blocks of the IC according to the RF_EN status; A logic reset of the SPI registers is generated by the low to high transitions of the CHIP_EN pin while the RF_EN is LOW. RF_EN LOW → the crystal oscillator and only one output buffer are enabled, XTAL_CLK if MODE = 1 or GPS_CLK if MODE = 0; HIGH → the whole chip is active and functional; TEST_EN1 → must be set LOW; TEST_EN2 → 'must be set HIGH (VCC_IO); 22/29 STA5620 8.2 Chip enable and reset timing Default configuration This table describes the default configuration of the STA5620 internal registers. Table 15. Bit Name Default configuration Description Values (MODE_EN=0) (MODE_EN=1) 0 1 16.368MHz 19.200MHz Sample mode configuration MST Sample clock Source Selector 0 = Xtal Osc 1 = VCO/96, Default xtal/TCXO frequency Power enable configuration ENM RF Chain Enable (From the RFA Input to the AGC Output) 0 = RF chain OFF, 1 = RF chain On If RFE bit or RF_EN pin = 1 1 1 RFE RF Chain Enable (From the RFA Input to the AGC Output) 0 = controlled by RF_EN pin, 1 = RF chain On 0 0 GCE GPS Clock Enable 0 = GPS clock Off, 1 = GPS clock On 1 1 AGC Automatic Control Gain Enable 0 = AGC function Off, 1 = AGC function On 1 1 XCE Xtal Clock Enable 0 = Off, 1 = On 0 1 IFB IF Output Buffer Enable 0 = Off, 1 = On 0 0 Voltage Controlled Oscillator Enable 0 = Off, 1 = On 1 1 IF enable 0 = Off, 1 = On 1 1 MIX Mixer enable 0 = Off, 1 = On 1 1 RFA RF Amplifier enable 0 = Off, 1 = On 1 1 PLL Phase Locked Loop Enable (Dividers, PFD, Charge Pump). 0 = Off, 1 = On 1 1 VCO IF 23/29 Chip enable and reset timing Table 15. STA5620 Default configuration (continued) Bit Name Description Values (MODE_EN=0) (MODE_EN=1) Divider configuration NDIV[11:0] PLL Feedback Divider Division Ratio (mapped as 2 byte registers) 56 to 4095 96 1555 RDIV[5:0] Reference Divider Division Ratio (write of this register updates all of the ndiv, rdiv vector) 1 to 63 1 19 00 = 50μA 01 = 100μA 10 = 150μA 11 = 200μA 11 11 0 = Fast 1 = Slow 1 1 Charge pump current selector CPI[1:0] Charge Pump Current Selector Output slew rate control LSR Note: 24/29 XTAL_CLK, GPS_CLK,TEST_CLK, SPI_DO, SIGN and MAG Output Drivers Slew Rate Disabling a digital output buffer means driving it low. STA5620 9 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. VFQFPN 32L (5x5x1.0mm) mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 0.800 0.900 1.000 0.031 0.035 0.039 A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.020 0.050 A3 0.200 0.0008 0.0020 0.0079 b 0.180 0.250 0.300 0.0071 0.0098 0.0118 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.500 3.600 3.700 0.1378 0.1417 0.1457 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.500 3.600 3.700 0.1378 0.1417 0.1457 e L ddd 0.500 0.300 0.400 OUTLINE AND MECHANICAL DATA 0.0197 0.500 0.0118 0.0157 0.0197 0.050 0.0020 VFQFPN32 (5x5x1.0mm) Very Fine Quad Flat Package No lead 7376875 F 25/29 Packing information 10 Packing information Figure 7. 26/29 STA5620 Reel, leader and trailer dimensions Tape sizes A max B min C D min N min G T max 12mm 330 1.5 13 ±0.2 20.2 60 12.4 +2/-0 18.4 STA5620 Packing information Figure 8. Carrier tape requirements Figure 9. Orientation 27/29 Revision history 11 STA5620 Revision history Table 16. 28/29 Document revision history Date Revision 24-Jul-2007 1 Changes Initial release. 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