Preliminary PT4501 Sub-1 GHz Wideband FSK Transceiver DESCRIPTION The PT4501 is a highly integrated wideband FSK multi-channel half-duplex transceiver operating in sub-1 GHz license-free ISM bands. The PT4501 is supplied in a small 4 mm x 4 mm QFN-24 package, offers low power consumption, and is specified to operate in the consumer –40°C to +85°C temperature range. The receive part utilizes a fully integrated low-IF architecture. Direct PLL modulation with the fractional-N synthesizer is used for FSK transmission. The device supports data rates up to 50 Kb/s in Manchester, bi-phase and other coding formats in transparent mode and provides a typical output power of +10 dBm into a 50 Ω load at 433.92 MHz, and +9 dBm at 915 MHz and achieves typical sensitivities of – 113 dBm at 433.92 MHz and –110 dBm at 915 MHz for FSK data. The PT4501 is suitable for wireless applications in unlicensed (ISM) bands and requires few external components due to its high level of integration. APPLICATIONS Remote Control / Remote Sensing Remote Metering 2-Way Remote Keyless Entry Home Automation Local Telemetry Systems Wireless Modem FEATURES Carrier frequency range: 300 MHz to 960 MHz Supply voltage range: 1.9 V to 3.6 V Low current consumption: frequency band: 14.5 mA for receive-mode and 30 mA for transmit-mode (+9 dBm at 915 MHz and +10 dBm at 433.92 MHz) Programmable RF output power with 20 dB power control range Programmable channel-select filter bandwidth of 200 KHz / 300 KHz / 400 KHz Excellent FSK sensitivity: –113 dBm (300 KHz channel bandwidth and 0.1% BER) at 433.92 MHz and –110 dBm 915 MHz > 25 dB image-rejection Few external components 50 dB RSSI range Power down function (< 1 μA current consumption in power-down mode) 4-wire SPI interface 2 separate TX and RX FIFOs (32 bytes each) QFN-24 package (4 mm × 4 mm) BENEFITS Low system cost due to high system integration level Extended battery life because of the low power consumption and the minimum supply voltage down to 1.9 V Merged RF input/output matching to save the external T/R switch Single-ended RF interface with high isolation of PLL/VCO from PA and the power supply allows for easy incorporation of dipole or loop antenna Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan PT4501 CSF_ VTUNE RSSI CWTHRE CE 23 22 21 20 Regulator AGC 2 RXIN 3 Limiter LNA I Q 90o Frequency Synthesizer I/Q Generator 0o TXOUT RX FIFOs 19 SCLK 18 MOSI 17 MISO 16 SS 15 GIO 14 RFSEL 13 TXRXHW Channel Select BPF 4 PA Digital Control Interface VSSLNA RSSI Image-Rejection Mixer Enhanced Baseband Engine 1 24 FSK Modulator/ Demodulator VRF VIF BLOCK DIAGRAM TX FIFOs XOSC VDDTX 6 PRE1.1 2 10 11 12 TVDD VD VVCO 9 XO 8 Regulator XI 7 AVDD Regulator September 2014 PT4501 CE SCLK 23 22 21 20 19 CSF_ VTUNE RSSI CWTHRE CE SCLK APPLICATION CIRCUIT C8 R1 R2 VIF U1 24 VRF 2 VSSLNA 3 RXIN 4 TXOUT 5 NC 6 VDDTX C9 VDDTX 8 9 10 11 X1 17 MISO SS 16 SS GIO 15 GIO RFSEL 14 TXRXHW 13 12 C7 C4 C10 MOSI MISO VD 7 AVDD R4 TVDD VDDTX R3 VVCO VDD_3V L3 AVDD C3 18 PT4501 ANT L2 MOSI TVDD C2 1 XI L1 XO C1 R5 AVDD C5 C11 C6 R6 TVDD C13 C12 BILL OF MATERIALS Part Value 315 MHz 434 MHz 470 MHz 868 MHz 915 MHz Unit C1/C4/C7/C10/C13 10n 10n 10n 10n 10n F C2 2.7p 1.5p 1.5p 1.2p 1.5p F C3 220p 220p 220p 680p 680p F C5/C6 33p/33p 33p/33p 33p/33p 33p/33p 33p/33p F C8 680p 680p 680p 680p 680p F C9 10μ 10μ 10μ 10μ 10μ F C11/C12 NC NC NC NC NC F L1 39n 6.8n 33n 10n 8.2n H L2 47n 6.8n 6.8n 5.6n 5.6n H L3 18n 22n 22n 33n 39n H R1 68K 68K 68K 68K 68K Ω R2 150K 150K 150K 150K 150K Ω R3 0 0 0 0 0 Ω R4/R5/R6 10 10 10 10 10 Ω X1 (crystal) 20 MHz U1 PT4501 IC - Notes: 1. L1/L2/L3 and C2/C3 are the components for input matching network. They may need to be adjusted for different PCB layout and antenna requirements. 2. R1 is used for adjusting the threshold voltage of carrier sense window. PRE1.1 3 September 2014 PT4501 ORDER INFORMATION Valid Part Number PT4501 Package Type 24 Pins, QFN Top Code PT4501 PRE1.1 VIF CSF_ VTUNE RSSI CWTHRE CE SCLK 24 23 22 21 20 19 PIN CONFIGURATION VRF 1 18 MOSI VSSLNA 2 17 MISO RXIN 3 16 SS TXOUT 4 15 GIO NC 5 14 RFSEL VDDTX 6 13 TXRXHW 7 8 9 10 11 12 AVDD VVCO XI XO TVDD VD Ground Paddle 4 September 2014 PT4501 PIN DESCRIPTION PRE1.1 Pin No. Pin Name I/O Description 1 VRF P Regulated 1.8V voltage for RF domain of receive chain 2 VSSLNA G Ground for low noise amplifier (LNA) 3 RXIN I Receiver RF input, connected to antenna through matching circuit 4 TXOUT O Transmitter RF output, connected to antenna through matching circuit 5 NC — No connection 6 VDDTX P External supply voltage for transmit and LO chains, 3 V input 7 AVDD P External supply voltage for analog domain, 3 V input 8 VVCO P Regulated 1.8V supply voltage for VCO 9 XI I Crystal oscillator input 10 XO O Crystal oscillator output 11 TVDD P External supply voltage for digital domain, 3 V input 12 VD P Regulated 1.8V supply voltage for digital domain 13 TXRXHW I TX/RX hardware control pin 14 RFSEL I RF frequency band (433.92/915 MHz) select pin 15 GIO I/O 16 SS I 4-wire SPI interface low active slave select, 3 V logic 17 MISO O 4-wire SPI interface serial data output, 3 V logic 18 MOSI I 4-wire SPI interface serial data input, 3 V logic 19 SCLK I 20 CE I 4-wire SPI interface serial clock, 3 V logic Chip-enable control pin, 3 V logic (CE = H = chip enable; CE = L = chip disable) 21 CWTHRE I/O Threshold voltage for carrier sense window General purpose input/output, 3 V logic 22 RSSI O Received signal strength indicator voltage 23 CSF_VTUNE I/O Tuning voltage for channel select filter 24 VIF P Regulated 1.8V voltage for analog domain of receive chain 5 September 2014 PT4501 FUNCTIONAL DESCRIPTION The PT4501 is a low power, wideband FSK single-chip radio transceiver intended primarily for sub-GHz frequency bands, including 304–316, 430–440, 470–510, 860–880, and 900–930 MHz. The PT4501 operates as a time division duplex (TDD) transceiver where the device alternately transmits and receives data. Both transparent mode (data stream through GIO pin), or packet mode (data packet through FIFOs) are supported. Designed with a high level of integration and typically paired with a microcontroller while requiring few external passive components, the PT4501 works over a supply voltage range from 1.9 to 3.6 V and its low current consumption is well-suited for portable applications. A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate simultaneously. The LO signal is generated with a monolithic VCO and fractional-N PLL synthesizer 16 with a maximum frequency resolution of fREF/2 Hz. The transmit chain is based on direct synthesis of the transmit frequency by the fractional-N synthesizer (in-loop modulation of the FSK data). The transmit chain contains a power amplifier (PA) that provides an output power up to +10 dBm with a power control range of 20 dB. The PA output is single-ended to allow for easy antenna matching since no transformer is needed. The receive chain consists of a low noise amplifier to suppress the noise of succeeding stages for optimal sensitivity, a down-conversion mixer to convert the modulated RF signal to a low IF frequency, a channel select filter (CSF) to provide selectivity, a limiting amplifier followed by a digital FSK demodulator, baseband filter and data slicer to recover the received data. The PT4501 supports data rates up to 50 Kb/s in Manchester, bi-phase and other coding formats when operated in transparent mode. POWER-DOWN AND TX/RX MODE CONTROL The PT4501 provides four distinct operating modes: (1) fully active, (2) stand-by, (3) doze, and (4) sleep and includes both hardware (CE pin) and software (PWDN<1:0> bits in the MAIN (0x00h) control register) power-down mode control. The setting of the hardware power-down pin, CE, overrides the software-controlled power-saving modes when CE is tied to logic LOW. When the CE pin is tied to logic HIGH, the PWDN<1:0> bits set the operating state of the chip. Gray coding has been used for the PWDN<1:0> bits in order to minimize glitches while switching from one operating mode to the other. When switching from doze to fully active mode, stand-by should be selected first. In the fully-active mode, the PT4501 is set to operate in transmit or receive mode according to a combination of the HTRC control bit and either the TXRXHW pin or the TXRX control bit. When the HTRC bit is logic HIGH (default), the TX/RX select hardwire control pin (TXRXHW) is active. When the HTRC bit is set to logic LOW, the TXRX control bit is active. The relationships among the CE and TXRXHW control pins and the PWDN<1:0> and TXRX register bits and the PT4501’s operating state are described in the table below. CE Pin PWDN<1:0> fully-active (receive) fully-active (transmit) HIGH 10 stand-by HIGH doze sleep HIGH LOW Operating Mode PRE1.1 Hardwire TX/RX Control Software TX/RX Control (HTRC = HIGH) (HTRC = LOW) Description TXRX TXRXHW Pin TXRX TXRXHW Pin × LOW LOW × all receiver circuits active × HIGH HIGH × all transmit circuits active 11 × × × × 0× ×× × × × × × × × × 6 SPI active; reference oscillator active SPI data retained all circuits disabled September 2014 PT4501 FREQUENCY SYNTHESIZER The fully-integrated, fractional-N PLL synthesizer provides coverage for several sub-GHz frequency bands listed previously. Use of the fractional-N synthesizer allows for flexibility in channel frequency and channel spacing selection. For a nominal 20 MHz crystal reference frequency (fREF), the frequency resolution is 305 Hz for the 900–930 MHz band. The fully-monolithic VCO output drives a divider with selectable modulus (determined by the BSEL<2:0> setting) which divides the VCO signal down to the desired output frequency band. Transmit FSK modulation is achieved by directly programming the N-divider modulus under the closed-loop control of the fractional-N synthesizer. REFERENCE INPUT The PT4501 supports both 16 and 20 MHz reference frequencies according to the FREF control bit setting. The on-chip amplitude-regulated Pierce reference oscillator circuit may utilize an inexpensive quartz crystal to operate as a reliable PLL reference. The reference oscillator is enabled by default upon chip power-up and is disabled in either (1) power-down mode by setting the CE pin to logic LOW or (2) doze mode by setting the control bits PWDN<1:0> to 01 b. Errors in the crystal frequency in receive mode may be corrected by adjusting the FEC<11:0> bits. N-DIVIDER The synthesized VCO output frequency is controlled thru the integer (NK<23:16>) and fractional (NK<15:0>) divider control registers. The VCO output frequency is also determined by the modulator dither control setting (PLLNS<1:0>) according to the table below. Note that the general NK<23:0> frequency control word refers to the specific names which include suffixes in the configuration register tables according to whether the PT4501 is operating in receive or transmit mode (e.g. NKRX<23:0> or NKTX<23:0>). Dither mode Low noise Low noise/low spur 1 Low noise/low spur 2 Low spur PRE1.1 PLLNS<1:0> 00 01 10 11 VCO Frequency (fVCO) 16 fREF × (NK<23:16> + K<15:0>/2 ) 16 fREF × (NK<23:16> + (2 × K<15:1>)/2 ) 16 fREF × (NK<23:16> + K<15:0>/2 ) 16 fREF × (NK<23:16> + (2 × K<15:0> + 0.5)/2 ) 7 September 2014 PT4501 LOCK DETECT The synthesizer includes a digitally-filtered lock detect function which is implemented by comparing the phase error between the inputs to the PLL’s phase/frequency detector to an R-C generated delay of 15 ns. To enter the locked state, the phase error must be less than 15 ns for sixteen (16) consecutive comparison cycles. To exit the locked state, the phase error must exceed 30 ns. A flow chart representing the operation of the lock detect circuit is given below. The lock detect circuit asserts a logic HIGH when the PLL is phase-locked and is LOW when the PLL is not phase-locked. When the PLL is in stand-by mode, the lock detect output is forced LOW. The lock detect output may be observed on the GIO pin when the GIO<1:0> setting is 00b and the FMUX<2:0> setting is 011b. REFERENCE OSCILLATOR STABLE DETECT Additionally, the synthesizer may be configured to generate a reference oscillator stable output flag. The oscillator stable flag is initially set to logic LOW and is set to logic HIGH once the reference oscillator output voltage swing is sufficiently large and stable to drive digital logic. The oscillator stable flag may be observed on the GIO pin when the GIO<1:0> setting is 00b and the FMUX<2:0> setting is 010b. PRE1.1 8 September 2014 PT4501 TRANSMIT CHAIN RF OUTPUT STAGE The PA is a high-efficiency, single-ended open-drain amplifier capable of providing up to +10 dBm of output power into a 50 Ohm load at a maximum frequency of 960 MHz. The PA output power is programmable over a range from –10 to +10 dBm thru the PA<2:0> control bit settings. Use of an appropriate external output matching network helps to suppress carrier harmonics and transforms the antenna impedance to an optimal impedance at the TXOUT pin. The following plot shows the PA output power and transmit mode current consumption vs. PA<2:0> control bit setting at 915 MHz. FSK MODULATION The PT4501 utilizes a fully-integrated, fractional-N PLL to achieve in-loop modulation of the transmit FSK data. The transmit carrier frequency is set using the TXFREQH<7:0>, TXFREQM<7:0>, TXFREQL<7:0> control bits and the peak deviation from the carrier center frequency is set using the FDEV<10:0> bits according to the equation Peak frequency deviation fREF (FDEV 10 : 0 )dec 1 [Hz] , 2 MQ 216 where MQ is the quadrature generator modulus determined from the BSEL<2:0> setting. PRE1.1 9 September 2014 PT4501 RECEIVE CHAIN The received RF signal is amplified by the internal LNA before being down-converted by the image-reject quadrature mixer, eliminating the need for a costly front-end SAW filter in many applications. The mixer is followed by an on-chip channel-select filter, 5-stage ac-coupled IF limiting amplifier, digital FSK demodulator, data filter, and data slicer. RF FRONT END The LNA is a wideband, resistively-loaded cascode design that may be input-matched using two external components to cover various sub-GHz bands. The RXIN input pin is connected to the LNA input thru an internal ac-coupling capacitor. The doubly-balanced quadrature mixer relies on a high-side LO frequency (fLO = fRF + fIF) to down-convert the RF input to an IF of 1 MHz and achieves image-rejection greater than 20 dB utilizing an R-C poly-phase filter topology. The LNA and mixer combination includes two-state gain control circuitry offering a total of over 40 dB of gain control to extend the receiver’s input dynamic range. CHANNEL-SELECT FILTER The mixer’s differential IF outputs drive the fully-integrated channel-select filter. The center frequency of the bandpass filter is set to 1 MHz using a master-slave automatic-tuning circuit based on a tuning clock signal derived from the reference oscillator. The bandwidth of the programmable channel-select filter is user-selectable according to the FBS<1:0> setting (see table below). The bandwidth should be chosen as a compromise between interference rejection and attenuation of the desired signal. 00b 01b Channel-select Filter Bandwidth (KHz) 200 300 1×b 400 FBS<1:0> A plot of the channel-select filter’s normalized frequency response vs. FBS<1:0> setting is shown below. RSSI/AGC Following the channel-select filter, the IF signal is amplified by a 5-stage ac-coupled logarithmic amplifier which provides a successive detection-based RSSI and which also serves as an IF limiting amplifier for the succeeding FSK demodulator. The RSSI circuitry produces DC levels used by both the AGC loop and carrier-sense functions. The average RSSI slope is approximately 9 mV/dB. The AGC loop is enabled by default (control bit AGCEN is logic HIGH) and monitors the RSSI voltage. When the RSSI voltage is above the fixed “high” threshold voltage (Vhigh), the RF front-end gain is reduced and the RSSI voltage subsequently drops. When the RSSI voltage further decreases and remains below the fixed “low” threshold voltage (Vlow), the RF front-end gain is increased after a delay of 512 s, which is used to prevent AGC loop instability. PRE1.1 10 September 2014 PT4501 The AGC loop may be disabled by setting AGCEN is logic LOW. When the AGC loop is disabled, the RF front-end gain may be manually controlled by the RFLGC control bit. The default value for the RFLGC bit is logic LOW (high-gain mode). A plot of the RSSI response is shown in the figure below. FSK DEMODULATION The fully-integrated FSK demodulator, data filter, and data slicer convert the data contained in the frequency modulated, limited IF signal into a bit stream. The frequency discriminator function of the FSK demodulator is implemented as a digital logic quadri-correlator. The post-demodulator data filter removes excess noise from the demodulated bit stream. The bandwidth of this data filter is programmable according to the DFSEL<2:0> setting (see table below) and must be optimized for each particular data rate. If the bandwidth is set too narrow, receiver performance may be degraded due to inter-symbol interference (ISI). If the bandwidth is set too wide, receiver performance may be degraded due to excess noise. DFSEL<2:0> 000b 001b 010b 011b 100b 101b 110b 111b Data Filter –3-dB Bandwidth (KHz) 102.4 51.2 25.6 12.8 6.4 3.2 1.6 0.8 The data slicer converts the analog output from the data filter into a full-swing digital output with balanced rise and fall times. The slicer includes a Schmitt trigger stage with built-in hysteresis to eliminate output “chattering” when the slicer input signal is noisy near the transition threshold between logic levels. PRE1.1 11 September 2014 PT4501 ENHANCED BASEBAND ENGINE Forward Error Correction (FEC) is a technique that allows the receiver to correct a certain amount of errors in the received message. This is achieved by letting a FEC encoder add redundancy to the data message at the transmitter according to certain prescribed rules. The FEC decoder at the receiver uses the knowledge of these rules to identify and, if possible, correct any errors that have appeared. The PT4501 implements a rate r = 1/2 convolutional, non-recursive encoder. Convolutional coding works best if the erroneous bits are evenly (or at least randomly) spaced throughout the received coded sequence. Unfortunately, due to the bursty nature of many radio interference sources and the characteristics of the demodulator, it is more likely that erroneous bits will clump together. To combat this problem, so-called interleaving of the coded data is performed after encoding in the transmitter and de-interleaving before decoding in the receiver. The purpose of interleaving is to ensure that adjacent symbols in the coded sequence are spaced out in the transmitted sequence, so that any clumps of bit errors in the received sequence are spread out more uniformly by the de-interleaver, letting the decoder work under optimum conditions. The PT4501 employs a 4x4 matrix interleaver with 2 bits (one encoder output symbol) per cell as shown below. Packet Engine FEC Encoder Modulator The decoder in the PT4501 implements a Viterbi algorithm that works on 3-bit soft-decision values from the demodulator. The Viterbi algorithm conceptually compares the received coded sequence with the encoded sequences resulting from encoding of all possible input message sequences, calculates a deviation value for each and then selects the most likely one (the one with the lowest deviation). The PT4501 FEC implementation appends 00001011b to the data input to the encoder/interleaver when an odd number of data bytes is transmitted and 00001011 00001011b when an even number of data bytes is transmitted. The first three zeros of these sequences are used to terminate the trellis and the rest are used to fill up the last interleaver block. (The reason that not all zeros are transmitted is to ensure that there are some symbol transitions in the output of the interleaver to facilitate clock recovery.) 8 x n bits 16/32 bits 8 bits 8 bits Data Field 8 x n bits CRC-16 Syncword Address field Preamble bits (1010...1010) Length field PACKET FORMAT 16bits CRC16: optional Data Field Length: variable PRE1.1 12 September 2014 PT4501 BIT SYNCHRONIZATION The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate. 1 0 1 0 1 0 1 0 Syncword 8 x n bits The number of PREAMBLE BYTES is user-selectable. Setting 0 1 2 3 4 5 6 7 Number of PREAMBLE BYTES 2 3 4 6 8 12 16 24 BYTE SYNCHRONIZATION Byte synchronization is achieved by a continuous sync word search. The sync word is a 16/32 bit configurable field that is automatically inserted at the start of the packet by the modulator in transmit mode. Setting 0 1 2 3 4 5 6 7 Number of PREAMBLE BYTES No Preamble/Sync 14/16 sync word bits detected 15/16 sync word bits detected 16/16 sync word bits detected 29/32 sync word bits detected 30/32 sync word bits detected 31/32 sync word bits detected 32/32 sync word bits detected The synchronization pattern must be chosen wisely to minimize errors (e.g. PN16: EB22 or PN32: F3485762). DATA WHITENING The data often contains long sequences of ones and zeros. The PT4501 improves the performance by whitening the data before transmitting and de-whitening the data in the receiver. The whitening/de-whitening process will be done automatically in PT4501. Expect the preamble and PN9 sync word, PT4501 uses a 9-bit pseudo-random (PN9) sequence for whitening before the data is transmitted. At the receiver end, the data will be de-whitened with the same pseudo-random sequence and the original data appears in the receiver. WAKE ON RADIO The digital baseband logic is generally idle until a received SYNCH enables the gate clock. PRE1.1 13 September 2014 PT4501 DATA FIFO The PT4501 contains two 64 byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through a fixed address. The TX FIFO is accessed when the R/W¯ bit is zero and the RX FIFO is accessed when the R/W¯ bit is one. The TX FIFO is write-only, while the RX FIFO is read-only. The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. PRE1.1 14 September 2014 PT4501 CONFIGURATION REGISTERS 4-WIRE SERIAL PERIPHERAL INTERFACE A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave devices. The master is defined as a microcontroller providing the SPI clock and the slave as any integrated circuit receiving the SPI clock from the master. The PT4501 always operates as a slave device in master-slave operation mode. The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a low active Slave Select (SS). Data is transmitted with a 3-wire interface consisting of wires for serial data input (MOSI), serial data output (MISO) and serial clock (SCK). SS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK DATA IN MOSI 7 6 5 HIGH IMPEDANCE 3 2 1 0 3 2 1 0 DATA OUT MISO PRE1.1 4 7 15 6 5 4 September 2014 PT4501 REGISTER OVERVIEW PRE1.1 Address Name Description 0x00h MAIN Main transceiver control 0x01h PLLA Phase-locked loop control A 0x02h PLLB Phase-locked loop control B 0x03h RXFREQH Receive frequency control A 0x04h RXFREQM Receive frequency control B 0x05h RXFREQL Receive frequency control C 0x06h TXFREQH Transmit frequency control A 0x07h TXFREQM Transmit frequency control B 0x08h TXFREQL Transmit frequency control C 0x09h FECH Receive frequency error correction control A 0x0Ah FECL Receive frequency error correction control B 0x0Bh DEVIATIONH Transmit frequency deviation control A 0x0Ch DEVIATIONL Transmit frequency deviation control B 0x0Dh VCO VCO control 0x0Eh RXA Receive chain control A 0x0Fh RXB Receive chain control B 0x10h TX Transmit chain control 0x11h MACA Media access control A 0x12h MACB Media access control B 0x13h MACC Media access control C 0x14h MACD Media access control D 0x15h MACE Media access control E 0x16h MACF Media access control F 0x17h MACG Media access control G 0x1Eh FIFOA Single byte access to TX FIFO 0x1Fh FIFOB Burst access to TX FIFO 0x3Eh FIFOC Single byte access to RX FIFO 0x3Fh FIFOD Burst access to RX FIFO 16 September 2014 PT4501 PT4501 TRANSCEIVER CONTROL BIT DEFINITIONS Default values are set for the 915 MHz frequency band, i.e. fRF = 915 MHz, fLO = 916 MHz, fIF = 1 MHz and fREF = 20 MHz. Bit Default Location Value MAIN(0x00): MAIN TRANSCEIVER CONTROL 7:6 Bit Name Description Reserved General purpose input/output pin 00b = PLL FMUX output 01b = Maskable interrupt output (IRQ), used when HTRC = LOW 10b GIO<1:0> 5:4 10b = Serial output RX recovered data (stream mode) 11b = Serial input TX data bypassing the enhanced baseband engine (stream mode) Note: GIO<1:0> = 11b sets the GIO pin as an input pin Gray-coded power-down mode select (while EN pin is logic HIGH) 00b = sleep PWDN<1:0> 3:2 10b 01b = doze 11b = stand-by 10b = fully-active Hardware/Software T/R control select HTRC 1 HIGH LOW = Software control thru MAIN (0x00) <0> HIGH = Hardware control thru TXRXHW pin Transmit/receive mode select (HTRC has to be set to LOW) TXRX 0 LOW LOW = receive mode HIGH = transmit mode PLLA (0x01): PHASE-LOCKED LOOP CONTROL A 7:2 Reserved Charge pump mode select 00b = normal operation CPMODE<1:0> 1:0 00b 01b = pump-down only 10b = pump-up only 11b = high-Z state PLLB (0x02): PHASE-LOCKED LOOP CONTROL B 7:6 Reserved Reference frequency select FREF 5 HIGH LOW = 16 MHz HIGH = 20 MHz SDM dither mode select 00b = normal mode (low noise) PLLNS<1:0> 4:3 01b 01b = fractional word (K) LSB set to 1 10b = initial condition set on SDM 1st-stage DPA 11b = LFSR LSB dither mode (low spur) Test multiplexer output 000b = logic LOW 001b = logic HIGH 010b = Crystal oscillator stable flag FMUX<2:0> 2:0 000b 011b = PLL lock detector output 100b = Feedback divider output 101b = Reference buffer output 110b = PFD up output 111b = PFD down output RXFREQH (0x03): RX FREQUENCY CONTROL A PRE1.1 17 September 2014 PT4501 Bit Name Bit Location NKRX<23:16> 7:0 Default Value Description 8 MSBs of receive VCO frequency control word 01011011b minimum divide ratio = 64 (91dec) maximum divide ratio = 255 RXFREQM (0x04): RX FREQUENCY CONTROL B NKRX<15:8> 7:0 10011001b Bits 15 to 8 of receive VCO frequency control word RXFREQL (0x05): RX FREQUENCY CONTROL C NKRX<7:0> 7:0 10011001b 8 LSBs of receive VCO frequency control word TXFREQH (0x06): TX FREQUENCY CONTROL A NKTX<23:16> 7:0 8 MSBs of transmit VCO frequency control word 01011011b minimum divide ratio = 64 (91dec) maximum divide ratio = 255 TXFREQM (0x07): TX FREQUENCY CONTROL B NKTX<15:8> 7:0 10000000b Bits 15 to 8 of transmit VCO frequency control word TXFREQH (0x08): TX FREQUENCY CONTROL C NKTX<7:0> 7:0 00000000b 8 LSBs of transmit VCO frequency control word FECH (0x09): RX FREQUENCY ERROR CORRECTION CONTROL A 7:4 Reserved FEC<11:8> 3:0 0000b 4 MSBs of receive VCO frequency error correction 2’s complement control word FECL (0x0A): RX FREQUENCY ERROR CORRECTION CONTROL B 8 LSBs of receive VCO frequency error correction 2’s complement control word [Hz] FEC<7:0> 7:0 00000000b Frequency error correction fREF (FEC 11 : 0 )dec 1 [Hz] MQ 216 DEVIATIONH (0x0B): TX FREQUENCY DEVIATION CONTROL A 7:4 Reserved FSKPOL 3 LOW Transmit DATA invert select LOW = TXDATA HIGH = TXDATA FDEV<10:8> 2:0 001b 3 MSBs of non-negative transmit frequency deviation control word DEVIATIONL (0x0C): TX FREQUENCY DEVIATION CONTROL B 8 LSBs of non-negative transmit frequency deviation control word [Hz] (MQ is quadrature generator modulus according to BSEL<2:0>) FDEV<7:0> 7:0 01001000b Peak frequency deviation PRE1.1 18 fREF (FDEV 10 : 0 )dec 1 [Hz] 2 MQ 216 September 2014 PT4501 Bit Location VCO (0x0D): VCO CONTROL Bit Name Default Value Description VCO frequency band select (MQ is quadrature generator modulus) BSEL<2:0> 7:5 011b BSEL <2:0> MQ VCO Frequency Range (MHz) Output Frequency Range (MHz) 000b 001b 101b 010b 011b 6 4 4 2 2 1824 – 1896 1720 – 1760 1880 – 2040 1720 – 1760 1800 – 1860 304 – 316 430 – 440 470 – 510 860 – 880 900 – 930 VCOCUR<3:0> 4:1 1000b VCO nominal bias current select 0000b = 0 0001b = 0.46 mA 0010b = 0.50 mA 0011b = 0.82 mA 0100b = 0.86 mA 0101b = 1.11 mA 0110b = 1.14 mA 0111b = 1.34 mA 1000b = 1.37 mA 1001b = 1.54 mA 1010b = 1.56 mA 1011b = 1.71 mA 1100b = 1.73 mA 1101b = 1.85 mA 1110b = 1.87 mA 1111b = 1.98 mA VCOENB 0 LOW VCO disable input LOW = VCO is enabled HIGH = VCO is disabled RXA (0x0E): RECEIVE CHAIN CONTROL A FTS<2:0> 7:5 011b Channel-select filter (CSF) test mode 001b = for CSF trimming 1 010b = for CSF trimming 2 011b = for CSF trimming 3 100b = for CSF trimming 4 Channel-select filter bandwidth select FBS<1:0> PRE1.1 4:3 01b 19 FBS<1:0> Channel-select Filter Bandwidth (KHz) 00b 01b 1xb 200 300 400 September 2014 PT4501 Bit Name DFSEL<2:0> Bit Location 2:0 Default Value 101b RXB (0x0F): RECEIVE CHAIN CONTROL B 7:4 - Description Data filter (-3-dB) bandwidth select 000b = BW -3-dB is 102.4 KHz 001b = BW -3-dB is 51.2 KHz 010b = BW -3-dB is 25.6 KHz 011b = BW -3-dB is 12.8 KHz 100b = BW -3-dB is 6.4 KHz 101b = BW -3-dB is 3.2 KHz 110b = BW -3-dB is 1.6 KHz 111b = BW -3-dB is 0.8 KHz Reserved AGC enable input LOW = AGC is disabled (conversion voltage gain of RF front-end will be set by RXC(0x0F) <7>) HIGH = AGC is enabled AGCEN 3 HIGH RFLGC 2 LOW RF front-end low-gain control input (AGCEN has to be set to LOW) LOW = RF front-end is set to high-gain mode HIGH = RF front-end is set to low-gain mode CWEN 1 HIGH Carrier sense enable input LOW = disable carrier sense function HIGH = enable carrier sense function RXDPOL 0 LOW Receive DATA polarity select LOW = RXDATA HIGH = RXDATA TX (0x10): TRANSMIT CHAIN CONTROL 7:3 - PA<2:0> 2:0 011b Reserved Transmit output power select 000b = –10 dBm 001b = –6 dBm 010b = –3 dBm 011b = 0 dBm 100b = +3 dBm 101b = +6 dBm 110b = +8 dBm 111b = +10 dBm MACA (0x11): MEDIA ACCESS CONTROL A DRSEL PRE1.1 7:5 001b Date rate select 000b = 1 Kb/s 001b = 2 Kb/s 010b = 4 Kb/s 011b = 5 Kb/s 100b = 10 Kb/s 101b = 20 Kb/s 110b = 50 Kb/s 111b = 100 Kb/s 20 September 2014 PT4501 Bit Name Bit Location Default Value LCDET 4 LOW Leader code detection enable input LOW = leader code detection function is not used. HIGH = enable leader code detection function. HIGH Data recovery enable input LOW = bypass mode. Input signal passes through (unchanged). HIGH = enable data recovery function (using bit decision for recovering the data). DRECEN 3 Description Forward error correction (FEC) enable input FECEN 2 LOW LOW = FEC is disabled. Thus, data whitening, CRC and Auto-ACK function will be invalid. HIGH = FEC is enabled Data whitening/de-whitening (PN9) on/off WHITEEN 1 HIGH LOW = Whitening/de-whitening is turned-off HIGH = Whitening/de-whitening is turned-on Cyclic redundancy check (CRC16) enable input CRCEN 0 HIGH MACB (0x12): MEDIA ACCESS CONTROL B 7:6 - PREAM<2:0> SYNC<2:0> 5:3 2:0 Reserved 010b Preamble bytes select 000b = 2 bytes preamble 001b = 3 bytes preamble 010b = 4 bytes preamble 011b = 6 bytes preamble 100b = 8 bytes preamble 101b = 12 bytes preamble 110b = 16 bytes preamble 111b = 24 bytes preamble 001b Synchronization (sync word search) select PN16: AF12; PN32: F3485762 000b = reserved 001b = 14/16 sync word bits detected 010b = 15/16 sync word bits detected 011b = 16/16 sync word bits detected 100b = 29/32 sync word bits detected 101b = 30/32 sync word bits detected 110b = 31/32 sync word bits detected 111b = 32/32 sync word bits detected MACC (0x13): MEDIA ACCESS CONTROL C 7:6 PRE1.1 LOW = CRC is disabled HIGH = CRC is enabled Reserved 21 September 2014 PT4501 Bit Name Bit Location Default Value Description Set the threshold for RX FIFO. RXFIFOTHR <2:0> 5:3 RXFIFOTHR<3:0> Bytes in RX FIFO 000b 001b 010b 011b 100b 101b 110b 111b 4 8 12 16 20 24 28 32 011b Set the threshold for TX FIFO. TXFIFOTHR <2:0> 2:0 TXFIFOTHR<3:0> Bytes in TX FIFO 000b 001b 010b 011b 100b 101b 110b 111b 29 25 21 17 13 9 5 1 011b MACD (0x14): MEDIA ACCESS CONTROL D (READ ONLY) 7 Reserved Receive CRC pass Check whether CRC is correct when both CRCEN and CRCPASS 6 LOW PACKET_RDONE are set to HIGH. LOW = CRC is incorrect HIGH = CRC is correct PACKET_RDONE PACKET_TDONE PRE1.1 5 4 LOW RX packet done PACKET_RDONE will be set to HIGH after a packet was completely received. It will be not cleared off until RESTART signal is coming. LOW TX packet done PACKET_TDONE will be set to HIGH after a packet was completely transmitted. It will be not cleared off until RESTART signal is coming. RXDO 3 LOW TXDU 2 HIGH RXFULL 1 LOW Data Overflow RX FIFO flag (RX FIFO threshold is reached). Asserted when new data arrives RX FIFO. LOW = Write data to RX FIFO HIGH = RX FIFO overflow Data Underflow TX FIFO flag (TX FIFO threshold is reached). Asserted when packet transmitted on TX. LOW = Write data to TX FIFO HIGH = TX FIFO underflow RX FIFO full flag LOW = Available locations in RX FIFO HIGH = RX FIFO full 22 September 2014 PT4501 Bit Name Bit Location Default Value Description TX FIFO empty flag TXEMPTY 0 HIGH LOW = Available data in TX FIFO HIGH = TX FIFO EMPTY MACE (0x15): MEDIA ACCESS CONTROL E PACKET_RDONE_IRQEN 7 LOW IRQ enable control when PACKET_RDONE = HIGH LOW = disable IRQ when PACKET_RDONE = HIGH HIGH = enable IRQ when PACKET_RDONE = HIGH PACKET_TDONE_IRQEN 6 LOW IRQ enable control when PACKET_TDONE = HIGH LOW = disable IRQ when PACKET_TDONE = HIGH HIGH = enable IRQ when PACKET_TDONE = HIGH RXDO_IRQEN 5 LOW IRQ enable control when RXDO = HIGH LOW = disable IRQ when RXDO = HIGH HIGH = enable IRQ when RXDO = HIGH TXDU_IRQEN 4 LOW RXFIFOCLR 3 LOW TXFIFOCLR 2 LOW GCLKEN 1 HIGH RESTART 0 LOW IRQ enable control when TXDU = HIGH LOW = disable IRQ when TXDU = HIGH HIGH = enable IRQ when TXDU = HIGH RX FIFO pointer clearance LOW = normal operation HIGH = clear RX FIFO pointer TX FIFO pointer clearance LOW = normal operation HIGH = clear TX FIFO pointer Gating clock enable control for power saving LOW = disable gating clock HIGH = enable gating clock FEC restart control (write only) RESTART must be set to HIGH after a packet was completely received or transmitted and wait the next packet. Reset by itself. When FEC is failed, set RESTART to HIGH could reset FEC block. LOW = receive/transmit data HIGH = FEC restart MACF (0x16): MEDIA ACCESS CONTROL F LCRDET<7:0> 7:0 8 MSBs of leader code re-detect time control word 01100010b minimum divide ratio = 81 (98dec) maximum divide ratio = 255 MACG (0x17): MEDIA ACCESS CONTROL G LCTOUT<7:0> 7:0 8 MSBs of leader code time-out control word 10000010b (130dec) minimum value = 93 maximum value = 255 FIFOA (0x1E): SINGLE BYTE ACCESS to TX FIFO STXFIFO<7:0> 7:0 00000000b Write only FIFOB (0x1F): BURST ACCESS to TX FIFO BTXFIFO<7:0> 7:0 00000000b Write only FIFOC (0x3E): SINGLE BYTE ACCESS to RX FIFO SRXFIFO<7:0> 7:0 – Read only FIFOD (0x3F): BURST ACCESS to RX FIFO BRXFIFO<7:0> 7:0 – PRE1.1 Read only 23 September 2014 PT4501 PLL FREQUENCY PROGRAMMING EXAMPLE RECEIVE MODE For a specific RF input frequency (fRF) and intermediate frequency (fIF), the PT4501 IC’s LO frequency (fLO) may be given by the expression fLO = fRF + fIF. Given an fRF of 433.92 MHz and for the system-specified fIF of 1 MHz, fLO = 433.92 + 1.00 = 434.92 [MHz]. Now, to generate the desired fLO for the 433.92 MHz band, the required VCO frequency (fVCO) may be calculated using the expression fVCO = 4 × fLO. For fLO = 434.92 MHz, the required synthesized fVCO = 4 × 434.92 MHz = 1739.68 MHz. Given a reference oscillator frequency (fREF) = 20 MHz, the on-chip PLL’s feedback divider modulus (N.K) required to fVCO 1739.68 86.984 . The integer synthesize the desired fVCO = 1739.68 MHz is given by the expression N.K fREF 20 portion of the divider modulus is represented as N. Here, N = 86. The fractional portion of the divider modulus is represented by K. Here, K = 0.984. From the register table definition, the receive frequency control word is NKRX<23:0>. The 8 MSBs (NKRX<23:16>) of the receive frequency control word are used to represent the integer portion of the divider modulus. Hence, for N = 86, NKRX<23:16> = 1010 1100b = 56h. The 16 LSBs (NKRX<15:0>) of the receive frequency control word are used to represent the fractional portion of the 16 divider modulus and are nominally related to K by the expression NKRX<15:0> = K × 2 . For K = 0.984, NKRX<15:0> = 0.984 × 65536 = 64487 = 1111 1011 1110 0111b = FB E7h. Note that the final phase-locked VCO frequency is also dependent upon the dither mode setting (PLLNS<1:0>) as explained in the FUNCTIONAL DESCRIPTION section. TRANSMIT MODE For a transmit RF carrier frequency (fTX), the PT4501 IC’s required VCO frequency (fVCO) may be calculated using the expression fVCO = MQ × fTX, where MQ (quadrature generator modulus) is given in the VCO (0x0Dh) section of the PT4501 TRANSCEIVER CONTROL BIT DEFINITIONS table. For fTX = 433.92 MHz, MQ = 4 and the required synthesized fVCO = 4 × 433.92 MHz = 1735.68 MHz. Given a reference oscillator frequency (fREF) = 20 MHz, the on-chip PLL’s feedback divider modulus (N.K) required to fVCO 1735.68 86.784 . The integer synthesize the desired fVCO = 1735.68 MHz is given by the expression N.K fREF 20 portion of the divider modulus is represented as N. Here, N = 86. The fractional portion of the divider modulus is represented by K. Here, K = 0.784. From the register table definition, the transmit frequency control word is NKTX<23:0>. The 8 MSBs (NKTX<23:16>) of the transmit frequency control word are used to represent the integer portion of the divider modulus. Hence, for N = 86, NKTX<23:16> = 1010 1100b = 56h. The 16 LSBs (NKTX<15:0>) of the transmit frequency control word are used to represent the fractional portion of the 16 divider modulus and are nominally related to K by the expression NKTX<15:0> = K × 2 . For K = 0.784, NKTX<15:0> = 0.784 × 65536 = 51380 = 1100 1000 1011 0100b = C8 B4h. Note that the final phase-locked VCO frequency is also dependent upon the dither mode setting (PLLNS<1:0>) as explained in the FUNCTIONAL DESCRIPTION section. PRE1.1 24 September 2014 PT4501 RECOMMENDED REGISTER VALUES For stream mode, data rate = 2 Kb/s and frequency deviation = ±50 KHz. Address Recommended Register Values (hexadecimal) 0x01h 315 MHz 29hex/28hex (TX/RX) 10hex 433.92 MHz 29hex/28hex (TX/RX) 10hex 470 MHz 29hex/28hex (TX/RX) 10hex 868 MHz 29hex/28hex (TX/RX) 10hex 915 MHz 29hex/28hex (TX/RX) 10hex 0x02h 28hex 28hex 28hex 28hex 28hex 0x03h 5Ehex 56hex 5Ehex 56hex 5Bhex 0x04h CChex FBhex 33hex E6hex 99hex 0x05h CDhex E7hex 33hex 67hex 9Ahex 0x06h 5Ehex 56hex 5Ehex 56hex 5Bhex 0x07h 80hex C8hex 00hex CChex 80hex 0x08h 00hex B4hex 00hex CDhex 00hex 0x09h 00hex 00hex 00hex 00hex 00hex 0x0Ah 00hex 00hex 00hex 00hex 00hex 0x0Bh 03hex 02hex 02hex 01hex 01hex 0x0Ch D8hex 90hex 90hex 48hex 48hex 0x0Dh 10hex 30hex B0hex 50hex 70hex 0x0Eh EDhex EDhex EDhex EDhex EDhex 0x0Fh 0Ahex 0Ahex 0Ahex 0Ahex 0Ahex 0x10h 07hex 07hex 07hex 07hex 07hex 0x11h 2Bhex 2Bhex 2Bhex 2Bhex 2Bhex 0x00h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h Not be used in stream mode 0x1Eh 0x1Fh 0x3Eh 0x3Fh PRE1.1 25 September 2014 PT4501 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Range Operating Temperature Range Storage Temperature Range Symbol Min. Max. Unit VDD TA TSTG –0.5 –40 –40 3.6 +85 +125 V °C °C PACKAGE THERMAL CHARACTERISTIC Parameter From Chip Conjunction Dissipation to External Environment From Chip Conjunction Dissipation to Package Surface PRE1.1 Symbol Condition Rja Min. Typ. Max. - 37.15 - - 1 1.8 TA = 27°C Rjc 26 Unit °C/W September 2014 PT4501 ELECTRICAL CHARACTERISTICS Nominal conditions: VDD = 3.3 V, VSS = 0 V, CE = HIGH, TA = +27°C, fRF= 915 MHz, fREF = 20 MHz Parameter Symbol Conditions Min. Typ. Max. Unit General Characteristics Supply Voltage VDD 1.9 3.3 3.6 V Standby Current ISTBY – – 1 μA 300 – 960 MHz for 915 MHz 13 14.5 16 mA for 915 MHz -112 -110 -108 dBm for 433.92 MHz -115 -113 -111 dBm DRate – 2 50 Kb/s PIN,MAX – -20 -10 dBm – – –65 dBm RLIN,RX – -8 –6 dB Conversion Voltage Gain of RF Front-End GRF 45 49 53 dB Noise Figure NFRX 4.0 4.5 5.0 dB for 868/915 MHz 25 – – dB Image Rejection Ratio IRR for 315/433.92 MHz 28 – – dB FBS<1:0> = 00b – 200 – KHz FBS<1:0> = 01b – 300 – KHz FBS<1:0> = 1× b – 400 – KHz AGC = OFF 50 55 60 dB < 1 GHz – – –57 dBm > 1 GHz – – –47 dBm PA<2:0> = 111b, 433.92 MHz – +10 +12 dBm PA<2:0> = 111b, 915 MHz – +9 +10 dBm PA<2:0> from 000b to 111b at 915 MHz – 20 – dB PA<2:0> = 111b, 433.92 MHz – 33 – mA PA<2:0> = 111b, 915 MHz – 30 – mA 22.5 50 125 KHz < 1 GHz – – –30 dBm > 1 GHz – – –36 dBm – – –25 dBc Operating Frequency Range CE = LOW fRF Receiver Section RX Current Consumption Note 1 Receiver Sensitivity Data Rate Receiver Maximum Input Power LO Leakage IDD,RX SRX LLO Input Return Loss (S11) Receiver Bandwidth BW RX RSSI Dynamic Range DRRSSI RX Spurious Emission SpurRX measured at antenna input Transmitter Section TX Output Power Note 2 POUT TX Output Power Control Range POUT TX Current Consumption IDD,TX Binary FSK Frequency Deviation TX Spurious Emission nd 2 Harmonic PRE1.1 Note4 Note3 fDEV SpurTX HP2ND 27 September 2014 PT4501 Parameter rd 3 Harmonic Note4 Symbol Conditions Min. Typ. Max. Unit – – –30 dBc FREF<0> = LOW – 16 – MHz FREF<0> = HIGH – 20 – MHz – – 2 msec at 100 KHz offset – –72 –67 dBc/Hz at 200 KHz offset – –75 –70 dBc/Hz at 1 MHz offset – –105 –100 dBc/Hz – 150 – KHz – ±100 – μA HP3RD VCO and Phase-Locked Loop Reference Frequency Crystal Oscillator Start-Up Time LO SSB Phase Noise fREF TStart,XOSC PNLO PLL Loop Bandwidth BW PLL Charge Pump Current ICP CPCUR<2:0> = 100b Digital Inputs / Outputs Logic Input / Output HIGH Level VHI / VHO 0.7 – 1 VDD Logic Input / Output LOW Level VLI / VLO 0 – 0.3 VDD SPI Interface Clock Frequency CKSPI – – 100 KHz Notes: 1. Channel BW=300 KHz; BER < 1e-3; Data Rate = 2 Kb/s and Frequency Deviation = ±50 KHz in FSK mode. 2. Depends on the matching network.. 3. Using antenna matching network. 4. Using antenna matching network and RLoad = 50 PRE1.1 28 September 2014 PT4501 PACKAGE INFORMATION 24 PINS, QFN (BODY SIZE: 4X4MM) Symbol A A1 A3 b D E D2 E2 e L Min. Dimensions Nom. 0.70 0.75 0.00 0.18 0.02 0.20 REF. 0.25 4.00BSC 4.00BSC 2.50 2.50 2.65 2.65 2.80 2.80 0.35 0.50 BSC 0.40 0.45 Max. 0.80 0.05 0.30 Notes: 1. All dimensions refer to JEDEC MO-220 WGGD-6 2. All dimensions are in millimeter. PRE1.1 29 September 2014 PT4501 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw PRE1.1 30 September 2014