DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL IDT74SSTUBF32866B design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC). All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUBF32866B operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). Features A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0, C12 = 1) • 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register. The second register produces to PPO and QERR signals. The QERR of the first register is left floating. The valid error information is latched on the QERR output of the second register. If an error occurs QERR is latched low for two cycles or until RESET is low. • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on C0, C1, and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 96-ball LFBGA package B - Single Configuration (C0 = 0, C1 = 0) The device supports low-power standby operation. When the RESET input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. Applications • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A • Ideal for DDR2 667 and 800 In the DDR-II RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Functional Block Diagram for 1:1 Mode (Positive Logic) RESET CLK CLK VREF DCKE D C1 QCKEA C1 QOTDA C1 QCSA R DODT D R DCS 1D R CSR D1 O 1 Q1A 1D C1 R Q1B (1) TO 21 OTHER CHANNELS NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Functional Block Diagram for 1:2 Mode (Positive Logic) RESET CLK CLK VREF DCKE QCKEA 1D C1 R DODT QCKEB (1) QODTA 1D C1 R DCS QODTB (1) QCSA 1D C1 R QCSB (1) CSR D1 0 1 1D Q1A C1 R Q1B (1) TO 10 OTHER CHANNELS (D2-D6, D8-D10, D12-D13) NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 3 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Pin Configurations 14 BIT 1:2 REGISTERS 1 2 3 4 A DCKE PPO VREF VDD B D2 NC GND GND 5 6 1 2 3 4 5 6 VREF VDD Q1A Q1B GND GND Q2A Q2B A D1 PPO Q2A Q2B B D2 NC Q3A Q3B C D3 NC VDD VDD Q3A Q3B D D4 QERR GND GND Q4A Q4B Q5B E D5 NC VDD VDD Q5A Q5B Q6B F D6 NC GND GND Q6A Q6B VDD VDD QCKEA QCKEB C D3 NC VDD VDD D DODT QERR GND GND E D5 NC VDD VDD Q5A F D6 NC GND GND Q6A QODTA QODTB G PAR_IN RESET VDD VDD C1 C0 C1 C0 H CLK DCS GND GND QCSA QCSB H CLK DCS GND GND QCSA QCSB J CLK CSR VDD VDD ZOH ZOL J CLK CSR VDD VDD ZOH ZOL GND Q8A Q8B K D8 NC GND GND Q8A Q8B VDD Q9A Q9B L D9 NC VDD VDD Q9A Q9B D10 NC GND GND Q10A Q10B G PAR_IN RESET K D8 NC GND L D9 NC VDD M D10 NC GND GND Q10A Q10B M N D11 NC VDD VDD Q11A Q11B N DODT NC VDD VDD D12 NC GND GND P D12 NC GND GND Q12A Q12B P R D13 NC VDD VDD Q13A Q13B R D13 NC VDD VDD Q14B T DCKE NC VREF VDD T D14 NC VREF VDD Q14A QODTA QODTB Q12A Q12B Q13A Q13B QCKEA QCKEB REGISTER B (C0 = 1, C1 = 1) REGISTER A (C0 = 0, C1 = 1) 25 BIT 1:1 REGISTER 2 3 4 5 6 A DCKE 1 PPO VREF VDD QCKE NC B D2 D15 GND GND Q2 Q15 C D3 D16 VDD VDD Q3 Q16 D DODT QERR GND GND QODT NC E D5 D17 VDD VDD Q5 Q17 F D6 D18 GND GND Q6 Q18 G PAR_IN RESET VDD VDD C1 C0 H CLK DCS GND GND QCS NC J CLK CSR VDD VDD ZOH ZOL K D8 D19 GND GND Q8 Q19 L D9 D20 VDD VDD Q9 Q20 M D10 D21 GND GND Q10 Q21 N D11 D22 VDD VDD Q11 Q22 P D12 D23 GND GND Q12 Q23 R D13 D24 VDD VDD Q13 Q24 T D14 D25 VREF VDD Q14 Q25 C0 = 0, C1 = 0 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 4 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE 96 Ball LFBGA Package Attributes 6 5 4 3 2 1 A Top Marking B C D E F G H J K L M L M N P R T TOP VIEW A B C D E F G H J K N P R T 1 2 3 4 5 6 BOTTOM VIEW 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 5 CONFIDENTIAL SIDE VIEW IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Function Table Inputs1 Outputs RESET DCS CSR CLK CLK Dn, DODT, DCKE Qn QCS QODT, QCKE H L L ↑ ↓ L L L L H L L ↑ ↓ H H L H H L L L or H L or H X Q 02 Q02 Q02 H L H ↑ ↓ L L L L H L H ↑ ↓ H H H L H L or H L or H X Q0 H H L ↑ ↓ L L H H L ↑ ↓ H H L 2 Q0 H Q0 H L L or H L or H X Q0 H H H ↑ ↓ L Q 02 H H H H ↑ ↓ H Q 02 H X Q0 2 X or Floating L H L X or Floating 1 2 H L or H L or H X or X or X or Floating Floating Floating Q0 L Q02 L H 2 H H H 2 H 2 Q02 L H 2 Q02 L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW Output level before the indicated steady-state conditions were established. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 6 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity and Standby Function Table Inputs1 Outputs RESET DCS CSR CLK CLK Σ of Inputs = H (D1 - D25) PAR_IN2 H L X ↑ ↓ Even L L H H L X ↑ ↓ Odd L H L H L X ↑ ↓ Even H H L H L X ↑ ↓ Odd H L H H X L ↑ ↓ Even L L H H X L ↑ ↓ Odd L H L H X L ↑ ↓ Even H H L H X L ↑ ↓ Odd H L H H H H ↑ ↓ X X PPO0 QERR0 H X X L or H L or H X X PPO0 QERR0 L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating L H PPO QERR3 1 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0. Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1. Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1. 2 PAR_IN arrives one clock cycle after the data to which it applies when C0 = 0, and two clock cycles when C0 = 1. 3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 7 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Logic Diagram (1:1) G2 RESET CLK CLK D2 - D3, D5 - D6, D8 - D25 VREF H1 J1 LPS0 (Internal Node) 22 CE CE D A3, T3 22 Q CLK D2 - D3, D5 - D6, D8 - D25 Q2 - Q3, Q5 - Q6, Q8 - Q25 22 R 22 D2 - D3, D5 - D6, D8 - D25 Parity Check C1 G5 1 0 Q D R R C0 Q D CLK CLK PAR_IN Q D 1 A2 PPO 0 CLK R CE G1 D2 QERR G6 CLK 2-Bit Counter LPS1 (Internal Node) R 0 D Q 1 CLK R Parity Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 8 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Logic Diagram (1:2) G2 RESET CLK CLK D2 - D3, D5 - D6, D8 - D14 VREF H1 J1 LPS0 (Internal Node) 11 CE CE D A3, T3 11 Q CLK D2 - D3, D5 - D6, D8 - D14 Q2A - Q3A, Q5A - Q6A, Q8A - Q14A 11 11 Q2B - Q3B, Q5B - Q6B, Q8B - Q14B R 11 D2 - D3, D5 - D6, D8 - D14 Parity Check C1 G5 1 0 Q D D 1 R R C0 Q D CLK CLK PAR_IN Q A2 PPO 0 CLK R CE G1 D2 QERR G6 CLK 2-Bit Counter LPS1 (Internal Node) R 0 D Q 1 CLK R Parity Logic Diagram for 1:2 Register - A Configuration (Positive Logic); C0 = 0, C1 = 1 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 9 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Logic Diagram (1:2) G2 RESET CLK CLK H1 J1 D1 - D6, D8 - D13 VREF LPS0 (Internal Node) 11 D1 - D6, D8 - D13 CE CE D A3, T3 Q CLK 11 Q1A - Q6A, Q8A - Q13A 11 Q1B - Q6B, Q8B - Q13B 11 R 11 D1 - D6, D8 - D13 Parity Check C1 G5 1 0 Q D 1 R R C0 Q D CLK CLK PAR_IN Q D A2 PPO 0 CLK R CE G1 D2 QERR G6 CLK 2-Bit Counter LPS1 (Internal Node) 0 D Q R 1 CLK R Parity Logic Diagram for 1:2 Register - B Configuration (Positive Logic); C0 = 1, C1 = 1 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 10 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Rating Supply Voltage, VDD -0.5V to 2.5V 1 -0.5V to 2.5V VO1,2 -0.5V to VDD + 0.5V Input Voltage Range, VI Output Voltage Range, Input Clamp Current, IIK ±50mA Output Clamp Current, IOK ±50mA Continuous Output Clamp Current, IO ±50mA Continuous Current through each VDD or GND ±100mA Package Thermal Impedance (θja)3 0m/s Airflow 70.9°C/W 1m/s Airflow 65°C/W Storage Temperature -65 to +150°C 1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 11 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Terminal Functions Terminal Name Electrical Characteristics GND Ground Input Ground VDD 1.8V nominal Power Supply Voltage VREF 0.9V nominal Input Reference Clock ZOH Input Reserved for future use ZOL Input Reserved for future use CLK Differential Input Positive Master Clock Input CLK Differential Input Negative Master Clock Input C0, C1 LVCMOS Input Configuration Control Inputs RESET LVCMOS Input Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers. CSR, DCS SSTL_18 Input Chip Select Inputs. Disables outputs D1 - D24 output switching when both inputs are HIGH. D1 - D25 SSTL_18 Input Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. DODT SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls DCKE SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls Q1 - Q25 1.8V CMOS Data Outputs that are suspended by the DCS and CSR controls QCS 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls QODT 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls QCKE 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls PPO 1.8V CMOS Partial Parity Output. Indicates off parity of D1 - D25 PAR_IN SSTL_18 Input QERR Open Drain Output 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description Parity Input arrives one cycle after corresponding data input Output Error bit, generated one cycle after the corresponding data output 12 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Operating Characteristics The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Symbol Parameter Min. Typ. Max. Units 1.9 V VDDQ I/O Supply Voltage 1.7 VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V VTT Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDD V VI Input Voltage VIH AC High-Level Input Voltage 0 VIL Data, CSR, AC Low-Level Input Voltage and PAR_IN DC High-Level Input Voltage inputs DC Low-Level Input Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage VIL VIH RESET, C0, C1 VREF + 0.25 VREF - 0.25 VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ VICR Common Mode Input Range VID Differential Input Voltage IOH High-Level Output Current -8 IOL Low-Level Output Current 8 IERROL TA CLK, CLK 0.675 1.125 600 QERR LOW Level Output Current 25 Operating Free-Air Temperature 0 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 V 13 CONFIDENTIAL V V mV mA mA +70 IDT74SSTUBF32866B °C 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDD = 1.7V to 1.9V. Symbol Parameter VIK Test Conditions Min. Typ. II = -18mA Max. Units -1.2 V VOH Output HIGH Voltage IOH = -6mA VOL Output LOW Voltage IOL = 6mA 0.5 V VERROL QERR Output LOW Voltage IERROL = 25mA, VDD = 1.7V 0.5 V All Inputs VI = VDD or GND; VDD = 1.9V +5 μA Static Standby IO = 0, VDD = 1.9V, RESET = GND 100 μA IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) 10 IIL IDD Static Operating V -5 mA IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) 90 Dynamic Operating (clock only) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 210 Dynamic Operating (per each data input) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. Data Inputs VI = VREF ± 350mV 2 3 CLK and CLK VICR = 1.25V, VIPP = 360mV 2 3 RESET VI = VDD or GND IDDD CIN 1.2 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1:1 mode μA/Clock MHz 65 1:2 mode μA/Clock MHz/ Data Input 120 pF 5 14 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range VDD = 1.8V ± 0.1V Symbol fCLOCK tW Min. Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW tACT 1 tINACT2 tSU Units 410 MHz 1 ns Differential Inputs Active Time 10 ns Differential Inputs Inactive Time 15 ns Setup Time Hold Time tH Max. DCS before CLK↑, CLK↓, CSR HIGH; CSR before CLK↑, CLK↓, DCS HIGH 0.6 DCS before CLK↑, CLK↓, CSR LOW 0.5 DODT, DOCKE, and data before CLK↑, CLK↓ 0.5 PAR_IN before CLK↑, CLK↓ 0.5 DCS, DODT, DCKE, and data after CLK↑, CLK↓ 0.4 PAR_IN after CLK↑, CLK↓ 0.4 ns ns 1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of tACT(max) after RESET is taken HIGH. 2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of tINACT(max) after RESET is taken LOW. Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted) VDD = 1.8V ± 0.1V Symbol fMAX tPDM 1 tPDQ2 tPDMSS 1 Parameter Min. Max Input Clock Frequency 410 Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn 1.1 1.5 ns Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn 0.4 0.8 ns 1.6 ns Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn Max. Units MHz tPD Propagation Delay, CLK and CLK to PPO 0.5 1.7 ns tLH LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to QERR 1.2 3 ns tHL HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to QERR 1 2.4 ns tPHL HIGH to LOW Propagation Delay, RESET↓ to PPO to Qn↓ 3 ns tPLH LOW to HIGH Propagation Delay, RESET↓ to QERR↑ 3 ns 1 2 Design target as per JEDEC specifications. Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.) 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 15 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V ± 0.1V Parameter dV/dt_r dV/dt_f dV/dt_Δ 1 Min. Max. Units 1 4 V/ns 1 4 V/ns 1 V/ns 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 16 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n +1 n+2 n+3 n+4 CLK CLK tACT tH tSU (1) D1 - D25 tPDM, tPDMSS CLK to Q Q1 - Q25 tSU tH (1) PARIN tPD CLK to PPO PPO tPHL CLK to QERR tPHL, tPLH CLK to QERR (2) QERR Data to QERR Latency H, L, or X H or L Timing Diagram for SSTUBF32866B Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from L to H NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tACTMAX, to avoid false error. 2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 17 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing Timing Diagram for the First SSTUBF32866B Used as a Single Device; C0 = 0, C1 = 0, RESET Held HIGH NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 18 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT DCS (1) (1) CSR CLK CLK (1) (1) (1) D1 - D25 tRPHL RESET to Q Q1 - Q25 (1) PARIN tRPHL RESET to PPO PPO QERR tRPLH RESET to QERR H, L, or X H or L Timing Diagram for SSTUBF32866B Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from H to L NOTE: 1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 19 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n +1 n+2 n+3 n+4 CLK CLK tACT tH tSU (1) D1 - D14 tPDM, tPDMSS CLK to Q Q1 - Q14 tSU tH (1) PARIN tPD CLK to PPO PPO tPHL, tPLH CLK to QERR tPHL CLK to QERR (2) QERR (not used) Data to QERR Latency H, L, or X H or L Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1, RESET Switches from Lto H NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tACTMAX, to avoid false error. 2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. . 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 20 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1, RESET Held HIGH NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 21 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT (1) DCS (1) CSR CLK CLK (1) (1) (1) D1 - D14 tRPHL RESET to Q Q1 - Q14 (1) PARIN tRPHL RESET to PPO PPO QERR (not used) tRPLH RESET to QERR H, L, or X H or L Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) Device Used in a Pair; C0 = 1, C1 = 1; RESET Switches from H to L NOTE: 1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 22 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n +1 n+2 n+3 n+4 CLK CLK tACT tH tSU (1) D1 - D14 tPDM, tPDMSS CLK to Q Q1 - Q14 tSU tH (1,2) PARIN tPD CLK to PPO PPO (not used) tPHL CLK to QERR tPHL, tPLH CLK to QERR (3) QERR Data to QERR Latency H, L, or X H or L Timing Diagram for the Second SSTUBF32866B (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1, RESET Switches from L to H NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tactmax, to avoid false error. 2.PAR_IN is driven from PPO of the first SSTUAF32866 device. 3.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 23 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing Timing Diagram for the Second SSTUBF32866B (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1, RESET Held HIGH NOTES: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. 2.PAR_IN is driven from PPO of the first SSTUAF32866 device. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 24 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT (1) DCS (1) CSR CLK CLK (1) (1) (1) D1 - D14 tRPHL RESET to Q Q1 - Q14 (1) PARIN tRPHL RESET to PPO PPO (not used) QERR tRPLH RESET to QERR H, L, or X H or L Timing Diagram for the First SSTUBF32866B (1:2 Register-A Configuration) Device Used in a Pair; C0 = 1, C1 = 1; RESET Switches from H to L NOTE: 1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 25 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) VDD/2 VDD DUT R L = 1KΩ TL = 50Ω CLK CLK CLK Inputs ZO = 50Ω Test Point ZO = 50Ω Test Point CLK Inputs Test Point CL = 30 pF Test Point CLK TL = 350ps, 50Ω Out DUT RL = 50Ω ZO = 50Ω Out CLK R L = 1KΩ Test Point RL = 100Ω Test Point Production-Test Load Circuit Simulation Load Circuit CLK tPLH VDD LVCMOS RESET Input VDD/2 V ICR V ICR CLK V ID tPHL V OH Output VDD/2 V TT V TT V OL 0V tACT tINACT Voltage Waveforms - Propagation Delay Times 90% IDD 10% LVCMOS RESET Input Voltage and Current Waveforms Inputs Active and Inactive Times VIH VDD/2 VIL tRPHL VOH Output VTT VOL tW Input VICR VICR Voltage Waveforms - Propagation Delay Times VID NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. Voltage Waveforms - Pulse Duration CLK VID VICR CLK tSU tH VIH Input VREF VREF VIL Voltage Waveforms - Setup and Hold Times 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 26 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) VDD DUT VDD DUT RL = 50Ω Out RL = 1KΩ Out Test Point Test Point CL = 10 pF CL = 10 pF Load Circuit: Error Output Measurements Load Circuit: High-to-Low Slew-Rate Adjustment Output LVCMOS RESET Input VOH 80% VCC VCC/2 0V tPLH VOH 20% dv_f 0.15V Output Waveform 2 VOL 0V dt_f Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input) Voltage Waveforms: High-to-Low Slew-Rate Adjustment Timing Inputs DUT VICR VICR VI(PP) tHL Out Test Point CL = 10 pF VCC/2 VOL Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs) Load Circuit: Low-to-High Slew-Rate Adjustment Timing Inputs dt_r VOH dv_r VCC Output Waveform 1 RL = 50Ω 80% VICR VICR VI(PP) tHL VOH Output Waveform 2 20% Output VOL 0.15V 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs) Voltage Waveforms: Low-to-High Slew-Rate Adjustment NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 27 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) DUT Out Test Point CL = 5 pF RL = 1KΩ Load Circuit: Partial-Parity-Out Load Circuit CLK VICR VICR CLK tPLH VI(P-P) tPHL VOH Output VTT VTT VOL Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to clock inputs) LVCMOS RESET Input VIH VDD/2 VIL tRPHL VOH VTT Output VOL Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to RESET input) 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 28 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 C SEATING PLANE Numeric Designations for Horizontal Grid A1 b REF T 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) D d TYP D1 -e- TYP TOP VIEW E c REF -e- TYP h TYP 0.12 C E1 ALL DIMENSIONS IN MILLIMETERS ----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E h Min/Max 0.25/0.41 0.25/0.35 REF. DIMENSIONS b c 0.75 0.875 * Source Ref.: JEDEC Publication 95, 0.75 0.875 MO-205 10-0055C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 29 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Ordering Information IDT XX SSTUBF XX Family Temp. Range XXX XX Device Type Package X Shipping Carrier 8 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Tape and Reel BFG Low Profile, Fine Pitch, Ball Grid Array - Green 866B 25-Bit Configurable Registered Buffer for DDR2 32 Double Density 74 0°C to +70°C (Commercial) 30 CONFIDENTIAL IDT74SSTUBF32866B 7067/9 IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA