IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL TRANSCEIVER/ REGISTER (3-STATE) DESCRIPTION: FEATURES: • • • • • • • • • IDT54/74FCT646T/AT/CT The FCT646T consists of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The FCT646T utilizes the enable control (G) and direction (DIR) pins to control the transceiver functions. SAB and SBA control pins are provided to select either real- time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data and a high selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. Std., A, and C grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: – Industrial: SOIC, SSOP, QSOP, TSSOP – Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM G DIR CPB A SBA CPA B SAB B REG ONE OF EIGHT CHANNELS 1D C1 A1 A REG B1 1D C1 TO SEVE N OTHER CHANN ELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES JUNE 2002 1 © 2002 Integrated Device Technology, Inc. DSC-5505/3 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES A1 4 21 G A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 15 B6 A8 11 14 B7 GND 12 13 B8 Max Unit –0.5 to +7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +120 mA Typ. SBA 26 24 B1 A3 7 23 B2 NC 8 22 NC A4 9 21 B3 A5 10 20 B4 A6 11 19 B5 B1 - B8 12 13 14 15 16 17 18 Max. CPAB, CPBA SAB, SBA DIR, G Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs CAPACITANCE (TA = +25°C, F = 1.0MHz) Conditions 27 6 A2 Pin Names A1 - A8 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. Parameter(1) 28 1 PIN DESCRIPTION VTERM(2) Terminal Voltage with Respect to GND Symbol 2 LCC TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Description 3 G 5 CERDIP/ SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW Symbol 4 25 A1 B6 SBA CPBA 22 B7 3 Vcc DIR B8 CPBA NC 23 NC 2 CPAB SAB INDEX GND VCC SAB 24 A8 1 A7 CPAB DIR PIN CONFIGURATION NOTE: 1. This parameter is measured at characterization but not tested. 2 Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES FUNCTION TABLE(1) Data I/O(2) Inputs G DIR CPAB CPBA SAB SBA A1 - A8 B1 - B8 H X H or L H or L H X ↑ ↑ X X Input Input X X L L X X X L L L X H or L X H L H X X L X L H H or L X H X Operation or Function Isolation Store A and B Data Output Input Input Output Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus NOTES: 1. H = HIGH L = LOW X = Don't Care ↑ = LOW-to-HIGH transition. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. 2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 3. A in B Register. 4. B in A Register. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10% Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1 µA IIL Input LOW Current(4) VCC = Max. VI = 0.5V — — ±1 µA IOZH High Impedance Output Current VCC = Max VO = 2.7V — — ±1 µA IOZL (3-State output pins)(4) VO = 0.5V — — ±1 II VIK VH Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis VCC = Max., VI = VCC (Max.) VCC = Min, IIN = -18mA — — — — –0.7 200 ±1 –1.2 — µA V mV ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 µA Min. 2.4 Typ.(2) 3.3 Max. — Unit 2 3 — — 0.3 0.55 V — OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC = Min VIN = VIH or VIL Test Conditions(1) IOH = –6mA MIL IOH = –8mA IND IOH = –12mA MIL IOH = –15mA IND IOL = 48mA MIL IOL = 64mA IND V VOL Output LOW Voltage VCC = Min VIN = VIH or VIL IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 –225 mA IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = –55°C. 5. This parameter is guaranteed but not tested. 3 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) BUS A DIR L G L MILITARY AND INDUSTRIAL TEMPERATURE RANGES BUS B CPAB X CPBA X BUS A SAB X DIR H SBA L G L Real-Time Transfer Bus B to A BUS A BUS B CPAB X CPBA X SAB L SBA X Real-Time Transfer Bus A to B BUS A BUS B DIR G CPAB CPBA SAB SBA H L ↑ X X X L L X ↑ X X X H ↑ ↑ X X DIR L H Storage From A and/or B G L L BUS B CPAB X H or L CPBA H or L X Transfer Stores (1) Data to A and/or B NOTE: 1. Cannot transfer data to A bus and B bus simultaneously. 4 SAB X H SBA H X IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 0.5 2 mA VIN = VCC VIN = GND — 0.15 0.25 mA/ MHz VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle VIN = VCC VIN = GND — 1.5 3.5 mA G = DIR = GND One Bit Toggling at fi = 5MHz VIN = 3.4V VIN = GND — 2 5.5 VCC = Max. Outputs Open fCP = 10MHz VIN = VCC VIN = GND — 3.8 7.3(5) VIN = 3.4V VIN = GND — 6 16.3(5) Symbol Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open G = DIR = GND One Input Toggling 50% Duty Cycle Total Power Supply Current(6) IC 50% Duty Cycle G = DIR = GND Eight Bits Toggling at fi = 2.5MHz NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 5 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW Parameter Propagation Delay, Bus to Bus Output Enable Time, G, DIR to Bus Output Disable Time, G, DIR to Bus Propagation Delay, Clock to Bus Propagation Delay, SBA or SAB to Bus Set-up Time HIGH or LOW, Bus to Clock Hold Time HIGH or LOW, Bus to Clock Clock Pulse Width, HIGH or LOW Condition(1) CL = 50pF RL = 500Ω 54FCT646T Mil. (2) Min. Max. 2 11 54/74FCT646AT Ind. Mil. (2) (2) Min. Max. Min. Max. 2 6.3 2 7.7 54/74FCT646CT Ind. Mil. (2) (2) Min. Max. Min. Max. Unit 1.5 5.4 1.5 6 ns 2 15 2 9.8 2 10.5 1.5 7.8 1.5 8.9 ns 2 11 2 6.3 2 7.7 1.5 6.3 1.5 7.7 ns 2 10 2 6.3 2 7 1.5 5.7 1.5 6.3 ns 2 12 2 7.7 2 8.4 1.5 6.2 1.5 7 ns 4.5 — 2 — 2 — 2 — 2 — ns 2 — 1.5 — 1.5 — 1.5 — 1.5 — ns 6 — 5 — 5 — 5 — 5 — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 6 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500Ω V OUT VIN Pulse Generator D.U.T . 50pF RT 500Ω Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL Octal link Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V 3V 1.5V 0V tREM tSU LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 3V 1.5V 0V tH 1.5V Octal link Pulse Width Octal link Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V CONTROL INPUT OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Octal link SWITCH CLOSED tPZH SWITCH OPEN 0V tPLZ tPZL VOH 1.5V VOL 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V Octal link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 7 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX IDT XX FCT Device Type Temp. Range XX Package X Process CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Blank B Industrial MIL-STD-883, Class B SO PY Q PG Industrial Options Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package Thin Shrink Small Outline Package D L Military Options CERDIP Leadless Chip Carrier 646T 646AT 646CT Fast CMOS Octal Transceiver/Register (3-State) 54 74 – 55°C to +125°C – 40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: [email protected] (408) 654-6459