S6AE101A Energy Harvesting PMIC for Wireless Sensor Node The S6AE101A is a power management IC (PMIC) for energy harvesting that is built into circuits of solar cells connected in series, output power control circuits, output capacitor storage circuits, and power switching circuits of primary batteries. Super-low-power operation is possible using a consumption current of only 250 nA and startup power of only 1.2 µW. As a result, even slight amounts of power generation can be obtained from compact solar cells under low-brightness environments of approximately 100 lx. The S6AE101A stores power generated by solar cells to an output capacitor using built-in switch control, and it turns on the power switching circuit while the capacitor voltage is within a preset maximum and minimum range for supplying energy to a load. If the power generated from solar cells is not enough, energy can also be supplied in the same way as solar cells from connected primary batteries for auxiliary power. Also, an over voltage protection (OVP) function is built into the input pins of the solar cells, and the open voltage of solar cells is used by this IC to prevent an overvoltage state. The S6AE101A is provided as a battery-free wireless sensor node solution that is operable by super-compact solar cells. Features Input power selection control: Solar cell or primary battery Block Diagram Operated by solar cells without the need for primary batteries Battery Storage of energy from power supply to storage capacitors (Optional) S6AE101A Power Gating Switch Output power gating control, output voltage regulation Multiplexer Storage Control Operation input voltage range Solar cell power battery power Primary : 2.0V to 5.5V : 2.0V to 5.5V Adjustable output voltage range : 1.1V to 5.2V Low-consumption current : 250 nA Minimum input power at startup : 1.2 µW Input overv oltage protection : 5.4V Compact SON-10 package : 3 mm×3 mm System Load Solar Cell Over Voltage Protection Control Block Voltage Reference Circuit Applications Energy harvesting power system with a very small solar cell Bluetooth® Smart sensor Wireless HVAC sensor Wireless lighting control Security system Smart home / Building / Industrial wireless sensor Cypress Semiconductor Corporation Document Number: 002-08493 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 25, 2016 S6AE101A Contents Features................................................................................................................................................................................... 1 Applications ............................................................................................................................................................................ 1 Block Diagram......................................................................................................................................................................... 1 1. Pin Assignment ................................................................................................................................................................. 3 2. Pin Descriptions ................................................................................................................................................................ 3 3. Architecture Block Diagram ............................................................................................................................................. 4 4. Absolute Maximum Ratings ............................................................................................................................................. 5 5. Recommended Operating Conditions ............................................................................................................................. 5 6. Electrical Characteristics ................................................................................................................................................. 6 7. Functional Description ..................................................................................................................................................... 7 7.1 Power Supply Control .................................................................................................................................................... 7 7.2 Power Gating ............................................................................................................................................................... 14 7.3 Discharge .................................................................................................................................................................... 14 7.4 Over Voltage Protection (OVP Block) .......................................................................................................................... 14 8. Application Circuit Example and Parts list ................................................................................................................... 15 9. Application Note.............................................................................................................................................................. 16 9.1 Setting the Operation Conditions ................................................................................................................................. 16 9.2 PCB Layout ................................................................................................................................................................. 17 10. Development Support ..................................................................................................................................................... 17 11. Reference Data ................................................................................................................................................................ 18 12. Usage Precaution ............................................................................................................................................................ 20 13. RoHS Compliance Information ...................................................................................................................................... 20 14. Ordering Information ...................................................................................................................................................... 20 15. Package Dimensions ...................................................................................................................................................... 21 16. Major Changes ................................................................................................................................................................ 22 Document History ................................................................................................................................................................. 22 Sales, Solutions, and Legal Information............................................................................................................................. 23 Document Number: 002-08493 Rev. *B Page 2 of 23 S6AE101A 1. Pin Assignment Figure 1-1 Pin Assignment (TOP VIEW) N.C. 1 10 VSTORE1 VINT 2 9 VOUT1 VBAT 3 8 SET_VOUTL VDD 4 7 SET_VOUTH AGND 5 6 SET_VOUTFB (VNE010) 2. Pin Descriptions Table 2-1 Pin Descriptions Pin No. Pin Name 1 N.C 2 VINT 3 VBAT 4 VDD 5 AGND 6 SET_VOUTFB 7 SET_VOUTH 8 SET_VOUTL 9 VOUT1 10 VSTORE1 I/O − O I I − O I I O O Description Non connection pin (Leave this pin open) Internal circuit storage output pin Primary battery input pin (when being not used, leave this pin open ) Solar cell input pin (when being not used, leave this pin open ) Ground pin. Reference voltage output pin (for connecting resistor) VOUT1 output voltage setting pin (for connecting resistor) VOUT1 output voltage setting pin (for connecting resistor) Output voltage pin Storage output pin Figure 2-1 I/O Pin Equivalent Circuit Diagram VSTORE1 VINT VBAT VDD VOUT1 VINT SET_VOUTFB AGND AGND Document Number: 002-08493 Rev. *B AGND VINT SET_VOUTL SET_VOUTH AGND Page 3 of 23 S6AE101A 3. Architecture Block Diagram Figure 3-1 Architecture Block Diagram Primary Battery Power supply block VBAT VOUT1 + Solar Cell SW4 SW1 to system Load Discharge VDD VSTORE1 SW2 VINT OVP block SW7 + 1.15V SW9 - VINT Power supply for internal circuit VINT SET_VOUTFB 1.15V + SET_VOUTH VSTORE1 SET_VOUTL Control + - AGND Document Number: 002-08493 Rev. *B Page 4 of 23 S6AE101A 4. Absolute Maximum Ratings Parameter Symbol Rating Condition Min −0.3 −0.3 − − −55 Max +6.9 VVDD 0.1 1200 (*2) +125 Unit Power supply voltage (*1) VDD, VBAT pin VMAX V Signal input voltage(*1) VINPUTMAX SET_VOUTH, SET_VOUTL pin V VDD slew rate VSLOPE VDD pin mV/µs Power dissipation (*1) Ta ≤+ 25°C PD mW Storage temperature TSTG − °C *1: When GND=0V *2: θja (wind speed 0m/s): +58°C/W Warning: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.Do not exceed any of these ratings. 5. Recommended Operating Conditions Parameter Symbol Condition Value Typ 3.3 3.0 Unit − − Sum of R1, R2, R3 VDD pin VINT pin VSTORE1 pin 10 10 1 100 − − − − Max 5.5 5.5 VINT pin voltage 50 − − − VSYSH VSTORE1 pin 1.3 − 5.2 V VSYSL VSTORE1 pin VSYSH ≥ 1.7V VSYSH < 1.7V 1.1 1.1 − − VSYSH × 0.90 VSYSH × 0.85 V V − −40 − +85 °C Power supply voltage 1 (*1) Power supply voltage 2 (*1) VVDD VVBAT VDD pin VBAT pin Signal input voltage (*1) VINPUT SET_VOUTH, SET_VOUTL pin VOUT1 setting resistance VDD capacitance VINT capacitance VSTORE1 capacitance VOUT maximum setting voltage VOUT minimum setting voltage Operating ambient temperature *1: When GND = 0V RVOUT C1 C2 C3 Ta Min 2.0 2.0 V V V MΩ µF µF µF Warning: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-08493 Rev. *B Page 5 of 23 S6AE101A 6. Electrical Characteristics The electrical characteristics excluding the effect of external resistors and external capacitors are shown in below. Table 6-1 Electrical Characteristics (System Overall) (Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.) Parameter Symbol Minimum Input power in start-up WSTART Consumption current 1 IQIN1 Power detection voltage Power undetection voltage Power detection hysteresis VDETH VDETL VDETHYS VOUT maximum voltage VVOUTH Input power reconnect voltage VVOUTM VOUT minimum voltage VVOUTL OVP detection voltage OVP release voltage OVP detection hysteresis OVP protection current VOVPH VOVPL VOVPHYS IOVP Condition VDD pin, Ta = +25°C, VVOUTH setting =3V, By applying 0.4 µA to VDD, when VOUT1 reaches 3V × 95% after the point when VDD reaches 3V. VDD pin input current, VDD=3V, Open VBAT pin, SW2 = OFF, Ta = +25°C, SET_VOUTFB resistance = 50 MΩ, VOUT1 Load = 0 mA VDD, VBAT ,VINT pin VDD, VBAT ,VINT pin VDD, VBAT ,VINT pin VSYSH ≥ 2V VSTORE1 pin, VOUT1 Load=0 mA VSYSH < 2V VSTORE1 pin, VOUT1 Load=0 mA VSTORE1 pin, VOUT1 Load=0 mA VDD pin VDD pin VDD pin VDD pin input current VSYSH ≥ 2V VSYSH < 2V VSYSL ≥ 2V VSYSL < 2V Min Value Typ Max − − 1.2 µW − 250 390 nA 1.0 0.9 − VSYSH×0.950 VSYSH×0.935 VVOUTH ×0.90250 VVOUTH ×0.88825 VSYSL×0.950 VSYSL×0.935 5.2 5.1 − 6 1.4 1.3 0.1 VSYSH VSYSH VVOUTH × 0.95 VVOUTH × 0.95 VSYSL VSYSL 5.4 5.3 0.1 − Unit 2.0 V 1.9 V − V VSYSH×1.050 V VSYSH×1.065 V VVOUTH V × 0.99750 VVOUTH V ×1.01175 VSYSL×1.050 V VSYSL×1.065 V 5.5 V 5.4 V − V − mA Table 6-2 Electrical Characteristics (Switch) VDD ≥ 3V, VBAT ≥ 3V, VINT ≥ 3V, VVOUTL ≥ 3V, VSTORE1 ≥ VVOUTL (Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.) Parameter Symbol On resistance 1 RON1 On resistance 2 RON2 On resistance 4 RON4 Discharge resistance RDIS Document Number: 002-08493 Rev. *B Condition SW1, In connection of VSTORE1 pin and VOUT1 pin SW2, In connection of VDD pin and VSTORE1 pin SW4, In connection of VDD pin and VSTORE1 pin VOUT1 pin Min Value Typ Max − 1.5 2.5 Ω − 5 10 kΩ − 5 10 kΩ − 1 2 kΩ Page 6 of 23 Unit S6AE101A 7. Functional Description 7.1 Power Supply Control This IC can operate by two input power supplies, namely, the solar cell voltage VDD and the primary battery voltage VBAT. The voltages at the VDD pin and VBAT pin are monitored, and selection control of the input power supply is performed based on this voltage state (Figure 7-1). The input power (solar cell or primary battery) is temporarily stored to a capacitor connected to the VSTORE1 pin. When the voltage of the VSTORE1 pin reaches a certain threshold value or higher, the power switching switch (SW1) connects VSTORE1 and VOUT1. Table 7-1 Input Power Supply Selection Control VDD Voltage (Solar Cell) VBAT Voltage (Primary Battery) VDETH (1.55V) or higher VDETH (1.55V) or higher VDETL (1.45V) or less VDETH (1.55V) or higher VDETL (1.45V) or less VDETL (1.45V) or less Operation VDD input power supply is performed VDD input power supply is performed VBAT input power supply is performed All paths are disconnected Figure 7-1 Input Power Selection Control (a) Switching Between VDD Input and VBAT Input [V] VDD VDD VBAT VBAT VDETH VDETL time VBAT input operation VDD input operation VBAT input operation (b) Switching Between VDD Input and Disconnection of All Paths [V] VDD VDD VBAT VBAT VDETH VDETL time Disconnection of All Paths Document Number: 002-08493 Rev. *B VDD Input Operation Disconnection of All Paths Page 7 of 23 S6AE101A 1. VDD input voltage operation This section describes operation when the VDD pin is set as the input power (Figure 7-2). [1] When the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, the switch (SW2) connects VDD and VSTORE1 (path S1). Also, when the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45V) or less, SW2 disconnects the path S1. [2] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the SET_VOUTH pin, SW2 disconnects the path S1. Also, the VOUT switch (SW1) connects VSTORE1 and VOUT1 (path S2). [3] When the voltage of the VSTORE1 pin falls to the input power reconnect voltage (VVOUTM) or less, SW2 connects the path S1 (path S1+S2). [4] In addition, when the voltage falls to the threshold value (VVOUTL) or less that was set by the SET_VOUTL pin, SW1 disconnects the path S2. [5] When SW1 disconnects the path S2, the discharge function is activated. Document Number: 002-08493 Rev. *B Page 8 of 23 S6AE101A Figure 7-2 VDD Pin Input Power Operation (a) Internal Operation Diagram VOUT1 S6AE101A Solar Cell SW1 S2 VDD VSTORE1 SW2 MCU + RF S1 VINT SW7 (b) Operation Sequence [1] [2] [3] [4] [V] VDD VINT [5] Open Voltage of Solar Cell VDD VDETH VDETL VINT [V] S2 VVOUTH VVOUTM VSTORE1 S1 S1 + S2 S2 S1 + S2 S1 VVOUTL S1 + S2 S2 S1 [V] VOUT1 [mA] VOUT1 Load time SW1 SW2 SW7 off off on on off off on on on off off off on on on VDETH VDETL VVOUTH VVOUTM VVOUTH VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH VDETH(VINT) VDETH(VDD) Document Number: 002-08493 Rev. *B Page 9 of 23 S6AE101A 2. VBAT input voltage operation This section describes operation when the VBAT pin is set as the input power (Figure 10-3). [1] When the voltage of the VBAT pin reaches the power detection voltage (VDETH = 1.55V) or higher, the switch (SW2) connects VBAT and VSTORE1 (path S3). Also, when the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45V) or less, SW4 disconnects the path S3. [2] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the SET_VOUTH pin, SW4 disconnects the path S3. Also, the VOUT switch (SW1) connects VSTORE1 and VOUT1 (path S2). [3] When the voltage of the VSTORE1 pin falls to the input power reconnect voltage (VVOUTM) or less, SW4 connects the path S3 (path S3+S2). [4] In addition, when the voltage falls to the threshold value (VVOUTL) or less that was set by the SET_VOUTL pin, SW1 disconnects the path S2. [5] When SW1 disconnects the path S2, the discharge function is activated. Document Number: 002-08493 Rev. *B Page 10 of 23 S6AE101A Figure 7-3 VBAT Pin Input Power Operation (a) Internal Operation Diagram VOUT1 S6AE101A SW1 S2 Primary Battery VBAT VSTORE1 SW4 MCU + RF S3 + VINT SW9 (b) Operation Sequence [1] [2] [3] [4] [V] VBAT VINT [5] VBAT VDETH VDETL VINT [V] S2 VVOUTH VVOUTM VSTORE1 S3 S3 + S2 S2 S3 + S2 S3 VVOUTL S3 + S2 S2 S3 [V] VOUT1 [mA] VOUT1 Load time SW1 SW4 SW9 off off on on off off on on on off off off on on VVOUTL VVOUTH VVOUTM VVOUTH VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH VDETH(VINT) VDETH(VDD) Document Number: 002-08493 Rev. *B Page 11 of 23 S6AE101A 3. Input power supply switching This section describes the input power switching operation (Figure 7-4). [1] If the voltages of the VDD pin and VBAT pin increase from a state where both are less than the power detection voltage (VDETH = 1.55V) so that the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, and operation switches to VDD input power operation back from the stage of disconnecting all paths. [2] When the voltage of the VBAT pin increases to the power detection voltage (VDETH = 1.55V) or higher, if the power from the solar cell is reduced, and when the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45V) or less, operation switches from VDD input power operation to VBAT input power operation. [3] When the amount of power supplied from the solar cell increases, and the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, operation switches back to VDD input power operation. After switching, operation is performed based on VDD input power operation. Document Number: 002-08493 Rev. *B Page 12 of 23 S6AE101A Figure 7-4 Input Power Switching (a) Internal Operation Diagram S6AE101A Primary Battery VBAT SW4 + VOUT1 SW1 SW9 S2 VDD Solar Cell VSTORE1 SW2 MCU + RF S1 VINT S3 SW7 (b) Operation Sequence [1] [2] Operation Stop [3] VDD Input Operation VBAT Input Operation VDD Input Operation [V] VBAT VDETH VDETL [V] Open Voltage of Solar Cell VINT VDD VINT VDD VDD VDD VDETH VDETL VINT [V] S2 S2 VVOUTH VVOUTM VSTORE1 S1 S1 + S2 S2 S1 + S2 S1 S3 S3 + S2 S2 VVOUTL S3 + S S2 3 S1 S2 off on off on off off on [V] VOUT1 time [mA] VOUT1 Load time SW1 off on SW2 off on SW7 off on SW4 off on SW9 off on off on on on off on on off off VVOUTH VDETH (VDD) VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH VDETL (VDD) VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH VDETH (VINT) VDETH (VDD,VBAT) Document Number: 002-08493 Rev. *B off Page 13 of 23 S6AE101A 7.2 Power Gating This IC has a power gating function for the external system. Once it is detected that the voltage of the VSTORE1 pin has reached the VOUT maximum voltage (VVOUTH), the VSTORE1 pin and VOUT pin are connected by an internal switch until the VOUT minimum voltage (VVOUTL) is reached. Figure 7-5 Power Gating Operation [V] VVOUTH VSTORE1 VVOUTL [V] VOUT1 SW1 OFF SW1 ON SW1 OFF time 7.3 Discharge This IC includes a VOUT1 pin discharge function. When SW1 disconnects the VSTORE1 and VOUT1 path, the discharge circuit is activated between the VOUT1 pin and GND. The power of the VOUT1 pin is discharged to the GND level. 7.4 Over Voltage Protection (OVP Block) This IC includes an input overvoltage protection (OVP) function for the VDD pin voltage. When the VDD pin voltage reaches the OVP detection voltage (VOVPH=5.4V) or higher, the OVP current (IOVP) from the VDD pin is drawn in for limiting the increase in the VDD pin voltage for preventing damage to the IC. Also, when the OVP release voltage (VOVPL=5.3V) or less is reached, drawing-in of the OVP current is stopped. Figure 7-6 OVP Operation [V] VDD Open Voltage of Solar Cell VOVPH VOVPL [mA] IOVP IOVP time Document Number: 002-08493 Rev. *B Page 14 of 23 S6AE101A 8. Application Circuit Example and Parts list Figure 8-1 Application Circuit Example Primary Battery VBAT VOUT1 + VSTORE1 C3 Solar Battery D1 VDD C1 VINT S6AE101A C2 MCU + RF SET_VOUTFB R1 SET_VOUTH R2 SET_VOUTL R3 AGND Table 8-1 Parts List Symbol Item Value C1 Ceramic capacitor 10 μF C2 Ceramic capacitor 1 μF C3 Ceramic capacitor 100 μF R1 Resistor 6.8 MΩ (*1) R2 Resistor 2.7 MΩ (*1) R3 Resistor 9.1 MΩ (*1) D1 Diode − *1: Setting of VOUT maximum voltage: VVOUTH ≈ 3.3V, VOUT minimum voltage: VVOUTL ≈ 2.6V. Document Number: 002-08493 Rev. *B Remarks − − − − − − − Page 15 of 23 S6AE101A 9. Application Note 9.1 Setting the Operation Conditions Setting of output voltage (VOUT1) The resistor connecting the SET_VOUTH pin and SET_VOUTL pin can be changed to set the VOUT1 output voltage of this IC. This is because the VOUT maximum voltage (VVOUTH) and VOUT minimum voltage (VVOUTL) are set based on the connected resistance. The SET_VOUTFB pin outputs a reference voltage for setting the VOUT maximum voltage and VOUT minimum voltage. Resistor voltage division can be performed on this reference voltage outside the IC for creating a voltage applied to the SET_VOUTH pin and SET_VOUTL pin. Figure 9-1 Setting of output voltage (VOUT1) S6AE101A SET_VOUTFB R1 R2 SET_VOUTH SET_VOUTL R3 The VOUT maximum voltage (VVOUTH) and VOUT minimum voltage (VVOUTL) can be calculated using the formulas below. VOUT maximum voltage 57.5 × (R2 + R3) 11.1 × (R1 + R2 + R3) VVOUTH [V] = VOUT minimum voltage VVOUTL [V] = 57.5 × R3 11.1 × (R1 + R2 + R3) The characteristics when the total value for R1, R2, and R3 is from 10 MΩ to 50 MΩ are shown in "6. Electrical Characteristics". Document Number: 002-08493 Rev. *B Page 16 of 23 S6AE101A 9.2 PCB Layout Take into account the following points when designing the layout. Try to route the wiring for the diode (D1) and input capacitor (C1) for connecting the solar cell on the top layer as m uch as possible, and avoid implementing a connection using a through hole. For the AGND pin of S6AE101A, provide a through hole nearby, and connect it to the GND plane. Locate the capacitor (C2) for the internal power as near as possible to the VINT pin. Locate the resistors (R1, R2, R3) for setting the output voltage in a grid-type configuration with small loops, and locat e them as near as possible to each pin (SET_VOUTFB, SET_VOUTH, SET_VOUTL). Also, removing the GND plane under the parts can be effective in preventing malfunctions due to the leakage current. To prevent a leakage current, locate and route the storage capacitor (C3) as far as possible from patterns that are dif ferent from the electrical potential of VSTORE1 (such as the GND line). Generally, the insulation resistor of printed cir cuit boards is extremely high, and normally, the passing of leakage current through the board does not pose a proble m. However, in certain rare cases, the surface of the board may have a low insulation resistance, and when using th ese boards, a leakage current that cannot be ignored may occur. C2 Figure 9-2 PCB Layout Example Battery Input C1 D1 Solar Input C3 N.C. VSTORE1 VINT VOUT1 VBAT SET_VOUTL VDD SET_VOUTH AGND Through Hole Top Layer SET_VOUTFB R3 VOUT R2 R1 Remove Solid Pattern GND Layer 10. Development Support This IC has a set of documentation, such as application notes, development tools, and online resources to assist you during your development process. Visit www.cypress.com/energy-harvesting to find out more. Document Number: 002-08493 Rev. *B Page 17 of 23 S6AE101A 11. Reference Data For the circuit diagram of the reference data, Refer to "Figure 8-1 Application Circuit Example". Figure 11-1 Reference Data RON1 vs Temp. IQIN1 vs VVDD 600 VBAT voltage = 0V, SW2 = OFF, RVOUT = 50 MΩ 1.8 RDIS vs Temp. VVDD = 3V 1.4 VVDD = 3V VVOUTH = 1.3V, VVOUTL = 1.1V 1.6 500 1.3 o TA = +95 C 1.4 1.2 300 o RDIS [kΩ] TA = +25oC RON1 [Ω] IQIN1 [nA] 400 1.2 1.0 TA = -40 C 1.1 1.0 200 0.8 100 0.9 0.6 0 2.0 2.5 3.0 3.5 4.0 VVDD [V] 4.5 5.0 0.4 -40 -20 5.5 0 20 40 Temp. [oC] 60 0.8 -40 -20 100 VDETH, VDETL (of VDD) vs Temp. VDETH, VDETL (of VBAT) vs Temp. 1.9 1.9 1.9 1.8 1.8 1.8 1.7 1.7 1.4 1.3 VDETH VDETL 1.6 1.5 1.4 1.5 1.4 1.3 1.2 1.2 1.2 1.1 1.1 1.1 1.0 -40 -20 1.0 -40 -20 20 40 Temp. [oC] 60 80 100 0 20 40 Temp. [oC] 60 S6AE101AGraph004 80 100 1.0 -40 -20 0 20 40 Temp. [oC] 60 S6AE101AGraph005 VDD Input Power Supply VDD current = 0A TA=+25oC VDD current = 4 µA TA=+25oC 4 µA, VOUT1 current = 1 µA, C3 = 100 µF, VVOUTH = 5.2V, VVOUTL = 4.68V 80 0A, VOUT1 current = 1 µA, C3 = 100 µF, VVOUTH = 5.2V, VVOUTL = 4.68V VDD 2 V/div VDD 2 V/div VINT 2 V/div VINT 2 V/div VSTORE1 2 V/div VSTORE1 2 V/div VOUT1 2 V/div VOUT1 2 V/div 10 s/div 10 s/div S6AE101AGraph019 100 S6AE101AGraph006 VDD Input Power Supply Document Number: 002-08493 Rev. *B 100 VDETH VDETL 1.6 1.3 0 80 1.7 VINT voltage [V] VBAT voltage [V] 2.0 1.5 60 VDETH, VDETL (of VINT) vs Temp. 2.0 VDETH VDETL 20 40 Temp. [oC] S6AE101AGraph018-1 2.0 1.6 0 S6AE101AGraph017-1 S6AE101AGraph001 VDD voltage [V] 80 S6AE101AGraph020 Page 18 of 23 S6AE101A VDD Input Power Supply VDD Input Power Supply VDD current = 0A TA=+25oC VDD current = 40 µA TA=+25oC 40 µA, VOUT1 current = 10 µA, C3 =100µF, VVOUTH = 5.2V, VVOUTL = 4.68V 0A, VOUT1 current = 10 µA, C3 =100µF, VVOUTH = 5.2V, VVOUTL = 4.68V VDD 2 V/div VDD 2 V/div VINT 2 V/div VINT 2 V/div VSTORE1 2 V/div VSTORE1 2 V/div VOUT1 2 V/div VOUT1 2 V/div 1 s/div 10 s/div S6AE101AGraph021 S6AE101AGraph022 VDD & VBAT Input Power Supply o VDD & VBAT Input Power Supply o VOUT1 current = 10 µA, C3 = 100 µF, TA= +25 C, VDD voltage = 0V 5.5V, VBAT voltage = 2V VOUT1 current = 10 µA, C3 = 100 µF, TA= +25 C, VDD voltage = 5.5V 0V, VBAT voltage = 2V VVOUTH = 1.3V, VVOUTL = 1.1V VVOUTH = 1.3V, VVOUTL = 1.1V VDD 4 V/div VDD 4 V/div VBAT 4 V/div VBAT 4 V/div VINT 4 V/div VINT 4 V/div VOUT1 0.5 V/div VOUT1 0.5 V/div 0.4 s/div 0.4 s/div S6AE101AGraph027 S6AE101AGraph028 VDD & VBAT Input Power Supply o VDD & VBAT Input Power Supply o VOUT1 current = 10 µA, C3 = 100 µF, TA= +25 C, VDD voltage = 0V 2V, VBAT voltage = 5.5V VOUT1 current = 10 µA, C3 = 100 µF, TA= +25 C, VDD voltage = 2V 0V, VBAT voltage = 5.5V VVOUTH = 1.3V, VVOUTL = 1.1V VVOUTH = 1.3V, VVOUTL = 1.1V VDD 4 V/div VDD 4 V/div VBAT 4 V/div VBAT 4 V/div VINT 4 V/div VINT 4 V/div VOUT 0.5 V/div VOUT 0.5 V/div 0.4 s/div 0.4 s/div S6AE101AGraph029 Document Number: 002-08493 Rev. *B S6AE101AGraph030 Page 19 of 23 S6AE101A 12. Usage Precaution Printed circuit board ground lines should be set up with consideration for common impedance. Take appropriate measures against static electricity. Containers for semiconductor materials should have anti−static protection or be made of conductive material. mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground. After Do not apply negative voltages. The use of negative voltages below −0.3 V may make the parasitic transistor activated to the LSI, and can cause malfunctions. 13. RoHS Compliance Information This product has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). 14. Ordering Information Table 14-1 Ordering Part Number Part number (MPN) S6AE101A0DGNAB000 Package 10-pin plastic SON (0.5mm pitch) (VNE010) MPN: Marketing Part Number Figure 14-1 Ordering Part Number Definitions S 6A E 1 0 1 A 0D G NA B 0 0 0 Fixed on 000 Packing: B = 13 inch Tape and Reel (ER) Package: NA = SON, Pd-PPF/Low-Halogen Reliability Grade: G = 100 ppm (Commercial Sample) Preset Condition Revision: A = 1st Revision Product ID: 01 Topology: 1 = Buck Power Supply Product Type: E = Energy Harvesting PMIC Product Class: 6A = Consumer Analog Company ID: S = Cypress Document Number: 002-08493 Rev. *B Page 20 of 23 S6AE101A 15. Package Dimensions Document Number: 002-08493 Rev. *B Page 21 of 23 S6AE101A 16. Major Changes Spansion Publication Number: S6AE101A_DS405-00026 Page Section Change Results Preliminary 0.1 Initial release − − NOTE: Please see “Document History” about later revised information. Document History Document Title: S6AE101A Energy Harvesting PMIC for Wireless Sensor Node Document Number: 002-08493 Revision ECN ** − Orig. of Submission Change Date TAOA Description of Change 04/27/2015 New Spec. Added Block Diagram Updated 5. Recommended Operating Conditions *A 5054369 TAOA 12/17/2015 Updated 6. Electrical Characteristics Updated Table 8-1 Parts List Updated 9.1 Setting the Operation Conditions: Changed the formulas for the VOUT maximum voltage and VOUT minimum voltage. Added Figure 2-1 I/O Pin Equivalent Circuit Diagram *B 5103619 HIXT 01/25/2016 Updated Figure 3-1 Architecture Block Diagram Added 10. Development Support Added 11. Reference Data Document Number: 002-08493 Rev. *B Page 22 of 23 S6AE101A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface Lighting & Power Control cypress.com/go/interface cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF Spansion Products psoc.cypress.com/solutions cypress.com/go/wireless cypress.com/spansionproducts Cypress, the Cypress logo, Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2015-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsi bility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 002-08493 Rev. *B January 25, 2016 Page 23 of 23