VISHAY SILICONIX www.vishay.com Power MOSFETs Application Note AN834 Estimating Junction Temperature by Top Surface Temperature in Power MOSFETs By Satoru Sawahata ABSTRACT The thermal data provided on MOSFET datasheets is usually limited to thermal impedance between junction-to-lead and junction-to-ambient. While a number of sophisticated tools are available for more accurate thermal simulation based on customized conditions, quite often design engineers simply do to have resources or the time to utilize them. However, measuring the top surface temperature is relatively easy, and a simple way of estimating the MOSFET junction temperature based on this top surface measurement would give designers quite a useful tool. Just such a methodology is presented by this application note. To study the relationship between junction temperature and top surface temperature, we ran ThermaSim™ under specific conditions. To get better agreement with the datasheet, MOSFETs should be mounted on 1-in by 1-in square FR-4 board. Si4800BDY: SO-8 SINGLE-DIE, BONDING-WIRED PACKAGE Figure 1 shows the ThermaSim results of the Si4800BDY when dissipating 0.5 W. The results show a die temperature of +80.95 °C and a top temperature of +77 °C. MIN. TEMP. MAX. TEMP. DIE. TEMP. TOP TEMP. BOTTOM TEMP. FLUX to PCB +62.15 °C +81.01 °C +80.95 °C +77.00 °C +67.16 °C 0.47 W Revision: 01-Oct-15 Document Number: 69993 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE Fig. 1 - ThermaSim Output Result Application Note AN834 www.vishay.com Vishay Siliconix Estimating Junction Temperature by Top Surface Temperature in Power MOSFETs Figure 2 shows the temperature rise of the top surface and Die with power dissipation up to 1 W. 120 100 Temperature Rise (°C) Tdie rise 80 Ttop rise 60 40 20 0 0 0.2 0.4 0.6 0.8 1 1.2 Power Dissipation (W) Fig. 2 - Si4800BDY Top and Die Temperature Rise The simulation results for power dissipation levels of 0.2 W to 1 W are shown in table 1. Tdie rise = Tdie - 25, and Ttop rise = Ttop - 25, respectively, and K = [Tdie rise]/[Ttop rise]. The coefficient K is consistent with the power dissipation, and by averaging K, we arrive at 1.074 as a ratio of Ttop rise to Tdie rise. TABLE 1 - ThermaSIM RESULTS FOR Si4800BDY Pd (W) Tdie (°C) Ttop (°C) Tdie rise (°C) Ttop rise (°C) K 1 121.998 114.720 97.0 89.7 1.081 0.8 104.879 99.143 79.9 74.1 1.077 0.6 86.614 82.337 61.6 57.3 1.075 0.4 67.791 64.941 42.8 39.9 1.071 0.2 48.156 46.760 23.2 21.8 1.064 - - - - AVG 1.074 Another approximation line can be determined by [Tdie rise] = 1.074 x [Ttop rise]. This linear approximation line describes the actual data well, as shown in figure 3. For this particular part, the die temperature rise is approximately 7.4 % higher than the top surface temperature. Revision: 01-Oct-15 Document Number: 69993 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE The temperature difference between the top and the die is proportional to the power dissipation. Application Note AN834 www.vishay.com Vishay Siliconix Estimating Junction Temperature by Top Surface Temperature in Power MOSFETs 120 100 Tdie rise Tdie rise (°C) 80 Series 2 60 40 20 0 0 10 20 30 40 50 60 Ttop rise (°C) 70 80 90 100 Fig. 3 - Top Temperature Rise vs. Die Temperature Rise of Si4800BDY Si4686DY: SINGLE SO-8 BONDING-WIRE-LESS (BWL) PACKAGE A bonding-wire-less (BWL) package will make some difference on the heat spread, since a clip between the die and source pins makes another heat flux to the board. Figure 4 shows the results of using Si4686DY as a sample for this simulation. 90 80 Tdie rise Series 2 70 Tdie rise (°C) 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Ttop rise (°C) Fig. 4 - Top Temperature Rise vs. Die Temperature Rise of Si4686BDY The graph shows a similar result to the Si4800BDY simulation. However, the temperature difference between the top surface to die is 6.6 % for this part. Revision: 01-Oct-15 Document Number: 69993 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE 0 Application Note AN834 www.vishay.com Vishay Siliconix Estimating Junction Temperature by Top Surface Temperature in Power MOSFETs Si7336ADP: SINGLE PowerPAK® SO-8 BWL PACKAGE The next example is the PowerPAK SO-8 with a BWL package. Figure 5 shows the top temperature rise vs. the die temperature rise for the Si7336ADP. 80 70 Tdie rise 60 Series 2 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 Fig. 5 - Top Temperature Rise vs. Die Temperature Rise of Si736ADP Because it has a thinner package than the standard SO-8, the PowerPAK SO-8 shows a top temperature closer to the die temperature. It shows similar results to the previous simulations; however, the temperature difference between the top surface to die is only 1.4 % for this part, while it is 6.6 % or 7.4 % for the standard SO-8. We have run this thermal simulation on other packages as well, as shown in table 2. TABLE 2 - THERMAL COEFFICIENT FOR DIFFERENT PARTS PACKAGE SO-8 BWL SO-8 ChipFET® PowerPAK SO-8 DPAK D2PAK Revision: 01-Oct-15 COEFFICIENT Si4336DY 1.029 Si4686DY 1.066 Si4800BDY 1.074 Si4894BDY 1.044 Si5404BDC 1.028 Si5441BDC 1.035 Si7112DN 1.016 Si7806ADN 1.017 Si7336ADP 1.014 Si7880ADP 1.022 SUD50N02-06 1.080 SUD50N25-06P 1.083 SUM110N04-02L 1.182 SUM110N10-09 1.175 Document Number: 69993 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE PowerPAK 1212 PART NUMBER Application Note AN834 www.vishay.com Vishay Siliconix Estimating Junction Temperature by Top Surface Temperature in Power MOSFETs The coefficients for the D2PAK are the largest among all the packages because it has the thickest molding. The second largest is the DPAK, which has the second thickest molding. The PowerPAK SO-8 and PowerPAK 1212 show smaller numbers due to their thinner molding. CONCLUSION From the investigation above, we have determined that the die temperature rise is proportional to the top surface temperature rise: [Tdie rise] = k x [Ttop rise] Coefficient K depends on the package and is approximately 1.18 for the D2PAK and 1.08 for the DPAK. For the PowerPAK SO-8 and PowerPAK 1212, it is roughly 1.02. For other packages it varies from 1.03 to 1.07, depending on the die size or package construction. The ThermaSim simulations have shown that the die temperature is much closer to the top surface temperature than was expected. REFERENCE 1. Kandarp Pandya and Serge Jaunay, “Thermal Analysis of Power MOSFETs Using Rebecca-3D Thermal Modeling Software (From Epsilon Ingenierie) versus Physical Measurements and Possible Extractions,” The 6th IEEE EuroSimE Conference Berlin. 2. Wharton McDaniel, “MOSFET Thermal Characterization in the Application,” Application Note AN819, Vishay Siliconix. Document Number: 69993 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE Revision: 01-Oct-15