RT7300A PFC Controller with Critical Conduction Mode General Description Features The RT7300A is an active Power Factor Correction (PFC) controller with critical conduction mode (CRM) operation that is designed to meet line current harmonic regulations for the applications of AC/DC adapters, electronic ballasts and medium off-line power converters (<300W). The CRM and Feed-Forward schemes provide near unity power factor across a wide range of input voltages and output powers. The totem-pole gate driver with 600mA sourcing current and 800mA sinking current provides powerful driving capability for power MOSFET to improve conversion efficiency. The RT7300A features an extra low start-up current (20A) and supports a disable function to reduce power consumption in standby mode, which makes it easy to comply with energy saving regulations such as Blue Angel, Energy Star and Energy 2000. This controller integrates comprehensive safety protection functions for robust designs including input under voltage lockout, output over voltage protection, Critical Conduction Mode (CRM) Operation Constant On-Time Control (Voltage Mode) Near Unity Power Factor Ultra Low Start-up Current (<20A) Input Voltage Feed-Forward Compensation Wide Supply Voltage Range from 12V to 25V Totem Pole Gate Driver with 600mA/800mA Maximum Frequency Clamping (120kHz) DCM THD Optimization Fast Dynamic Response Light Load Burst Mode Operation Disable Function Maximum/Minimum On-Time Limit Cycle-by-Cycle Current Limit Output Over Voltage Protection (OVP) Output Under Voltage Protection (UVP) Under Voltage Lockout (UVLO) RoHS Compliant and Halogen Free Applications Electrical Lamp Ballast under voltage protection and cycle-by-cycle current limit. The RT7300A is a cost-effective solution for PFC power converter with minimum external components. It is available in the SOP-8 package. LED Lighting AC/DC Adapter/Charger for Desktop PC, NB, TV, Monitor, Etc. Entry-Level Server, Web Server Simplified Application Circuit BD LPFC DOUT Line VOUT+ RG Q1 CSIN COUT RCS Neutral VOUTGD RZCD ZCD DVDD RFF1 INV VDD CINV CVDD RSTART CFF Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 May 2014 ROUT2 COMP RCOMP FF RFF2 ROUT1 CS RT7300A RAUX GND CCOMP2 CCOMP1 is a registered trademark of Richtek Technology Corporation www.richtek.com 1 RT7300A Ordering Information Marking Information RT7300AGS : Product Number YMDNN : Date Code RT7300A Package Type S : SOP-8 Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RT7300A GSYMDNN Pin Configurations (TOP VIEW) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. INV Suitable for use in SnPb or Pb-free soldering processes. 8 VDD COMP 2 7 GD FF 3 6 GND CS 4 5 ZCD SOP-8 Functional Pin Description Pin No. Pin Name Pin Function 1 INV Inverting Input of the Internal Error Amplifier. Connect a resistive divider from output voltage to this pin for voltage feedback. It also used for OVP and UVP detections. 2 COMP Output of the Internal Error Amplifier. Connect a compensation network between this pin and GND for dynamic load performance. 3 FF Feed-Forward Input for Line Voltage. This pin senses the line input voltage via a resistive divider. Connect a suitable capacitor to filter out the line voltage ripple & noise. 4 CS Current Sense Input. The current sense resistor between this pin and GND is used for current limit setting. 5 ZCD Zero Current Detection Input. Input from secondary winding of PFC choke for detecting demagnetization timing of PFC choke. This pin also can be used to enable/disable the controller. 6 GND Ground of the Controller. 7 GD Gate Driver Output for External Power MOSFET. 8 VDD Supply Voltage Input. The controller will be enabled when VDD exceeds VON_TH (12.45V typ.) and disabled when VDD decreases lower than VOFF_TH (9V typ.). Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A Function Block Diagram Blank & Maximum Frequency Clamping Clamping Circuit ZCD CS S Zero Current Detect Start GD Disable + Leading Edge Blanking 0.85V COMP 1.5V Feed- Forward & THD Optimize Ramp Generator FF Soft Driver Q R - + GM - - 1.65V - OVP VDD UVLO + GND + - UVP 0.25V + INV Operation Critical Conduction Mode (CRM) Constant On-Time Voltage Mode Control The Critical Conduction Mode is also called Transition Mode or Boundary Mode. Figure 1 shows the CRM operating at the boundary between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). Figure 2 shows a typical Boost converter. When the MOSFET turns on with a fixed on-time (TON), the inductor current can be calculated by the following equation (1). LPFC In CRM, the power switch turns on immediately when the inductor current decreases to zero. The CRM is the preferred control method for medium power (<300W) VIN applications due to the features of zero current switching and lower peak current than that in DCM. Inductor Current DOUT Q1 COUT RLOAD Figure 2. Typical Boost Converter IL_PK = VIN TON LPFC (1) If the input voltage is a sinusoidal waveform and rectified by a bridge rectifier, the inductor current can DCM CRM be expressed with equation (2). When the converter operates in CRM with constant on-time voltage mode CCM control, the envelope of inductor peak current will follow the input voltage waveform with in-phase. The average Figure 1. Inductor Current of DCM, CRM and CCM inductor current will be half of the peak current shown as Figure 3. Therefore, the near unity power factor is easy to be achieved by this control scheme. IL_pk | sinθ | = Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 May 2014 VIN_pk | sinθ | TON LPFC (2) is a registered trademark of Richtek Technology Corporation www.richtek.com 3 RT7300A IL_pk = Iin_avg VIN TON LPFC = 1 IPK 2 Feedback Voltage Detection Figure 5 shows the feedback voltage detection circuit. The INV pin is the inverting input of the Error Amplifier with 1.5V reference voltage. Over voltage and under voltage protections are provided with threshold voltage 1.65V and 0.25V respectively. If the INV voltage is over 1.65V or under 0.25V, the gate driver will be disabled to prevent output over voltage condition or feedback open condition. Although the INV is an input pin with high impedance, it is suggested that the bias current of the potential divider should be over 30A for noise immunity. IL_PK Input Voltage Peak Inductor Current IQ1 MOSFET Current Iin_avg Average Input Current IDOUT Output Diode Current VIN COMP 1.5V VOUT+ ROUT1 VQ1_GATE MOSFET Gate Voltage INV Figure 3. Inductor Current of CRM with Constant ROUT2 1.65V Under Voltage Lockout - OVP + - CINV 0.25V On-Time Voltage Mode Control + GM - UVP + Figure 5. Feedback Voltage Detection The controller will be enabled when VDD exceeds VON_TH (12.45V typ.) and disabled when VDD decreases lower than VOFF_TH (9V typ.). Transconductance Error Amplifier When the VDD is available, the precise reference is generated for internal circuitries such as Error The RT7300A implements transconductance error amplifier with non-linear GM design to regulate the Boost output voltage and provide fast dynamic response. The transconductance value is 100A/V in normal operation. When the INV voltage increases over 1.65V or decreases under 1.35V, the output of error amplifier will source or sink 1mA maximum current at Amplifier, Current Sense, OVP, UVP. The internal reference equips with excellent temperature coefficient COMP pin respectively shown as Figure 6. Thus, the non-linear GM design can provide fast response for the performance so that the RT7300A can be operated in varied environments. dynamic load of PFC converters even though the bandwidth of control loop is lower than line frequency. The maximum VDD voltage is set at 27V typically for over voltage protection shown as Figure 4. An internal 29V zener diode is also used to avoid over voltage stress for the internal circuits. UVLO + Bias & Band Gap - VDD Hys. = 3.45V 29V + 12.45V + 10µs De-Bounce - + 27V OVP Figure 4. VDD and UVLO Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A In RT7300A, the Ton is implemented by a constant ICOMP_Sourcing Current Max. Sourcing Current current charging a capacitor till VComp threshold voltage is reached. Therefore, the TON is a function of >1mA Vcomp. TON = UV OV 0.25V 1.35V INV 1.5V 1.65V GM =1 00 µA /V Cramp VComp Iramp (4) Then, the VComp can be derived from equation (3) and (4). Cramp VComp 4 P i LPFC = 2 Iramp VIN_pk VComp = 4 P i LPFC Iramp Cramp VIN_pk 2 (5) According to equation (5), the VComp is reversely proportional to the squared input voltage so that the VComp has a large variation for the change of line Figure 6. Non-linear GM voltage between high and low input voltages. This variation will impact TON, Burst mode entry level and Feed-Forward Compensation The FF pin is an input pin with high impedance to detect the line input voltage shown as Figure 7. A proper voltage divider should be applied to sense the line voltage after bridge diode rectifier. Since the FF voltage is proportional to the line input voltage, it provides a feed-forward signal to compensate the loop loop bandwidth. bandwidth for high line and low line input conditions. VComp (FF) = In order to compensate the variation, the Iramp is designed to be proportional to the squared input voltage shown as equation (6). Iramp (Vpk ) = k VIN_pk 2 gmramp (6) 2 P i LPFC gmramp Cramp (7) VCSIN When k = 0.5, the VComp is compensated to be RFF1 RFF2 FF Feed- Forward & THD Optimize Ramp Generator CFF 1.5V + GM - + PWM OFF proportional to the power only. So, the Ton will be stable to support good power factor for high and low line voltage conditions. - Ramp Generator INV COMP The RT7300A provides constant on-time voltage mode control to achieve near unity power factor for the CRM Figure 7. FF Detection Circuit The constant on-time, TON, can be derived from the following equations. P i = 1 VIN_pk IL_pk 4 IL_pk = VIN_pk TON LPFC boost converters. Figure 8 shows the Ramp Generator with Feed-Forward compensation and THD optimization circuit for the constant on-time operation. 2 VIN_pk VIN_pk P i = 1 VIN_pk TON = 1 TON 4 LPFC 4 LPFC 4 P i LPFC TON = (3) VIN_pk 2 Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 May 2014 is a registered trademark of Richtek Technology Corporation www.richtek.com 5 RT7300A FF 2 k x V FF gmramp + GM Cramp D′ DOUT N1 VOUT+ Q1 NAUX COUT VOUT- Ramp Generator 1.5V INV + + GM - PWM OFF + RZCD Upper Clamp - ZCD VZCDA 1.6V - VZCDT 1V + S Q Dmag R Q - COMP Figure 8. Ramp Generator Lower Clamp The charging current of ramp generator is modulated following the squared FF voltage with line voltage compensation and the THD optimization scheme is - 0.25V/1V Disable + Figure 9. ZCD Block Diagram implemented to compensate the harmonic distortion when the converter is operated in DCM. The RT7300A provides shutdown function to save power consumption in standby mode. When the ZCD pin is pulled lower than 250mV, the gate driver will be ZCD and Enable Function turned off and operate in standby mode with low quiescent current less than 600µA. Once the ZCD pin is released, the controller will be activated. In CRM operation, when the power switch turns on, the inductor current increases linearly to the peak value. When the power switch turns off, the inductor current The RT7300A also provides ZCD time-out detection decreases linearly to zero. The zero current can be detected by the ZCD pin with the auxiliary winding of function. If the controller runs at maximum frequency and there is no ZCD signal being detected after 4s Boost inductor. delay time, the PWM will be turned on for ZCD time-out detection. Figure 9 and Figure 10 show the ZCD block diagram and related waveforms. The ZCD block diagram provides zero current detection, voltage clamp and shutdown control functions. When the inductor current decreases to zero, the auxiliary winding voltage will turn from high to low. Once the ZCD voltage decreases to the VZCDT threshold, the controller will generate a signal for gate driver. The hysteresis voltage between the threshold VZCDA and VZCDT is designed to avoid mis-triggering. In order to prevent over voltage stress, the ZCD pin voltage is clamped at VZCDH if the input voltage is too high from the auxiliary winding and the ZCD pin voltage is clamped at VZCDL if the input voltage is lower than zero. VAUX ILPFC GD VZCD Upper Clamp VZCDA VZCDT VZCD_en VZCD_dis Lower Clamp Figure 10. ZCD Related Waveforms Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A Absolute Maximum Ratings (Note 1) Supply Voltage, VDD ------------------------------------------------------------------------------------------------ 0.3V to 30V Gate Driver Output, GD --------------------------------------------------------------------------------------------- 0.3V to 20V Other Pins -------------------------------------------------------------------------------------------------------------- 0.3V to 6V Power Dissipation, PD @ TA = 25C SOP-8 ------------------------------------------------------------------------------------------------------------------- 0.625W Package Thermal Resistance (Note 2) SOP-8, JA ------------------------------------------------------------------------------------------------------------- 160C/W Junction Temperature ----------------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260C Storage Temperature Range -------------------------------------------------------------------------------------- 65C to 150C ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------- 2kV MM (Machine Model) ------------------------------------------------------------------------------------------------ 200V Recommended Operating Conditions (Note 4) Supply Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V Junction Temperature Range ------------------------------------------------------------------------------------- 40C to 125C Electrical Characteristics (VDD = 15V, TA = 25C, unless otherwise specification) Parameter Symbol Test Conditions Min Typ Max Unit 25.5 27 28.5 V -- 10 -- s VDD Section VDD OVP Threshold Voltage VOVP VDD OVP De-bounce Time VDD On Threshold Voltage VON_TH VDD Off Threshold Voltage VOFF_TH 8 9 10 V Zener Voltage 29 -- -- V Operating Supply Current VZ IDD_OP IZCD = 0, @ GATE = open, 70kHz -- -- 2.5 mA Quiescent Current IQ Turn on in burst mode @ gate open -- -- 1.7 mA PFC is disabled -- -- 0.6 mA IDD_ST Before VON_TH -- -- 20 A Upper Clamp Voltage VZC_DH IZCD = 2.5mA 4.5 4.8 5.5 V Lower Clamp Voltage VZC_DL IZCD = 2.5mA 0.3 0.65 -- V Arming Voltage VZC_DA (Note 5) -- 1.6 -- V Trigger Voltage Delay Time Between Trigger Point and Gate Turn On Sourcing Current Capability VZC_DT (Note 5) -- 1 -- V -- 100 170 ns 2.5 -- 6.5 mA 2.5 -- -- mA Standby Current Start-Up Current 11.45 12.45 13.45 V ZCD Section Sinking Current Capability Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 May 2014 is a registered trademark of Richtek Technology Corporation www.richtek.com 7 RT7300A Parameter Disable Voltage Symbol VZCD_ DIS Restart Voltage VZCD_ EN Test Conditions Min Typ Max Unit -- -- 250 mV 1 -- -- V 30 75 100 A -- -- 1 A 1.47 1.5 1.53 V -- -- 1 A If |VERROR| < 0.25V 80 100 120 A/V Otherwise -- 1 -- mA 4.25 -- -- V INV OVP Threshold Voltage 1.55 1.65 1.75 V INV UVP Threshold Voltage 0.18 0.25 0.32 V -- 20 -- s Pull-High Current After Disable FF Section Input Bias Current IBIAS Leakage Current of FF Pin VREF Including Offset, Full VDD Range, TA = 25C GM Section Non-Inverting Input Reference INV Bias Current Transconduction gm Non-linear Gm COMP Maximum Voltage VCOMP_OP PWM Section INV OVP/UVP De-bounce Time Burst Mode Entry Level High VBurst_H Measure at COMP Pin 1.85 2.15 2.45 Level Low VBurst_L Measure at COMP Pin 1.75 2.05 2.35 1.5 2 4 s -- 70 -- mV/S De-bounce Time of Burst Mode V Ramp Slope VFF = 0.8V Minimum On-Time TON(MIN)_PFC = 3pF x 2.5V / (IZCD x 0.02), IZCD = 75A 4.4 5.4 6.4 s LEB + Delay (Note 6) 240 400 570 ns 0.74 0.85 0.96 V Current Sense Section Leading Edge Blanking Time TLEB_PFC Current Sense Threshold Voltage VCS_PFC Gate Driver Section Rising Time TR CL = 1nF -- 40 80 ns Falling Time TF CL = 1nF -- 30 70 ns VDD = 25V -- 13 -- V -- 12 -- k Gate Output Clamping Voltage VCLAMP Internal Pull Low Resistor Oscillator Section Valley Mask Time TMASK 7 8.5 10 s Duration of Starter TSTART 75 130 300 s Maximum On-Time TON(MAX)_PFC Maximum TON(MAX)_PFC -- 50 -- s Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability Note 2. JA is measured at TA = 25C on a low effective thermal conductivity single-layer test board per JEDEC 51-3. Note 3. Devices are ESD sensitive. Handling precaution is recommended Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by Design. Note 6. Leading edge blanking time and internal propagation delay time is guaranteed by design. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A Typical Application Circuit Boost PFC Pre-Regulator DS F1 BD LPFC DOUT Line VOUT+ RG Q1 CSIN COUT RCS RNTC Neutral VOUT7 GD RZCD 5 ZCD INV CAUX 8 DVDD CFF Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 May 2014 CCS ROUT1 1 VDD CINV COMP 3 RFF2 4 ROUT2 CVDD RSTART RFF1 CS RT7300A RAUX DZ RS 2 RCOMP FF CCOMP2 CCOMP1 GND 6 is a registered trademark of Richtek Technology Corporation www.richtek.com 9 RT7300A Typical Operating Characteristics Transconduction vs. Temperature 102 1.52 100 Transconduction (µA/V)1 Non-inverting Reference (V) Non-inverting Reference vs. VDD 1.53 1.51 1.50 1.49 1.48 98 VDD = 10V VDD = 26V 96 VDD = 16V 94 92 90 VCOMP = 0.5V 1.47 88 9 14 19 24 29 -50 -25 0 VDD (V) Transconduction vs. Temperature 50 0 100 125 100 Non-linear Region -500 98 I COMP (µA) 1 VDD = 10V VDD = 26V 96 VDD = 16V 94 -1000 VDD = 26V, TA = 25°C -1500 VDD = 10V, TA = 25°C VDD = 26V, TA = 125°C VDD = 10V, TA = 125°C -2000 92 VDD = 26V, TA = 40°C VCOMP = 4V VDD = 10V, TA = 40°C -2500 90 -50 -25 0 25 50 75 100 0 125 1 2 3 4 5 VCOMP (V) Temperature (°C) ICOMP vs. VCOMP (Sinking) Maximum COMP Voltage vs. VDD 4.440 1800 Maximum COMP Voltage (V)1 Non-linear Region 1500 I COMP (µA) 1 75 ICOMP vs. VCOMP (Sourcing) 102 Transconduction (µA/V)1 25 Temperature (°C) 1200 VDD = 26V, TA = 25°C 900 VDD = 10V, TA = 25°C VDD = 26V, TA = 125°C 600 VDD = 10V, TA = 125°C VDD = 26V, TA = 40°C 300 VDD = 10V, TA = 40°C 4.435 4.430 4.425 4.420 4.415 4.410 0 0 1 2 3 4 VCOMP (V) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 5 8 10.5 13 15.5 18 20.5 23 25.5 28 VDD (V) is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A Maximum COMP Voltage vs. Temperature Burst Mode Entry Level vs. VDD 2.18 Burst Mode Entry Level (V)1 Maximum COMP Voltage (V)1 4.43 4.42 4.41 4.40 4.39 4.38 4.37 VBurst_H 2.16 2.14 2.12 2.10 2.08 VBurst_L 2.06 VDD = 10V 2.04 4.36 -50 -25 0 25 50 75 100 8 125 13 18 23 28 VDD (V) Temperature (°C) On-Time vs. COMP Voltage On-Time vs. Feed-Forward Voltage 50 3.5 45 3.0 2.5 On-Time (µs) On-Time (µs) 40 2.0 1.5 35 30 25 20 15 1.0 10 0.5 VCOMP = 4V 5 FF = 2.8V 0.0 0 1 2 3 4 COMP Voltage (V) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 VCOMP = 3V 0 May 2014 5 0 0.5 1 1.5 2 2.5 3 Feed-Forward Voltage (V) is a registered trademark of Richtek Technology Corporation www.richtek.com 11 RT7300A Application Information where Vinac_min is the minimum input voltage. Note that the start-up resistor must have adequate voltage rating for reliability. 2 resistors in series can be applied for most of applications. Start-Up Circuit Design VCSIN BD Line CSIN Neutral IST RSTART IDD_ST VDD IchVDD RT7300A DVDD CVDD For example, the system required start-up time is 3sec, Vinac_min = 75V and maximum IDD_ST = 20A. If CVDD AUX. = 22F is selected and the leakage current of CVDD can be ignored, the start-up resistor should be less than 772k. Ileakage GND The capacitor CFF is applied to filter out the input ripple voltage. The corner frequency should be lower than line frequency (f line). If the FF pin voltage is not flat, the PF and THD performance will be degraded. Figure 11. Start-Up Circuit tstart VDD VON_TH 1 < 0.1 fline 2 (RFF1 // RFF2 ) CFF VOFF_TH (10) Boost Inductance Design Differ from the traditional transient mode PFC, the Supplied by IST IDD IDD_ST ~20µA Supplied by AUX. and IST Boost inductor design is based on the RT7300A internal parameters and the parameter “S”. ~ mA S= Figure 12. Start-Up Waveforms of VDD and IDD Figure 11 and Figure 12 show the equivalent start-up circuit and VDD waveform during start-up. In general, the start-up time (tstart) is required from system specification. The charging current (IchVDD) can be RFF1 RFF2 RFF2 (11) Assume the maximum input power is Pin, the inductance of the Boost inductor can be derived as following equations. estimated by the following equation. CVDD VON_TH IchVDD = tstart (8) where CVDD is the capacitor connected between VDD IL_pk = 2 = Pin 2 VIN(MIN) 2 VIN(MIN) LPFC and GND, VON_TH is the power on threshold (12.45V typ.). The start-up resistor (Rstart) connected between VCSIN and VDD should be able to support the charging current (IchVDD), start-up current (IDD_ST) and leakage current (Ileakage) of CVDD before the VDD is supported by the auxiliary winding. The maximum start-up resistance can be calculated by the equation (11). RStart = 2 Vinac_min IDD_ST IchVDD Ileakage Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 (9) LPFC = VCOMP CRamp 2 VIN(MIN) 2 0.5 gmRamp S 2 2 m VCOMP_OP CRamp S2 8 Pin gmRamp 2 = m S 13.63 Pin (μH) (12) where “m” is the ratio of VComp/VComp_op which is the derating factor of the maximum power. It's suggested to use 0.6 to 0.9 for the m factor. is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A Current Limit Setting Output Capacitor Selection The maximum current of the power MOSFET is limited The hold-up time and output voltage (VOUT) are the by the current sense resistor between the CS pin and GND. The threshold voltage at CS pin is 0.85V typically. The current sense resistor can be calculated by the equation (15) with the peak current of MOSFET. major requirements for determining the output capacitance. The narrow VOUT range can improve the efficiency of DC/DC converter in next power stage. Lower ESR can reduce the power loss of PFC converter and get longer lifetime. RCS = 0.85V 80% IL_pk (13) COUT(MIN) = Zero Current Detection (17) 2 2 VOUT VOUT(MIN) IC(RMS) = The zero current of inductor is detected from the auxiliary winding shown as typical application circuit. The RZCD is used to limit the current into ZCD pin to be lower than 2.5mA. Thus, the RZCD is determined by the equation as below. VOUT RZCD > N 2.5mA 2 PIN THoldup (14) where VOUT is the output voltage of the PFC converter and N is the turn ratio of auxiliary winding and Boost inductor. 2 IL_pk 2 VIN(MAX) PIN VOUT VOUT 2 2 ac RMS load current (18) Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : MOSFET Selection PD(MAX) = (TJ(MAX) TA) / JA The RT7300A is designed to operate using an external where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction to N-channel power MOSFET. Important parameters for the power MOSFET are breakdown voltage (BVDSS), threshold voltage (VGS_TH), on-resistance (RDS(ON)), total gate charge (Qg) and maximum current (ID(MAX)). The gate driver voltage is from VDD and clamped under 13V typically. Lower Qg characteristics results in lower power losses and lower RDS(ON) results in higher efficiency. For high voltage application, it is important to select a device with low gate charge and balance the power consumption between switching loss and conduction loss. Since there is no reverse recovery loss of diode when converter operates in CRM, the diode choosing is based on reverse voltage, forward current and switching speed. 2 VIN(MIN) VOUT VD(PK) = VOUT junction to ambient thermal resistance, JA, is layout dependent. For SOP-8 package, the thermal resistance, JA, is 160C/W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : (15) The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, JA. The derating curve in Figure 13 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. (16) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 For recommended operating condition specifications, the maximum junction temperature is 125C. The PD(MAX) = (125C 25C) / (160C/W) = 0.625W for SOP-8 package Diode Selection ID(RMS) = IL_pk ambient thermal resistance. May 2014 is a registered trademark of Richtek Technology Corporation www.richtek.com 13 RT7300A are high frequency current loops. The path(3) from GD pin, MOSFET, RCS to ground is also a high frequency current loop. They must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as IC control circuit paths, especially. Besides, the path(4) between MOSFET ground(b) and IC ground(d) is recommended to be as short as possible, too. It is good for reducing noise, output ripple and EMI issue to separate ground traces of input capacitor(a), MOSFET(b), auxiliary winding(c) and IC control Figure 13. Derating Curve of Maximum Power circuit(d). Finally, connect them together on input Dissipation capacitor ground(a). The areas of these ground traces should be kept large. Layout Considerations A proper PCB layout can abate unknown noise interference and EMI issue in the switching power supply. Please refer to the guidelines when designing a highly recommended. The capacitors CINV and CCS should be placed as close to controller as possible. PCB layout for switching power supply. Placing bypass capacitor for abating noise on IC is In addition, apply sufficient copper area at the anode The current path(1) from input capacitor, inductor, and cathode terminal of the diode for heat-sinking. It MOSFET, RCS return to input capacitor and the is recommended to apply a larger area at the quiet current path(2) from input capacitor, inductor, output cathode terminal. A large anode area will induce diode, output filter capacitor return to input capacitor high-frequency radiated EMI. F1 Line VOUT+ (c) RNTC (1) GD (2) Neutral VOUTZCD CS (a) RCS CCS (3) RT7300A Input capacitor Ground(a) (4) GND VDD (b) (d) Trace Trace Trace INV CINV IC Ground(d) Auxiliary Ground(c) MOSFET Ground(b) COMP FF Figure 14. PCB Layout Guide Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation DS7300A-00 May 2014 RT7300A Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS7300A-00 May 2014 is a registered trademark of Richtek Technology Corporation www.richtek.com 15