HFA1115 September 1998 File Number 3606.4 225MHz, Low Power, Output Limiting, Closed Loop Buffer Amplifier Features The HFA1115 is a high speed closed loop Buffer featuring both user programmable gain and output limiting. Manufactured on Intersil’s proprietary complementary bipolar UHF-1 process, the HFA1115 also offers a wide -3dB bandwidth of 225MHz, very fast slew rate, excellent gain flatness and high output current. • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ This buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overload recovery times. The limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The HFA1115 also allows for voltage gains of +2, +1, and -1, without the use of external resistors. Gain selection is accomplished via connections to the inputs, as described in the “Application Information” text. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. • Very Fast Slew Rate (AV = -1) . . . . . . . . . . . . . . 1135V/µs Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path, should a higher closed loop gain be needed at a future date. For Military product, refer to the HFA1115/883 data sheet. • User Programmable Output Voltage Limiting • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% • Differential Phase . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . . 225MHz • Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 7.1mA • High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA • Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V • User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors • Fast Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . <1ns • Standard Operational Amplifier Pinout Applications • Flash A/D Drivers • Video Cable Drivers • High Resolution Monitors • Professional Video Processing Pinout • Medical Imaging HFA1115 (PDIP, SOIC) TOP VIEW NC 1 350 • Video Digitizing Boards/Systems • Battery Powered Communications 350 8 VH _ + 7 V+ -IN 2 +IN 3 6 OUT V- 4 5 VL Ordering Information PART NUMBER (BRAND) Pin Descriptions NAME PIN NUMBER NC 1 No Connection -IN 2 Inverting Input +IN 3 Non-Inverting Input V- 4 Negative Supply VL 5 Lower Output Limit OUT 6 Output V+ 7 Positive Supply VH 8 Upper Output Limit 1 DESCRIPTION TEMP. RANGE (oC) PACKAGE PKG. NO. HFA1115IP -40 to 85 8 Ld PDIP E8.3 HFA1115IB (H1115I) -40 to 85 8 Ld SOIC M8.15 HFA11XXEVAL High Speed Op Amp DIP Evaluation Board CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HFA1115 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Output Current (Note 2) . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .600V Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 5V to 10V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current should not exceed 30mA for maximum reliability. VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified Electrical Specifications (NOTE 3) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS A 25 - 2 10 mV A Full - 3 15 mV B Full - 22 70 µV/oC ∆VCM = ±1.8V A 25 42 45 - dB ∆VCM = ±1.8V A 85 40 44 - dB ∆VCM = ±1.2V A -40 40 45 - dB ∆VPS = ±1.8V A 25 45 49 - dB ∆VPS = ±1.8V A 85 43 48 - dB ∆VPS = ±1.2V A -40 43 48 - dB A 25 - 1 15 µA A Full - 3 25 µA B Full - 30 80 nA/oC A 25 - 0.5 1 µA/V A Full - - 3 µA/V TEST CONDITIONS PARAMETER INPUT CHARACTERISTICS Output Offset Voltage Average Output Offset Voltage Drift Common-Mode Rejection Ratio Power Supply Rejection Ratio Non-Inverting Input Bias Current Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity ∆VPS = ±1.25V Non-Inverting Input Resistance ∆VCM = ±1.8V A 25 0.8 1.1 - MΩ ∆VCM = ±1.8V A 85 0.5 1.4 - MΩ ∆VCM = ±1.2V A -40 0.5 1.3 - MΩ Inverting Input Resistance C 25 280 350 420 Ω Input Capacitance C 25 - 1.6 - pF Input Voltage Common Mode Range (Implied by VIO CMRR and +RIN Tests) A 25, 85 ±1.8 ±2.4 - V A -40 ±1.2 ±1.7 - V Input Noise Voltage Density (Note 4) f = 100kHz B 25 - 7 - nV/√Hz Non-Inverting Input Noise Current Density (Note 4) f = 100kHz B 25 - 3.6 - pA/√Hz 2 HFA1115 VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications (NOTE 3) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS A 25 -0.98 -0.996 -1.02 V/V A Full -0.975 -1.000 -1.025 V/V A 25 0.98 0.992 1.02 V/V A Full 0.975 0.993 1.025 V/V A 25 1.96 1.988 2.04 V/V A Full 1.95 1.990 2.05 V/V AV = -1 B 25 - 225 - MHz AV = +1, +RS = 620Ω B 25 - 200 - MHz AV = +2 B 25 - 225 - MHz AV = -1 B 25 - 157 - MHz AV = +1, +RS = 620Ω B 25 - 140 - MHz AV = +2 B 25 - 125 - MHz AV = +1, +RS = 620Ω B 25 - ±0.1 - dB AV = +2 B 25 - ±0.04 - dB AV = +1, +RS = 620Ω B 25 - ±0.25 - dB AV = +2 B 25 - ±0.1 - dB AV = -1, RL = 100Ω A 25 ±3.0 ±3.2 - V A Full ±2.8 ±3.0 - V A 25, 85 50 55 - mA A -40 28 42 - mA B 25 - 90 - mA TEST CONDITIONS PARAMETER TRANSFER CHARACTERISTICS Gain AV = -1 AV = +1 AV = +2 AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Note 4) Full Power Bandwidth (VOUT = 5VP-P at AV = +2/-1, 4VP-P at AV = +1, Note 4) Gain Flatness (to 25MHz, VOUT = 0.2VP-P, Note 4) Gain Flatness (to 50MHz, VOUT = 0.2VP-P, Note 4) OUTPUT CHARACTERISTICS Output Voltage Swing (Note 4) Output Current (Note 4) AV = -1, RL = 50Ω Output Short Circuit Current Output Resistance (Note 4) DC, AV = +2 B 25 - 0.07 - Ω Second Harmonic Distortion (AV = +2, VOUT = 2VP-P) 10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc Third Harmonic Distortion (AV = +2, VOUT = 2VP-P) 10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc TRANSIENT RESPONSE AV = +2, Unless Otherwise Specified Rise and Fall Times (VOUT = 0.5VP-P, Note 4) Rise Time B 25 - 1.7 - ns Fall Time B 25 - 1.9 - ns Overshoot (VOUT = 0.5VP-P, VIN tRISE = 2.5ns) +OS B 25 - 0 - % -OS B 25 - 0 - % Slew Rate (VOUT = 5VP-P, AV = -1) +SR B 25 - 1660 - V/µs -SR (Note 5) B 25 - 1135 - V/µs +SR B 25 - 1125 - V/µs -SR (Note 5) B 25 - 800 - V/µs Slew Rate (VOUT = 4VP-P, AV = +1, +RS = 620Ω) 3 HFA1115 VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications (NOTE 3) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS +SR B 25 - 1265 - V/µs -SR (Note 5) B 25 - 870 - V/µs To 0.1% B 25 - 23 - ns To 0.05% B 25 - 33 - ns To 0.02% B 25 - 45 - ns Differential Gain f = 3.58MHz, AV = +2, RL = 150Ω B 25 - 0.02 - % Differential Phase f = 3.58MHz, AV = +2, RL = 150Ω B 25 - 0.03 - Degrees TEST CONDITIONS PARAMETER Slew Rate (VOUT = 5VP-P, AV = +2) Settling Time (VOUT = +2V to 0V step, Note 4) VIDEO CHARACTERISTICS OUTPUT LIMITING CHARACTERISTICS AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified Limit Accuracy (Note 4) VIN = ±1.6V, AV = -1 A Full -125 -70 125 mV Overdrive Recovery Time (Note 4) VIN = ±1V B 25 - 0.8 - ns Negative Limit Range B 25 -5.0 to +2.5 V Positive Limit Range B 25 -2.5 to +5.0 V Limit Input Bias Current A Full - 85 200 µA Limit Input Bandwidth C 25 - 100 - MHz Power Supply Range C 25 4.5 - 5.5 ±V Power Supply Current (Note 4) A 25 6.6 6.9 7.1 mA A Full - 7.1 7.3 mA POWER SUPPLY CHARACTERISTICS NOTE: 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. See Typical Performance Curves for more information. 5. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details. Application Information Relevant Application Notes The following Application Notes pertain to the HFA1115: • AN9653-Use and Application of Output Limiting Amplifiers • AN9752-Sync Stripper and Sync Inserter for Composite Video These publications may be obtained from Intersil’s web site (http://www.intersil.com) or via our AnswerFax system. HFA1115 Advantages The HFA1115 features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. Implementing a gain of 2, cable driver with this IC eliminates 4 the two gain setting resistors, which frees up board space for termination resistors. Like most newer high performance amplifiers, the HFA1115 is a current feedback amplifier (CFA). CFAs offer high bandwidth and slew rate at low supply currents, but can be difficult to use because of their sensitivity to feedback capacitance and parasitics on the inverting input (summing node). The HFA1115 eliminates these concerns by bringing the gain setting resistors on-chip. This yields the optimum placement and value of the feedback resistor, while minimizing feedback and summing node parasitics. Because there is no access to the summing node, the PCB parasitics do not impact performance at gains of +2 or -1 (see “Unity Gain Considerations” for discussion of parasitic impact on unity gain performance). HFA1115 frequencies, which prevents the increased output offset voltage but delivers less gain flatness. The HFA1115’s closed loop gain implementation provides better gain accuracy, lower offset and output impedance, and better distortion compared with open loop buffers. Closed Loop Gain Selection This “buffer” operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the ±inputs. Applying the input signal to +IN and floating -IN selects a gain of +1 (see next section for layout caveats), while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded through a 50Ω resistor. The table below summarizes these connections: CONNECTIONS GAIN (AV) +INPUT (PIN 3) -INPUT (PIN 2) -1 50Ω to GND Input +1 Input NC (Floating) +2 Input GND Unity gain selection is accomplished by floating the -Input of the HFA1115. Anything that tends to short the -Input to GND, such as stray capacitance at high frequencies, will cause the amplifier gain to increase toward a gain of +2. The result is excessive high frequency peaking, and possible instability. Even the minimal amount of capacitance associated with attaching the -Input lead to the PCB results in approximately 3dB of gain peaking. At a minimum this requires due care to ensure the minimum capacitance at the -Input connection. . TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS PEAKING (dB) BW (MHz) +SR/-SR (V/µs) ±0.1dB GAIN FLATNESS (MHz) Remove Pin 2 2.5 400 1200/850 20 +RS = 620Ω 0.6 170 1125/800 25 +RS = 620Ω and Remove Pin 2 0 165 1050/775 65 Short Pins 2, 3 0 200 875/550 45 100pF cap. between pins 2, 3 0.2 190 900/550 19 Table 1 lists five alternate methods for configuring the HFA1115 as a unity gain buffer, and the corresponding performance. The implementations vary in complexity and involve performance trade-offs. The easiest approach to implement is simply shorting the two input pins together, and applying the input signal to this common node. The amplifier bandwidth drops from 400MHz to 200MHz, but excellent gain flatness is the benefit. Another drawback to this approach is that the amplifier input noise voltage and input offset voltage terms see a gain of +2, resulting in higher noise and output offset voltages. Alternately, a 100pF capacitor between the inputs shorts them only at high 5 Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND. Pulse Undershoot and Asymmetrical Slew Rates Unity Gain Considerations APPROACH Another straightforward approach is to add a 620Ω resistor in series with the positive input. This resistor and the HFA1115 input capacitance form a low pass filter which rolls off the signal bandwidth before gain peaking occurs. This configuration was employed to obtain the datasheet AC and transient parameters for a gain of +1. The HFA1115 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figures 9, 13, and 17). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (see Figures 9, 13, and 17), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (see Figures 7, 11, and 15). PC Board Layout This amplifier’s frequency response depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. For unity gain applications, care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input. At higher frequencies this capacitance tends to short the -INPUT to GND, resulting in a closed loop gain which increases with frequency. This causes excessive high frequency peaking and potentially other problems as well. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. HFA1115 Driving Capacitive Loads BOARD SCHEMATIC (MODIFIED) Capacitive loads, such as an A/D input, or an improperly terminated transmission line degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. R1 = ∞ (AV = +1) or 0Ω (AV = +2) VH R1 50Ω 1 8 2 7 0.1µF 10µF +5V 50Ω IN 10µF 3 6 4 5 0.1µF OUT VL GND GND -5V TOP LAYOUT VH RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 200MHz (AV = +1). By decreasing RS as CLincreases (as illustrated by the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. For example, at AV = +1, RS = 50Ω, CL = 22pF, the overall bandwidth is 185MHz, but the bandwidth drops to 50MHz at AV = +1, RS = 15Ω, CL = 330pF. 1 +IN OUT V+ VL VGND BOTTOM LAYOUT 50 45 40 35 RS (Ω) 30 25 20 AV = +1 15 FIGURE 2. EVALUATION BOARD SCHEMATIC (AFTER MODIFICATION FOR BUFFER USE) AND LAYOUT AV = +2 10 5 Limiting Operation 0 0 40 80 120 160 200 240 280 320 360 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE Evaluation Board The performance of the HFA1115 may be evaluated using the HFA11XX Evaluation Board, slightly modified as follows: 1. 1. Remove the 510Ω feedback resistor (R2), and leave the connection open. 2. 2. a. For AV = +1 evaluation, remove the 510Ω gain setting resistor (R1), and leave pin 2 floating. b. For AV = +2, replace the 510Ω gain setting resistor with a 0Ω resistor to GND. The layout and modified schematic of the board are shown in Figure 2. To order evaluation boards (Part Number HFA11XXEVAL), please contact your local sales office. 6 General The HFA1115 features user programmable output clamps to limit output voltage excursions. Limiting action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5) of the amplifier. VH sets the upper output limit, while VL sets the lower limit level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL (± the limit accuracy), respectively. The low input bias currents of the limit pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs. Limit Circuitry Figure 3 shows a simplified schematic of the HFA1115 input stage, and the high limit (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of: ISLEW = (V-IN - VOUT)/RF + V-IN/RG HFA1115 V+ QP3 QP4 QN2 QP1 +IN R1 Z ILIMIT +1 VV+ 200Ω QN1 QN5 QP2 VH QN6 QP6 QN3 V- 50kΩ QN4 QP5 V-IN RG = 350Ω (INTERNAL) RF = 350Ω (INTERNAL) VOUT -IN FIGURE 3. HFA1115 SIMPLIFIED VH LIMIT CIRCUITRY This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no limiting is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches its quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. Tracing the path from VH to Z illustrates the effect of the limit voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5. QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5’s base voltage + 2VBE (QP5 and QN5). Thus, QP5 limits node Z whenever Z reaches VH. R1 provides a pull-up network to ensure functionality with the limit inputs floating. A similar description applies to the symmetrical low limit circuitry controlled by VL. When the output is limited, the negative input continues to source a slewing current (ILimit) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while limiting, because the -IN current is always mirrored onto the high impedance node. The limiting current is calculated as: ILIMIT = (V-IN - VOUT LIMITED)/RF + V-IN/RG. As an example, a unity gain circuit with VIN = 2V, and VH = 1V, would have ILIMIT = (2V - 1V)/350Ω + 2V/∞ = 2.8mA (RG = ∞ because -IN is floated for unity gain applications). Note that ICC increases by ILIMIT when the output is limited. Limit Accuracy The limited output voltage will not be exactly equal to the voltage applied to VH or VL . Offset errors, mostly due to VBE mismatches, necessitate a limit accuracy parameter which is 7 found in the device specifications. Limit accuracy is a function of the limiting conditions. Referring again to Figure 3, it can be seen that one component of limit accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ILimit . VBE increases as ILIMIT increases, causing the limited output voltage to increase as well. ILIMIT is a function of the overdrive level ((AV x VIN - VLIMIT) / VLIMIT), so limit accuracy degrades as the overdrive increases (see Figures 28 and 29). For example, accuracy degrades from -20mV to +30mV when the overdrive increases from 100% to 200% (AV = +2, VH = 500mV). Consideration must also be given to the fact that the limit voltages have an effect on amplifier linearity. The “Linearity Near Limit Voltage” curves, Figures 30 and 31, illustrate the impact of several limit levels on linearity. Limit Range Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HFA1115 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won’t be a DC output voltage from an AC input signal. A 150mV - 200mV AC signal will still be present at the output. Recovery from Overdrive The output voltage remains at the limit level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VLIMIT/AV) the amplifier returns to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. Overdrive recovery time is defined as the difference between the amplifier’s propagation delay exiting limiting and the amplifier’s normal propagation delay, and it is a strong function of the overdrive level. Figure 32 details the overdrive recovery time for various limit and overdrive levels Benefits of Output Limiting The plots of “Pulse Response Without Limiting” and “Pulse Response With Limiting” (Figures 4 and 5) highlight the advantages of output limiting. Besides the obvious benefit of constraining the output swing to a defined range, limiting the output excursions also keeps the output transistors from saturating, which prevents unwanted saturation artifacts from distorting the output signal. Output limiting also takes advantage of the HFA1115’s ultra-fast overdrive recovery time, reducing the recovery time from 2.5ns to 0.5ns, based on the amplifier’s normal propagation delay of 1.2ns. HFA1115 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified AV = +2 AV = +2 2.0 4.0 2.0 3.0 1.5 IN 1.0 0.5 0 0 -0.5 -1.0 -1.0 -2.0 2.0 1.0 OUT 1.0 0.5 0 0 -1.0 -0.5 -1.0 VH = +2.0V, VL = 0V TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 4. PULSE RESPONSE WITHOUT LIMITING FIGURE 5. PULSE RESPONSE WITH LIMITING 3.0 300 AV = +2 250 2.5 200 2.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = +2 150 100 50 0 -50 1.5 1.0 0.5 0 -0.5 -100 -1.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 6. SMALL SIGNAL POSITIVE PULSE RESPONSE FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE 2.0 200 AV = +2 150 1.5 100 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = +2 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) FIGURE 8. SMALL SIGNAL BIPOLAR PULSE RESPONSE 8 TIME (5ns/DIV.) FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE OUTPUT VOLTAGE (V) 2.0 INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUT 1.0 OUTPUT VOLTAGE (V) IN 1.5 HFA1115 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 300 AV = +1 2.5 200 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 250 3.0 AV = +1 150 100 50 0 -50 2.0 1.5 1.0 0.5 0 -0.5 -100 -1.0 TIME (5ns/DIV.) FIGURE 10. SMALL SIGNAL POSITIVE PULSE RESPONSE TIME (5ns/DIV.) FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE 200 AV = +1 1.5 100 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 150 2.0 AV = +1 50 0 -50 -100 -150 1.0 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) FIGURE 12. SMALL SIGNAL BIPOLAR PULSE RESPONSE FIGURE 13. LARGE SIGNAL BIPOLAR PULSE RESPONSE 3.0 300 AV = -1 AV = -1 250 2.5 200 2.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) TIME (5ns/DIV.) 150 100 50 0 -50 1.5 1.0 0.5 0 -0.5 -100 -1.0 TIME (5ns/DIV.) FIGURE 14. SMALL SIGNAL POSITIVE PULSE RESPONSE 9 TIME (5ns/DIV.) FIGURE 15. LARGE SIGNAL POSITIVE PULSE RESPONSE HFA1115 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 2.0 200 AV = -1 150 1.5 100 1.0 OUTPUT VOLTAGE (V) 50 0 -50 -100 0.5 0 -0.5 -1.0 -1.5 -150 -200 -2.0 TIME (5ns/DIV.) TIME (5ns/DIV.) 0 -3 AV = +2 -6 PHASE AV = -1 0 90 AV = -1 180 270 AV = +1 360 AV = +2 1 10 100 FREQUENCY (MHz) PHASE 0 VOUT = 1VP-P 90 180 270 360 VOUT = 1VP-P VOUT = 4VP-P 10 100 FREQUENCY (MHz) 3 AV = -1 1000 PHASE 0 -3 VOUT = 2.5VP-P PHASE 0 90 180 270 360 VOUT = 1VP-P GAIN -6 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P VOUT = 4VP-P FIGURE 19. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES VOUT = 2.5VP-P -6 VOUT = 2.5VP-P -6 VOUT = 4VP-P VOUT = 2.5VP-P GAIN (dB) 0 -3 1 GAIN -3 0 PHASE (DEGREES) GAIN (dB) AV = +1 VOUT = 1VP-P GAIN 1000 FIGURE 18. FREQUENCY RESPONSE 3 AV = +2 3 PHASE (DEGREES) GAIN FIGURE 17. LARGE SIGNAL BIPOLAR PULSE RESPONSE NORMALIZED GAIN (dB) AV = +1 VOUT = 200mVP-P 3 NORMALIZED PHASE (DEGREES) NORMALIZED GAIN (dB) FIGURE 16. SMALL SIGNAL BIPOLAR PULSE RESPONSE VOUT = 4VP-P VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 0 90 180 270 360 FREQUENCY (MHz) 10 100 FREQUENCY (MHz) FIGURE 20. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FIGURE 21. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES 1 10 100 10 1000 1 NORMALIZED PHASE (DEGREES) OUTPUT VOLTAGE (mV) AV = -1 1000 HFA1115 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 260 250 BANDWIDTH (MHz) NORMALIZED GAIN (dB) 240 AV = +1, VOUT = 4VP-P 3 0 -3 -6 230 200 10 AV = +1 190 AV = -1, VOUT = 5VP-P 1 AV = +2 210 AV = +2, VOUT = 5VP-P -9 AV = -1 220 180 100 170 -75 1000 -50 -25 0 FREQUENCY (MHz) FIGURE 22. FULL POWER BANDWIDTH -20 0.3 100 125 AV = +1 0.2 AV = -1 -30 -40 0.1 GAIN (dB) NORMALIZED GAIN (dB) 75 -10 AV = -1 0 -0.1 -0.2 -50 -60 AV = +1 -80 -0.3 -90 -0.4 -100 10 AV = +2 -70 AV = +2 1 100 1 10 FREQUENCY (MHz) 100 1000 FREQUENCY (MHz) FIGURE 24. GAIN FLATNESS FIGURE 25. REVERSE ISOLATION (S12) AV = +2 0.1 1K SETTLING ERROR (%) OUTPUT RESISTANCE (Ω) 50 FIGURE 23. -3dB BANDWIDTH vs TEMPERATURE VOUT = 200mVP-P 0.4 25 TEMPERATURE (oC) 100 10 1 0.1 0.01 0.05 0.025 0 -0.025 -0.05 -0.1 0.3 1 10 100 FREQUENCY (MHz) 1000 3 13 23 33 43 53 63 73 83 TIME (ns) FIGURE 26. OUTPUT RESISTANCE 11 FIGURE 27. SETTLING TIME RESPONSE 93 103 HFA1115 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 150 150 VL = -500mV 100 100 VH = +500mV LIMIT ACCURACY (mV) LIMIT ACCURACY (mV) AV = +2 AV = +2 50 VH = +1V 0 -50 VH = +2.0V -100 100 200 0 VL = -2.0V -50 -100 -150 0 VL = -1.0V 50 300 400 500 -150 0 100 200 OVERDRIVE (% OF VH) FIGURE 28. VH LIMIT ACCURACY vs OVERDRIVE 1.6 VL = -2V VH = +2V 1.4 1.2 VL = -1V VH = +1V 1.0 0.8 0.6 VL = -500mV 0.4 AV = +1 1.8 LINEARITY ERROR (%) 1.6 LINEARITY ERROR (%) 500 2.0 AV = +2 1.8 VH = +500mV VH = +2V VL = -2V 1.4 1.2 VL = -1V 1.0 VH = +1V 0.8 VL = -500mV 0.6 VH = +500mV 0.4 0.2 0.2 0 -2.0 -1.5 -1.0 -0.5 0.5 0 AV x VIN (V) 1.0 1.5 0 -2.0 2.0 FIGURE 30. LINEARITY NEAR LIMIT VOLTAGE 3.6 AV = +2 VL = -2V 3.5 2.5 VL = -1V VL = -3V VH = +1V 1.0 -0.5 0 0.5 AV x VIN (V) 1.0 1.5 2.0 AV = -1 |-VOUT| (RL = 100Ω) +VOUT (RL = 100Ω) 3.0 1.5 -1.0 3.5 VH = +2V 2.0 -1.5 FIGURE 31. LINEARITY NEAR LIMIT VOLTAGE OUTPUT VOLTAGE (V) OVERDRIVE RECOVERY TIME (ns) 400 FIGURE 29. VL LIMIT ACCURACY vs OVERDRIVE 2.0 4.0 300 OVERDRIVE (% OF VL) 3.4 3.3 3.2 |-VOUT| (RL = 50Ω) 3.1 +VOUT (RL = 50Ω) 3.0 2.9 2.8 0.5 2.7 VH = +3V 0 0 100 200 300 400 OVERDRIVE (% OF VH OR VL) FIGURE 32. OVERDRIVE RECOVERY TIME vs OVERDRIVE 12 2.6 -50 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 33. OUTPUT VOLTAGE vs TEMPERATURE 125 HFA1115 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 7.1 2.2 RISE/FALL TIMES (ns) FALL TIMES 6.9 6.8 6.7 4.0 AV = +2 2.1 7.0 AV = -1 2.0 1.9 AV = +1 AV = +2 RISE TIMES 4.5 5.0 5.5 6.0 6.5 7.0 AV = +1 1.6 -75 -50 -25 0 25 50 AV = +2 75 100 TEMPERATURE (oC) SUPPLY VOLTAGE (±V) FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 35. RISE AND FALL TIMES vs TEMPERATURE ENI 10 10 INI 1 0.1 1 1 10 FREQUENCY (kHz) 100 FIGURE 36. INPUT NOISE CHARACTERISTICS NOISE CURRENT (pA/√ Hz) 100 100 13 AV = -1 1.8 1.7 NOISE VOLTAGE (nV/√ Hz) SUPPLY CURRENT (mA) VOUT = 500mVP-P 125 HFA1115 Die Characteristics DIE DIMENSIONS: SUBSTRATE POTENTIAL (Powered Up): 59 mils x 58.2 mils x 19 mils 1500µm x 1480µm x 483µm Floating (Recommend Connection to V-) PASSIVATION: METALLIZATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ TRANSISTOR COUNT: Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ 89 Metallization Mask Layout HFA1115 -IN VH V+ OUT +IN V- VL All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 14