HFA3841 TM Data Sheet P RE L I M I NA R Y January 2000 File Number 4661.2 Wireless LAN Medium Access Controller Features The Intersil HFA3841 Wireless LAN Medium Access Controller is part of the PRISM® Enterprise 2.4GHz WLAN chip set. The HFA3841 directly interfaces with the Intersil HFA386x family of Baseband Processors, offering a complete end-toend chip set solution for wireless LAN products. Protocol and PHY support are implemented in firmware to allow custom protocol and different PHY transceivers. • IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps The HFA3841 is designed to provide maximum performance with minimum power consumption. External pin layout is organized to provide optimal PC board layout to all user interfaces. • Part of the Intersil PRISM Wireless LAN Chip Set • Full Implementation of the MAC Protocol Specified in IEEE Std. 802.11-1999 and the 802.11b Draft Standard • Host Interface Supports Full 16-Bit Implementation of PC Card 95, also ISA PnP with Additional Chip • Host Interface Provides Dual Buffer Access Paths • External Memory Interface Supports up to 4M bytes RAM • Internal Encryption Engine Executes IEEE802.11 WEP • Low Power Operation; 25mA Active, 8mA Doze, <1mA Sleep • Operation at 2.7V to 3.6V Supply Firmware implements the full IEEE 802.11 Wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF, and operation under the optional Point Coordination Function (PCF). Low level protocol functions such as RTS/CTS generation and acknowledgement, fragmentation and de-fragmentation, and automatic beacon monitoring are handed without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrent operations from multi-threaded I/O drivers. Additional firmware functions specific to access point applications are also available. Designing wireless protocol systems using the HFA3841 is made easier with the availability of evaluation board, firmware, software device drivers, and complete documentation. • 3V to 5V Tolerant Input/Outputs • 128 Pin LQFP Package Targeted for Type II PC Cards • IEEE802.11 Wireless LAN MAC Protocol Firmware and Microsoft® Windows® Software Drivers Applications • High Data Rate Wireless LAN • PC Card Wireless LAN Adapters • ISA, ISA PnP WLAN Cards • PCI Wireless LAN Cards (Using Ext. Bridge Chip) • Wireless LAN Modules • Wireless LAN Access Points • Wireless Bridge Products • Wireless Point-to-Multipoint Systems Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. Q128.14x20 HFA3841CN 0 to 70 128 Ld LQFP HFA3841CN96 0 to 70 Tape and Reel CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1 Microsoft® and Windows® are registered trademarks of Microsoft Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. Preliminary - HFA3841 PJ4 NVCSVSS_IO3 VCC_IO3 MWELMOERAMCS- MA0 MA1 HD8 HD9 HD10 PL7 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 VCC_IO3 VSS_IO3 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 INDEX CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 HCE1HD7 HD6 HD5 HD4 HD3 PJ6 PJ5 PJ7 TCLKIN PL6 PL5 VSS_CORE3 VCC_CORE3 PL0 RESET TXD TXC RXD RXC PK5 PK6 PK7 VSS_CORE3 VCC_CORE3 PL2 PL1 PL3 PJ3 PJ1 PJ0 PJ2 PK2 PK1 PK0 HSTSCHGVSS_CORE3 HINPACKHWAITVCC _IO5 HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HIREQVSS _IO3 HWEHA8 HA9 HIOWRHIORDHOEHCE2HD15 VCC _IO3 HD14 HD13 HD12 HD11 102 101 100 HREGHD0 HD1 HD2 VCC_IO3 VSS_IO3 Pinout Simplified Block Diagram HFA3841 PRISM RADIO BASEBAND PROCESSOR TXD/RXD PHY INTERFACE (MDI) CTRL/STATUS WEP ENGINE SERIAL CONTROL SERIAL CONTROL (MMI) PRISM RADIO RF SECTION HOST COMPUTER MICROPROGRAMMED MAC ENGINE MEMORY CONTROLLER PC CARD HOST INTERFACE ON-CHIP MEMORY 2 SELECT DATA 44MHz CLOCK SOURCE ADDRESS RADIO AND SYNTH SERIAL CONTROL EXTERNAL SRAM AND FLASH MEMORY DATA ADDRESS CONTROL PK4 PK3 TRSTMD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 VCC_CORE3 VSS_IO3 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 PL4 VSS_IO3 XTALO XTALI VCC_CORE3 Preliminary - HFA3841 HFA3841 Pin Descriptions Host Interface Pins PIN NAME HA0-9 PIN NUMBER PIN I/O TYPE 106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down DESCRIPTION PC Card address input, bits 0 to 9 HCE1- 1 5V tol, CMOS, Input, 50K Pull Up PC Card card select, low byte HCE2- 122 5V tol, CMOS, Input, 50K Pull Up PC Card card select, high byte HD0-15 101-99, 6-2, 96-94, 128-125, 123 5V tol, BiDir, 2mA, 50K Pull Down PC Card data bus, bit 0 to 15 HINPACK- 103 CMOS Output, 2mA PC Card I/O decode confirmation HIORD- 120 5V tol, CMOS, Input, 50K Pull Up PC Card I/O space read HIOWR- 119 5V tol, CMOS, Input, 50K Pull Up PC Card I/O space write HRDY/HIREQ- 114 CMOS Output, 4mA PC Card interrupt request (I/O mode) Card ready (memory mode) HOE- 121 5V tol, CMOS, Input, 50K Pull Up PC Card memory attribute space output enable HREG- 102 5V tol, CMOS, Input, 50K Pull Up PC Card attribute space select HRESET 16 5V tol, CMOS, ST Input, 50K Pull Up Hardware Reset HSTSCHG- 36 CMOS Output, 4mA PC Card status change HWAIT- 104 CMOS Output, 4mA PC Card not ready (force host wait state) HWE- 116 5V tol, CMOS Input, 50K Pull Up PC Card memory attribute space write enable Memory Interface Pins PIN NAME MA0 MWEH- MA1-18 PIN NUMBER PIN I/O TYPE DESCRIPTION 72 CMOS TS Output, 2mA MBUS address bit 0 (byte) for x8 memory High byte write enable for x16 memory 73-81, 84-92 CMOS TS Output, 2mA MBUS address bits 1 to 18 PL4 43 CMOS BiDir, 2mA MBUS address bit 19 PL5 12 CMOS BiDir, 2mA, 50K Pull Up MBUS address bit 20 PL6 11 CMOS BiDir, 2mA MBUS address bit 21 MOE- 70 CMOS TS Output, 2mA Memory output enable MWEL- 71 CMOS TS Output, 2mA Low (or only) byte memory write enable RAMCS- 69 CMOS TS Output, 2mA RAM select NVCS- 68 CMOS TS Output, 2mA NV memory select MD0-7 61-54 5V tol, CMOS, BiDir, 2mA, 100K Pull Up MBUS low data byte, bits 0 to 7 MD8-15 51-44 5V tol, CMOS, BiDir, 2mA 50K Pull Down MBUS high data byte, bits 8 to 15 3 Preliminary - HFA3841 Radio Interface and General Purpose Port Pins PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION OF FUNCTION (IF OTHER THAN IO PORT) TXD 17 CMOS Output, 2mA, 50K Pull Down Transmit data out TXC 18 5V tol, CMOS, BiDir 2mA, ST Transmit clock in/out RXD 19 CMOS Input Receive data in RXC 20 CMOS Input, ST Receive clock in PJ0 31 CMOS BiDir, 2mA, ST, 50K Pull Down MMI serial clock in/out PJ1 30 CMOS BiDir, 2mA, 50K Pull Down MMI serial data in/out PJ2 32 CMOS BiDir, 2mA, 50K Pull Down MMI serial data read/write control, or data output PJ3 29 CMOS BiDir, 2mA MMI device enable PJ4 65 CMOS BiDir, 2mA PJ5 8 CMOS BiDir, 2mA, 50K Pull Up PJ6 7 CMOS BiDir, 2mA PJ7 9 CMOS BiDir, 2mA, 50K Pull Up PK0 35 CMOS BiDir, 2mA, ST, 50K Pull Down PK1 34 CMOS BiDir, 2mA, 50K Pull Down PK2 33 CMOS BiDir, 2mA, 50K Pull Down PK3 63 CMOS BiDir, 2mA PK4 64 CMOS BiDir, 2mA PK5 21 CMOS BiDir, 2mA MDREADY - PHY or MAC data available (in) PK6 22 CMOS BiDir, 2mA Medium busy (CCA from PHY) PK7 23 CMOS BiDir, 2mA PL0 15 CMOS BiDir, 2mA Transmitter enable PL1 27 CMOS BiDir, 2mA Receiver enable (or PHY sleep control) PL2 26 CMOS BiDir, 2mA PL3 28 CMOS BiDir, 2mA PL4 43 CMOS BiDir, 2mA PL5 12 CMOS BiDir, 2mA, 50K Pull Up MBUS address bit 20 PL6 11 CMOS BiDir, 2mA MBUS address bit 21 or PHY control I/O PL7 93 CMOS BiDir, 2mA Transmitter ready MBUS address bit 19 Clocks PIN NAME PIN NUMBER PIN I/O TYPE DESCRIPTION XTALI 40 CMOS Input, ST Crystal or external clock input (at >= 2X desired MCLK frequency) XTALO 41 CMOS Output, 2mA Crystal output CLKOUT 38 CMOS, TS Output, 2mA Clock output (selectable as OSC or MCLK) TCLKIN 10 CMOS Input, ST, 50K Pull Down Timebase Reference Clock Input 4 Preliminary - HFA3841 Power PIN NAME PIN NUMBER PIN I/O TYPE VCC_CORE3 14, 25, 39, 53 3.3V Core Supply VCC_IO3 66, 83, 98. 124 3.3V I/O Supply VCC_IO5 105 VSS_CORE3 VSS_IO3 5V Tolerance Supply 13, 24, 37 Core VSS 42, 52, 67, 82, 97, 115 TRST- DESCRIPTION I/O VSS 62 CMOS Input Reserved - Must be tied low through 1K ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low. NOTE: Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at rated loads. Port Pin Uses for PRISM Application PIN NAME PRISM I USE PRISM II™ USE 20 RXC RXC - Receive clock RXC - Receive clock 19 RXD RXD - Receive data RXD - Receive data 18 TXC TXC - Transmit clock TXC - Transmit clock 17 TXD TXD - Transmit data TXD - Transmit data 31 PJ0 SCLK - Clock for the SD serial bus. SCLK - Clock for the SD serial bus. 30 PJ1 SD - Serial bi-directional data bus SD - Serial bi-directional data bus 32 PJ2 R/W - An input to the HFA3860A used to change the direction of the SD bus when reading or writing data on the SD bus. Not Used 29 PJ3 CS - A Chip select for the device to activate the se- CS_BAR - Chip select for HFA3861 baseband rial control port. (active low) (active low) 65 PJ4 Not Used 8 PJ5 SYNTH_LE - Latches a frame of 22 bits after it has LE_IF - Load enable for HFA3783 Quad IF been shifted by the SCLK into the synthesizer registers. 7 PJ6 LED - Activity indicator LED - Activity indicator 9 PJ7 Not Used RADIO_PE - RF power enable 35 PK0 Not Used LE_RF - Load enable for HFA3983 RF chip 34 PK1 Not Used SYNTHCLK - Serial clock to front end chips 33 PK2 Not Used SYNTHDATA - Serial data to front end chips 63 PK3 TX_PE_RF - Power Enable PA_PE - Transmit PA power enable 64 PK4 RX_PE_RF - Power Enable PE2 - Power Enable 2 21 PK5 MD_RDY - Header data and data packet are ready MDREADY - Header data and data packet are to be transferred from Baseband on RXD ready to be transferred from Baseband on RXD 22 PK6 CCA - Signal that the channel is clear to transmit. CCA - Signal that the channel is clear to transmit. 23 PK7 RADIO_PE - Master power control for the RF section CAL_EN - Calibration mode enable 15 PL0 TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband 27 PL1 RX_PE - Receive Enable to Baseband RX_PE - Receive Enable to Baseband 26 PL2 RESET - Reset to Baseband RESET_BB - Reset Baseband 28 PL3 Not Used T/R-SW_BAR - Transient/Receive Control (Inverted) 43 PL4 MA19 (if required) MA19 (if required) 12 PL5 MA20 (if required) MA20 (if required) 11 PL6 MA21 (if required) Reserved 93 PL7 TX_RDY - Baseband ready to receive data on TXD T/R_SW - Transmit/Receive Control (not used by firmware) 5 PE1 - Power Enable 1 Preliminary - HFA3841 Special Hardware Functions for Port Pins PJ0 SCK MMI serial clock in or out PJ1 SDO/SDIO MMI serial data out or I/O MOSI SPI Master Out/Slave In SDI/MISO MMI serial data in Or SPI Master In/Slave Out SDDIR MMI (SDIO) data direction Low while SDIO is driven as an output SDE0 MMI serial device enable 0 Generally selects PHY controller PCS- SPI/MMI transfer qualifier Asserted by hardware during transfer PHYCS- PHY chip select (3-3.5MB) For memory-mapped PHY controllers SDE1 MMI serial device enable 1 For serial EPROM, synthesizer, etc. SDDQ MMI data delivery qualifier Low for data on SDIO, high for address SS- SPI slave select In slave mode SCK is serial clock input PJ2 PJ3 PJ4 PJ5 MREQ- MBUS request PJ6 MGNT- MBUS grant Also for MicroWire LED2 LED 2 driver (Directly from I/O port) PJ7 LED1 LED 1 driver (Directly from I/O port) PK0 GPCK GP serial port clock in or out PK1 PK2 PK3 UHSIn Async handshake in GPDO GP serial port data output UTXD Async transmit data GPDI GP serial port data input URXD Async receive data GPDS0 GP device select 0 Indicates external async Rx ready UHSOut Async handshake out PK4 GPDS1 GP device select 1 PK5 PDA PHY (or MAC) data available Qualifies RXD input to MAC controller UWDET Unique word detected Output from MAC controller MBUSY Medium busy CCA status (PHY-dependent source) PK6 Indicates GP port async Rx ready RATE0 Data Rate select 0 EDET Energy (or modulation) detect RATE1 Data Rate select 1 PL0 TXE Transmitter enable PL1 RXE Receiver enable Can drive “awake” LED PHYSLP PHY sleep (Directly from I/O port) (Directly from I/O port) PK7 PL2 PHYRES PHY reset PL3 SLOT Slot time reference (in or out) ANTSEL Antenna select (Directly from I/O port) PL4 MA19 MBUS address bit 19 For 1M byte SRAM LED0 LED 0 driver (Directly from I/O port) PL5 MA20 MBUS address bit 20 For 2M byte SRAM PL6 MA21 MBUS address bit 21 For 4M byte SRAM PL7 TXR Transmitter ready 6 Preliminary - HFA3841 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Typical, Note 1) θJA (oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .100oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.70V to +3.60V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Maximum test temperature = 100oC, VCC = 3.0V to 3.3V ±10%, TA = -40oC to 85oC DC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Power Supply Current ICCOP VCC = 3.6V, CLK Frequency 44MHz - 35 45 mA Standby Power Supply Current ICCSB VCC = Max, Outputs not Loaded - 0.5 1 mA Input Leakage Current II VCC = Max, Input = 0V or VCC -10 1 10 mA Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 1 10 mA Logical One Input Voltage VIH VCC = Max, Min 0.7VCC - - V Logical Zero Input Voltage VIL VCC = Min, Max - - VCC/3 V Logical One Output Voltage VOH IOH = -1mA, VCC = Min VCC-0.2 - - V Logical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.2 0.2 V Input Capacitance CIN CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC - 5 10 pF COUT CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC - 5 10 pF Output Capacitance NOTE: All values in this table have not been measured and are only estimates of the performance at this time. AC Electrical Specifications PARAMETER SYMBOL MIN TYP MAX UNITS tCYC 22 22.7 200 High Period tH1 15 11.36 - Low Period tL1 15 11.36 - Delay from OSC Edge to MCLK Edge tD1 - 10 - Rising Edge MCLK to EMA[15:0], EMCSxN, EMOEN, EMWRN tD1 0 - 10 ns Width EMOEN tD2 2*tMCLK - 10 - 9*tMCLK + 10 ns EMD[15:0] Read Data Setup tS1 10 - - ns EMD[15:0] Read Data Hold tH1 - - 0 ns Minimum Width between Read and Write tD3 tMCLK - 10 tMCLK tMCLK + 10 ns Width EMWRN tD4 2*tMCLK - 10 - 9*tMCLK + 10 ns EMWRN Rising to EMCSxN Rising tD5 1*tMCLK - 10 1*tMCLK 1*tMCLK + 10 ns EMD[15:0] Write Data Hold Time to Rising Edge EMWRN tD6 1*tMCLK - 10 1*tMCLK 1*tMCLK + 10 ns CLOCK SIGNAL TIMING OSC Clock Period (Typ. 44MHz) EXTERNAL MEMORY INTERFACE 7 Preliminary - HFA3841 AC Electrical Specifications (Continued) PARAMETER SYMBOL MIN TYP MAX UNITS tCYC 90 - 4,000 ns SPCLK Width Hi tH1 tCYC /2 - 10 - tCYC /2 + 10 ns SPCLK Width Lo tL1 tCYC /2 - 10 - tCYC /2 + 10 ns SYNCLE to Rising Edge SPCLK tD1 35 - - ns SPDATA Hold Time from Falling Edge of SPCLK tD2 0 - - ns SPCLK Falling Edge to SYNLE Inactive tD3 35 - - ns tCYC 90ns - 4µs tH1, tL1 tCYC/2 -10 - tCYC/2 + 10 tCD - 10 - ns tDRS 15 - - ns Hold Time of SPDATA Read from SPCLK Falling Edge tDRH 0 - - Hold Time of SPDATA Write from SPCLK Falling Edge tDWH 0 - - Data Delay After SIORDN tDIORD - - 100 ns Data Hold Following SIORDN tHIORD 0 - - ns SIORDN Width Time tWIORD 165 - - ns tSUA 70 - - ns SCE(1,2)N Setup Before SIORDN tSUCE 5 - - ns SCE(1,2)N Hold After SIORDN tHCE 20 - - ns SREGN Setup Before SIORDN tSUREG 5 - - ns SREGN Hold Following SIORDN tHREG 0 - - ns SINPACKN Delay Falling from SIORDN tDFINPACK 0 - 45 ns SINPACKN Delay Rising from SIORDN dDRINPACK - - 45 ns SIOIS16N Delay Falling from Address tDFIOIS16 - - 35 ns SIOIS16N Delay Rising from Address tDRIOIS16 - - 35 ns SWAITN tDFWT - - 35 ns Data Delay from SWAITN Rising tDRWT - - 0 ns SWAITN Width Time tWWT - - 12,000 ns tSUIOWR 60 - - ns Data Hold Following SIOWRN tHIOWR 30 - - ns SIOWRN Width Time tWIOWR 165 - - ns Address Setup Before SIOWRN tSUA 70 - - ns Address Hold Following SIOWRN tHA 20 - - ns SCE(1,2)N Setup Before SIOWRN tSUCE 5 - - ns SCE(1,2)N Hold Following SIOWRN tHCE 20 - - ns SREGN Setup Before SIOWRN tSUREG 5 - - ns SREGN Hold Following SIOWRN tHREG 0 - - ns SYNTHESIZER SPCLK Period SERIAL PORT - HFA3824A/HFA3860B SPCLK Clock Period High Period Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SPDATA Outputs Setup Time of SPDATA Read to SPCLK Falling Edge SYSTEM INTERFACE - PC CARD IO READ 16 Address Setup Before SIORDN SYSTEM INTERFACE - PC CARD IO WRITE 16 Data Setup Before SIOWRN 8 Preliminary - HFA3841 AC Electrical Specifications (Continued) PARAMETER SYMBOL MIN TYP MAX UNITS SIOIS16N Delay Falling from Address tDFIOIS16 - - 35 ns SIOIS16N Delay Rising from Address tDRIOIS16 - - 35 ns SWAITN Delay Falling from IOWRN tDFWT - - 35 ns SWAITN Width Time tWWT - - 12,000 ns tDRIOWR 0 - - ns tDTXD - - 10 ns TXC Period tTXC 4* tTMCK - - ns TXC Width Hi tCHM 31 - - ns TXC Width Lo tCLM 31 - - ns MCLK Period ttMCK 22.7 - - ns tDTX_PE2 - TBD TBD ns ns SIOWRN High from SWAITN High RADIO TX DATA - TX PATH TXC Rising to TXD TXC Rising to TX_PE2 Deassert (See Note 9) TX_RDY Assert Before TXC Rising tTX_RDY 10 - - tTX_RDYH 0 - - tSURX_RDY 10 - - ns RX_RDY Hold Time from RXC Positive Edge (See Note 4) tHRX_RDY 45 - - ns RX_PE2 Delay from RX_RDY deAssert (See Note 8) tDRX_PE2 - 3 * tMCLK - ns RX_PE2 Low Pulse Width (See Note 7) tWRX_PE2 - 4 * tMCLK - ns tSURXD 10 - - ns tHRXD 0 - - ns RXC Period (See Note 9) tRXC - 3 * tMCLK - ns MCLK Period tMCLK 22.7 - - ns RXC Width Hi tRCHM 31 - - ns RXC Width Lo tRCLM 31 - - ns TX_RDY Hold After TXC Rising (See Note 2) RADIO RX DATA - RX PATH RX_RDY Setup Time to RXC Positive Edge (See Note 3) RXD Setup Time to RXC Positive Edge (See Note 5) RXD Hold Time from RXC Positive Edge (See Note 5) NOTES: 2. TX_RDY is and'd with TXC_ONE_SHOT to shift data in shift register. However, once the last data bit is put on TXD output pin no further shifting of bits is required. In addition, TX_RDY remains asserted until TX_PE2 is de-asserted which occurs several MAC MCLK's after the last data bit is shifted into the BBP TX_PORT. Therefore, 0ns hold time is required for this signal. TX_RDY is used by the BBP to signal that the PLCP header and preamble have been generated and the MAC must provide the MPDU data. TX_RDY will remain asserted until TX_PE2 is deasserted by the MAC. TX_PE2 is async to the TX_PORT. 3. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time. 4. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY (MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP header length field are received. THEREFORE, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal be cleared when the last RXD bit is received the hold time w/r RXC must be honored. 5. RXC positive edge clocks a flop which stores the RXD for internal usage. 6. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low. Since RXC can be async to MAC MCLK it is assumed that 3 MCLK periods will suffice. 7. RX_PE inactive width at BBP is 3 BBP MCLK's. Since BBP MCLK and MAC MCLK can be async minimum should be 4 MAC MCLK's. 8. Not yet verified, but seems reasonable. When RX_RDY drops before expected number of RXD bits is received, then Tx/Rx FSM in mpctl.v signals timers which clear rx_pe2_int. More of a functional spec than a timing spec. 9. Need to sample 1 RXC high and 1 RXC low with MAC MCLK. 9 Preliminary - HFA3841 Waveforms OSC tH1 tH1 tD1 tCYC MCLK (INTERNAL) FIGURE 1. CLOCK SIGNAL TIMING 44MHz 23ns OSC 10ns (NOTE 10) 11MHz 91ns MCLK (INTERNAL) QCLK (INTERNAL) 23ns MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns 17ns MOE_ 24ns tH≥0 VALID DATA AT MDIN MD0-15 READ DATA 13ns 16ns MWEH/L_ tH≥0 MD0-15, WRITE DATA VALID DATA 20ns MBUS READ CYCLE MBUS WRITE CYCLE NOTE: 10. Timing delays between OSC and internal clocks are shown for information purposes only. FIGURE 2. MBUS MEMORY TIMING - 11MHz MCLK 10 Preliminary - HFA3841 Waveforms (Continued) 44MHz 23ns OSC 10ns (NOTE 12) 14.67MHz 68.2ns 10ns (NOTE 12) 10ns (NOTE 12) MCLK (INTERNAL) QCLK (INTERNAL) MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns 17ns MOE_ tH≥0 24ns MD0-15 READ DATA VALID DATA AT MDIN 13ns 16ns MWEH/L_ tH≥0 MD0-15 WRITE DATA VALID DATA 20ns MBUS READ CYCLE MBUS WRITE CYCLE NOTES: 11. 14.67MHz requires an odd divisor in the prescaler. Note that both edges of OSC are used to create MCLK and QCLK, thus a deviation from 50% duty cycle in OSC will result in corresponding changes in MBUS timing. 12. Timing delays between OSC and internal clocks are shown for information purposes only. FIGURE 3. MBUS MEMORY TIMING - 14.67MHz MCLK MCLK tD1 EMA [15:0] EMCSxN tD2 EMOEN tD1 tD3 EMWRN tS1 tH1 EMD [15:0] FIGURE 4. 11 tD4 tD5 tD6 Preliminary - HFA3841 Waveforms (Continued) SPCLK tH1 SYNLE SPCSPWR tL1 tCYC tD1 SPDATA tD3 tD2 D[n] D[n -1] D[n -2] D[2] D[1] D[0] FIGURE 5. SYNTHESIZER SPCLK TH1 TL1 tCD tCYC SPCSX tCD tCD SPAS tCD tCD SPREAD (READ) tDRS tDRH SPDATA (READ) A[7] A[6] A[0] D[1] tCD D[0] tCD SPREAD (WRITE) tDWH SPDATA (WRITE) A[7] A[6] A[0] D[7] FIGURE 6. SERIAL PORT - HFA3824A/HFA3860B 12 D[1] D[0] Preliminary - HFA3841 Waveforms (Continued) SA[15:0] tSUREG tHA tHREG SREGN ISUCE tHCE SCE(1, 2) N tWIORD tDIORD SIORDN tSUA tDRINPACK tDFINPACK SINPACKN tDFIOIS16 tDRIOIS16 SIOIS16N SWAITN tWWT tDFWT tDRWT tHIORD D[15:0] FIGURE 7. PC CARD IO READ 16 SA[15:0] tHA tHREG tSUREG SREGN tHCE tSUCE SCE (1, 2) N tSUA tWIOWR SIOWRN tDRINPACK tDRIOIS16 tDFIOIS16 SIOIS16N tDRIOWR SWAITN tDFWT tSUIOWR tWWT D[15:0] FIGURE 8. PC CARD IO WRITE 16 13 tHIOWR Preliminary - HFA3841 Waveforms (Continued) TXDATA TXCLK tTX_RDY TX_RDY TX_PE2 FIGURE 9. TX PATH B A TXD tDTXD C tTXCLK tCHM TXCLK tCLM tMCLK MCLK TXCLK_INT TXCLK_INT2 TXCLK_ONE _SHOT TXD_INT A B FIGURE 10. 14 C Preliminary - HFA3841 Waveforms (Continued) RXDATA RXCLK tSURX_RDY tHRX_RDY RX_RDY tDRX_PE2 RX_PE2 tWRX_PE2 CCA tCCAF FIGURE 11. RX PATH A RXDATA B tRCHM C tHRXD tSURXD RXCLK tRCLM tRXCLK A RXD_INT B tMCLK MCLK RXCLK_INT RXCLK_INT2 RXCLK_ONE _SHOT FIGURE 12. 15 Preliminary - HFA3841 HFA3841 System Overview I/O BUS HOST SYSTEM (I/O DRIVER) FOR STATION ADAPTER HOST INTERFACE HFA3841 WIRELESS MAC CONTROLLER LAN DISTRIBUTION SYSTEM PHY TRANSCEIVER WIRELESS MEDIUM MAC BRIDGE FOR ACCESS POINT FIGURE 13. TYPICAL APPLICATION HFA3841 FLASH 128Kx8 MD0..15 MD0..7 MA1..17 MA0..16 NVCS_ CS_ MOE_ OE_ SPAM 128Kx8 SRAM 128Kx8 MD0..7 MA1..17 OE_ MD8..15 MWEL_ WE_ MA1..17 MA0/MWEH_ CS_ OE_ WE_ CS_ RAMCS_ FIGURE 14. External Memory Interface An external memory space is provided for firmware and for buffers that are used for temporary storage of received and transmitted frames. The total memory space is 4M bytes. 64K words are used for control store, where firmware is located. The high data bus has weak pull-up resistors so that external pull-down resistors can set the configuration of the HFA3841 during reset. NVCS- is the enable to the Flash memory device. Typically the contents of the Flash are copied entirely into SRAM at initialization, and then rarely if ever accessed during normal operation. For this reason, it is acceptable to use low cost, slow Flash devices. During initialization, the clock prescaler is set to produce a longer cycle time while the Flash is accessed. Once all the data has been copied, execution 16 jumps into SRAM and the clock is raised to the normal operating frequency. It is possible to operate without a Flash device. In such a system, the firmware must be downloaded through the host interface before operation can commence. The external SRAM memory must be organized in a 16-bit width to provide adequate performance to implement the 802.11 protocol at 11Mb/s rates. Systems designed for lower performance applications may be able to use 8-bit wide memory. The minimum implementation of external memory consists of 128K bytes of SRAM organized as 64K x 16. Typical applications will use 256K bytes organized as 128K x 16. An access point application could make use of the full address space of the device with 4M bytes organized as 2M x 16. Preliminary - HFA3841 The HFA3841 was designed to implement 16-bit wide memory by using two 8-bit RAM chips. The HFA3841 provides high and low write enable signals (MWEH_ and MWEL_), and a single output enable (MOE_). This allows a direct connection, enabling a pair of 8-bit SRAMs to function as a 16-bit device. MA0 functions as Address 0 for 8-bit access (such as Flash), and as MWEH (High Byte Write Enable) for 16-bit access (such as SRAM), since address bit 0 is not used for 16-bit accesses. HWE-, HOEHOE- and HWE- are only used to access attribute memory. Common Memory, as specified in the PC Card standard, is not used in the HFA3841. HOE- is the strobe that enables an attribute memory read cycle. HWE- is the corresponding strobe for the attribute memory write cycle. The attribute space contains the Card Information Structure (CIS) as well as the Function Configuration Registers (FCR). HIORD-, HIOWR- Some single chip 16-bit SRAMs use an alternate connection scheme with five pins: a Chip Select, an Output Enable, a single Write Enable, and Upper and Lower byte enables, which control both read and write cycles. Thus, external logic is required to generate the required signals. See Application Note AN9844, "HFA3841 to PRISMII Connections" for important information regarding the connection of these types of 16-bit SRAM chips to the HFA3841. HIORD- and HIOWR- are the enabling strobes for register access cycles to the HFA3841. These cycles can only be performed once the initialization procedure is complete and the HFA3841 has been put into IO mode. HREGThis signal must be asserted for I/O or attribute cycles. A cycle with HREG- unasserted will be ignored as the HFA3841 does not support common memory. HINPACK- Host Interface PC Card Physical Interface The Host interface is compatible to the PC Card 95 Standard (PCMCIA v2.1). The HFA3841 Host Interface pins connect directly to the correspondingly named pins on the PC Card connector with no external components (other than resistors) required. The HFA3841 operates as an I/O card using less than 64 octet locations. Reads and writes to internal registers and buffer memory are performed by I/O accesses. Attribute memory (256 octets) is provided for the CIS table which is located in external memory. Common memory is not used. The following describes specific features of various pins: HA[9:0] Decoding of the system address space is performed by the HCEx-. During I/O accesses HA[5:0] decode the register. HA[9:6] are ignored when the internal HAMASK register is set to the defaults used by the standard firmware. During attribute memory accesses HA[9:1] are used. This signal is asserted by the HFA3841 whenever a valid I/O read cycle takes place. A valid cycle is when HCE1-, HCE2-, HREG-, and HIORD- are asserted, once the initialization procedure is complete. HWAITWait states are inserted in accesses using HWAIT-. The host interface synchronizes all PC Card cycles to the internal HFA3841 clock. The following wait states should be expected: Direct Read or Write to Hardware Register • 1/2 to 1 MCLK assertion of HWAIT- for internal synchronization. Write to Memory Mapped Register, Buffer Access Path, or Attribute Space (Post-Write) • The data required for the write cycle will be latched and therefore only the synchronizing wait state will occur. • Until the queued cycle has actually written to the memory, any subsequent access by the Host will result in a WAIT. HD[15:0] Read to Attribute Space and Memory Mapped Registers The host interface is primarily designed for word accesses, although all byte access modes are fully supported. See HCE1-, HCE2- for a further description. Note that attribute memory is specified for and operates with even bytes accesses only. • WAIT will assert until the memory arbitration and access have completed. HCE1-, HCE2The PC Card cycle type and width are controlled with the CE signals. Word and Byte wide accesses are supported, using the combinations of HCE1-, HCE2-, and HA0 as specified in the PC Card standard. 17 Buffer Access Paths, BAP0 and BAP1 • An internal Pre-Read cycle to memory is initiated by a host Buffer Read cycle, after the internal address pointer has auto-incremented. If the next host cycle is a read to the same buffer, the data will be available without a memory arbitration delay. • A single register holds the pre-read data. Thus, any read access to any other memory-mapped register (or the other Preliminary - HFA3841 buffer access path) will result in the pre-read data becoming invalidated. MEMORY MAPPED REGISTERS IN DATA RAM (MM) • 1 to 1 correspondence. • If another read cycle has invalidated the pre-read, then a memory arbitration delay will occur on the next buffer access path read cycle. • Requires memory arbitration, since registers are actually locations in HFA3841 memory. HIREQ- • Attribute memory access is mapped into RAM as Baseaddress + 0x400. Immediately after reset, the HIREQ- signal serves as the RDY/BSY (per the PC Card standard). Once the HFA3841 firmware initialization procedure is complete, HIREQ- is configured to operate as the interrupt to the PC Card socket controller. Both Level Mode and Pulse Mode interrupts are supported. By default, Level mode interrupts are used, so the interrupt source must be specifically acknowledged or disabled before the interrupt will be removed. HRESET When reset is removed, the CIS table is initialized and, once complete, HIREQ- is set high (HIREQ- acts as RDY/BSY from reset and is set high to indicate the card is ready for use). The CIS table resides in Flash memory and is copied to RAM during firmware initialization. The host system can then initialize the card by reading the CIS information and writing to the configuration register. • AUX port provides host access to any location in HFA3841 RAM (reserved). BUFFER ACCESS PATH (BAP) • No 1 to 1 correspondence between register address and memory address (due to indirect access through buffer address pointer registers). • Auto increment of pointer registers after each access. • Require memory arbitration since buffers are located in HFA3841 memory. • Buffer access may incur additional delay for Hardware Buffer Chaining. I/O OFFSET NAME TYPE 00 Command MM 02 Param0 MM ISA PnP 04 Param1 MM The HFA3841 can be connected to the ISA bus and operate in a Plug and Play environment with an additional chip such as the Fujitsu MB86703, Texas Instruments TL16PNP200A, or Fairchild Semiconductor NM95MS15. See the Application Note AN9874, "ISA Plug and Play with the HFA3841" for more details. 06 Param2 MM 08 Status MM Register Interface The logical view of the HFA3841 from the host is a block of 32 word wide registers. These appear in IO space starting at the base address determined by the socket controller. There are three types of registers. 0A Resp0 MM 0C Resp1 MM 0E Resp2 MM 10 InfoFID MM 20 RxFID MM 22 AllocFID MM 24 TxComplFID MM 18 BAP Select0 MM 1C BAP Offset0 MM HARDWARE REGISTERS (HW) 36 BAP Data0 BAP • 1 to 1 correspondence between addresses and registers. 1A BAP Select1 MM • No memory arbitration delay, data transfer directly to/from registers. 1E BAP Offset1 MM 38 BAP Data1 BAP • AUX base and offset are write-only, to set up access through AUX data port. 30 EvStat HW 32 IntEn HW • Note: All register cycles, including hardware registers, incur a short wait state on the PC Card bus to insure the host cycle is synchronized with the HFA3841's internal MCLK. 34 EvAck HW 14 Control MM 28 SwSupport0 MM 2A SwSupport1 MM 2C SwSupport2 MM 3A AuxBase HW 18 3C AuxOffset HW 3E AuxData (reserved) Preliminary - HFA3841 Buffer Access Paths host driver and the HFA3841 by writing or reading a single register location (The Buffer Access Path, or BAP). Each access increments the address in the buffer memory. Internally, the firmware allocates blocks of memory as needed to provide the requested buffer size. These blocks may not be contiguous, but the firmware builds a linked list of pointers between them. When the host driver is transferring data through a buffer access path and reaches the end of a physical memory block, hardware in the host interface follows the linked list so that the buffer access path points to the beginning of the next memory block. This process is completely transparent to the host driver, which simply writes or reads all buffer data to the same register. If the host driver attempts to access beyond the end of the allocated buffer, subsequent writes are ignored, and reads will be undefined. The HFA3841 has two independent buffer access paths, which permits concurrent read and write transfers. The firmware provides dynamic memory allocation between Transmit and Receive, allowing efficient memory utilization. On-the-fly allocation of (128-byte) memory blocks as needed for reception wastes minimal space when receiving fragments. The HFA3841 hides management of free memory from the driver, and allows fast response and minimum data copying for low latency. The firmware provides direct access to TX and RX buffers based on Frame ID (FID). This facilitates Power Management queuing, and allows dynamic fragmentation and defragmentation by controller. Simple Allocate/Deallocate commands insure low host CPU overhead for memory management. Hardware buffer chaining provides high performance while reading and writing buffers. Data is transferred between the FID BUFFER DESCRIPTOR ACCESS (FIRMWARE) ALLOCATE/ DEALLOCATE REQUEST BLOCK BUFFER MEMORY VIRTUAL FRAME BUFFER STATUS A OFFSET CENTER OFFSET HEADER HOST BUS DATA PORT PRE-READ/ POST-WRITE D DATA FIGURE 15. BLOCK DIAGRAM OF A BUFFER ACCESS PATH 19 Preliminary - HFA3841 PHY Interface The PRISM II baseband processor mode works as follows: The HFA3841 is intended to support the PRISM family of Baseband processors with no additional components. This family currently includes the HFA3860B and HFA3861 DSSS baseband processors and the other ICs in the PRISM WLAN chip set. (Other baseband processors may be supported with custom firmware. See your sales representative for more information). The HFA3841 interfaces to the HFA386X baseband processors through two serial interfaces. The Modem Management Interface (MMI) is used to read and write internal registers in the baseband processor and access per-packet PLCP information. The Modem Data Interface (MDI) provides the receive and transmit data paths which transfer the actual MPDU data. The Control Port consists of 4 signals: SD (serial data), SCLK (serial clock), R/W (read/write) and CS_BAR (activelow chip select). Control Port signaling for read and write operations is illustrated in Figures 16 and 17 respectively. Detailed timing relationships appear in Figure 18 and timing specifications are contained in Table 1. The BBP always uses the rising edge when clocking data on the Control Port. This means that when the BBP is receiving data it uses the rising edge of clock to sample; when driving data, transitions occur on the rising edge. Address bits 6 through 1 are significant for selecting configuration registers. Address bits 7 and 0 are unused. See the BBP Programming section for register addresses and suggested values. Serial Control Port (MMI) The HFA3841 has a serial port that is used to program the baseband processor. There are individual chip selects and shared clock and data lines. For read operations, the rising edge of R/W must occur after the 7th but prior to the 8th rising edge of SCLK. This ensures that the first data bit is clocked out of the BBP prior to the edge used to clock it into the MAC. The MMI is used to program the registers and functionality of the PHY baseband processor. PHY BASEBAND PROCESSOR For more detailed information on the Control Port and BBP register programming see the HFA386x data sheets. The PHY baseband processor is programmed by HFA3841 firmware. FIRST DATABIT OUT FIRST ADDRESS BIT 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SCLK SD 7 6 5 MSB 4 3 2 1 07 7 6 6 5 ADDRESS IN 4 MSB 3 2 1 0 DATA OUT LSB R/W CS FIGURE 16. PRISM II BASEBAND PROCESSOR CONTROL PORT READ TIMING 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SCLK SD 7 MSB 6 5 4 3 ADDRESS IN 2 1 0 7 MSB 6 5 4 DATA IN 3 2 1 0 LSB R/W CS FIGURE 17. PRISM II BASEBAND PROCESSOR SERIAL CONTROL PORT WRITE TIMING 20 Preliminary - HFA3841 tSCP tSCW tSCW SCLK tSCS tSCH SDI, R/W, SD, CS tSCD SD (AS OUTPUT) R/W SD tSCED tSCED FIGURE 18. BBP CONTROL PORT SIGNAL TIMING TABLE 1. BBP CONTROL PORT AC ELECTRICAL SPECIFICATIONS PARAMETER LE_RF SYMBOL MIN MAX UNITS SCLK Clock Period tSCP 90 - ns SCLK Width Hi or Low tSCW 20 - ns Setup to SCLK + Edge (SD, SDI, R/W, CS) tSCS 30 - ns Hold Time from SCLK + Edge (SD, SDI, R/W, CS) tSCH 0 - ns SD Out Delay from SCLK + Edge tSCD - 30 ns SD Out Enable/Disable from R/W tSCED - 15 ns SYNTHCLK SYNTHDATA D23 D22 D21 D20 D1 D0 FIGURE 19. SYNTHESIZER DATA FORMAT PHY Data Interface (MDI) The HFA3841 has a dedicated serial port to provide the data interface to the baseband processor. This is referred to as the Modem Data Interface (MDI). The MDI operates on the data being transferred to and from the baseband on a word by word basis. There are no FIFOs needed, since the firmware is able to control the protocol in real time. SYNTHESIZER For the PRISM II, the synthesizer is programmed by firmware using different pins than the MMI. The HFA3841 will exchange data with the baseband during transmit and receive operations over the MMI interface. If the MMI interface was connected to the front end chips, the transitions on SCLK and SD could couple noise into them. The synthesizer serial bus consists of SYNTHDATA, SYNTHCLK, LE_IF and LE_RF. SYNTHDATA is on pin PK2, SYNTHCLK is on PK1, LE_IF is the enable for the HFA3783 Quad IF chip, and LE_RF is the enable for the HFA3683 synthesizer. Data is provided on SYNTHDATA and clock on SYNTHCLK. The data is updated the falling edge of SYNTHCLK and expected to be latched into the synthesizer on the rising edge. The enable signal LE_RF is asserted while data is clocked out. 21 The MDI performs the following functions: • Serial to parallel conversion of received data from the baseband, with synchronization between the incoming RX clock to the internal HFA3841 clock. • Generating CRCs (HEC and FCS) from the received data stream to verify correct reception. • Decrypt the received data when WEP is enabled. • Parallel to serial conversion of transmit data, with the serial timing synchronized with the TX clock. • Insertion of the CRCs (HEC and FCS) at the appropriate point during transmission. • Encrypt the transmitted data when WEP is enabled. The receive data path uses RX_RDY, RXC, RXD. The transmit data path uses TX_RDY, TXC, TXD and the CCA input to determine (under the IEEE802.11 protocol) whether to transmit. Preliminary - HFA3841 go active after SFD is detected. This signals the HFA3841, allowing it to pick off the needed header fields from the realtime demodulated bitstream rather than having to read these fields through the BBP Control Port. In transmit mode, the HFA386X is used in the mode where it generates the PLCP header internally and only the MPDU is passed from HFA3841. In receive, the HFA386X is used in the mode where it passes the PLCP header and the MPDU to the HFA3841. Assuming all is well with the header, the BBP decodes the signal field in the header and switches to the appropriate data rate. If the signal field is not recognized, or the CRC16 is in error, then MDRDY will go inactive shortly after CRC16 and the demodulator will return to acquisition mode looking for another packet. If all is well with the header, and after the demodulator has switched to the appropriate data rate, then the demodulator will continue to provide data to the HFA3841 indefinitely. BBP Packet Reception There are 4 signals associated with the BBP Receive Port: RX_PE (receive enable), MDRDY (receive ready), RXD (receive data), and RXCLK (receive clock). These connect to the HFA3841 on pins PL1, PK5, RXD, and RXC, respectively. The receive demodulator in the BBP is activated via RX_PE. When RX_PE goes active the demodulator scrutinizes I and Q for packet activity. When a packet arrives at a valid signal level the demodulator acquires and tracks the incoming signal. It then sifts through the demodulator data for the Start Frame Delimiter (SFD). Normally, MDRDY is programmed to Receive Port exchange details are depicted in Figure 20. Detailed timing is related in Figure 21 and Table 2. For more detailed information concerning BBP packet reception see the HFA386x data sheets. RXC RX_PE HEADER FIELDS DATA MDRDY PROCESSING PREAMBLE/HEADER LSB MSB DATA PACKET RXD FIGURE 20. BBP RECEIVE PORT TIMING tRLP RX_PE tRD3 tREH IIN , QIN tRD2 MDRDY tRCP RXC RXD tCCA tRCD tRCD tRDS CCA, RSSI tRDI tRDD FIGURE 21. BBP RECEIVE PORT SIGNAL TIMING NOTE: RXD, MDRDY is output two MCLK after RXC rising to provide hold time. RSSI output on TEST (5:0). 22 Preliminary - HFA3841 TABLE 2. BBP RECEIVE PORT AC ELECTRICAL SPECIFICATIONS signals the BBP with the signal TX_PE. The BBP forms the preamble and header and then signals the MAC to begin transferring data with the signal TXRDY. This sequence is illustrated in Figure 22 with detailed signal timing shown in Figure 23 and specified delays contained in Table 3. Note that if the MAC deactivates TX_PE too early it may cut off modulation of the final symbol. For this reason, when TX_PE is de-asserted the BBP will hold TXRDY active until the last symbol containing data is modulated. This is important for power sequencing and is discussed in more detail in that section. PARAMETER SYMBOL MIN MAX UNITS RX_PE Inactive Width tRLP 70 - ns (Note 13) RXC Period (11MBps Mode) tRCP 77 - ns RXC Width Hi or Low (11MBps Mode) tRCD 31 - ns RXC to RXD tRDD 20 60 ns MD_RDY to 1st RXC tRD1 940 - ns (Note 14) RXD to 1st RXC tRD! 940 - ns Setup RXD to RXC tRDS 31 - ns RXC to RX_PE Inactive (1MBps) tREH 0 925 ns (Note 15) PARAMETER SYMBOL MIN MAX UNITS 0 380 ns (Note 15) tD1 2.3 tREH TX_PE to IOUT/QOUT (1st Valid Chip) 2.18 RXC to RX_PE Inactive (2MBps) µs (Note 19) TX_PE Inactive Width - tREH 0 140 ns (Note 15) tTLP 2.22 RXC to RX_PE Inactive (5.5MBps) µs (Note 20) TXC Width Hi or Low tTCD 40 - ns RXC to RX_PE Inactive (11MBps) tREH 0 50 ns (Note 15) TXRDY Active to 1st TX_CLK Hi tRC 260 - ns RX_PE inactive to MD_RDY Inactive tRD2 5 30 ns (Note 16) Setup TXD to TXC Hi tTDS 30 - ns Hold TXD to TXC Hi 0 - ns tRD3 2.77 2.86 µs (Note 14) tTDH Last Chip of SFD in to MD_RDY Active TXC to TX_PE Inactive (1MBps) tPEH 0 965 ns (Note 22) TXC to TX_PE Inactive (2MBps) tPEH 0 420 ns (Note 22) TXC to TX_PE Inactive (5.5MBps) tPEH 0 160 ns (Note 22) 13. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition. TXC to TX_PE Inactive (11MBps) tPEH 0 65 ns (Note 22) 14. MD_RDY programmed to go active after SFD detect (measured from IIN, QIN). TXRDY Inactive To Last Chip of MPDU Out tRI -20 20 ns TXD Modulation Extension tME 2 - RX Delay 2.77 2.86 µs (Note 17) RX_PE to CCA Valid tCCA - 10 µs (Note 18) RX_PE to RSSI Valid tCCA - 10 µs (Note 18) For more detailed information concerning BBP packet transmission see the HFA3861 data sheet. TABLE 3. BBP TRANSMIT PORT AC ELECTRICAL SPECIFICATIONS NOTES: 15. RX_PE active to inactive delay to prevent next RXC. 16. Assumes RX_PE inactive after last RXC. 17. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at IIN, QIN to MD_RDY active. µs (Note 21) NOTES: 18. CCA and RSSI are measured once during the first 10µs interval following RX_PE going active. RX_PE must be pulsed to initiate a new measurement. RSSI may be read via serial port or from Test Bus. 19. IOUT/QOUT are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits. BBP Packet Transmission 21. IOUT/QOUT are modulated after last chip of valid data to provide ramp down time for RF/IF circuits. There are 4 signals associated with the BBP Transmit Port: TX_PE (transmit enable), TXRDY (transmit ready), TXD (transmit data), and TXCLK (transmit clock). These connect to the HFA3841 on PL0, PL7, TXD, and TXC, respectively. 22. Delay from TXC to inactive edge of TXPE to prevent next TXC. Because TXPE asynchronously stops TXC, TXPE going inactive within 40ns of TXC will cause TXC minimum hi time to be less than 40ns. State machines within the BBP control packet transmission and reception. In the case of a transmission, the MAC 23 20. TX_PE must be inactive before going active to generate a new packet. Preliminary - HFA3841 TXC TX_PE LAST DATA BIT SAMPLED FIRST DATA BIT SAMPLED LSB TXD DATA PACKET MSB DEASSERTED WHEN LAST CHIP OF MPDU CLEARS MOD PATH OF 3861 TXRDY NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC. FIGURE 22. BBP TRANSMIT PORT TIMING tTLP TX_PE tDI tPEH tME IOUT, QOUT tRI tTCD t TCD TXRDY tRC TXC TXD tTDH tTDS FIGURE 23. BBP TRANSMIT PORT SIGNAL TIMING Power Sequencing The HFA3841 provides a number of firmware controlled port pins that are used for controlling the power sequencing and other functions in the front end components of the PHY. machine in the BBP. Lastly, PA_PE activates the PA. Delays for these signals related to the initiation of transmission are referenced to PE2. Packet transmission requires precise control of the radio. Ideally, energy at the antenna ceases after the last symbol of information has been transmitted. Additionally, the transmit/receive switch must be controlled properly to protect the receiver. It's also important to apply appropriate modulation to the PA while it's active. Immediately after the final data bit has been clocked out of the HFA3841, TX_PE is de-asserted. The HFA3841 then waits for TXRDY to go inactive, signaling that the BBP has modulated the final information-rich symbol. It then immediately de-asserts PA_PE followed by placing the transmit/receive switch in the receive position and ending with PE2 going high. Delays for these signals related to the termination of transmission are referenced to the rising edge of PE2. Signaling sequences for the beginning and end of normal transmissions are illustrated in Figure 24. Table 4 lists applicable delays. A transmission begins with PE2 as shown in Figure 24. Next, the transmit/receive switch is configured for transmission via the differential pair TR_SW and TR_SW_BAR. This is followed by TX_PE which activates the transmit state 24 Preliminary - HFA3841 PE1 PE2 TR_SW TR_SW_BAR tD5 tD1 TX_PE tD2 TX_RDY PA_PE tD3 tD4 FIGURE 24. TRANSMIT CONTROL SIGNAL SEQUENCING TABLE 4. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER SYMBOL DELAY PE2 to TR Switch tD1 2 ±0.1 µs PE2 to BBP TX_PE tD2 TBD ±0.1 PE2 to PA_PE tD3 3 PA_PE to PE2 tD4 TR Switch to PE2 tD5 PE1 PE2 PLL_PE Power Down State 0 0 1 µs Receive State 1 1 1 ±0.1 µs Transmit State 1 0 1 3 ±0.1 µs PLL Active State 0 1 1 2 ±0.1 µs PLL Disable State X X 0 PE1 and PE2 encoding details are found in Table 5. Note that during normal receive and transmit operation that PE1 is static and PE2 toggles for receive and transmit states. 25 TABLE 5. POWER ENABLE STATES TOLERANCE UNITS NOTE: PLL_PE is controlled via the serial interface, and can be used to disable the internal synthesizer, the actual synthesizer control is an AND function of PLL_PE, and a result of the OR function of PE1 and PE2. PE1 and PE2 will directly control the power enable functionality of the LO buffer(s)/phase shifter. Preliminary - HFA3841 Master Clock Prescaler The HFA3841 contains a clock prescaler to provide flexibility in the choice of clock input frequencies. For 11Mb/s operation, the internal master clock, MCLK, must be between 11MHz and 16MHz. The clock generator itself requires an input from the prescaler that is twice the desired MCLK frequency. Thus the lowest oscillator frequency that can be used for an 11MHz MCLK is 22MHz. The prescaler can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that the divisor ratio between the external clock source and the internal MCLK may be integers between 2 and 14. Typically, the 44MHz baseband clock is used as the input, and the prescaler is set to divide by 2. Another useful configuration is to set the prescaler to divide by 1.5 (resulting in 44MHz ÷3) for an MCLK of 14.67MHz. Off Chip If an off chip oscillator source is used, it should be connected to the XTALI pin. Insure that the signal amplitude meets CMOS levels at the XTALI pin. Oscillator The XTALI and XTALO pins provide an on-chip oscillator function to generate the master clock. For a standard pierce oscillator, the crystal is connected between XTALI and XTALO. Two capacitors, typically 15pF each, are connected from each pin to ground. The crystal should be a fundamental mode, specified under parallel resonance conditions. The load capacitance seen by the crystal will be approximately 2pF more than the series combination of C1 and C2 plus stray capacitance. After power on, the crystal will require time to stabilize before normal operation can commence. Insure that reset remains asserted for enough time for the crystal oscillator to stabilize. C1 XTALI The MD[15:8] pin values are sampled on the falling edge of HRESET or SRESET. These pins have internal 50K pulldown resistors. External pull-up resistors (typically 10kΩ) are used for bits that should be read as high at reset. The table below summarizes the effect per pin. TABLE 6. POR PINS AND FUNCTIONALITY PIN LATCH OUTPUT MD[8] Reserved MD[9] Nvdis MD[10] MEM16 MD[11] IDLE MD[12] Reserved MD[15:13] MD15/14/13 FUNCTIONALITY Disable mapping of CS to NV (Flash) External memory (RAM and Flash) is 16 bits wide See below FW purposes MD[11], IDLE, has no equivalent functionality in any control register. When asserted at reset, it will inhibit firmware execution. This is used to allow the initial download of firmware in “Genesis Mode”. See the Hardware Reference Manual for more details. The latch is cleared when the Software Reset, SRESET, COR(7) is active. References For Intersil documents available on the internet, see web site http://www.intersil.com/ Intersil AnswerFAX (321) 724-7800. [1] IEEE Std 802.11-1999 Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification. [2] HFA3860B Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4594. [3] HFA3861 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4699. [4] HFA3783 Data Sheet, Quad IF, Intersil Corporation, AnswerFAX Doc. No. 4633. X1 C2 XTALO FIGURE 25. POWER ON RESET CONFIGURATION [5] HFA3683 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4634. [6] PC Card Standard 1996, PCMCIA/JEIDA. [7] AN9874 Application Note, Intersil Corporation, “ISA Plug and Play with the HFA3841”. Power On Reset Configuration Power On Reset is issued to the HFA3841 with the HRESET pin or via the soft reset bit, SRESET, in the Configuration Option Register (COR, bit 7). HRESET originates from the HOST system which applies HRESET for at least 0.01ms after VCC has reached 90% of its end value (see PC-Card standard, Vol. 2, Ch. 4.12.1). 26 [8] AN9844 Application Note, Intersil Corporation, “HFA3841 to PRISMII Connections”, AnswerFAX Doc. No. 99844 Preliminary - HFA3841 Thin Plastic Quad Flatpack Packages (LQFP) Q128.14x20 (JEDEC MS-026BHB ISSUE C) D 128 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE D1 -D- -B- -AE E1 e PIN 1 SEATING A PLANE -H- 0.08 0.003 -C- INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.062 - 1.60 - A1 0.002 0.005 0.05 0.15 - A2 0.054 0.057 1.35 1.45 - b 0.007 0.010 0.17 0.27 6 b1 0.007 0.009 0.17 0.23 - D 0.862 0.870 21.90 22.10 3 D1 0.783 0.791 19.90 20.10 4, 5 E 0.626 0.634 15.90 16.10 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.018 0.029 0.45 0.75 N 128 128 e 0.0197 BSC 0.50 BSC 7 Rev. 0 7/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 0.13 A-B S 0.005 M C D S b 11o-13o 0.020 0.008 MIN b1 0o MIN A2 A1 GAGE PLANE 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 0.09/0.16 0.004/0.006 7. “N” is the number of terminal positions. BASE METAL WITH PLATING L 0o-7o 4. Dimensions D1 and E1 to be determined at datum plane -H- . 11o-13o 0.25 0.010 0.09/0.20 0.004/0.008 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 27 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029